Display module and overcurrent protection test method

Abstract

The application provides a display module and an overcurrent protection test method. The display module comprises a display panel, a plurality of signal lines, a gate drive circuit electrically connected to the plurality of signal lines, and a circuit board. The circuit board comprises a plurality of resistance adjusting devices, and at least one resistance adjusting device is electrically connected between a corresponding signal line and a signal input end. By adjusting the plurality of resistance adjusting devices, the phenomenon of short circuit between at least two signal lines can be simulated. In this way, the number of laser display panels required in the OCP debugging process can be reduced, thereby saving resources.

Description

Technical Field

[0001] This invention relates to the field of display technology, specifically to a display module and an overcurrent protection test method. Background Technology

[0002] In related technologies, display panels require OCP (Over Current Protection) debugging and setting. During OCP debugging, the OCP function needs to be disabled, and then the signal lines of the GOA (Gate Driver On Array) circuit of the display panel are laser-etched to achieve a short circuit effect, thus enabling OCP debugging and setting. However, the GOA circuit has many signal lines, requiring laser etching of multiple display panels, resulting in resource waste. Summary of the Invention

[0003] The embodiments of the present invention provide a display module and an overcurrent protection test method, which can improve the technical problem of resource waste in the OCP debugging and setting process.

[0004] An embodiment of the present invention provides a display module, comprising: a display panel including a plurality of signal lines and a gate driving circuit electrically connected to the ends of the plurality of signal lines; and a circuit board; wherein the circuit board includes a plurality of resistance adjustment devices, at least one of the resistance adjustment devices being electrically connected between the end of a corresponding signal line away from the gate driving circuit and a signal input terminal.

[0005] In some embodiments, the circuit board further includes a plurality of first switches, and at least one of the resistance adjustment devices is electrically connected between the corresponding signal line and the signal input terminal through a first switch connected in series with the resistance adjustment device.

[0006] In some embodiments, the range of the resistance adjustment device corresponding to the signal line with a larger resistance value is smaller than the range of the resistance adjustment device corresponding to the signal line with a smaller resistance value.

[0007] In some embodiments, at least one of the resistance adjustment devices is a sliding rheostat.

[0008] In some embodiments, the plurality of signal lines include a cascade signal line for transmitting a cascade signal, a clock signal line for transmitting a clock signal, an inverting signal line for transmitting an inverted signal, a first power signal line for transmitting a first power signal, and a second power signal line for transmitting a second power signal; the gate drive circuit includes a plurality of cascaded gate drive units, at least one of the gate drive units including a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down sustaining unit; the pull-up control unit is used to pull up the voltage of a first node in response to the cascade signal; the pull-up unit is used to output the clock signal to the scan line in response to the voltage of the first node being pulled up; the pull-down unit is used to transmit the second power signal to the scan line to pull down the voltage of the scan line; the pull-down sustaining unit is used to transmit the second power signal and the first power signal to the scan line and the first node respectively in response to the inverted signal to pull down the voltage of the scan line and the first node.

[0009] In some embodiments, the signal input terminal is used to load the clock signal.

[0010] In some embodiments, the circuit board includes a timing controller electrically connected to the display panel.

[0011] An embodiment of the present invention also provides an overcurrent protection test method for obtaining an overcurrent protection value of a display module as described above, comprising: obtaining current signals of at least two of the signal lines, wherein the overcurrent protection module of the display panel is turned off, and the resistor adjustment device corresponding to the at least two of the signal lines is adjusted to simulate a short circuit phenomenon of at least two of the signal lines; and generating the overcurrent protection value of the display panel based on the current signals.

[0012] In some embodiments, there is no short circuit between at least two of the signal lines.

[0013] In the display module and overcurrent protection testing method provided in the embodiments of the present invention, by adjusting multiple resistor adjustment devices, a short circuit between at least two signal lines can be simulated. This reduces the number of display panels requiring laser etching during the OCP debugging process, thereby saving resources. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the display module structure according to an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of the circuit board structure of the display module according to an embodiment of the present invention;

[0017] Figure 3 This is a circuit diagram of the gate driving unit of the display module according to an embodiment of the present invention;

[0018] Figure 4 This is a flowchart illustrating the overcurrent protection test method according to an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0020] like Figure 1 As shown, an embodiment of the present invention provides a display module 1. The display module 1 may include a display panel 2 and a circuit board 3. The display panel 2 may be an LCD (Liquid Crystal Display) panel or an active-matrix display panel, such as an OLED (Organic Light Emitting Diode) display panel, a MiniLED (Miniature Light Emitting Diode) display panel, or a Micro LED (Micro Light Emitting Diode) display panel. The circuit board 3 may be a PCB (Printed Circuit Board).

[0021] The display panel 2 includes a display area DA and a non-display area NDA. The display area DA may be an area for setting sub-pixels PX of the displayed image. The non-display area NDA may be an area for providing drive signals to the sub-pixels PX and some lines such as power lines connecting the drive units. The non-display area NDA may be located on at least one side of the display area DA. The non-display area NDA may at least partially surround the display area DA.

[0022] The display panel 2 includes multiple sub-pixels PX, multiple signal lines SG, and a gate driving circuit GDC. The multiple sub-pixels PX are located within the display area DA and arranged in an array to form multiple rows of sub-pixels PX. The multiple signal lines SG are located within the non-display area NDA. The gate driving circuit GDC, located within the non-display area NDA, is electrically connected to the ends of the multiple signal lines SG to receive signals transmitted by the multiple signal lines SG, and drives the multiple rows of sub-pixels PX through multiple scan lines to sequentially open the multiple rows of sub-pixels PX. Simultaneously, display data is sequentially loaded onto the multiple rows of sub-pixels PX, thereby enabling the display panel 2 to display a complete frame of image within one frame.

[0023] like Figure 2 As shown, the circuit board 3 includes a plurality of resistance adjustment devices 30, at least one of the resistance adjustment devices 30 being electrically connected between the end of the corresponding signal line SG furthest from the gate drive circuit GDC and the signal input terminal SIN. Exemplarily, at least one of the resistance adjustment devices 30 is a sliding rheostat.

[0024] In related technologies, debugging OCP requires laser-etching at least two of the signal lines to short-circuit them. Since the resistance of the short-circuited signal lines changes, in the display module 1 provided in the embodiments of the present invention, by adjusting multiple resistance adjustment devices 30, the phenomenon of a short circuit between at least two of the signal lines SG can be simulated. This reduces the number of display panels that need to be laser-etched during the OCP debugging process, thereby saving resources.

[0025] In some embodiments, the circuit board 3 further includes a plurality of first switches 31, and at least one of the resistance adjustment devices 30 is electrically connected between the corresponding signal line SG and the signal input terminal SIN through the first switch 31 connected in series with the resistance adjustment device 30. Exemplarily, the first switch 31 is a DIP switch. Thus, when the first switch 31 is turned on, OCP debugging of the display panel 2 can be performed. When the first switch 31 is turned off, the resistance adjustment device 30 does not affect the normal driving of the display panel 2. Therefore, the normal driving and OCP debugging of the display panel 2 are separated.

[0026] In some embodiments, the range of the resistance adjustment device 30 corresponding to the signal line SG with a larger resistance value is smaller than the range of the resistance adjustment device 30 corresponding to the signal line SG with a smaller resistance value. Since the adjustment amount for the signal line SG with a larger resistance value is smaller than the adjustment amount for the signal line SG with a smaller resistance value, setting the range of the resistance adjustment device 30 corresponding to the signal line SG with a larger resistance value to be smaller can further save resources.

[0027] In some embodiments, the plurality of signal lines SG include a transmission signal line for transmitting a transmission signal ST, a clock signal line for transmitting a clock signal CK, an inverting signal line for transmitting an inverted signal LC, a first power signal line for transmitting a first power signal VSSG, and a second power signal line for transmitting a second power signal VSSQ. Exemplarily, the signal input terminal SIN is used to load the clock signal CK, thus saving the number of signal sources.

[0028] Please see Figure 3 The gate drive circuit GDC includes multiple cascaded gate drive units, and at least one of the gate drive units includes a pull-up control unit 100, a pull-up unit 200, a cascade unit 300, a pull-down unit 400, a bootstrap unit 500, and a pull-down sustaining unit 600.

[0029] The pull-up control unit 100 is used to pull up the voltage of the first node Q(n) in response to the (n-1)th stage transmission signal ST(n-1). Exemplarily, the pull-up control unit 100 includes a first thin-film transistor T1. The gate of the first thin-film transistor T1 is connected to the (n-1)th stage transmission signal ST(n-1), the source is connected to the scan signal G(n-1) of the (n-1)th stage GOA unit, and the drain is electrically connected to the first node Q(n).

[0030] The pull-up unit 200 is used to output the clock signal CK to the scan line in response to the voltage of the first node Q(n) being pulled up. Exemplarily, the pull-up unit 200 includes a second thin-film transistor T2. The gate of the second thin-film transistor T2 is electrically connected to the first node Q(n), the source is connected to the clock signal CK, and the drain is connected to the scan signal G(n).

[0031] For example, the cascading unit 300 includes a third thin-film transistor T3. The gate of the third thin-film transistor T3 is electrically connected to the first node Q(n), the source is connected to the clock signal CK, and the drain outputs the nth cascading signal ST(n).

[0032] The pull-down unit 400 is used to transmit the second power signal VSSG to the scan line to pull down the scan signal G(n). Exemplarily, the pull-down unit 400 includes a fourth thin-film transistor T4 and a fifth thin-film transistor T5. The gate of the fourth thin-film transistor T4 is connected to the scan signal G(n+1) of the (n+1)th stage GOA unit, its source is electrically connected to the first node Q(n), and its drain is connected to the first power signal VSSQ. The gate of the fifth thin-film transistor T5 is connected to the scan signal G(n+1) of the (n+1)th stage GOA unit, its source is connected to the scan signal G(n), and its drain is connected to the second power signal VSSG.

[0033] For example, the bootstrap unit 500 includes a bootstrap capacitor C1, the first end of which is electrically connected to the first node Q(n), and the second end is connected to the scan signal G(n).

[0034] The pull-down sustaining unit 600 is used to respond to the inverted signal LC to transmit the second power signal VSSG and the first power signal VSSQ to the scan line and the first node Q(n) respectively, and pull down the voltage of the scan signal G(n) and the first node Q(n).

[0035] For example, the pull-down sustaining unit 600 includes a sixth thin-film transistor T6, a seventh thin-film transistor T7, an eighth thin-film transistor T8, and an inverter 601.

[0036] The gate of the sixth thin-film transistor T6 is electrically connected to the output terminal of the inverter 601, the source is connected to the scan signal G(n), and the drain is connected to the second power supply signal VSSG. The gate of the seventh thin-film transistor T7 is electrically connected to the output terminal of the inverter 601, the source is electrically connected to the first node Q(n), and the drain is connected to the first power supply signal VSSQ. The gate of the eighth thin-film transistor T8 is electrically connected to the output terminal of the inverter 601, the source is connected to the (n-1)th stage transmission signal ST(n-1), and the drain is connected to the first power supply signal VSSQ.

[0037] The input terminal of the inverter 601 is electrically connected to the first node Q(n). The inverter 601 is a Darlington structure inverter, specifically including: a ninth thin-film transistor T9, a tenth thin-film transistor T10, an eleventh thin-film transistor T11, and a twelfth thin-film transistor T12.

[0038] The gate and source of the ninth thin-film transistor T9 are both connected to the inverted signal LC, and its drain is electrically connected to the gate of the twelfth thin-film transistor T12. The gate of the tenth thin-film transistor T10 is electrically connected to the first node Q(n), its source is electrically connected to the gate of the twelfth thin-film transistor T12, and its drain is connected to the first power supply signal VSSQ. The gate of the eleventh thin-film transistor T11 is electrically connected to the first node Q(n), its source is electrically connected to the drain of the twelfth thin-film transistor T12, and its drain is connected to the first power supply signal VSSQ. The source of the twelfth thin-film transistor T12 is connected to the inverted signal LC. The drain of the twelfth thin-film transistor T12 is the output terminal of the inverter 601, and the gate of the tenth thin-film transistor T10 is the input terminal of the inverter 601.

[0039] In some embodiments, please refer to Figure 1 The circuit board 3 includes a timing controller 33, which is electrically connected to the display panel 2. This allows for the installation of a resistance adjustment device 30 on the circuit board 3 controlling the display panel 2, saving resources.

[0040] In some embodiments, the resistance adjustment device 30 can also be used to adjust the resistance values ​​of multiple fan-out traces of the display panel 2 to make the impedances of the multiple fan-out traces consistent. The circuit board 3 also includes multiple second switches. One end of at least one of the resistance adjustment devices 30 is electrically connected to the corresponding signal line SG through a first switch 31, and is electrically connected to one end of the corresponding fan-out trace through a second switch. The other end of at least one of the resistance adjustment devices 30 is electrically connected to the signal input terminal SIN through a first switch 31, and is electrically connected to the other end of the corresponding fan-out trace through a second switch. By opening the two second switches corresponding to at least one of the resistance adjustment devices 30, the resistance value of the corresponding fan-out trace can be adjusted through the resistance adjustment device 30.

[0041] Please see Figure 4 The embodiments of the present invention also provide an overcurrent protection test method for obtaining the overcurrent protection value of the display module 1 as described above, including:

[0042] Step S1: Obtain the current signals of at least two of the signal lines SG, wherein the overcurrent protection module of the display panel 2 is turned off, and the resistance adjustment device 30 corresponding to at least two of the signal lines SG is adjusted to simulate a short circuit in at least two of the signal lines SG.

[0043] In this case, at least two of the signal lines SG do not need to be laser-cut to short-circuit them.

[0044] Step S2: Generate the overcurrent protection value of the display panel 2 based on the current signal.

[0045] The overcurrent protection value of the display panel 2 can be generated based on the current signal obtained by simulating a short circuit between at least two of the signal lines SG. For example, the overcurrent protection value can be obtained by taking the average, maximum, or minimum value of the current signal over a certain period of time, or by adding an empirical coefficient to the value of the current signal.

[0046] In related technologies, OCP debugging requires laser-etching at least two of the signal lines to short-circuit them. Since the resistance of the short-circuited signal lines changes, the overcurrent protection test method provided in this embodiment of the invention simulates a short circuit between at least two of the signal lines SG by adjusting multiple resistance adjustment devices 30, and then generates the overcurrent protection value of the display panel 2 based on the current signals of the at least two signal lines SG. This reduces the number of display panels that need to be laser-etched during the OCP debugging process, thereby saving resources.

[0047] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display module, characterized in that, include: The display panel includes a plurality of signal lines and a gate driving circuit electrically connected to the ends of the plurality of signal lines. The plurality of signal lines include a transmission signal line for transmitting a transmission signal, a clock signal line for transmitting a clock signal, an inverting signal line for transmitting an inverted signal, a first power signal line for transmitting a first power signal, and a second power signal line for transmitting a second power signal. The gate driving circuit outputs a scan signal according to the signals transmitted by the plurality of signal lines. The circuit board includes multiple resistor adjustment devices and multiple first switches. At least one of the resistor adjustment devices is electrically connected between the end of the corresponding signal line away from the gate drive circuit and the signal input terminal. The signal input terminal is used to load the clock signal. At least one of the resistor adjustment devices is electrically connected between the corresponding signal line and the signal input terminal through the first switch connected in series with the resistor adjustment device. The overcurrent protection module of the display panel is configured to be off, and the resistor adjustment device corresponding to at least two of the signal lines is adjusted to simulate a short circuit in at least two of the signal lines. The overcurrent protection value of the display panel is generated based on the current signals of at least two of the signal lines.

2. The display module according to claim 1, characterized in that, The range of the resistance adjustment device corresponding to the signal line with a larger resistance value is smaller than the range of the resistance adjustment device corresponding to the signal line with a smaller resistance value.

3. The display module according to claim 1, characterized in that, At least one of the resistor adjustment devices is a sliding rheostat.

4. The display module according to claim 1, characterized in that, The gate driving circuit includes a plurality of cascaded gate driving units. At least one of the gate driving units includes a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down sustaining unit. The pull-up control unit is used to pull up the voltage of the first node in response to the cascaded signal. The pull-up unit is used to output the clock signal to the scan line in response to the voltage of the first node being pulled up. The pull-down unit is used to transmit the second power signal to the scan line to pull down the voltage of the scan line. The pull-down sustaining unit is used to transmit the second power signal and the first power signal to the scan line and the first node respectively in response to the inverting signal to pull down the voltage of the scan line and the first node.

5. The display module according to claim 1, characterized in that, The circuit board includes a timing controller, which is electrically connected to the display panel.

6. An overcurrent protection test method, used to obtain the overcurrent protection value of the display module as described in any one of claims 1-5, characterized in that, include: Acquire current signals from at least two of the signal lines, wherein the overcurrent protection module of the display panel is turned off, and the resistor adjustment device corresponding to at least two of the signal lines is adjusted to simulate a short circuit in at least two of the signal lines; as well as The overcurrent protection value of the display panel is generated based on the current signal.

7. The overcurrent protection test method according to claim 6, characterized in that, There should be no short circuit between at least two of the signal lines.

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