Display device and driving method thereof

Abstract

A display device and a driving method thereof are disclosed. In the display device, a display panel has a plurality of first pixel columns and a plurality of second pixel columns arranged alternately. In a first time interval, a first gate driver sequentially drives the first pixel columns in a first driving manner. In a second time interval, a second gate driver sequentially drives the second pixel columns in the first driving manner. In a third time interval, a third gate driver sequentially drives the first pixel columns in a second driving manner. In a fourth time interval, a fourth gate driver sequentially drives the second pixel columns in the second driving manner. One of the first driving manner and the second driving manner is a pulse amplitude modulation driving manner, and the other is a pulse width modulation driving manner.

Description

Technical Field

[0001] This invention relates to a driving technology, and more particularly to a display device and its driving method. Background Technology

[0002] In typical display devices, pixel circuits usually have a PWM block controlled by pulse width modulation (PWM) and / or a PAM block controlled by pulse amplitude modulation (PAM). The pixel circuit is driven by the PWM block and / or the PAM block to adjust the brightness of the light-emitting element.

[0003] However, in existing driving technologies, the design of display devices is more susceptible to insufficient charging rate, which can affect display quality.

[0004] Therefore, improving the charging efficiency of pixel circuits to enhance the display quality of images will be an important topic for those skilled in the art. Summary of the Invention

[0005] This invention provides a display device and its driving method, which can effectively improve the charging efficiency of pixel circuits to improve the display quality of the displayed image.

[0006] The display device of the present invention includes a display panel, a first gate driver, a second gate driver, a third gate driver, and a fourth gate driver. The display panel has a plurality of first pixel columns and a plurality of second pixel columns, which are arranged alternately. In a first time interval, the first gate driver sequentially drives the plurality of first pixel columns in a first driving mode. In a second time interval following the first time interval, the second gate driver sequentially drives the plurality of second pixel columns in the first driving mode. In a third time interval following the second time interval, the third gate driver sequentially drives the plurality of first pixel columns in a second driving mode. In a fourth time interval following the third time interval, the fourth gate driver sequentially drives the plurality of second pixel columns in the second driving mode. One of the first driving mode and the second driving mode is a pulse amplitude modulation (PAM) driving mode, and the other is a pulse width modulation (PWM) driving mode.

[0007] The driving method of the display device of the present invention includes: providing a display panel having a plurality of first pixel columns and a plurality of second pixel columns, wherein the plurality of first pixel columns and the plurality of second pixel columns are respectively arranged alternately; in a first time interval, providing a first gate driver to sequentially drive the plurality of first pixel columns in a first driving mode; in a second time interval after the first time interval, providing a second gate driver to sequentially drive the plurality of second pixel columns in a first driving mode; in a third time interval after the second time interval, providing a third gate driver to sequentially drive the plurality of first pixel columns in a second driving mode; and in a fourth time interval after the third time interval, providing a fourth gate driver to sequentially drive the plurality of second pixel columns in a second driving mode, wherein one of the first driving mode and the second driving mode is a pulse amplitude modulation (PAM) driving mode, and the other is a pulse width modulation (PWM) driving mode.

[0008] Based on the above, the display device and driving method of the present invention can sequentially drive the pixels of the first and second pixel columns in a first driving mode using the first and second gate drivers during the first and second time intervals. Furthermore, during the third and fourth time intervals, the display device can sequentially drive the pixels of the first and second pixel columns in a second driving mode using the third and fourth gate drivers. In this way, the display device of the present invention can effectively increase the charging time of the pixel circuit, thereby improving the charging efficiency of the pixel circuit and thus improving the display quality of the displayed image. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention;

[0010] Figure 2 This is the present invention. Figure 1 A schematic diagram of the pixel circuit in the embodiment;

[0011] Figures 3A to 3D These are the present inventions. Figure 1 A schematic diagram of the first to fourth gate drivers in the embodiment;

[0012] Figure 4 This is the present invention. Figure 1 Timing diagram of the display device in the embodiment;

[0013] Figures 5A to 5C These are the present inventions. Figure 1 A schematic diagram of three operating scenarios of the display device in the embodiment;

[0014] Figure 6This is a flowchart of a driving method for a display device according to an embodiment of the present invention.

[0015] Symbol Explanation

[0016] 100: Display device

[0017] 110: Display panel

[0018] 121_1, 121_2: First gate driver

[0019] 122_1, 122_2: Second gate drivers

[0020] 123_1, 123_2: Third gate driver

[0021] 124_1, 124_2: Fourth gate driver

[0022] 125_1, 125_2: Light-emitting circuits

[0023] 130: Source Driver

[0024] 200: Pixel Circuit

[0025] 210: PAM Block

[0026] 220: PWM block

[0027] 300, 310, 320, 330: Gate drivers

[0028] BLK: Vertical blanking time interval

[0029] DATA[1]~DATA[n]: Data voltage

[0030] EM[1]~EM[4]、EM[n]: Light emission control signals

[0031] P11~PN1, P12~PN2, P13~PN3, P14~PN4: pixels

[0032] PC1~PC4: Pixel Columns

[0033] STV1~STV4: Start Signal

[0034] SPAM[1]~SPAM

[11] 、SPAM[n]: PAM control signals

[0035] SPWM[1]~SPWM

[11] 、SPWM[n]: PWM control signals

[0036] SR11~SR112: Shift temporary storage circuit

[0037] S610~S650: Steps

[0038] TFR: Pixel Period

[0039] T1: First time interval

[0040] T2: Second time interval

[0041] T3: Third time interval

[0042] T4: Fourth Time Interval

[0043] VPAM1~VPAM4: PAM data voltage

[0044] VPWM1~VPWM4: PWM data voltage Detailed Implementation

[0045] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or some means of connection. Furthermore, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same reference numerals or the same terminology in different embodiments may be referred to mutually in the relevant descriptions.

[0046] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present invention. Please refer to... Figure 1 The display device 100 includes a display panel 110, first gate drivers 121_1, 121_2, second gate drivers 122_1, 122_2, third gate drivers 123_1, 123_2, fourth gate drivers 124_1, 124_2, light-emitting circuits 125_1, 125_2, and source driver 130.

[0047] In this embodiment, the display panel 110 includes a plurality of pixels (or pixel circuits) P11-PN1, P12-PN2, P13-PN3, and P14-PN4. These pixels P11-PN1, P12-PN2, P13-PN3, and P14-PN4 can be configured at the intersection of data lines and gate lines, and the operation of the pixel circuits can be controlled by the corresponding gate lines and data lines.

[0048] These pixels P11–PN1, P12–PN2, P13–PN3, and P14–PN4 can be arranged into multiple pixel columns PC1–PC4. For example, pixels P11–PN1 can be arranged into pixel column PC1; pixels P12–PN2 can be arranged into pixel column PC2; pixels P13–PN3 can be arranged into pixel column PC3; and pixels P14–PN4 can be arranged into pixel column PC4. These pixel columns PC1–PC4 can be arranged in an alternating pattern.

[0049] It should be noted that in this embodiment, pixel columns PC1 and PC3 can be odd-numbered pixel columns (i.e., the first pixel columns) of the display panel 110, while pixel columns PC2 and PC4 can be even-numbered pixel columns (i.e., the second pixel columns) of the display panel 110. In this embodiment of the invention, those skilled in the art can determine the number of pixels on the display panel 110 according to the design requirements of the display device 100; the invention is not limited to the numbers exemplified above. Here, N is a positive integer.

[0050] It is worth mentioning that for the descriptions of the pixels (or pixel circuits) P11~PN1, P12~PN2, P13~PN3, and P14~PN4 of the display panel 110, please also refer to... Figure 1 as well as Figure 2 , Figure 2 According to the present invention Figure 1 A schematic diagram of the pixel circuit in the embodiment. In this diagram, any one of the pixels (or pixel circuits) P11-PN1, P12-PN2, P13-PN3, and P14-PN4 of the display panel 110 can be... Figure 2 The pixel circuit 200 shown is used for implementation.

[0051] In this embodiment, the pixel circuit 200 may include a PAM block 210 and a PWM block 220. The PAM block 210 may include related electronic circuitry for implementing PAM control, while the PWM block 220 may include related electronic circuitry for implementing PWM control.

[0052] Specifically, the pixel circuit 200 can receive the PAM control signal SPAM[n] generated by the first gate drivers 121_1, 121_2 and / or the second gate drivers 122_1, 122_2 through the PAM block 210, and also receive the data voltage DATA[n] generated by the source driver 130.

[0053] Therefore, the first gate drivers 121_1, 121_2 and / or the second gate drivers 122_1, 122_2 can initiate the operation of the PAM block 210 of the pixel circuit 200 through the enabled PAM control signal SPAM[n], so as to perform PAM driving on the pixel circuit 200. At the same time, the source driver 130 can correspondingly write the data voltage DATA[n] into the pixel circuit 200.

[0054] On the other hand, the pixel circuit 200 can receive the PWM control signal SPWM[n] generated by the third gate driver 123_1, 123_2 and / or the fourth gate driver 124_1, 124_2 through the PWM block 220, and receive the data voltage DATA[n] generated by the source driver 130.

[0055] Therefore, the third gate drivers 123_1, 123_2 and / or the fourth gate drivers 124_1, 124_2 can activate the operation of the PWM block 220 of the pixel circuit 200 through the enabled PWM control signal SPWM[n], so as to drive the pixel circuit 200 with PWM. At the same time, the source driver 130 can correspondingly write the data voltage DATA[n] into the pixel circuit 200.

[0056] Furthermore, in this embodiment, the pixel circuit 200 can receive the light-emitting control signal EM[n] generated by the light-emitting circuits 125_1 and 125_2. Therefore, the pixel circuit 200 can illuminate the light-emitting element according to the enabled light-emitting control signal EM[n].

[0057] It is worth noting that this embodiment does not limit the implementation of the pixel circuit 200. For example, in some embodiments, the pixel circuit 200 may include a pixel circuit with a PAM block (or related circuits applying PAM driving) and a PWM block (or related circuits applying PWM driving), which are well known to those skilled in the art.

[0058] Please return to the reference. Figure 1 In this embodiment, the first gate driver 121_1, the second gate driver 122_1, the third gate driver 123_1, the fourth gate driver 124_1, and the light-emitting circuit 125_1 can be configured on the first side of the display panel 110 (such as the left side of the display panel 100), while the first gate driver 121_2, the second gate driver 122_2, the third gate driver 123_2, the fourth gate driver 124_2, and the light-emitting circuit 125_2 can be configured on the second side of the display panel 110 relative to the first side (such as the right side of the display panel 100). However, the present invention is not limited thereto.

[0059] In this embodiment, the first gate drivers 121_1 and 121_2 can be coupled to multiple pixels in the odd-numbered columns of the display panel 110 (that is, multiple pixels P11 to PN1 in the first pixel column PC1 and multiple pixels P13 to PN3 in the first pixel column PC3). The first gate drivers 121_1 and 121_2 can generate PAM control signals SPAM[1] and SPAM[3] to the corresponding multiple pixels P11 to PN1 in the first pixel column PC1 and multiple pixels P13 to PN3 in the first pixel column PC3 according to the start pulse signal.

[0060] In this case, the first gate drivers 121_1 and 121_2 can drive the corresponding pixels (or pixel circuits) in the first pixel column PC1 and / or the first pixel column PC3 in a PAM driving mode via the PAM control signal SPAM[1] and / or the PAM control signal SPAM[3].

[0061] On the other hand, the second gate drivers 122_1 and 122_2 can be coupled to multiple pixels in even-numbered columns of the display panel 110 (that is, multiple pixels P12 to PN2 in the second pixel column PC2 and multiple pixels P14 to PN4 in the second pixel column PC4). The second gate drivers 122_1 and 122_2 can generate PAM control signals SPAM[2] and SPAM[4] to the corresponding multiple pixels P12 to PN2 in the second pixel column PC2 and multiple pixels P14 to PN4 in the second pixel column PC4 according to the start signal.

[0062] In this case, the second gate drivers 122_1 and 122_2 can drive the corresponding pixels (or pixel circuits) in the second pixel column PC2 and / or the second pixel column PC4 in a PAM driving mode via the PAM control signal SPAM[2] and / or the PAM control signal SPAM[4].

[0063] On the other hand, the third gate drivers 123_1 and 123_2 can be coupled to multiple pixels in the odd-numbered columns of the display panel 110 (that is, multiple pixels P11 to PN1 in the first pixel column PC1 and multiple pixels P13 to PN3 in the first pixel column PC3). The third gate drivers 123_1 and 123_2 can generate PWM control signals SPWM[1] and SPWM[3] to the corresponding multiple pixels P11 to PN1 in the first pixel column PC1 and multiple pixels P13 to PN3 in the first pixel column PC3 according to the start signal.

[0064] In this case, the third gate drivers 123_1 and 123_2 can drive the corresponding pixels (or pixel circuits) in the first pixel column PC1 and / or the first pixel column PC3 in a PWM driving mode by using the PWM control signal SPWM[1] and / or the PWM control signal SPWM[3].

[0065] On the other hand, the fourth gate drivers 124_1 and 124_2 can be coupled to multiple pixels in even-numbered columns of the display panel 110 (that is, multiple pixels P12 to PN2 in the second pixel column PC2 and multiple pixels P14 to PN4 in the second pixel column PC4). The fourth gate drivers 124_1 and 124_2 can generate PWM control signals SPWM[2] and SPWM[4] to the corresponding multiple pixels P12 to PN2 in the second pixel column PC2 and multiple pixels P14 to PN4 in the second pixel column PC4 according to the start signal.

[0066] In this case, the fourth gate drivers 124_1 and 124_2 can drive the corresponding pixels (or pixel circuits) in the second pixel column PC2 and / or the second pixel column PC4 in a PWM driving mode via the PWM control signal SPWM[2] and / or the PWM control signal SPWM[4].

[0067] For implementation details of the first gate driver 121_1 (or 121_2), the second gate driver 122_1 (or 122_2), the third gate driver 123_1 (or 123_2), and the fourth gate driver 124_1 (or 124_2) in this embodiment, please refer to [the relevant documentation]. Figure 1 as well as Figures 3A to 3D , Figures 3A to 3D According to the present invention Figure 1 A schematic diagram of the first to fourth gate drivers in the embodiment.

[0068] Please refer to the following at the same time: Figure 1 as well as Figure 3A In this embodiment, the first gate driver 121_1 (or 121_2) can be derived from... Figure 3A The gate driver 300 shown is used for implementation.

[0069] In this embodiment, the gate driver 300 may include multiple shift register circuits (e.g., shift register circuits SR11, SR31, SR51, SR71, SR91, and SR111). These shift register circuits SR11, SR31, SR51, SR71, SR91, and SR111 may be connected in series with each other. The first-stage shift register circuit SR11 of the gate driver 300 may receive a start signal STV1. The shift register circuits SR11, SR31, SR51, SR71, SR91, and SR111 of the gate driver 300 may generate multiple PAM control signals (e.g., PAM control signals SPAM[1], SPAM[3], SPAM[5], SPAM[7], SPAM[9], and SPAM

[11] , etc.) that are sequentially enabled (e.g., low voltage level) according to the start signal STV1.

[0070] Please refer to the following at the same time: Figure 1 as well as Figure 3B In this embodiment, the second gate driver 122_1 (or 122_2) can be provided by Figure 3B The gate driver 310 shown is used for implementation.

[0071] In this embodiment, the gate driver 310 may include multiple shift register circuits (e.g., shift register circuits SR21, SR41, SR61, SR81, and SR101). These shift register circuits SR21, SR41, SR61, SR81, and SR101 may be connected in series with each other. The first-stage shift register circuit SR21 of the gate driver 310 may receive a start signal STV2. The shift register circuits SR21, SR41, SR61, SR81, and SR101 of the gate driver 310 may generate multiple PAM control signals (e.g., PAM control signals SPAM[2], SPAM[4], SPAM[6], SPAM[8], and SPAM

[10] , etc.) that are sequentially enabled (e.g., low voltage level) according to the start signal STV1.

[0072] Please refer to the following at the same time: Figure 1 as well as Figure 3C In this embodiment, the third gate driver 123_1 (or 123_2) can be... Figure 3C The gate driver 320 shown is used for implementation.

[0073] In this embodiment, the gate driver 320 may include multiple shift register circuits (e.g., shift register circuits SR12, SR32, SR52, SR72, SR92, and SR112). These shift register circuits SR12, SR32, SR52, SR72, SR92, and SR112 may be connected in series with each other. The first-stage shift register circuit SR12 of the gate driver 320 may receive a start signal STV3. The shift register circuits SR12, SR32, SR52, SR72, SR92, and SR112 of the gate driver 320 may generate multiple PWM control signals (e.g., PWM control signals SPWM[1], SPWM[3], SPWM[5], SPWM[7], SPWM[9], and SPWM

[11] , etc.) that are sequentially enabled (e.g., low voltage level) according to the start signal STV3.

[0074] Please refer to the following at the same time: Figure 1 as well as Figure 3D The fourth gate driver 124_1 (or 124_2) in this embodiment can be derived from... Figure 3D The gate driver 330 shown is used for implementation.

[0075] In this embodiment, the gate driver 330 may include multiple shift register circuits (e.g., shift register circuits SR22, SR42, SR62, SR82, and SR102). These shift register circuits SR22, SR42, SR62, SR82, and SR102 may be connected in series with each other. The first-stage shift register circuit SR22 of the gate driver 330 may receive a start signal STV4. The shift register circuits SR22, SR42, SR62, SR82, and SR102 of the gate driver 330 may generate multiple PWM control signals (e.g., PWM control signals SPWM[2], SPWM[4], SPWM[6], SPWM[8], and SPWM

[10] , etc.) that are sequentially enabled (e.g., low voltage level) according to the start signal STV4.

[0076] It should be noted that this embodiment does not limit the implementation of the gate drivers 300-330. For example, in some embodiments, each shift register circuit in the gate drivers 300-330 may include a shift register or shift register circuit well known to those skilled in the art, and the related operations of each element will not be described in detail here.

[0077] Please return to the reference. Figure 1In this embodiment, the light-emitting circuits 125_1 and 125_2 can be coupled to multiple pixels in the first pixel columns PC1 and PC3 and the second pixel columns PC2 and PC4 of the display panel 110. The light-emitting circuits 125_1 and 125_2 can generate multiple light-emitting control signals EM[1] to EM[4] to the corresponding first pixel columns PC1 and PC3 and the second pixel columns PC2 and PC4 to light up the corresponding pixels.

[0078] In another embodiment, the source driver 130 is coupled to the display panel 110. The source driver 130 can generate data voltages to a plurality of first pixel columns and / or second pixel columns according to the driving modes of the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver.

[0079] Figure 4 According to the present invention Figure 1 Timing diagram of the display device in the embodiment. Please refer to... Figure 4 In this embodiment, the time interval (TFR) of one pixel of the display device 100 can be divided into a first time interval T1, a second time interval T2, a third time interval T3, and a fourth time interval T4. The display device 100 can operate sequentially in the first time interval T1, the second time interval T2, the third time interval T3, and the fourth time interval T4, and the first time interval T1, the second time interval T2, the third time interval T3, and the fourth time interval T4 do not overlap with each other.

[0080] For implementation details of the display device 100, please also refer to... Figure 1 , Figure 2 as well as Figure 4 Specifically, during the first time interval T1, the first gate drivers 121_1 and 121_2 can generate sequentially enabled (e.g., low voltage level) PAM control signals SPAM[1] and SPAM[3] to PAM blocks of multiple pixels in odd-numbered columns of the display panel 110 (i.e., multiple pixels P11 to PN1 in the first pixel column PC1 and multiple pixels P13 to PN3 in the first pixel column PC3).

[0081] In this case, the first gate drivers 121_1 and 121_2 can sequentially drive the first pixel columns PC1 and PC3 (that is, the odd-numbered pixel columns of the display panel 110) in a PAM driving mode. Furthermore, the source driver 130 can sequentially write the corresponding data voltage DATA[n] (for example, the PAM data voltages VPAM1 and VPAM3 under the PAM driving of the first pixel columns PC1 and PC3 by the first gate drivers 121_1 and 121_2) into the pixels of these first pixel columns PC1 and PC3.

[0082] Then, in the second time interval T2 after the first time interval T1, the second gate drivers 122_1 and 122_2 can generate sequentially enabled (e.g., low voltage level) PAM control signals SPAM[2] and SPAM[4] to PAM blocks of multiple pixels in even-numbered columns of the display panel 110 (that is, multiple pixels P12 to PN2 in the second pixel column PC2 and multiple pixels P14 to PN4 in the second pixel column PC4).

[0083] In this case, the second gate drivers 122_1 and 122_2 can sequentially drive these second pixel columns PC2 and PC4 (that is, the even-numbered pixel columns of the display panel 110) in a PAM driving mode. Furthermore, the source driver 130 can sequentially write the corresponding data voltage DATA[n] (for example, the PAM data voltages VPAM2 and VPAM4 under the PAM driving of the second pixel columns PC2 and PC4 by the second gate drivers 122_1 and 122_2) into the pixels of these second pixel columns PC2 and PC4.

[0084] After the first gate drivers 121_1, 121_2 and the second gate drivers 122_1, 122_2 sequentially drive the first pixel columns PC1, PC3 and the second pixel columns PC2, PC4 in PAM driving mode, in the third time interval T3, the third gate drivers 123_1, 123_2 can generate sequentially enabled (e.g., low voltage level) PWM control signals SPWM[1], SPWM[3] to the PWM blocks of multiple pixels in the odd-numbered columns of the display panel 110 (that is, multiple pixels P11 to PN1 in the first pixel column PC1 and multiple pixels P13 to PN3 in the first pixel column PC3).

[0085] In this case, the third gate drivers 123_1 and 123_2 can sequentially drive the first pixel columns PC1 and PC3 (that is, the odd-numbered pixel columns of the display panel 110) in a PWM driving mode. Furthermore, the source driver 130 can sequentially write the corresponding data voltage DATA[n] (for example, the PWM data voltages VPWM1 and VPWM3 driven by the third gate drivers 123_1 and 123_2 in a PWM driving mode) into the pixels of the first pixel columns PC1 and PC3.

[0086] Next, in the fourth time interval T4 after the third time interval T3, the fourth gate drivers 124_1 and 124_2 can generate sequentially enabled (e.g., low voltage level) PWM control signals SPWM[2] and SPWM[4] to the PWM blocks of multiple pixels in the even-numbered columns of the display panel 110 (that is, multiple pixels P12 to PN2 in the second pixel column PC2 and multiple pixels P14 to PN4 in the second pixel column PC4).

[0087] In this case, the fourth gate drivers 124_1 and 124_2 can sequentially drive these second pixel columns PC2 and PC4 (that is, the even-numbered pixel columns of the display panel 110) in a PWM driving mode. Furthermore, the source driver 130 can sequentially write the corresponding data voltage DATA[n] (for example, the PWM data voltages VPWM2 and VPWM4 under the PWM driving of the second pixel columns PC2 and PC4 by the fourth gate drivers 124_1 and 124_2) into the pixels of these second pixel columns PC2 and PC4.

[0088] Based on the above description, it can be understood that under certain design requirements (in some embodiments), the display device 100 can first sequentially drive a plurality of odd-numbered pixel columns (i.e., the first pixel columns) of the display panel 110 in a PAM driving mode via the first gate drivers 121_1 and 121_2. Then, the display device 100 can further sequentially drive a plurality of even-numbered pixel columns (i.e., the second pixel columns) of the display panel 110 in a PAM driving mode via the second gate drivers 122_1 and 122_2.

[0089] After the first and second gate drivers have completed the operation of driving the first pixel column and the second pixel column in PAM driving mode, the display device 100 can then sequentially drive the multiple odd-numbered pixel columns (i.e., the first pixel column) of the display panel 110 in PWM driving mode through the third gate drivers 123_1 and 123_2.

[0090] Next, the display device 100 can sequentially drive multiple even-numbered pixel columns (i.e., second pixel columns) of the display panel 110 via fourth gate drivers 124_1 and 124_2 in a PWM driving mode to complete the data writing operations of pixels P11-PN1, P12-PN2, P13-PN3, and P14-PN4. Therefore, the display device 100 of this embodiment can effectively increase the charging time of the pixel circuit, thereby improving the charging efficiency of the pixel circuit and enhancing the display quality of the displayed image.

[0091] In other design requirements (in other embodiments), when the display device 100 operates in the first time interval T1, the display device 100 may first drive the multiple odd-numbered pixel columns (i.e., the first pixel columns) of the display panel 110 sequentially in a PWM driving mode via the third gate drivers 123_1 and 123_2. Then, the display device 100 may further drive the multiple even-numbered pixel columns (i.e., the second pixel columns) of the display panel 110 sequentially in a PWM driving mode via the fourth gate drivers 124_1 and 124_2.

[0092] Furthermore, after the third and fourth gate drivers have completed the operation of driving the first pixel column and the second pixel column in PWM driving mode, the display device 100 can then sequentially drive the multiple odd-numbered pixel columns (i.e., the first pixel column) of the display panel 110 in PAM driving mode through the first gate drivers 121_1 and 121_2.

[0093] Next, the display device 100 can sequentially drive multiple even-numbered pixel columns (i.e., second pixel columns) of the display panel 110 in PAM driving mode via the second gate drivers 122_1 and 122_2 to complete the data writing operation of pixels P11 to PN1, P12 to PN2, P13 to PN3, and P14 to PN4.

[0094] Figures 5A to 5C According to the present invention Figure 1 A schematic diagram illustrating three operating scenarios of the display device in this embodiment. (Continued here) Figure 4 Please refer to the description of the embodiments as well. Figure 1 , Figure 4 as well as Figures 5A to 5C In this embodiment, the TFR period of one pixel of the display device 100 may also include the vertical blanking time interval BLK.

[0095] Specifically, in Figure 5A In one embodiment, the display device 100 may begin sequentially driving multiple odd-numbered pixel columns (i.e., first pixel columns) and multiple even-numbered pixel columns (i.e., second pixel columns) of the display panel 110 in a PAM driving manner after the vertical blanking time interval BLK, via the first gate drivers 121_1, 121_2 and the second gate drivers 122_1, 122_2.

[0096] In other words, Figure 5A In the embodiments (same as or similar to) Figure 4In the embodiment, the first gate drivers 121_1, 121_2 and the second gate drivers 122_1, 122_2 can stop performing PAM driving mode on the pixel column during the vertical blanking time interval BLK.

[0097] On the other hand, Figure 5B In one embodiment, when the display device 100 operates in the vertical blanking time interval BLK, the display device 100 can start to sequentially drive the multiple odd-numbered pixel columns (i.e., the first pixel columns) and the multiple even-numbered pixel columns (i.e., the second pixel columns) of the display panel 110 in a PAM driving mode through the first gate drivers 121_1, 121_2 and the second gate drivers 122_1, 122_2.

[0098] In other words, Figure 5B In one embodiment, the first gate drivers 121_1, 121_2 and the second gate drivers 122_1, 122_2 can maintain the PAM driving mode for the pixel column during the vertical blanking time interval BLK.

[0099] On the other hand, Figure 5C In one embodiment, when the display device 100 operates in the vertical blanking time interval BLK, multiple shift storage circuits in the first gate drivers 121_1, 121_2 and the second gate drivers 122_1, 122_2 can generate simultaneously enabled PAM control signals to provide PAM control signals with fixed constants to the corresponding pixel columns.

[0100] After the display device 100 completes the vertical blanking time interval BLK operation, the display device 100 can then continue to drive the multiple odd-numbered pixel columns (i.e., the first pixel column) and multiple even-numbered pixel columns (i.e., the second pixel column) of the display panel 110 sequentially in PWM drive mode through the third gate driver 123_1, 123_2 and the fourth gate driver 124_1, 124_2.

[0101] Figure 6 This is a flowchart of a driving method for a display device according to an embodiment of the present invention. Please also refer to... Figure 1 as well as Figure 6 In step S610, the display device provides a display panel having a plurality of first pixel columns and a plurality of second pixel columns, wherein the plurality of first pixel columns and the plurality of second pixel columns are arranged alternately. In step S620, during a first time interval, the display device provides a first gate driver to sequentially drive the plurality of first pixel columns in a first driving manner.

[0102] In step S630, during a second time interval following the first time interval, the display device provides a second gate driver to sequentially drive a plurality of second pixel columns in a first driving mode. In step S640, during a third time interval following the second time interval, the display device provides a third gate driver to sequentially drive a plurality of first pixel columns in a second driving mode. In step S650, during a fourth time interval following the third time interval, the display device provides a fourth gate driver to sequentially drive a plurality of second pixel columns in a second driving mode.

[0103] The implementation details of each step are explained in detail in the foregoing embodiments and implementation methods, and will not be repeated hereafter.

[0104] In summary, the display device and driving method of the present invention can sequentially drive the pixels of the first and second pixel columns in a first driving mode via the first and second gate drivers during the first and second time intervals. Furthermore, during the third and fourth time intervals, the display device can sequentially drive the pixels of the first and second pixel columns in a second driving mode via the third and fourth gate drivers. In this way, the display device of the present invention can effectively increase the charging time of the pixel circuit, thereby improving the charging efficiency of the pixel circuit and thus improving the display quality of the displayed image.

Claims

1. A display device, comprising: The display panel has multiple first pixel columns and multiple second pixel columns, the first pixel columns and the second pixel columns being arranged alternately; A first gate driver sequentially drives the first pixel column in a first driving mode during a first time interval; The second gate driver sequentially drives the second pixel columns in the first driving manner during the second time interval following the first time interval; The third gate driver sequentially drives the first pixel columns in a second driving manner during a third time interval following the second time interval; and The fourth gate driver sequentially drives the second pixel columns in the second driving mode during the fourth time interval following the third time interval. The first, second, third, and fourth time intervals are four consecutive time intervals within the same pixel period that do not overlap with each other. One of the first driving methods and the second driving method is a pulse amplitude modulation (PAM) driving method, and the other is a pulse width modulation (PWM) driving method.

2. The display device of claim 1, wherein during the vertical blanking time interval, the first gate driver and the second gate driver maintain execution of the first driving mode.

3. The display device of claim 1, wherein during the vertical blanking time interval, the first gate driver and the second gate driver stop executing the first driving mode.

4. The display device as claimed in claim 1, wherein the display device further comprises: A source driver, coupled to the display panel, is used to provide multiple data voltages to multiple pixels in the first pixel column or multiple pixels in the second pixel column, depending on the type of the first driving mode or the second driving mode.

5. The display device of claim 1, wherein the first pixel columns are odd-numbered pixel columns of the display panel, and the second pixel columns are even-numbered pixel columns of the display panel.

6. A method for driving a display device, comprising: A display panel is provided having a plurality of first pixel columns and a plurality of second pixel columns, wherein the first pixel columns and the second pixel columns are respectively arranged alternately; During a first time interval, a first gate driver is provided to sequentially drive the first pixel columns in a first driving manner; In a second time interval following the first time interval, a second gate driver is provided to sequentially drive the second pixel columns in the first driving manner; In a third time interval following the second time interval, a third gate driver is provided to sequentially drive the first pixel columns in a second driving manner; and In the fourth time interval following the third time interval, a fourth gate driver is provided to sequentially drive the second pixel columns in the second driving manner. The first, second, third, and fourth time intervals are four consecutive time intervals within the same pixel period that do not overlap with each other. One of the first driving methods and the second driving method is a pulse amplitude modulation (PAM) driving method, and the other is a pulse width modulation (PWM) driving method.

7. The driving method as described in claim 6, further comprising: During the vertical blanking time interval, the first gate driver and the second gate driver continue to execute the first driving mode.

8. The driving method as described in claim 6, further comprising: During the vertical blanking time interval, the first gate driver and the second gate driver are stopped from executing the first driving mode.

9. The driving method as described in claim 6, further comprising: A source driver is provided to provide multiple data voltages to multiple pixels in the first pixel column or multiple pixels in the second pixel column, depending on the type of the first driving mode or the second driving mode.

10. The driving method of claim 6, wherein the first pixel columns are odd-numbered pixel columns of the display panel, and the second pixel columns are even-numbered pixel columns of the display panel.

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