Multi-core heterogeneous systems, chips, display systems, and vehicles

Abstract

The application provides a multi-core heterogeneous system, a chip, a display system and a vehicle. The multi-core heterogeneous system comprises a target hardware domain, and the target hardware domain comprises a first display controller, a second display controller and a display multiplexer. The display multiplexer is configured to control a first splitting unit to be connected with a first output terminal group and a second splitting unit to be connected with a second output terminal group; perform time synchronization on a first display signal based on a first clock signal through a first clock circuit, and perform time synchronization on a second display based on the first clock signal through a second clock circuit; and synchronously transmit the time-synchronized first display signal and the second display signal to a target display screen through the first output terminal group and the second output terminal group of an output interface. In this way, the first display content and the second display content can be displayed in a synchronous refreshing and seamless connection manner in different display regions of the same display screen.

Description

Technical Field

[0001] This application relates to the field of display control technology, and in particular to a multi-core heterogeneous system, chip, display system and vehicle. Background Technology

[0002] To enhance the intelligence and technological feel of the cockpit, many vehicles choose to integrate multiple independent displays in front of the cockpit into one large display, replacing the multiple independent displays in the previous model. The large display extends horizontally in front of the cockpit and displays different interfaces in different display areas.

[0003] Currently, there are two main solutions. One solution uses a single, large-size display screen to receive multiple display images from different systems, combining them into a single image before sending it to the large screen for display. This solution requires splicing the display images, resulting in high system resource utilization and potentially affecting display smoothness. The other solution physically splices multiple displays to form a single, large-size display screen. However, these are actually multiple independent displays, each controlled by a different system. Black borders exist at the junctions between adjacent displays, impacting the user's viewing experience. Summary of the Invention

[0004] In view of the above-mentioned problems existing in the prior art, this application provides a multi-core heterogeneous system, chip, display system and vehicle. The technical solutions adopted in the embodiments of this application are as follows.

[0005] The first aspect of this application provides a multi-core heterogeneous system, including a target hardware domain, the target hardware domain including a first display controller, a second display controller and a display multiplexer;

[0006] The display multiplexer includes a first splitting unit, a second splitting unit, a first clock circuit, a second clock circuit, and an output interface; the first splitting unit is connected to the first display controller, and the second splitting unit is connected to the second display controller; the output interface includes a first output terminal group and a second output terminal group, and the output interface is used to connect to a target display screen, the target display screen having a first display area and a second display area capable of independently outputting display content;

[0007] The display multiplexer is used for:

[0008] Control the first splitting unit to connect to the first output terminal group, and control the second splitting unit to connect to the second output terminal group;

[0009] The first display signal is received from the first display controller through the first splitting unit, and the second display signal is received from the second display controller through the second splitting unit;

[0010] The first clock circuit synchronizes the first display signal with time based on the first clock signal, and the second clock circuit synchronizes the second display signal with time based on the first clock signal.

[0011] The first and second display signals, synchronized by time, are transmitted synchronously to the target display screen through the first and second output terminal groups of the output interface; wherein, the first display signal is used to display the first display content in the first display area, and the second display signal is used to display the second display content in the second display area in sync with the first display content.

[0012] In some embodiments, the display multiplexer is further configured to:

[0013] The first splitting unit is connected to the first output terminal group and the second output terminal group respectively;

[0014] The first display signal is received from the first display controller through the first splitting unit, and the first display signal is split into two first display signals.

[0015] The first clock circuit and the second clock circuit synchronize based on the first clock signal to synchronize the time of the two first display signals respectively;

[0016] The first output terminal group and the second output terminal group of the output interface synchronously transmit the two time-synchronized first display signals to the target display screen; wherein, the two time-synchronized first display signals are used to synchronously display the first display content in the first display area and the second display area of ​​the target display screen.

[0017] In some embodiments, the display multiplexer further includes a first selection circuit and a second selection circuit;

[0018] The two sets of input terminals of the first selection circuit are respectively connected to the first splitting unit and the second splitting unit, and the output terminal of the first selection circuit is connected to the first output terminal group through the first clock circuit. The first selection circuit is used to: select one of the first splitting unit and the second splitting unit to be connected to the first clock circuit.

[0019] The two sets of input terminals of the second selection circuit are respectively connected to the first splitting unit and the second splitting unit. The output terminal of the second selection circuit is connected to the second output terminal group through the second clock circuit. The first selection circuit is used to select one of the first splitting unit and the second splitting unit to be connected to the second clock circuit.

[0020] In some embodiments, the display multiplexer includes a first register corresponding to the first selection circuit and a second register corresponding to the second selection circuit;

[0021] The first selection circuit is specifically used to: select one of the first split unit and the second split unit to be connected to the first clock circuit based on the first identifier or the second identifier added to the first register; wherein, the first identifier is used to identify the first split unit, and the second identifier is used to identify the second split unit;

[0022] The second selection circuit is specifically used to: select one of the first split unit and the second split unit to connect to the second clock circuit based on the first identifier or the second identifier added to the second register.

[0023] In some embodiments, the multi-core heterogeneous system further includes a first hardware domain and a second hardware domain;

[0024] The first display controller is connected to the first hardware domain, and the first display controller is specifically used to: obtain a first display signal that matches the first display area based on the first display data received from the first hardware domain;

[0025] The second display controller is connected to the second hardware domain, and the second display controller is specifically used to: obtain a second display signal that matches the second display area based on the second display data received from the second hardware domain.

[0026] In some embodiments, the first display controller is specifically configured to: acquire first display data; process the first display data based on the first clock signal to acquire the first display signal having a first refresh frequency; and / or

[0027] The second display controller is specifically used to: acquire second display data, process the second display data based on the first clock signal, and acquire the second display signal having a first refresh frequency.

[0028] In some embodiments, the first hardware domain includes a first display processor connected to the first display controller, the first display processor being configured to send the first display data to the first display controller;

[0029] The second hardware domain includes a second display processor connected to the second display controller, the second display processor being used to send the second display data to the second display controller.

[0030] In some embodiments, the multi-core heterogeneous system further includes a first hardware domain, which is connected to the first display controller and the second display controller respectively, and the first hardware domain is used for:

[0031] Obtain target display data that can output the target display content;

[0032] Based on the target display data, obtain first display data that matches the first display area and second display data that matches the second display area;

[0033] The first display data is transmitted to the first display controller, so that the first display controller generates a first display signal based on the first display data.

[0034] The second display data is transmitted to the second display controller, so that the second display controller generates a second display signal based on the second display data.

[0035] A second aspect of this application provides a chip including the multi-core heterogeneous system described above.

[0036] A third aspect of this application provides a display system, including the chip described above, and a target display screen, the target display screen including a display panel, a first timing controller and a second timing controller, the display panel having a first display area and a second display area;

[0037] The first timing controller is connected to the first output terminal group of the output interface. The first timing controller is used to control the first display area to output the first display content based on the first display signal after time synchronization.

[0038] The second timing controller is connected to the second output terminal group of the output interface. The second timing controller is used to control the second display area to output the second display content in sync with the first display content based on the second display signal after time synchronization.

[0039] A fourth aspect of this application provides a vehicle including the display system described above.

[0040] The multi-core heterogeneous system of this application embodiment does not require image stitching. It can achieve the purpose of displaying the first display content and the second display content in a synchronous and seamless manner in different display areas of the same display screen, which can form a better display effect. Moreover, the control logic is simple, which helps to reduce the difficulty of software development and the utilization rate of system resources. Attached Figure Description

[0041] Figure 1 This is a structural block diagram of a first embodiment of the multi-core heterogeneous system of this application.

[0042] Figure 2 This is a schematic diagram of one embodiment of the display multiplexer of this application.

[0043] Figure 3 This is a schematic diagram of another embodiment of the display multiplexer of this application.

[0044] Figure 4 This is a structural block diagram of a second embodiment of the multi-core heterogeneous system of this application.

[0045] Figure 5 This is a structural block diagram of a third embodiment of the multi-core heterogeneous system of this application.

[0046] Figure 6 This is a structural block diagram of the display system of this application. Detailed Implementation

[0047] Various embodiments and features of this application are described herein with reference to the accompanying drawings.

[0048] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.

[0049] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0050] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0051] It should also be understood that although this application has been described with reference to some specific examples, many other equivalent forms that can be definitively implemented by those skilled in the art should be considered to be within the scope of protection defined by this application.

[0052] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0053] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.

[0054] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.

[0055] This application provides a multi-core heterogeneous system 200. Figure 1 This is a structural block diagram of a first embodiment of the multi-core heterogeneous system 200 of this application. Figure 2 This is a schematic diagram of one embodiment of the display multiplexer 203 of this application. See also... Figure 1 and Figure 2 As shown, the multi-core heterogeneous system 200 of this application embodiment may include a target hardware domain 210, which includes a first display controller 201, a second display controller 202 and a display multiplexer 203.

[0056] The display multiplexer 203 includes a first splitting unit 204, a second splitting unit 205, a first clock circuit 206, a second clock circuit 207, and an output interface 208. The first splitting unit 204 is connected to the first display controller 201, and the second splitting unit 205 is connected to the second display controller 202. The output interface 208 includes a first output terminal group 209 and a second output terminal group 211, and is used to connect to the target display screen 100. The target display screen 100 has a first display area 101 and a second display area 102 capable of independently outputting display content.

[0057] The display multiplexer 203 is used to: control the connection of the first splitting unit 204 to the first output terminal group 209, and control the connection of the second splitting unit 205 to the second output terminal group 211; receive a first display signal from the first display controller 201 through the first splitting unit 204, and receive a second display signal from the second display controller 202 through the second splitting unit 205; synchronize the first display signal based on the first clock signal through the first clock circuit 206, and synchronize the second display signal based on the first clock signal through the second clock circuit 207; and synchronously transmit the time-synchronized first display signal and the time-synchronized second display signal to the target display screen 100 through the first output terminal group 209 and the second output terminal group 211 of the output interface 208, respectively; wherein, the first display signal is used to display the first display content in the first display area 101, and the second display signal is used to display the second display content in the second display area 102 in sync with the first display content.

[0058] Optionally, the target hardware domain 210 may acquire a first control command to instruct the multi-core heterogeneous system 200 to switch to a first display mode. In response to the first control command, the target hardware domain 210 may control the connection of the first splitting unit 204 to the first output group 209 via the display multiplexer 203, and control the connection of the second splitting unit 205 to the second output group 211, thereby causing the first display area 101 to display first display content, and causing the second display area 102 to display second display content in a synchronized manner with the first display content.

[0059] Optionally, the target hardware domain 210 may also, when determining that the multi-core heterogeneous system 200 is in the first display mode, control the connection of the first split unit 204 to the first output group 209 and the connection of the second split unit 205 to the second output group 211 via the display multiplexer 203. For example, in the initial state, the multi-core heterogeneous system 200 may default to the first display mode.

[0060] Optionally, the first display controller 201 can be configured to output the first display signal based on display data acquired from the target hardware domain 210. Alternatively, the first display controller 201 can be configured to output the first display signal based on display data acquired from other hardware domains in the multi-core heterogeneous system 200. Similarly, the second display controller 202 can be configured to output the second display signal based on display data acquired from the target hardware domain 210. Alternatively, the second display controller 202 can be configured to output the second display signal based on display data received from other hardware domains in the multi-core heterogeneous system 200.

[0061] Optionally, the multi-core heterogeneous system 200 may be provided with a clock unit 240 for generating clock signals. The target hardware domain 210 may be configured to, when the multi-core heterogeneous system 200 is in a first display mode, control both the first clock circuit 206 and the second clock circuit 207 to be connected to the clock unit 240, respectively receiving a first clock signal with the same frequency and phase from the clock unit 240. By synchronizing the first display signal based on the first clock signal using the first clock circuit 206, and synchronizing the second display signal based on the second clock signal using the second clock circuit 207, the first and second display signals can have the same frequency and phase, thereby ensuring that the first display area 101 and the second display area 102 refresh their display content synchronously.

[0062] Optionally, the first output terminal group 209 and the second output terminal group 211 may include one or more output terminals, which can be determined according to the communication protocol adopted. Optionally, the target display screen 100 may adopt a MIPI display serial interface, an LVDS display serial interface (Low-Voltage Differential Signaling), a parallel port, etc. Correspondingly, the output interface 208 may also adopt a MIPI display serial interface, an LVDS display serial interface (Low-Voltage Differential Signaling), a parallel port, etc. Taking the output interface 208 as an example of adopting an LVDS interface, both the first output terminal group 209 and the second output terminal group 211 may include ten output terminals, so that the first output terminal group 209 and the second output terminal group 211 can output four display signals and one clock signal through their respective ten output terminals.

[0063] Optionally, the output interface 208 can be connected to the target display screen 100 via the display interface of the multi-core heterogeneous system 200. For example, the display interface may have a first display terminal group and a second display terminal group, with the first output terminal group 209 connected via the first display terminal group and the second output terminal group 211 connected to the second display terminal group. Alternatively, the target display screen 100 may have multiple display interfaces, with the first output terminal group 209 connected to the first display interface of the target display screen 100 and the second output terminal group 211 connected to the second display interface of the target display screen 100.

[0064] It should be noted that the output interface 208 can be connected to the target display screen 100 in various ways, and the connection method between the output interface 208 and the target display screen 100 is not limited here. As long as a display signal transmission path can be formed between the first output terminal group 209 and the target display screen 100, and another display signal transmission path can be formed between the second output terminal group 211 and the target display screen 100, and the first and second display signals can be synchronously transmitted to the target display screen 100 through the two display signal transmission paths, it is acceptable.

[0065] Optionally, the target display screen 100 may have a single timing controller, which may be connected to the first output group 209 and the second output group 211 respectively. The timing controller may be configured to control the first display area 101 to display first display content and control the second display area 102 to synchronously display second display content based on the first display signal and the second display signal.

[0066] Optionally, the target display screen 100 may also have a first timing controller 103 and a second timing controller 104. The first timing controller 103 may be connected to the first output terminal group 209, and the second timing controller 104 may be connected to the second output terminal group 211. The first timing controller 103 may be configured to control the first display area 101 to display first display content based on a first display signal. The second timing controller 104 may be configured to control the second display area 102 to display second display content based on a second display signal.

[0067] Optionally, the first display area 101 and the second display area 102 may be arranged horizontally or vertically. The first display area 101 and the second display area 102 may have the same resolution or different resolutions. Similarly, the first display area 101 and the second display area 102 may have the same size or different sizes.

[0068] Optionally, the target display screen 100 is not limited to including two display areas capable of independently outputting display content, but may also include two or more display areas capable of independently outputting display content. The first display area 101 and the second display area 102 can be any two of these two or more display areas. For example, the target display screen 100 may include three display areas arranged sequentially along the horizontal direction. Another example is that the target display screen 100 may include four display areas arranged in a grid pattern. Based on this, the target hardware domain 210 is not limited to including two display controllers; the display multiplexer 203 may also include a third splitting unit, a fourth splitting unit, a third clock circuit, a fourth clock circuit, a third output group, a fourth output group, etc., thereby enabling the synchronous output of display content by multiple display areas of the target display screen 100.

[0069] Optionally, the first display content and the second display content can be matched to form a target display content. For example, the target display screen 100 can be a vehicle's cockpit display screen, extending laterally along the center of the cockpit to the front of the passenger seat. The target display screen 100 may include a first display area 101 located in the center of the cockpit and a second display area 102 located in front of the passenger seat. The central control interface can be displayed through the first display area 101, and the entertainment interface can be displayed through the second display area 102. The central control interface and the entertainment interface can adopt an integrated interface design, thereby jointly forming the display interface of the target display screen 100.

[0070] Of course, the target display content may also include a portion of the display interface of the target display screen 100. For example, the target display screen 100 may extend from in front of the driver along the flight path to in front of the co-driver, spanning the entire cockpit. The target display screen 100 may include a first display area 101 for displaying the instrument panel interface, a second display area 102 for displaying the central control interface, and a third display area for displaying the entertainment interface. The instrument panel interface and the central control interface together constitute a portion of the display interface of the target display screen 100.

[0071] It is understood that the display multiplexer 203 can also control the connection between the first splitting unit 204 and the second output group 211, and control the connection between the second splitting unit 205 and the first output group 209, thereby switching the display signal transmission path. In this way, the first display area 101 can be controlled to display the second display content, and the second display area 102 can be controlled to display the first display content, achieving the purpose of switching display content.

[0072] For example, still taking the multi-core heterogeneous system 200 applied to a vehicle, the first display area 101 can be located near the driver, and the second display area 102 can be located near the passenger side. In the initial state, the central control interface can be displayed through the first display area 101, and the application interface can be displayed through the second display area 102. If navigation needs to be activated during driving, the multi-core heterogeneous system 200 can switch to the second display mode. The display multiplexer 203, in response to the multi-core heterogeneous system 200 switching to the second display mode, controls the first splitting unit 204 to connect to the second output terminal group 211, and controls the second splitting unit 205 to connect to the first output terminal group 209. This switches the navigation interface to the first display area 101 near the driver and the central control interface to the second display area 102 near the passenger side, allowing for simultaneous and synchronized display of both the navigation and central control interfaces, and facilitating convenient access to navigation information for the driver.

[0073] The multi-core heterogeneous system 200 of this application embodiment can connect the first display controller 201 and the second display controller to the target display screen 100 simultaneously through the display multiplexer 203, forming two independent display signal transmission paths. The first display signal and the second display signal are synchronized based on the same clock signal by the first clock circuit 206 and the second clock circuit 207, resulting in first and second display signals with the same frequency and phase. By transmitting the first and second display signals with the same frequency and phase to the target display screen 100 through the two display signal transmission paths, the first display area 101 and the second display area 102 of the target display screen 100 can synchronously display the first and second display contents. The mutually matched and synchronously refreshed first and second display contents can be seamlessly connected to form the target display content. Thus, without image stitching, the purpose of displaying the first and second display contents in a synchronously refreshed and seamless manner in different display areas of the same display screen can be achieved, resulting in a better display effect. Furthermore, the control logic is simple, which helps reduce software development difficulty and improve system resource utilization.

[0074] In some embodiments, the display multiplexer 203 is further configured to: control the first splitting unit 204 to connect to the first output group 209 and the second output group 211 respectively. The first splitting unit 204 receives a first display signal from the first display controller 201 and splits the first display signal into two first display signals. The first clock circuit 206 and the second clock circuit 207 synchronize the two first display signals based on the first clock signal. The two time-synchronized first display signals are synchronously transmitted to the target display screen 100 through the output interface 208. These two time-synchronized first display signals are used to synchronously display first display content in the first display area 101 and the second display area 102 of the target display screen 100.

[0075] Thus, the target display screen 100 can simultaneously display the first display content through the first display area 101 and the second display area 102 based on the first display signal after the two time synchronizations, thereby achieving the purpose of displaying the same display content in the two display areas, improving the diversity and flexibility of content display of the target display screen 100, and helping to improve the user experience.

[0076] Optionally, the target hardware domain 210 may, in response to the multi-core heterogeneous system 200 being in a third display mode, control the first split unit 204 to connect to the first output terminal group 209 and the second output terminal group 211 respectively, thereby enabling the two display areas to display the same display content.

[0077] For example, taking the multi-core heterogeneous system 200 applied to a vehicle, the target display screen 100 can extend from the center of the cockpit to in front of the passenger seat. The first display area 101 can be located in the center of the cockpit, and the second display area 102 can be located in front of the passenger seat. When the driver needs to activate navigation in the first display area 101 or adjust the navigation route displayed in the first display area 101, but is unable to operate due to traffic conditions, a third display mode can be activated, so that the first display area 101 and the second display area 102 display the same content. At this time, the passenger in the front seat can operate the second display area 102 to activate the navigation interface or adjust the navigation route, and the corresponding first display area 101 will also activate the navigation interface or adjust the navigation route simultaneously, which can significantly improve the vehicle's operability and intelligence level.

[0078] In some embodiments, the display multiplexer 203 further includes a first selection circuit 212 and a second selection circuit 213.

[0079] The two sets of input terminals of the first selection circuit 212 are respectively connected to the first splitting unit 204 and the second splitting unit 205, and the output terminal of the first selection circuit 212 is connected to the first output terminal group 209 through the first clock circuit 206. The first selection circuit 212 is used to select one of the first splitting unit 204 and the second splitting unit 205 to be connected to the first clock circuit 206.

[0080] The two sets of input terminals of the second selection circuit 213 are respectively connected to the first splitting unit 204 and the second splitting unit 205, and the output terminal of the second selection circuit 213 is connected to the second output terminal group 211 through the second clock circuit 207. The first selection circuit 212 is used to select one of the first splitting unit 204 and the second splitting unit 205 to be connected to the second clock circuit 207.

[0081] When the multi-core heterogeneous system 200 is in the first display mode, the first selection circuit 212 can connect the first splitting unit 204 and the first clock circuit 206, and the second selection circuit 213 can connect the second splitting unit 205 and the second clock circuit 207. Thus, the first display area 101 displays the first display content, and the second display area 102 synchronously displays the second display content.

[0082] When the multi-core heterogeneous system 200 is in the second display mode, the first selection circuit 212 can connect the second splitting unit 205 and the first clock circuit 206, and the second selection circuit 213 can connect the first splitting unit 204 and the second clock circuit 207. Thus, the first display area 101 displays the second display content, and the second display area 102 displays the first display content.

[0083] When the multi-core heterogeneous system 200 is in the third display mode, the first selection circuit 212 can connect the first splitting unit 204 and the first clock circuit 206, and the second selection circuit 213 can connect the first splitting unit 204 and the second clock circuit 207. Thus, the first display area 101 and the second display area 102 can synchronously display the first display content.

[0084] The multi-core heterogeneous system 200 may further include a fourth display mode. When the multi-core heterogeneous system 200 is in the fourth display mode, the first selection circuit 212 can be connected to the second splitting unit 205 and the first clock circuit 206, and the second selection circuit 213 can be connected to the second splitting unit 205 and the second clock circuit 207. In this way, the first display area 101 and the second display area 102 can synchronously display the second display content.

[0085] As can be seen, the display signal transmission path can be easily adjusted through the first selection circuit 212 and the second selection circuit 213, thereby adjusting the display effect of the target display screen 100. The control logic is simple, which helps to reduce the difficulty of software development and the utilization rate of system resources.

[0086] It is understood that the display multiplexer 203 is not limited to including two selection circuits, but may also include three, four or more selection circuits. Each selection circuit is also not limited to including two sets of input terminals. When the display multiplexer 203 includes two or more split units and the target display screen 100 includes two or more display areas, the selection circuit may include two or more sets of input terminals corresponding one-to-one with the split units.

[0087] In some embodiments, the display multiplexer 203 includes a first register corresponding to the first selection circuit 212 and a second register corresponding to the second selection circuit 213.

[0088] The first selection circuit 212 is specifically used to: select one of the first splitting unit 204 and the second splitting unit 205 to connect to the first clock circuit 206 based on the first identifier or the second identifier added to the first register.

[0089] The second selection circuit 213 is specifically used to: select one of the first splitting unit 204 and the second splitting unit 205 to connect to the second clock circuit 207 based on the first identifier or the second identifier added to the second register. The first identifier is used to identify the first splitting unit 204, and the second identifier is used to identify the second splitting unit 205.

[0090] When the multi-core heterogeneous system 200 is in the first display mode, the first identifier can be added to the first register, and the second identifier can be added to the second register.

[0091] When the multi-core heterogeneous system 200 is in the second display mode, the first identifier can be added to the second register, and the second identifier can be added to the first register.

[0092] When the multi-core heterogeneous system 200 is in the third display mode, the first identifier can be added to the first register and the second register respectively.

[0093] When the multi-core heterogeneous system 200 is in the fourth display mode, the second identifier can be added to the first register and the second register respectively.

[0094] Similarly, when the target display screen 100 has two or more display areas, the display multiplexer 203 may have two or more selection circuits and multiple registers corresponding to the selection circuits. The display signal transmission path can also be adjusted by adding identifiers to the registers, thereby adjusting the display content of each display area of ​​the target display screen 100.

[0095] By using registers to control the connection method of the selection circuit, and thus control the display signal transmission path, the control logic is not only simple and easy to implement, but also highly flexible.

[0096] It is understood that the first identifier and the second identifier may include various information that can identify the first splitting unit 204 and the second splitting unit 205, and the content of the first identifier and the second identifier is not limited here.

[0097] For example, the output terminal of the first splitting unit 204 may include two output terminals, and the output terminal of the second splitting unit 205 may also include two input terminals. The first selection circuit 212 may have two sets of input terminals, and the two sets of input terminals of the first selection circuit 212 are respectively connected to the output terminals of the first splitting unit 204 and the second splitting unit 205. The second selection circuit 213 may also have two sets of input terminals, and the two sets of input terminals of the second selection circuit 213 may also be respectively connected to the output terminals of the first splitting unit 204 and the second splitting unit 205.

[0098] The output terminals of the first splitting unit 204 and the second splitting unit 205 can be uniformly numbered. For example, the four output terminals can be numbered "0", "1", "2", and "3" respectively. Based on this, the number of the first output terminal among the output terminals of the first splitting unit 204 and the second splitting unit 205 can be used as an identifier. Specifically, "0" can be used as the first identifier, and "2" can be used as the second identifier. When "0" is added to the first register and "2" is added to the second register, the first splitting unit 204 is connected to the first selection circuit 212, and the second splitting unit 205 is connected to the second selection circuit 213, such as... Figure 3 As shown, and so on.

[0099] It should be noted that the first splitting unit 204 is not limited to being connected to the first clock circuit 206 via the first selection circuit 212, and the second splitting unit 205 is not limited to being connected to the second clock circuit 207 via the second selection circuit 213. In practical applications, the display multiplexer 203 may not include the first selection circuit 212 and the second selection circuit 213. For example, the first splitting unit 204 may be connected to both the first clock circuit 206 and the second clock circuit 207, and the first splitting unit 204 may be configured to selectively activate either one, thereby adjusting the display signal transmission path. Similarly, the second splitting unit 205 may also be connected to both the first clock circuit 206 and the second clock circuit 207, and the second splitting unit 205 may be configured to selectively activate either one, thereby adjusting the display signal transmission path.

[0100] Cooperate Figure 4 As shown, in some embodiments, the multi-core heterogeneous system 200 further includes a first hardware domain 220, which is connected to the first display controller 201 and the second display controller 202, respectively. The first hardware domain 220 is used to: acquire target display data capable of outputting target display content; based on the target display data, acquire first display data matching the first display area 101 and second display data matching the second display area 102; transmit the first display data to the first display controller 201 so that the first display controller 201 generates a first display signal based on the first display data; and transmit the second display data to the second display controller 202 so that the second display controller 202 generates a second display signal based on the second display data.

[0101] For example, the target display data can be generated through a first display process in the first hardware domain 220. The first hardware domain 220 may include a first display processor 221, which may be connected to the first display controller 201 and the second display controller 202, respectively. The first display processor 221 may, based on the display parameters of the first display area 101 and the second display area 102, divide the target display data into first display data and second display data. Then, the first display data and the second display data are transmitted to the first display controller 201 and the second display controller 202, respectively. The display parameters include, but are not limited to, resolution, size, etc.

[0102] Cooperate Figure 5As shown, in some embodiments, the multi-core heterogeneous system 200 further includes a first hardware domain 220 and a second hardware domain 230. The first display controller 201 is connected to the first hardware domain 220. Specifically, the first display controller 201 is used to: acquire a first display signal matching the first display area 101 based on first display data received from the first hardware domain 220. The second display controller 202 is connected to the second hardware domain 230. Specifically, the second display controller 202 is used to: acquire a second display signal matching the second display area 102 based on second display data received from the second hardware domain 230. Thus, by generating display data through the first hardware domain 220 and the second hardware domain 230, and with the target hardware domain 210 responsible for switching the display signal transmission path, this reasonable functional division not only improves data processing efficiency but also increases response speed, thus contributing to maintaining system smoothness.

[0103] Optionally, the first display controller 201 is specifically configured to: acquire first display data; process the first display data based on the first clock signal to acquire the first display signal having a first refresh rate. The second display controller 202 is specifically configured to: acquire second display data; process the second display data based on the first clock signal to acquire the second display signal having a first refresh rate.

[0104] Optionally, the first hardware domain 220 includes a first display processor 221 connected to the first display controller 201, the first display processor 221 being used to send the first display data to the first display controller 201. The second hardware domain 230 includes a second display processor 231 connected to the second display controller 202, the second display processor 231 being used to send the second display data to the second display controller 202.

[0105] For example, display data for forming the first display content can be generated by a first display process running in the operating system of the first hardware domain 220. The first display processor 221 can process the display data for forming the first display content based on the display parameters of the first display area 101 to obtain first display data adapted to the first display area 101.

[0106] Similarly, display data for forming the second display content can be generated by a second display process running in the operating system of the second hardware domain 230. The second display processor 231 can process the display data for forming the second display content based on the display parameters of the second display area 102 to obtain second display data adapted to the second display area 102.

[0107] This application provides a chip 300, including the multi-core heterogeneous system 200 as described in any one or more of the above embodiments.

[0108] See Figure 6 As shown, this application embodiment provides a display system including a target display screen 100 and a chip 300 as described above. The target display screen 100 includes a display panel, a first timing controller 103 and a second timing controller 104, and the display panel has a first display area 101 and a second display area 102.

[0109] The first timing controller 103 is connected to the first output terminal group 209 of the output interface 208. The first timing controller 103 is used to control the first display area 101 to output the first display content based on the first display signal after time synchronization.

[0110] The second timing controller 104 is connected to the second output terminal group 211 of the output interface 208. The second timing controller 104 is used to control the second display area 102 to output the second display content in sync with the first display content based on the second display signal after time synchronization.

[0111] Optionally, the first display area 101 and the second display area 102 may be arranged horizontally or vertically. The first display area 101 and the second display area 102 may have the same resolution or different resolutions. Similarly, the first display area 101 and the second display area 102 may have the same size or different sizes.

[0112] Optionally, the target display screen 100 is not limited to including two display areas capable of independently outputting display content, but may also include two or more display areas capable of independently outputting display content. Based on this, the first display area 101 and the second display area 102 can be any two of these two or more display areas. For example, the target display screen 100 may include three display areas arranged sequentially along a horizontal direction. As another example, the target display screen 100 may include four display areas arranged in a grid pattern.

[0113] This application also provides a vehicle including the display system described in any one or more of the above embodiments. Specifically, the vehicle may include the chip 300 and the target display screen 100 as described above. Optionally, the target display screen 100 may be disposed in the instrument panel area of ​​the cockpit. For example, the target display screen 100 may extend from in front of the driver to the center of the cockpit, or from the center of the cockpit to in front of the passenger seat, or from in front of the driver to in front of the passenger seat. Optionally, the target display screen 100 may also be a windshield display screen, a rearview mirror display screen, or a display screen in front of the rear seats, etc.

[0114] Optionally, the vehicle in this application embodiment can be "automobile," "vehicle," or "complete vehicle," or other similar terms, including general motor vehicles such as sedans, SUVs, MPVs, buses, trucks, and other freight or passenger vehicles, water transport vehicles including various ships and boats, and aircraft, including hybrid vehicles, electric vehicles, gasoline vehicles, plug-in hybrid vehicles, fuel cell vehicles, and other alternative fuel vehicles. Hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles, range-extended electric vehicles, etc., which are not specifically limited in this application.

[0115] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. The scope of protection of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this application within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.

Claims

1. A multi-core heterogeneous system, characterized in that, The target hardware domain includes a first display controller, a second display controller, and a display multiplexer. The display multiplexer includes a first splitting unit, a second splitting unit, a first clock circuit, a second clock circuit, and an output interface; the first splitting unit is connected to the first display controller, and the second splitting unit is connected to the second display controller; the output interface includes a first output terminal group and a second output terminal group, and the output interface is used to connect to a target display screen, the target display screen having a first display area and a second display area capable of independently outputting display content; The display multiplexer is used for: Control the first splitting unit to connect to the first output terminal group, and control the second splitting unit to connect to the second output terminal group; The first display signal is received from the first display controller through the first splitting unit, and the second display signal is received from the second display controller through the second splitting unit; The first clock circuit synchronizes the first display signal with time based on the first clock signal, and the second clock circuit synchronizes the second display signal with time based on the first clock signal. The first and second display signals, synchronized by time, are transmitted synchronously to the target display screen through the first and second output terminal groups of the output interface; wherein, the first display signal is used to display the first display content in the first display area, and the second display signal is used to display the second display content in the second display area in sync with the first display content; The display multiplexer also includes a first selection circuit and a second selection circuit; The two sets of input terminals of the first selection circuit are respectively connected to the first splitting unit and the second splitting unit, and the output terminal of the first selection circuit is connected to the first output terminal group through the first clock circuit. The first selection circuit is used to: select one of the first splitting unit and the second splitting unit to be connected to the first clock circuit. The two sets of input terminals of the second selection circuit are respectively connected to the first splitting unit and the second splitting unit. The output terminal of the second selection circuit is connected to the second output terminal group through the second clock circuit. The first selection circuit is used to select one of the first splitting unit and the second splitting unit to be connected to the second clock circuit.

2. The multi-core heterogeneous system according to claim 1, characterized in that, The display multiplexer is also used for: The first splitting unit is connected to the first output terminal group and the second output terminal group respectively; The first display signal is received from the first display controller through the first splitting unit, and the first display signal is split into two first display signals. The first clock circuit and the second clock circuit synchronize based on the first clock signal to synchronize the time of the two first display signals respectively; The first output terminal group and the second output terminal group of the output interface synchronously transmit the two time-synchronized first display signals to the target display screen; wherein, the two time-synchronized first display signals are used to synchronously display the first display content in the first display area and the second display area of ​​the target display screen.

3. The multi-core heterogeneous system according to claim 1, characterized in that, The display multiplexer includes a first register corresponding to the first selection circuit and a second register corresponding to the second selection circuit; The first selection circuit is specifically used to: select one of the first split unit and the second split unit to be connected to the first clock circuit based on the first identifier or the second identifier added to the first register; wherein, the first identifier is used to identify the first split unit, and the second identifier is used to identify the second split unit; The second selection circuit is specifically used to: select one of the first split unit and the second split unit to connect to the second clock circuit based on the first identifier or the second identifier added to the second register.

4. The multi-core heterogeneous system according to claim 1, characterized in that, The multi-core heterogeneous system also includes a first hardware domain and a second hardware domain; The first display controller is connected to the first hardware domain, and the first display controller is specifically used to: obtain a first display signal that matches the first display area based on the first display data received from the first hardware domain; The second display controller is connected to the second hardware domain, and the second display controller is specifically used to: obtain a second display signal that matches the second display area based on the second display data received from the second hardware domain.

5. The multi-core heterogeneous system according to claim 4, characterized in that, The first display controller is specifically configured to: acquire first display data; process the first display data based on the first clock signal to acquire the first display signal having a first refresh frequency; and / or The second display controller is specifically used to: acquire second display data, process the second display data based on the first clock signal, and acquire the second display signal having a first refresh frequency.

6. The multi-core heterogeneous system according to claim 4, characterized in that, The first hardware domain includes a first display processor connected to the first display controller, the first display processor being used to send the first display data to the first display controller; The second hardware domain includes a second display processor connected to the second display controller, the second display processor being used to send the second display data to the second display controller.

7. The multi-core heterogeneous system according to claim 1, characterized in that, The multi-core heterogeneous system further includes a first hardware domain, which is connected to the first display controller and the second display controller respectively. The first hardware domain is used for: Obtain target display data that can output the target display content; Based on the target display data, obtain first display data that matches the first display area and second display data that matches the second display area; The first display data is transmitted to the first display controller, so that the first display controller generates a first display signal based on the first display data. The second display data is transmitted to the second display controller, so that the second display controller generates a second display signal based on the second display data.

8. A chip, characterized in that, Including the multi-core heterogeneous system as described in any one of claims 1 to 7.

9. A display system, characterized in that, Includes the chip as described in claim 8, and a target display screen, the target display screen including a display panel, a first timing controller and a second timing controller, the display panel having a first display area and a second display area; The first timing controller is connected to the first output terminal group of the output interface. The first timing controller is used to control the first display area to output the first display content based on the first display signal after time synchronization. The second timing controller is connected to the second output terminal group of the output interface. The second timing controller is used to control the second display area to output the second display content in sync with the first display content based on the second display signal after time synchronization.

10. A vehicle, characterized in that, Includes the display system as described in claim 9.

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