Gate driving circuit and display panel

Abstract

The application discloses a kind of gate drive circuit and display panel.The gate drive circuit includes first input module, second output module and coupling control module;First input module is connected with the second control end of second output module, and first input module is used to transmit input signal to the second control end based on second clock signal;Second output module is used to output second voltage signal when conducting;Coupling control module is electrically connected with the second control end, and coupling control module is used to carry out coupling control to the potential of second control end according to second clock signal and input signal, based on the jump of the first level of first clock signal to second level, so that the output end of gate drive circuit outputs second voltage signal.The technical scheme of the application improves the display effect of display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display panel. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming wider and wider, and people's requirements for display panels are also getting higher and higher.

[0003] However, current organic light-emitting display products have display abnormalities, and the display effect of these products needs to be improved. Summary of the Invention

[0004] This invention provides a gate driving circuit and a display panel to solve the problem of display abnormalities in display products.

[0005] According to one aspect of the present invention, a gate driving circuit is provided, the gate driving circuit comprising:

[0006] A first input module and a second output module are connected to the second control terminal of the second output module. The first input module is used to transmit an input signal to the second control terminal based on a second clock signal. The second output module is used to output a second voltage signal when it is turned on. A coupling control module is electrically connected to the second control terminal and is used to couple and control the potential of the second control terminal based on the transition from a first level to a second level of the first clock signal according to the second clock signal and the input signal, so that the output terminal of the gate drive circuit outputs the second voltage signal.

[0007] Optionally, the second level pulse of the second clock signal overlaps with the second level pulse of the input signal; the coupling control module is used to transmit the second level of the input signal to the internal node of the coupling control module when the second clock signal is at the second level, and to couple the potential of the internal node when the first clock signal changes from the first level to the second level, and transmit the coupled potential to the second control terminal;

[0008] Preferably, the second level is the same as the second voltage signal, and the first level is the same as the first voltage signal.

[0009] Optionally, the coupling control module includes: a first input unit, a first control unit, a first coupling unit, and a switching unit;

[0010] The control terminal of the first input unit is connected to the second clock signal, the first terminal of the first input unit is connected to the input signal, and the second terminal of the first input unit is connected to the internal node of the coupling control module. The first input unit is used to transmit the second level of the input signal to the internal node when the second clock signal is at the second level; wherein, the internal node is the first terminal of the first coupling unit.

[0011] The control terminal of the first control unit is connected to the internal node, the first terminal of the first control unit is connected to the first clock signal, and the second terminal of the first control unit is connected to the second terminal of the first coupling unit. The first control unit is used to couple the potential of the internal node when the first clock signal changes from a first level to a second level.

[0012] The control terminal and the first terminal of the switching unit are both connected to the internal node, and the second terminal of the switching unit is connected to the second control terminal. The switching unit is used to transmit the potential of the internal node after coupling to the second control terminal when the potential difference between the second control terminal and the internal node meets the conduction condition of the switching unit.

[0013] Optionally, the gate drive circuit further includes:

[0014] A first control module and a first output module, wherein the first control module is connected to a first control terminal of the first output module, the first control module is used to control the potential of the first control terminal based on the input signal, the first voltage signal and the first clock signal, and the first output module is used to turn on when the potential of the first control terminal is a second level, so as to output the first voltage signal when it is turned on.

[0015] Preferably, the coupling control module further includes: a second control unit;

[0016] The control terminal of the second control unit is connected to the first control terminal. The first terminal of the second control unit is connected to the first voltage signal. The second terminal of the second control unit is connected to the second terminal of the first coupling unit. The second control unit is used to transmit the first voltage signal to the second terminal of the first coupling unit when the potential of the first control terminal is at the second level.

[0017] Optionally, the first input unit includes a first transistor and a second transistor;

[0018] The control electrode of the first transistor is connected to the second clock signal, and the first electrode of the first transistor is connected to the input signal.

[0019] The control electrode of the second transistor is connected to the second voltage signal, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the internal node;

[0020] And / or, the first coupling unit includes a first capacitor, the first electrode of the first capacitor is the internal node, and the second electrode of the first capacitor is the second end of the first coupling unit;

[0021] And / or, the first control unit includes a third transistor, the control electrode of the third transistor is electrically connected to the internal node, the first electrode of the third transistor is connected to the first clock signal, and the second electrode of the third transistor is electrically connected to the second terminal of the first coupling unit;

[0022] And / or, the switching unit includes a fourth transistor, the control electrode and the first electrode of the fourth transistor are both electrically connected to the internal node, and the second electrode of the fourth transistor is electrically connected to the second control terminal;

[0023] And / or, the second control unit includes a fifth transistor, the control electrode of the fifth transistor being electrically connected to the first control terminal, the first electrode of the fifth transistor being connected to the first voltage signal, and the second electrode of the fifth transistor being electrically connected to the second terminal of the first coupling unit.

[0024] Optionally, the gate drive circuit further includes:

[0025] A coupling module is connected between the output terminal and the second control terminal, and is used to couple the potential of the second control terminal according to the potential change of the output terminal.

[0026] Optionally, the coupling module includes a second capacitor;

[0027] The second capacitor is connected between the output terminal and the second control terminal.

[0028] Optionally, the gate drive circuit further includes:

[0029] The node mutual control module is connected to the first control terminal and the second control terminal respectively, and is used to transmit the first voltage signal to the first control terminal in response to the potential of the second control terminal.

[0030] Optionally, the first control module includes:

[0031] The sixth transistor has its control electrode connected to the input signal and its first electrode connected to the first voltage signal.

[0032] A seventh transistor and a third capacitor are provided. The control electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor. The first electrode of the seventh transistor is connected to the first clock signal, and the second electrode of the seventh transistor is electrically connected to the first control terminal. The third capacitor is connected between the control electrode and the first electrode of the seventh transistor.

[0033] And / or, the first output module includes: a fourth capacitor and an eighth transistor;

[0034] The fourth capacitor is connected between the control electrode of the eighth transistor and the first electrode of the eighth transistor;

[0035] The control electrode of the eighth transistor is electrically connected to the first control terminal, and the second electrode of the eighth transistor is connected to the output terminal;

[0036] And / or, the second output module includes a ninth transistor; the control electrode of the ninth transistor is electrically connected to the second control terminal, the first electrode of the ninth transistor is connected to the second voltage signal, and the second electrode of the ninth transistor is the output terminal of the gate drive circuit.

[0037] According to another aspect of the present invention, a display panel is provided, the display panel including the gate driving circuit described in any embodiment of the present invention.

[0038] The technical solution of this invention, through the setting of a coupling control module, couples the potential of the second control terminal based on the transition from the first level to the second level of the first clock signal, according to the second clock signal and the input signal. This couples the second level to the second control terminal, causing the potential of the second control terminal to change towards the second level. When the input signal is at the second level, i.e., the potential of the second control terminal is at the second level, the coupling control module further couples the potential of the second control terminal towards the second level, resulting in an electrical signal lower or higher than the second level. This ensures that the second output module can be fully turned on, and that it outputs a second voltage signal. This ensures that the amplitude of the gate drive circuit's output voltage is equal to the amplitude of the second voltage signal. The amplitude of the second voltage signal is sufficient to fully turn on the corresponding transistors in the pixel circuit, thereby better controlling the on / off state of the transistors in the pixel circuit. This achieves accurate control of the light-emitting timing or brightness of the light-emitting devices corresponding to the pixel circuit, allowing the display panel to better display the image to be displayed, thus improving the display effect of the display panel.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0047] Figure 7 yes Figure 5 The corresponding timing diagram;

[0048] Figure 8 yes Figure 6 The corresponding timing diagram;

[0049] Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0050] Figure 10 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the term "comprising" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0053] The pixel unit of a display product includes a pixel circuit and a light-emitting device. The pixel circuit includes a 2T1C pixel circuit and its variations, or a 7T1C pixel circuit and its variations. The 7T1C pixel circuit, for example, includes a data writing transistor, a threshold compensation transistor, a driving transistor, a first initialization transistor, a second initialization transistor, a first light-emitting control transistor, and a second light-emitting control transistor. A gate driving signal is output by a gate driving circuit, which drives the transistors of the pixel circuit to turn on and off. The gate driving signal can be a scan driving signal corresponding to at least one of the data writing transistor, threshold compensation transistor, driving transistor, first initialization transistor, and second initialization transistor, or a light-emitting control signal corresponding to at least one of the first and second light-emitting control transistors. The gate driving circuit can include two output modules: one output module outputting a valid level, and the other output module outputting an invalid level. A valid level refers to a signal that controls the transistor to turn on, and an invalid level refers to a signal that controls the transistor to turn off. When the control terminal of the output module outputting the valid level is at a valid level, the output module outputs a valid level. When there is leakage in the transistor (the transistor connected to the control terminal of the output module that outputs an effective level) in the gate drive circuit, the potential of the control terminal of the output module that outputs an effective level may change towards an ineffective level. This prevents the output module that outputs an effective level from being fully turned on, thus failing to output an effective level. In other words, the amplitude of the level output by the output module is insufficient to meet the requirement of fully turning on the corresponding transistor in the pixel circuit. This results in the inability to accurately control the conduction of the transistor in the pixel circuit, which in turn prevents the pixel circuit from outputting the drive current normally. Consequently, the light-emitting device fails to emit light normally, causing display abnormalities in the display product.

[0054] To address the aforementioned technical problems, embodiments of the present invention provide a gate driving circuit. Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention, for reference. Figure 1 The gate driving circuit provided in this embodiment of the invention includes: a first input module 130, a second output module 140, and a coupling control module 150; the first input module 130 is connected to the second control terminal N2 of the second output module 140, and the first input module 130 is used to transmit the input signal EIN to the second control terminal N2 based on the second clock signal CK2; the second output module 140 is used to output the second voltage signal VG2 when it is turned on; the coupling control module 150 is electrically connected to the second control terminal N2, and is used to couple and control the potential of the second control terminal N2 based on the second clock signal CK2 and the input signal EIN, and based on the transition from the first level to the second level of the first clock signal CK1, so that the output terminal OUT of the gate driving circuit outputs the second voltage signal VG2.

[0055] The second output module 140 outputs a gate drive signal (OUT) from its gate drive circuit. This gate drive signal is the gate drive signal of the transistor in the pixel circuit of the display panel. The second level is a low-level signal, and the first level is a high-level signal; or, the second level is a high-level signal, and the first level is a low-level signal. For example, the second level might be a voltage controlling the first input module to turn on, and the first level might be a voltage controlling the first input module to turn off. The first clock signal CK1, the second clock signal CK2, and the input signal EIN are, for example, pulse signals, all of which include both the first and second levels.

[0056] Specifically, when the second clock signal CK2 is at the second level, the first input module 130 is turned on, and the first input module 130 transmits the input signal EIN to the second control terminal N2. When the input signal EIN is at the second level, the potential of the second control terminal N2 is at the second level. When the coupling control module 150 performs coupling control on the potential of the second control terminal N2 based on the second clock signal CK2 and the input signal EIN, and based on the transition from the first level to the second level of the first clock signal CK1, the second level can be coupled to the second control terminal N2, thereby causing the potential of the second control terminal N2 to change towards the second level. When the input signal EIN is the fourth signal, that is, when the second control terminal N2 is at the second level, through the coupling of the coupling control module 150, the potential of the second control terminal N2 can be changed to an electrical signal lower than the second level or higher than the second level (when the second level is low, the potential of the second control terminal N2 becomes a signal lower than the second level; when the second level is high, the potential of the second control terminal N2 becomes a signal higher than the second level).

[0057] In some embodiments, when the second level is low, since the potential of the second control terminal N2 is also at the second level when the input signal EIN is at the second level, and then coupled by the coupling control module 150, the potential of the second control terminal N2 is made to be ultra-low. In some embodiments, when the second level is high, since the potential of the second control terminal N2 is also at the second level when the input signal EIN is at the second level, and then coupled by the coupling control module 150, the potential of the second control terminal N2 is made to be ultra-high. When the potential of the second control terminal N2 is ultra-low or ultra-high, it can more effectively control the second output module 140 to conduct than the second level, thereby enabling the second output module 140 to conduct completely, allowing the second output module 140 to output the second voltage signal VG2, thus ensuring that the gate drive circuit can output the second voltage signal VG2, that is, ensuring that the amplitude of the output voltage of the gate drive circuit is equal to the amplitude of the second voltage signal VG2, ensuring the complete output of the second voltage signal VG2, and the amplitude of the second voltage signal VG2 is sufficient to fully conduct the corresponding transistor in the pixel circuit.

[0058] In this way, the gate drive circuit can output the second voltage signal VG2, thereby better controlling the conduction and cutoff of the transistors in the pixel circuit, and thus controlling the light emission timing or brightness of the light-emitting device corresponding to the pixel circuit. This allows the display panel to better display the image to be displayed, avoiding the situation where the gate drive circuit cannot output the second voltage signal VG2, which would cause display abnormalities and improve the display effect of the display panel.

[0059] The technical solution of this embodiment, by setting a coupling control module, controls the potential of the second control terminal based on the transition from the first level to the second level of the first clock signal, according to the second clock signal and the input signal. This couples the second level to the second control terminal, causing the potential of the second control terminal to change towards the second level. When the input signal is at the second level, i.e., the potential of the second control terminal is at the second level, the coupling control module further changes the potential of the second control terminal towards the second level, resulting in an electrical signal lower or higher than the second level. This ensures that the second output module can be fully turned on, and that it outputs a second voltage signal. This ensures that the amplitude of the gate drive circuit's output voltage is equal to the amplitude of the second voltage signal. The amplitude of the second voltage signal is sufficient to fully turn on the corresponding transistors in the pixel circuit, thereby better controlling the on / off state of the transistors in the pixel circuit. This achieves accurate control of the light-emitting timing or brightness of the light-emitting devices corresponding to the pixel circuit, allowing the display panel to better display the image to be displayed, thus improving the display effect of the display panel.

[0060] Based on the above technical solution, optionally, the second level pulse of the second clock signal CK2 overlaps with the second level pulse of the input signal EIN; the coupling control module 150 is used to transmit the second level of the input signal EIN to the internal node N3 of the coupling control module 150 when the second clock signal CK2 is at the second level, and to couple the potential of the internal node N3 when the first clock signal CK1 changes from the first level to the second level, and transmit the coupled potential to the second control terminal N2.

[0061] Specifically, when the second clock signal CK2 is at the second level, the first input module 130 is turned on, and the first input module 130 transmits the input signal EIN to the second control terminal N2. Therefore, when the second level pulse of the second clock signal CK2 overlaps with the second level pulse of the input signal EIN, the potential of the second control terminal N2 is at the second level.

[0062] When the second clock signal CK2 is at the second level, the coupling control module 150 transmits the second level of the input signal EIN to the internal node N3, making the potential of the internal node N3 the second level. When the first clock signal CK1 jumps from the first level to the second level, the coupling control module 150 couples the potential of the internal node N3, causing the potential of the internal node N3 to change further towards the second level, that is, the potential of the internal node N3 becomes an ultra-low level or an ultra-high level.

[0063] The coupling control module 150 transmits the potential of the internal node N3 after coupling to the second control terminal N2, so that the potential of the second control terminal N2 also changes further towards the second level, becoming an ultra-low level or an ultra-high level, that is, becoming a more effective level. This ensures that the second output module 140 can be fully turned on, which is beneficial to ensure that the second output module 140 outputs the second voltage signal VG2.

[0064] The gate drive circuit also includes a first voltage signal VG1, the level of which differs from that of the second voltage signal VG2. The first voltage signal VG1 is high, and the second voltage signal VG2 is low; or, the first voltage signal VG1 is low, and the second voltage signal VG2 is high.

[0065] Optionally, the second level is the same as the second voltage signal VG2, and the first level is the same as the first voltage signal VG1. Thus, when the second output module 140 outputs the second voltage signal VG2, it outputs the second level; when the first output module 120 outputs the first voltage signal VG1, it outputs the first level. This causes the gate drive signal output by the gate drive circuit to output high and low levels in a time-division manner, i.e., to output invalid and valid levels in a time-division manner, thereby controlling the transistors in the pixel circuit.

[0066] Based on the above technical solutions, the gate drive circuit will be further described below in conjunction with the possible structure of the coupling control module, but this is not intended to limit this application.

[0067] Figure 2 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 2 The coupling control module 150 includes: a first input unit 151, a first control unit 152, a first coupling unit 153, and a switching unit 154;

[0068] The control terminal of the first input unit 151 is connected to the second clock signal CK2. The first terminal of the first input unit 151 is connected to the input signal EIN. The second terminal of the first input unit 151 is connected to the internal node N3 of the coupling control module 150. The first input unit 151 is used to transmit the second level of the input signal EIN to the internal node N3 when the second clock signal CK2 is at the second level. The internal node N3 is the first terminal of the first coupling unit 153.

[0069] The control terminal of the first control unit 152 is connected to the internal node N3. The first terminal of the first control unit 152 is connected to the first clock signal CK1. The second terminal of the first control unit 152 is connected to the second terminal N4 of the first coupling unit 153. The first control unit 152 is used to couple the potential of the internal node N3 when the first clock signal CK1 changes from the first level to the second level.

[0070] The control terminal and the first terminal of the switching unit 154 are both connected to the internal node N3, and the second terminal of the switching unit 154 is connected to the second control terminal N2. The switching unit 154 is used to transmit the potential of the internal node N3 after coupling to the second control terminal N2 when the potential difference between the second control terminal N2 and the internal node N3 meets the conduction condition of the switching unit 154.

[0071] Specifically, when the second clock signal CK2 is at the second level, the first input unit 151 transmits the second level of the input signal EIN to the internal node N3, that is, to the first terminal of the first coupling unit 153, at which time the first control unit 152 is turned on. When the first clock signal CK1 changes from the first level to the second level, the first control unit 152 transmits the second level to the second terminal of the first coupling unit 153, causing a change in the potential of the second terminal N4 of the first coupling unit 153. Since the charge stored in the first coupling unit 153 remains unchanged, that is, the voltage difference across the first coupling unit 153 remains unchanged, when the potential change of the second terminal N4 of the first coupling unit 153 to the second level, the coupling change at the first terminal of the first coupling unit 153 further changes in the direction of the second level.

[0072] For example, when the second level is low, if the potential change of the second terminal N4 of the first coupling unit 153 is low, since the voltage difference across the first coupling unit 153 remains unchanged, the first terminal of the first coupling unit 153 further decreases, becoming an ultra-low level. When the second level is high, if the potential change of the second terminal N4 of the first coupling unit 153 is high, since the voltage difference across the first coupling unit 153 remains unchanged, the first terminal of the first coupling unit 153 further increases, becoming an ultra-high level.

[0073] When the potential of internal node N3 is lower or higher than the second level (ultra-high or ultra-low level), and the potential of the second control terminal N2 is at the second level, the potential difference between the second control terminal N2 and the internal node N3 satisfies the conduction condition of the switch unit 154. The switch unit 154 is turned on, and the switch unit 154 transmits the potential (ultra-high or ultra-low level) of the internal node N3 after coupling to the second control terminal N2, so that the potential of the second control terminal N2 becomes a more effective level (ultra-high or ultra-low level), thereby ensuring that the second output module 140 is fully turned on.

[0074] Optionally, refer to Figure 2 The gate drive circuit further includes a first control module 110 and a first output module 120. The first control module 110 is used to control the potential of the first control terminal N1 based on the input signal EIN, the first voltage signal VG1 and the first clock signal CK1. The first output module 120 is used to turn on when the potential of the first control terminal N1 is at the second level, so as to output the first voltage signal VG1 when it is turned on. The coupling control module 150 further includes a second control unit 155. The control terminal of the second control unit 155 is connected to the first control terminal N1. The first terminal of the second control unit 155 is connected to the first voltage signal VG1. The second terminal of the second control unit 155 is connected to the second terminal N4 of the first coupling unit 153. The second control unit 155 is used to transmit the first voltage signal VG1 to the second terminal N4 of the first coupling unit 153 when the potential of the first control terminal N1 is at the second level.

[0075] The output terminals of the first output module 120 and the second output module 140 are both output terminals OUT of the gate drive circuit. When the first control module 110 controls the potential of the first control terminal N1 to the second level based on the input signal EIN, the first voltage signal VG1, and the first clock signal CK1, the first output module 120 is turned on and outputs the first voltage signal VG1, so that the gate drive signal output by the gate drive circuit is the first voltage signal VG1.

[0076] Specifically, when the potential of the first control terminal N1 is at the second level, the first output module 120 is turned on and outputs the first voltage signal VG1. By transmitting the first voltage signal VG1 to the second terminal N4 of the first coupling unit 153 when the potential of the first control terminal N1 is at the second level, the potential of the second terminal N4 of the first coupling unit 153 is at the first level, thus preventing the potential of the internal node N3 from being coupled to an ultra-high or ultra-low level, and consequently preventing coupling control of the second control terminal N2, so that the second output module 140 does not output the second voltage signal VG2. In this way, the first output module 120 and the second output module 140 are prevented from being turned on simultaneously, thereby avoiding the gate drive circuit output signal disorder and helping to ensure the accuracy of the gate drive signal output by the gate drive circuit.

[0077] Based on the above technical solutions, Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 3 and Figure 4 The first input unit 151 includes a first transistor T1 and a second transistor T2. The control electrode of the first transistor T1 is connected to a second clock signal CK2, and the first electrode of the first transistor T1 is connected to an input signal EIN. The control electrode of the second transistor T2 is connected to a second voltage signal VG2, and the first electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1. The second electrode of the second transistor T2 is also electrically connected to an internal node N3. By setting the first transistor T1, when the second clock signal CK2 is at a second level, the input signal EIN can be transmitted to the internal node N3. By setting the control electrode of the second transistor T2 to be connected to the second voltage signal VG2, making the second transistor T2 normally open, the voltage of the internal node N3 can be prevented from being transmitted to the first transistor T1 when the internal node N3 is at a more effective level (ultra-low level or ultra-high level), thus avoiding damage to the first transistor T1.

[0078] Optionally, refer to Figure 3 and Figure 4 The first coupling unit 153 includes a first capacitor C1, the first terminal of the first capacitor C1 is an internal node N2, and the second terminal of the first capacitor C1 is the second terminal N4 of the first coupling unit 153. Since the voltage difference across the first capacitor C1 remains constant, when the potential of the second terminal of the first capacitor C1 changes to a second level, the coupling of the first terminal of the first capacitor C1 changes, further changing in the direction of the second level.

[0079] Optionally, refer to Figure 3 and Figure 4The first control unit 152 includes a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the internal node N3. The first electrode of the third transistor T3 is connected to the first clock signal CK1, and the second electrode of the third transistor T3 is electrically connected to the second terminal of the first coupling unit 153. By configuring the third transistor T3, when the first clock signal CK1 changes from a first level to a second level, the third transistor T3 transmits the second level to the second terminal N4 of the first coupling unit 153, facilitating the coupling control of the potential of the internal node N3 by the first coupling unit 153.

[0080] Optionally, refer to Figure 3 and Figure 4 The switching unit 154 includes a fourth transistor T4. The control electrode and the first electrode of the fourth transistor T4 are both electrically connected to the internal node N3, and the second electrode of the fourth transistor T4 is electrically connected to the second control terminal N2. The potential difference between the internal node N3 and the second control terminal N2 can control whether the fourth transistor T4 is turned on, thereby controlling whether potential coupling is performed to the second control terminal N2.

[0081] Optionally, refer to Figure 3 and Figure 4 The second control unit 155 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first control terminal N1. The first electrode of the fifth transistor T5 is connected to a first voltage signal VG1, and the second electrode of the fifth transistor T5 is electrically connected to the second terminal N4 of the first coupling unit 153. By setting the fifth transistor T5, when the potential of the first control terminal N1 is at the second level, the fifth transistor T5 transmits the first voltage signal VG1 to the second terminal N4 of the first coupling unit 153, so that the potential of the second terminal N4 of the first coupling unit 153 is at the first level. This prevents the potential of the internal node N3 from being coupled to an ultra-low level or an ultra-high level, and thus prevents coupling control of the second control terminal N2.

[0082] It should be noted that, Figure 3 The diagram shows a case where all transistors in the coupling control module 150 of the gate drive circuit are P-type transistors. Figure 4 The illustration shows a case where all transistors in the coupling control module 150 of the gate drive circuit are N-type transistors, but this is not a limitation. In some other embodiments, the transistors in the coupling control module 150 of the gate drive circuit may be partly P-type transistors and partly N-type transistors.

[0083] Based on the above technical solutions, Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Optionally, refer to... Figure 5 and Figure 6 The gate drive circuit also includes a coupling module 160; the coupling module 160 is connected between the output terminal OUT and the second control terminal N2, and is used to couple the potential of the second control terminal N2 according to the potential jump of the output terminal OUT. Specifically, the first end of the coupling module 160 is connected to the output terminal OUT, and the second end of the coupling module 160 is connected to the second control terminal N2.

[0084] Specifically, when the second clock signal CK2 is at the second level, the first input module 130 is turned on, and the first input module 130 transmits the input signal EIN to the second control terminal N2. When the input signal EIN is at the second level, the potential of the second control terminal N2 is at the second level, and at this time, the second output module 140 is turned on. After the second output module 140 is turned on, it transmits the second voltage signal VG2 and the threshold voltage of the second output module 140 to the output terminal OUT. The signal at the output terminal OUT is close to the second voltage signal VG2, that is, close to the second level, causing the potential of the first terminal of the coupling module 160 to jump. Since the charge stored in coupling module 160 remains constant, i.e., the voltage difference across coupling module 160 remains constant, when the potential of the first terminal of coupling module 160 changes, it couples the potential of the second control terminal N2, causing the potential of the second control terminal N2 to change towards the second level, i.e., to a level higher or lower than the second level, i.e., a more effective level (ultra-low level or ultra-high level). This controls the second output module 140 to be fully turned on, thereby ensuring that the gate drive circuit can output the second voltage signal VG2. Because the potential of the first terminal of coupling module 160 quickly couples the potential of the second control terminal N2 after the potential change, the time from turn-on to full turn-on of the second output module 140 is very short. In other words, when the second clock signal CK2 and the input signal EIN change to the second level, the second output module 140 can be fully turned on quickly, allowing the second output module 140 to immediately output the second voltage signal VG2, avoiding a step in the gate drive signal output by the gate drive circuit.

[0085] Optionally, refer to Figure 5 and Figure 6 The coupling module 160 includes a second capacitor C2; the second capacitor C2 is connected between the output terminal OUT and the second control terminal N2. The amount of charge stored in the second capacitor C2 does not change, that is, the voltage difference across the second capacitor C2 does not change. Therefore, when one end of the second capacitor C2 (output terminal OUT) changes, the potential of the other end (the second control terminal N2 of the second capacitor C2) can be coupled, thereby realizing the coupling control of the potential of the second control terminal N2.

[0086] In summary, the technical solution of this embodiment, by setting the coupling module 160, enables the second output module 140 to immediately output the second voltage signal VG2, avoiding a step in the gate drive signal output by the gate drive circuit; by setting the coupling control module 150, a more effective level (ultra-low level or ultra-high level) of the second control terminal N2 can be maintained, avoiding the leakage current in the circuit from affecting the second output module 140, maintaining the output of the second voltage signal VG2 by the second output module 140, and ensuring the output of the gate drive circuit.

[0087] Optionally, refer to Figure 5 and Figure 6 The gate drive circuit also includes a node inter-control module 170, which is connected to the first control terminal N1 and the second control terminal N2 respectively. The node inter-control module 170 is used to transmit the first voltage signal VG1 to the first control terminal N1 in response to the potential of the second control terminal N2.

[0088] Specifically, when the potential of the second control terminal N2 is at the second level, the node mutual control module 170 is turned on, transmitting the first voltage signal VG1 to the first control terminal N1, making the potential of the first control terminal N1 at the first level. This achieves mutual control of the node potentials of the first control terminal N1 and the second control terminal N2, reducing the possibility of intermediate potentials between high and low levels for the potentials of the first control terminal N1 and the second control terminal N2, ensuring that the potentials of the two control terminals are clearly defined, and preventing the first output module 120 and the second output module 140 from being turned on simultaneously, thereby ensuring the accurate output state of the gate drive circuit.

[0089] Optionally, refer to Figure 5 and Figure 6The first control module 110 includes a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The control electrode of the sixth transistor T6 is connected to the input signal EIN, and the first electrode of the sixth transistor T6 is connected to the first voltage signal VG1. The control electrode N5 of the seventh transistor T7 is electrically connected to the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7 is connected to the first clock signal CK1, and the second electrode of the seventh transistor T7 is electrically connected to the first control terminal N1. The third capacitor C3 is connected between the control electrode N5 and the first electrode of the seventh transistor T7. When the input signal EIN is at an invalid level (first level), the sixth transistor T6 is turned off. When the first clock signal CK1 is at an active level (second level), the control electrode N5 of the seventh transistor T7 is at an active level (second level), the seventh transistor T7 is turned on and outputs an active level (second level), that is, the first control terminal N1 is at an active level (second level), thereby controlling the first output module 120 to turn on, and the first output module 120 outputs the first voltage signal VG1. When the input signal EIN is at an active level (second level) and the first clock signal CK1 is at an active level (second level), the sixth transistor T6 and the seventh transistor T7 are turned on, and the first output module 120 outputs the first voltage signal VG1.

[0090] Optionally, refer to Figure 5 and Figure 6 The first output module 120 includes a fourth capacitor C4 and an eighth transistor T8. The fourth capacitor C4 is connected between the control electrode and the first electrode of the eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the first control terminal N1, and the second electrode of the eighth transistor T8 is connected to the output terminal. When the potential of the first control terminal N1 is at an effective level (second level), the eighth transistor T8 can be controlled to conduct, so that the eighth transistor T8 outputs a first voltage signal VG1.

[0091] Optionally, refer to Figure 5 and Figure 6 The second output module 140 includes a ninth transistor T9. The control electrode of the ninth transistor T9 is electrically connected to the second control terminal N2. The first electrode of the ninth transistor T9 is connected to the second voltage signal VG2, and the second electrode of the ninth transistor T9 is the output terminal OUT of the gate drive circuit. When the second control terminal N2 is at an active level (second level), the ninth transistor T9 can be controlled to conduct, and the ninth transistor T9 outputs the second voltage signal VG2. When the second control terminal N2 is at a more active level (ultra-low level or ultra-high level), the ninth transistor T9 can be controlled to fully conduct, and the ninth transistor T9 outputs the second voltage signal VG2 more effectively.

[0092] Optionally, refer to Figure 5 and Figure 6The node mutual control module 170 includes a tenth transistor T10. The control electrode of the tenth transistor T10 is electrically connected to the second control terminal N2. The first electrode of the tenth transistor T10 is connected to the first voltage signal VG1, and the second electrode of the tenth transistor T10 is electrically connected to the first control terminal N1. By controlling the conduction and turn-off of the tenth transistor T10 through the second control terminal N2, when the potential of the second control terminal N2 is at an effective level (second level), the potential of the first control terminal N1 is the first voltage signal VG1, which is an ineffective level (first level), thereby realizing the mutual control of the potentials of the first control terminal N1 and the second control terminal N2.

[0093] Optionally, refer to Figure 5 and Figure 6 The first input module 130 includes an eleventh transistor T11. The control electrode of the eleventh transistor T11 is connected to the second clock signal CK2, the first electrode of the eleventh transistor T11 is connected to the input signal EIN, and the second electrode of the eleventh transistor T11 is electrically connected to the second control terminal N2. When the second clock signal CK2 is at a valid level (second level), the eleventh transistor T11 is turned on, transmitting the input signal EIN to the second control terminal N2. When both the second clock signal CK2 and the input signal EIN are valid signals (second level), the second control terminal N2 can also be valid signals (second level), causing the second output module 140 to output a second voltage signal VG2, i.e., a valid level (second level), which facilitates the gate drive circuit to shift and output the input signal EIN.

[0094] Optionally, refer to Figure 5 and Figure 6 The gate drive circuit also includes a twelfth transistor T12. The control terminal of the twelfth transistor T12 is connected to the second clock signal CK2. The first terminal N6 of the twelfth transistor T12 is electrically connected to the first input module 130, and the second terminal of the twelfth transistor T12 is electrically connected to the second control terminal N2. When the second clock signal CK2 is at an active level (second level), that is, when the twelfth transistor T12 is normally open, it can prevent the second control terminal N2 from affecting the potential of the first input module 130 when it is at a more active level (ultra-low level or ultra-high level), thus avoiding damage to the first input module 130.

[0095] It should be noted that, Figure 5 The diagram shows a case where all transistors in the gate drive circuit are P-type transistors. Figure 6 The illustration shows a case where all transistors in the gate drive circuit are N-type transistors, but this is not a limitation. In some other embodiments, the transistors in the gate drive circuit may be partly P-type transistors and partly N-type transistors.

[0096] The operation of the gate drive circuit is described below with reference to specific timing details. In one embodiment, Figure 5 The first voltage signal VG1 is a high-level signal VGH, and the second voltage signal VG2 is a low-level signal VGL. Figure 7 yes Figure 5 The corresponding timing diagram can optionally be referenced. Figure 5 and Figure 7 The operation of the gate drive circuit includes the following stages.

[0097] In the first stage t1, the input signal EIN is a high-level signal VGH, and the sixth transistor T6 is turned off; the first clock signal CK1 is a high-level signal VGH, the potential VN5 of the control electrode N5 of the seventh transistor T7 is a high-level signal VGH, the seventh transistor T7 is turned off, the potential VN1 of the first control terminal N1 is a high-level signal VGH, and the eighth transistor T8 is turned off. The second clock signal CK2 is a low-level signal VGL, the eleventh transistor T11 is turned on, the input signal EIN is transmitted to the second control terminal N2, the potential VN2 of the second control terminal N2 is a high-level signal VGH, the potential VN6 of the first electrode N6 of the twelfth transistor T12 is also a high-level signal VGH, and the ninth transistor T9 is turned off. The potential VN1 of the first control terminal N1 is a high-level signal VGH, so the fifth transistor T5 is turned off. When the second clock signal CK2 is low (VGL), the first transistor T1 is turned on, transmitting the input signal EIN to the internal node N3. The potential VN3 of the internal node N3 is high (VGH), so the third transistor T3 and the fourth transistor T4 are turned off, and the potential VN4 of the second terminal N4 of the first capacitor C1 is high (VGH). Therefore, in the first stage t1, the potentials of each important node are VN1 = VN2 = VN3 = VN4 = VN5 = VN6 = VGH. The eighth transistor T8 and the ninth transistor T9 are both turned off, and the output terminal OUT maintains the voltage of the previous moment, continuing to output the low-level signal VGL.

[0098] In the second stage t2, the input signal EIN remains high (VGH), and the sixth transistor T6 remains off. The second clock signal CK2 transitions to high (VGH), the eleventh transistor T11 turns off, and the potential VN2 of the second control terminal N2 and the potential VN6 of the first terminal N6 of the twelfth transistor T12 maintain a high level (VGH). The first transistor T1 turns off, and the potential VN3 of the internal node N3 maintains a high level (VGH). The first clock signal CK1 transitions to low (VGL), and through the third capacitor C3, the low level (VGL) is coupled to the control terminal N5 of the seventh transistor T7 until the potential of the control terminal N5 of the seventh transistor T7 becomes VGL-Vth. At this point, the seventh transistor T7 turns on and outputs VGL-Vth, meaning the potential VN1 of the first control terminal N1 is VGL-Vth. The eighth transistor T8 turns on and outputs a high level (VGH), meaning the potential VOUT of the output terminal OUT transitions to high (VGH). Furthermore, when the second clock signal CK2 transitions to a high-level signal VGH, the first transistor T1 turns off. When the potential VN1 of the first control terminal N1 is VGL-Vth, the fifth transistor T5 turns on, and the potential VN4 of the second terminal N4 of the first capacitor C1 remains a high-level signal VGH. The potential VN3 of the internal node N3 also remains unchanged at VGH. Therefore, in the second stage t2, the potentials of each important node are VN2=VN3=VN4=VN6=VGH, VN1=VN5=VGL-Vth, and VOUT=VGH. Here, Vth is the threshold voltage of the transistor.

[0099] In the third stage t3, the input signal EIN remains high (VGH), and the sixth transistor T6 remains off. The second clock signal CK2 transitions to low (VGL), and the potentials of the first terminal N6 (VN6) and the second control terminal N2 (VN2) of the twelfth transistor T12 become high (VGH). The first clock signal CK1 transitions to high (VGH), and the potential of the control terminal N5 of the seventh transistor T7 becomes high (VGH), turning off the seventh transistor T7. Due to the presence of the fourth capacitor C4, the potential VN1 of the first control terminal N1 is maintained, ensuring that VN1 remains VGL-Vth. The eighth transistor T8 turns on, outputting a high (VGH) signal, meaning the potential VOUT of the output terminal OUT remains high (VGH). The second clock signal CK2 becomes low (VGL), the first transistor T1 turns on, transmitting the input signal EIN to the internal node N3. The potential VN3 of the internal node N3 becomes high (VGH), thus turning off the third transistor T3 and the fourth transistor T4. When the potential VN1 of the first control terminal N1 is VGL-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second terminal N4 of the first capacitor C1 remains a high-level signal VGH. Therefore, in the third stage t3, the potentials of each important node are VN2=VN3=VN4=VN5=VN6=VGH, VN1=VGL-Vth, and VOUT=VGH.

[0100] Stages 4 to 7 (t4 and t7) are cycles of stages 2 (t2) and 3 (t3). This means that the potentials of each node in stages 4 (t4) and 6 (t6) are the same as those in stage 2 (t2), and the conduction states of each transistor in stages 4 (t4) and 6 (t6) are the same as those in stage 2 (t2). The output of the gate drive circuit in stages 4 (t4), 6 (t6), and 2 (t2) is the same. Similarly, the potentials of each node in stages 5 (t5) and 7 (t7) are the same as those in stage 3 (t3), and the conduction states of each transistor in stages 5 (t5) and 7 (t7) are the same as those in stage 3 (t3). The output of the gate drive circuit in stages 5 (t5), 7 (t7), and 3 (t3) is the same.

[0101] In stage t8, the input signal EIN transitions to a low level signal VGL, the sixth transistor T6 turns on, and transmits the high level signal VGH to the control electrode N5 of the seventh transistor T7. The seventh transistor T7 turns off, and the fourth capacitor C4 maintains the potential VN1 of the first control terminal N1, VN1 = VGL - Vth. The eighth transistor T8 turns on and outputs a high level signal VGH, VOUT = VGH. The second clock signal CK2 transitions to a high level signal VGH, the eleventh transistor T11 turns off, and the potential VN6 of the first electrode N6 and the potential VN2 of the second control terminal N2 of the twelfth transistor T12 remain at a high level signal VGH. The second clock signal CK2 transitions to a high level signal VGH, the first transistor T1 turns off, and the potential VN3 of the internal node N3 is a high level signal VGH, so the third transistor T3 and the fourth transistor T4 turn off. When the potential VN1 of the first control terminal N1 is VGL-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second terminal N4 of the first capacitor C1 remains a high-level signal VGH. Therefore, in the eighth stage t8, the potentials of each important node are VN2=VN3=VN4=VN5=VN6=VGH, VN1=VGL-Vth, and VOUT=VGH.

[0102] In the ninth stage t9, the first clock signal CK1 transitions to a high-level signal VGH, the input signal EIN becomes a low-level signal VGL, the sixth transistor T6 turns on, and transmits the high-level signal VGH to the control terminal N5 of the seventh transistor T7, while the seventh transistor T7 turns off. The second clock signal CK2 transitions to a low-level signal VGL, the eleventh transistor T11 turns on, and transmits the input signal EIN to the first terminal N6 of the twelfth transistor T12. The potential VN6 of the first terminal N6 of the twelfth transistor T12 becomes a low-level signal VGL-Vth, the tenth transistor T10 turns on, and transmits the high-level signal VGH to the first control terminal N1. Therefore, the potential VN1 of the first control terminal N1 becomes a high-level signal VGH, the eighth transistor T8 turns off, and the fifth transistor T5 turns off. The potential VN6 of the first terminal N6 of the twelfth transistor T12 is a low-level signal VGL. The twelfth transistor T12 transmits the low-level signal VGL-Vth to the second control terminal N2, and the potential VN2 of the second control terminal N2 becomes VGL-Vth. The ninth transistor T9 is turned on. After the ninth transistor T9 is turned on, it outputs a lower level, pulling the potential of the output terminal OUT low. Due to the coupling effect of the second capacitor C2, the charge stored in the second capacitor C2 remains unchanged. The second capacitor C2 couples and pulls the potential of the second control terminal N2 low, making the potential of the second control terminal N2 an ultra-low level (more efficient level). Furthermore, the second clock signal CK2 jumps to the low-level signal VGL, the first transistor T1 is turned on, and the first transistor T1 and the second transistor T2 transmit the low-level signal VGL of the input signal EIN to the internal node N3. The potential VN3 of the internal node N3 becomes VGL-Vth. The control electrode potential of the third transistor T3 is VGL-Vth, so the third transistor T3 is turned on. The potential of its second electrode is VGH. The second electrode N4 of the first capacitor C1 maintains a high-level signal VGH. Therefore, the voltage difference across the first capacitor C1 is VGL-Vth-VGH. The control electrode potential of the fourth transistor T4 is VGL-Vth, and the second electrode N2 of the fourth transistor T4 is at an ultra-low level (more effective level). The fourth transistor T4 does not meet the turn-on condition and is turned off. The potential of the internal node N3 will not be transmitted to the second control terminal N2. The ultra-low level (more effective level) potential of the second control terminal N2 allows the ninth transistor T9 to be fully turned on, enabling the ninth transistor T9 to immediately output a low-level signal VGL. That is, the gate drive circuit can immediately output a low-level signal VGL, avoiding a step in the output gate drive signal. Therefore, in the ninth stage t9, the potentials of each important node are VN1 = VN4 = VN5 = VGH, VN2 is at an ultra-low level, VN3 = VN6 = VGL - Vth, and VOUT = VGL.

[0103] In the tenth stage t10, the first clock signal CK1 transitions to a low-level signal VGL. The third transistor T3 transmits the low-level signal VGL to the second terminal N4 of the first capacitor C1. The potential VN4 of the second terminal N4 of the first capacitor C1 is VGL-Vth, and the voltage difference across the first capacitor C1 is VGL-Vth-VGH. Therefore, the potential VN3 of the internal node N3 becomes VGL-Vth-VGH+VGL, i.e., VN3 = 2*VGL-Vth-VGH, which becomes an ultra-low level. Since the potential VN3 of the internal node N3 is ultra-low, if the potential of the second control terminal N2 increases due to the leakage of the twelfth transistor T12, the fourth transistor T4 turns on, causing the ultra-low level of the internal node N3 to be transmitted to the second control terminal N2, thereby maintaining the ultra-low level of the second control terminal N2, ensuring that the ninth transistor T9 can be fully turned on, and ensuring that the gate drive circuit outputs a low-level signal VGL. When the input signal EIN is a low-level signal VGL, the sixth transistor T6 is turned on, transmitting the high-level signal VGH to the control electrode N5 of the seventh transistor T7, which then turns off. The second clock signal CK2 transitions to a high-level signal VGH, turning off the eleventh transistor T11. Since the second control terminal N2 maintains a low-level signal VGL and the eleventh transistor T11 is off, the first electrode N6 of the twelfth transistor T12 maintains a level signal VGL-Vth. The tenth transistor T10 is turned on, transmitting the high-level signal VGH to the first control terminal N1. Therefore, the potential VN1 of the first control terminal N1 is a high-level signal VGH, and the eighth transistor T8 and the fifth transistor T5 are off. Thus, in the tenth stage t10, the potentials of each important node are VN1 = VN5 = VGH, VN4 = VN6 = VGL-Vth, VN3 = 2*VGL-Vth-VGH, VN2 is at an ultra-low level, and VN2 is close to VN3.

[0104] The subsequent stages are a cycle of stage 9 (t9) and stage 10 (t10), which will not be elaborated here.

[0105] In another implementation, Figure 6 The first voltage signal VG1 is a low-level signal VGL, and the second voltage signal VG2 is a high-level signal VGH. Figure 8 yes Figure 6 The corresponding timing diagram, optionally, can be referenced. Figure 6 and Figure 8 The operation of the gate drive circuit includes the following stages.

[0106] In the first stage t1', the input signal EIN is a low-level signal VGL, and the sixth transistor T6 is turned off; the first clock signal CK1 is a low-level signal VGL, the potential VN5 of the control electrode N5 of the seventh transistor T7 is a low-level signal VGL, the seventh transistor T7 is turned off, the potential VN1 of the first control terminal N1 is a low-level signal VGL, and the eighth transistor T8 is turned off. The second clock signal CK2 is a high-level signal VGH, the eleventh transistor T11 is turned on, the input signal EIN is transmitted to the second control terminal N2, the potential VN2 of the second control terminal N2 is a low-level signal VGL, the potential VN6 of the first electrode N6 of the twelfth transistor T12 is also a low-level signal VGL, and the ninth transistor T9 is turned off. The potential VN1 of the first control terminal N1 is a low-level signal VGL, so the fifth transistor T5 is turned off. The second clock signal CK2 is a high-level signal VGH, the first transistor T1 is turned on, transmitting the input signal EIN to the internal node N3. The potential VN3 of the internal node N3 is a low-level signal VGL, so the third transistor T3 and the fourth transistor T4 are turned off, and the potential VN4 of the second terminal N4 of the first capacitor C1 is a low-level signal VGL. Therefore, in the first stage t1', the potentials of each node are VN1=VN2=VN3=VN4=VN5=VN6=VGL, the eighth transistor T8 and the ninth transistor T9 are both turned off, and the output terminal OUT maintains the voltage of the previous moment, continuing to output the high-level signal VGH.

[0107] In the second stage t2', the input signal EIN remains low (VGL), and the sixth transistor T6 remains off. The second clock signal CK2 transitions to low (VGL), the eleventh transistor T11 turns off, and the potential VN2 of the second control terminal N2 and the potential VN6 of the first terminal N6 of the twelfth transistor T12 remain low (VGL). The first transistor T1 turns off, and the potential VN3 of the internal node N3 remains low (VGL). The first clock signal CK1 transitions to high (VGH), which is coupled to the control terminal N5 of the seventh transistor T7 through the third capacitor C3. When the potential of the control terminal N5 of the seventh transistor T7 becomes VGH-Vth, the seventh transistor T7 turns on and outputs VGH-Vth, meaning the potential VN1 of the first control terminal N1 is VGH-Vth. The eighth transistor T8 turns on and outputs low (VGL), meaning the potential VOUT of the output terminal OUT transitions to low (VGL). Furthermore, when the second clock signal CK2 transitions to a low-level signal VGL, the first transistor T1 is turned off. When the potential VN1 of the first control terminal N1 is VGH-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second terminal N4 of the first capacitor C1 remains low-level signal VGL. The potential VN3 of the internal node N3 also remains unchanged at VGL. Therefore, in the second stage t2', the potentials of each important node are VN2=VN3=VN4=VN6=VGL, VN1=VN5=VGH-Vth, and VOUT=VGL. Here, Vth is the threshold voltage of the transistor.

[0108] In the third stage t3', the input signal EIN remains low (VGL), and the sixth transistor T6 remains off. The second clock signal CK2 transitions to high (VGH), and the potentials of the first terminal N6 (VN6) and the second control terminal N2 (VN2) of the twelfth transistor T12 become low (VGL). The first clock signal CK1 transitions to low (VGL), and the potential of the control terminal N5 of the seventh transistor T7 becomes low (VGL), turning off the seventh transistor T7. Due to the presence of the fourth capacitor C4, the potential VN1 of the first control terminal N1 is maintained, ensuring that VN1 remains VGH-Vth. The eighth transistor T8 turns on, outputting a low (VGL) signal, meaning the potential VOUT of the output terminal OUT remains low (VGL). The second clock signal CK2 becomes high (VGH), the first transistor T1 turns on, transmitting the input signal EIN to the internal node N3. The potential VN3 of the internal node N3 becomes low (VGL), thus turning off the third transistor T3 and the fourth transistor T4. When the potential VN1 of the first control terminal N1 is VGH-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second terminal N4 of the first capacitor C1 remains at a low level signal VGL. Therefore, in the third stage t3', the potentials of each important node are VN2=VN3=VN4=VN5=VN6=VGL, VN1=VGH-Vth, and VOUT=VGL.

[0109] The fourth stage t4' to the seventh stage t7' is a cycle of the second stage t2' and the third stage t3', which will not be elaborated here.

[0110] In stage 8, t8', the input signal EIN transitions to a high-level signal VGH, the sixth transistor T6 turns on, and transmits a low-level signal VGL to the control terminal N5 of the seventh transistor T7. The seventh transistor T7 turns off, and the fourth capacitor C4 maintains the potential VN1 of the first control terminal N1, VN1 = VGH - Vth. The eighth transistor T8 turns on and outputs a low-level signal VGL, VOUT = VGL. The second clock signal CK2 transitions to a low-level signal VGL, the eleventh transistor T11 turns off, and the potential VN6 of the first terminal N6 and the potential VN2 of the second control terminal N2 of the twelfth transistor T12 remain at a low-level signal VGL. The second clock signal CK2 transitions to a low-level signal VGL, the first transistor T1 turns off, and the potential VN3 of the internal node N3 is a low-level signal VGL, so the third transistor T3 and the fourth transistor T4 turn off. When the potential VN1 of the first control terminal N1 is VGH-Vth, the fifth transistor T5 is turned on, and the potential VN4 of the second terminal N4 of the first capacitor C1 remains at a low level signal VGL. Therefore, in the eighth stage t8', the potentials of each important node are VN2=VN3=VN4=VN5=VN6=VGL, VN1=VGH-Vth, and VOUT=VGL.

[0111] In the ninth stage t9', the first clock signal CK1 transitions to a low-level signal VGL, the input signal EIN becomes a high-level signal VGH, the sixth transistor T6 turns on, and transmits the low-level signal VGL to the control terminal N5 of the seventh transistor T7, while the seventh transistor T7 turns off. The second clock signal CK2 transitions to a high-level signal VGH, the eleventh transistor T11 turns on, and transmits the input signal EIN to the first terminal N6 of the twelfth transistor T12. The potential VN6 of the first terminal N6 of the twelfth transistor T12 becomes a high-level signal VGH-Vth, the tenth transistor T10 turns on, and transmits the low-level signal VGL to the first control terminal N1. Therefore, the potential VN1 of the first control terminal N1 becomes a low-level signal VGL, the eighth transistor T8 turns off, and the fifth transistor T5 turns off. The potential VN6 of the first terminal N6 of the twelfth transistor T12 is a high-level signal VGH. The twelfth transistor T12 transmits the high-level signal VGH-Vth to the second control terminal N2, and the potential VN2 of the second control terminal N2 becomes VGH-Vth. The ninth transistor T9 is turned on. After the ninth transistor T9 is turned on, it outputs a lower level, pulling the potential of the output terminal OUT low. Due to the coupling effect of the second capacitor C2, the charge stored in the second capacitor C2 remains unchanged. The second capacitor C2 couples and pulls the potential of the second control terminal N2 low, making the potential of the second control terminal N2 a super-high level (more efficient level). Furthermore, the second clock signal CK2 jumps to a high-level signal VGH, the first transistor T1 is turned on, and the first transistor T1 and the second transistor T2 transmit the high-level signal VGH of the input signal EIN to the internal node N3. The potential VN3 of the internal node N3 becomes VGH-Vth. The control electrode potential of the third transistor T3 is VGH-Vth, so the third transistor T3 is turned on. The potential of its second electrode is VGL. The second electrode N4 of the first capacitor C1 maintains a low-level signal VGL. Therefore, the voltage difference across the first capacitor C1 is VGH-Vth-VGL. The control electrode potential of the fourth transistor T4 is VGH-Vth, and the second electrode N2 of the fourth transistor T4 is at an ultra-high level (more effective level). The fourth transistor T4 does not meet the turn-on condition and is turned off. The potential of the internal node N3 will not be transmitted to the second control terminal N2. The ultra-high level (more effective level) potential of the second control terminal N2 allows the ninth transistor T9 to be fully turned on, enabling the ninth transistor T9 to immediately output a high-level signal VGH. That is, the gate drive circuit can immediately output a high-level signal VGH, avoiding a step in the output gate drive signal. Therefore, in the ninth stage t9', the potentials of each important node are VN1 = VN4 = VN5 = VGL, VN2 is at an ultra-high level, VN3 = VN6 = VGH - Vth, and VOUT = VGH.

[0112] In the tenth stage t10', the first clock signal CK1 transitions to a high-level signal VGH. The third transistor T3 transmits the high-level signal VGH to the second terminal N4 of the first capacitor C1. The potential VN4 of the second terminal N4 of the first capacitor C1 is VGH-Vth, and the voltage difference across the first capacitor C1 is VGH-Vth-VGL. Therefore, the potential VN3 of the internal node N3 becomes VGH-Vth-VGL+VGH, i.e., VN3 = 2*VGH-Vth-VGL, which becomes an ultra-high level. Since the potential VN3 of the internal node N3 is ultra-high, if the potential of the second control terminal N2 increases due to the leakage of the twelfth transistor T12, the fourth transistor T4 turns on, allowing the ultra-high level of the internal node N3 to be transmitted to the second control terminal N2, thereby maintaining the ultra-high level of the second control terminal N2, ensuring that the ninth transistor T9 can be fully turned on, and ensuring that the gate drive circuit outputs a high-level signal VGH. When the input signal EIN is a high-level signal VGH, the sixth transistor T6 is turned on, transmitting the low-level signal VGL to the control electrode N5 of the seventh transistor T7, which then turns off. The second clock signal CK2 transitions to a low-level signal VGL, turning off the eleventh transistor T11. Since the second control terminal N2 maintains a high-level signal VGH and the eleventh transistor T11 is off, the first electrode N6 of the twelfth transistor T12 maintains a level signal VGH-Vth. The tenth transistor T10 is turned on, transmitting the low-level signal VGL to the first control terminal N1. Therefore, the potential VN1 of the first control terminal N1 is a low-level signal VGL, and the eighth transistor T8 and the fifth transistor T5 are off. Thus, in the tenth stage t10', the potentials of each important node are VN1 = VN5 = VGL, VN4 = VN6 = VGH-Vth, VN3 = 2*VGH-Vth-VGL, VN2 is at an extremely high level, and VN2 is close to VN3.

[0113] The subsequent stages are a cycle of the ninth stage t9' and the tenth stage t10', which will not be described in detail here.

[0114] This embodiment also provides a display panel. Figure 9 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 9The display panel includes multiple gate driving circuits 10 provided in any of the above embodiments. These multiple gate driving circuits 10 are cascaded. The input signal EIN of the nth-stage gate driving circuit 10 is provided by the output signal OUT of the (n-1)th-stage gate driving circuit 10, where n is a positive integer greater than or equal to 2. The input signal EIN of the first-stage gate driving circuit 10 can be provided by an external device. The display panel can be, for example, a display panel on a mobile phone, tablet, MP3 player, MP4 player, smartwatch, smart helmet, or other wearable device. Because the display panel of this embodiment includes the gate driving circuits provided in any of the above embodiments, the display panel of this embodiment has the same beneficial effects as the gate driving circuits provided in any of the above embodiments, and will not be described again here.

[0115] For example, such as Figure 9 As shown, the display panel also includes a first clock signal line CLK1 and a second clock signal line CLK2. The first clock signal line CLK1 is used to provide a first clock signal CK1 to the m-th stage gate driving circuit 10, and the second clock signal line CLK2 is used to provide a second clock signal CK2 to the m-th stage gate driving circuit 10. The first clock signal line CLK1 is also used to provide a second clock signal CK2 to the (m+1)-th stage gate driving circuit 10, and the second clock signal line CLK2 is used to provide a first clock signal CK1 to the (m+1)-th stage gate driving circuit 10. Here, m is a positive integer greater than or equal to 1, and m is an odd number.

[0116] For example, such as Figure 9 As shown, the display panel also includes multiple arrayed pixel circuits 20. The output terminal OUT of each stage gate drive circuit is connected to a row of pixel circuits 20 to control the transistors in the pixel circuits 20, thereby controlling the light emission timing or light emission duration of the light-emitting devices corresponding to the pixel circuits 20.

[0117] Figure 10 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 10 As shown, the pixel circuit 20 includes a data writing transistor M1, a threshold compensation transistor M2, a driving transistor M3, a first initialization transistor M4, a second initialization transistor M5, a first light-emitting control transistor M6, a second light-emitting control transistor M7, and a storage capacitor Cst. The pixel circuit 20 is connected to the light-emitting device 30. The light-emitting device 30 includes a light-emitting diode (OLED). Figure 10As shown, the control electrode of data writing transistor M1 is connected to the first scan line S1, the first electrode of data writing transistor M1 is connected to the data line Data, and the second electrode of data writing transistor M1 is electrically connected to the first electrode of driving transistor M3. The first electrode of threshold compensation transistor M2 is electrically connected to the second electrode of driving transistor M3, the second electrode of threshold compensation transistor M2 is electrically connected to the control electrode of driving transistor M3, and the control electrode of threshold compensation transistor M2 is connected to the first scan line S1. The control electrode of first initialization transistor M4 is connected to the second scan line S2, the first electrode of first initialization transistor M4 is connected to the initialization line Vref, and the second electrode of first initialization transistor M4 is electrically connected to the control electrode of driving transistor M3. The control electrode of second initialization transistor M5 is connected to the second scan line S2, the first electrode of second initialization transistor M5 is connected to the initialization line Vref, and the second electrode of second initialization transistor M5 is electrically connected to the anode of light-emitting diode OLED. The control electrode of first light-emitting control transistor M6 is connected to the light-emitting control line EM, the first electrode of first light-emitting control transistor M6 is connected to the first power supply VDD, and the second electrode of first light-emitting control transistor M6 is electrically connected to the first electrode of driving transistor M3. The control electrode of the second light-emitting control transistor M7 is connected to the light-emitting control line EM. The first electrode of the second light-emitting control transistor M7 is electrically connected to the second electrode of the driving transistor M3. The second electrode of the second light-emitting control transistor M7 is electrically connected to the anode of the light-emitting diode OLED. The cathode of the light-emitting diode OLED is connected to the second power supply VSS. The storage capacitor Cst is connected between the first power supply VDD and the control electrode of the driving transistor M3. The driving process of the pixel circuit 20 includes the following stages:

[0118] During the initialization phase, the second scan line S2 provides an active level (second level) to the first initialization transistor M4 and the second initialization transistor M5, turning both transistors on. The first scan line S1 provides an inactive level (first level) to the data write transistor M1 and the threshold compensation transistor M2, turning both transistors off. The light emission control line EM provides an inactive level (first level) to the first light emission control transistor M6 and the second light emission control transistor M7, turning both transistors off. The first initialization transistor M4 transmits the initialization signal on the initialization line Vref to the control electrode of the driving transistor M3, initializing the control electrode of the driving transistor M3. The second initialization transistor M5 transmits the initialization signal on the initialization line Vref to the anode of the light-emitting diode OLED, initializing the anode of the light-emitting diode OLED.

[0119] During the data writing and threshold compensation phase, the first scan line S1 provides an active level (second level) to the data writing transistor M1 and the threshold compensation transistor M2, turning both transistors on. The second scan line S2 provides an inactive level (first level) to the first initialization transistor M4 and the second initialization transistor M5, turning both transistors off. The light emission control line EM provides an inactive level (first level) to the first light emission control transistor M6 and the second light emission control transistor M7, turning both transistors off. The data writing transistor M1 writes the data voltage on the data line Data to the control electrode of the driving transistor M3 via the driving transistor M3 and the threshold compensation transistor M2, while the threshold compensation transistor M2 performs threshold compensation on the driving transistor M3.

[0120] During the light-emitting phase, the first scan line S1 provides an invalid level (first level) to the data writing transistor M1 and the threshold compensation transistor M2, turning off both transistors. The second scan line S2 provides an invalid level (first level) to the first initialization transistor M4 and the second initialization transistor M5, turning off both transistors. The light-emitting control line EM provides an active level (second level) to the first light-emitting control transistor M6 and the second light-emitting control transistor M7, turning both transistors on. The first power supply VDD, the first light-emitting control transistor M6, the driving transistor M3, the second light-emitting control transistor M7, the light-emitting diode OLED, and the second power supply VSS form a current loop. The light-emitting diode OLED emits light in response to the driving current generated by the driving transistor M3.

[0121] In the pixel circuit driving process described above, the effective level (second level) and ineffective level (first level) provided by the first scan line S1, the second scan line S2, and the light emission control line EM can be provided by the gate driving circuit provided in any of the above embodiments. Since the timing of the first scan line S1, the second scan line S2, and the light emission control line EM are different, the first scan line S1, the second scan line S2, and the light emission control line EM corresponding to the same pixel circuit can be connected to different gate driving circuits. The gate driving circuit provided in any of the above embodiments can guarantee an effective output level (second level), and the effective level (second level) is the same as the second voltage signal. By using the gate driving circuit provided in any of the above embodiments to provide effective levels (second level) and ineffective levels (first level) to the transistors of the pixel circuit, the conduction and turn-off of the transistors can be accurately controlled, ensuring the accuracy of the driving current generated by the pixel circuit.

[0122] It should be noted that, Figure 10The diagram only shows the case where all transistors in the pixel circuit are P-type transistors, but it is not limiting. All transistors in the pixel circuit can also be N-type transistors. The pixel circuit can have some P-type transistors and others N-type transistors. It is known that the effective level of the P-type transistor is a low-level signal VGL, and the gate drive signal of the P-type transistor is provided by the gate drive circuit whose output effective level is the low-level signal VGL. The effective level of the N-type transistor is a high-level signal VGH, and the gate drive signal of the N-type transistor is provided by the gate drive circuit whose output effective level is the high-level signal VGH.

[0123] It should also be noted that, in the above embodiments, the first electrode of each transistor can be the source or the drain, and correspondingly, the second electrode can be the drain or the source.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: A first input module and a second output module are connected to a second control terminal of the second output module. The first input module is used to transmit an input signal to the second control terminal based on a second clock signal. The second output module is used to output a second voltage signal when it is turned on. A coupling control module, electrically connected to the second control terminal, is used to couple and control the potential of the second control terminal based on the transition from a first level to a second level of the first clock signal according to the second clock signal and the input signal, so that the output terminal of the gate drive circuit outputs a second voltage signal. The coupling control module includes: a first input unit, a first control unit, a first coupling unit, and a switching unit; The control terminal of the first input unit is connected to the second clock signal, the first terminal of the first input unit is connected to the input signal, and the second terminal of the first input unit is connected to the internal node of the coupling control module. The first input unit is used to transmit the second level of the input signal to the internal node when the second clock signal is at the second level; wherein, the internal node is the first terminal of the first coupling unit. The control terminal of the first control unit is connected to the internal node, the first terminal of the first control unit is connected to the first clock signal, and the second terminal of the first control unit is connected to the second terminal of the first coupling unit. The first control unit is used to couple the potential of the internal node when the first clock signal changes from a first level to a second level. The control terminal and the first terminal of the switching unit are both connected to the internal node, and the second terminal of the switching unit is connected to the second control terminal. The switching unit is used to transmit the potential of the internal node after coupling to the second control terminal when the potential difference between the second control terminal and the internal node meets the conduction condition of the switching unit.

2. The gate driving circuit according to claim 1, characterized in that, The second level pulse of the second clock signal overlaps with the second level pulse of the input signal; the coupling control module is used to transmit the second level of the input signal to the internal node of the coupling control module when the second clock signal is at the second level, and to couple the potential of the internal node when the first clock signal changes from the first level to the second level, and transmit the coupled potential to the second control terminal; Wherein, the second level is the same as the second voltage signal, and the first level is the same as the first voltage signal.

3. The gate driving circuit according to claim 1, characterized in that, Also includes: A first control module and a first output module are provided. The first control module is connected to a first control terminal of the first output module. The first control module is used to control the potential of the first control terminal based on the input signal, the first voltage signal and the first clock signal. The first output module is used to turn on when the potential of the first control terminal is at a second level, so as to output the first voltage signal when it is turned on.

4. The gate driving circuit according to claim 3, characterized in that, The coupling control module further includes: a second control unit; The control terminal of the second control unit is connected to the first control terminal. The first terminal of the second control unit is connected to the first voltage signal. The second terminal of the second control unit is connected to the second terminal of the first coupling unit. The second control unit is used to transmit the first voltage signal to the second terminal of the first coupling unit when the potential of the first control terminal is at the second level.

5. The gate driving circuit according to claim 4, characterized in that, The first input unit includes a first transistor and a second transistor; The control electrode of the first transistor is connected to the second clock signal, and the first electrode of the first transistor is connected to the input signal. The control electrode of the second transistor is connected to the second voltage signal, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the internal node; And / or, the first coupling unit includes a first capacitor, the first electrode of the first capacitor is the internal node, and the second electrode of the first capacitor is the second end of the first coupling unit; And / or, the first control unit includes a third transistor, the control electrode of the third transistor is electrically connected to the internal node, the first electrode of the third transistor is connected to the first clock signal, and the second electrode of the third transistor is electrically connected to the second terminal of the first coupling unit; And / or, the switching unit includes a fourth transistor, the control electrode and the first electrode of the fourth transistor are both electrically connected to the internal node, and the second electrode of the fourth transistor is electrically connected to the second control terminal; And / or, the second control unit includes a fifth transistor, the control electrode of the fifth transistor being electrically connected to the first control terminal, the first electrode of the fifth transistor being connected to the first voltage signal, and the second electrode of the fifth transistor being electrically connected to the second terminal of the first coupling unit.

6. The gate driving circuit according to claim 1, characterized in that, Also includes: A coupling module is connected between the output terminal and the second control terminal, and is used to couple the potential of the second control terminal according to the potential change of the output terminal.

7. The gate driving circuit according to claim 6, characterized in that, The coupling module includes a second capacitor; The second capacitor is connected between the output terminal and the second control terminal.

8. The gate driving circuit according to claim 4, characterized in that, Also includes: The node mutual control module is connected to the first control terminal and the second control terminal respectively, and is used to transmit the first voltage signal to the first control terminal in response to the potential of the second control terminal.

9. The gate driving circuit according to claim 8, characterized in that, The first control module includes: The sixth transistor has its control electrode connected to the input signal and its first electrode connected to the first voltage signal. A seventh transistor and a third capacitor are provided. The control electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor. The first electrode of the seventh transistor is connected to the first clock signal, and the second electrode of the seventh transistor is electrically connected to the first control terminal. The third capacitor is connected between the control electrode of the seventh transistor and the first electrode of the seventh transistor. And / or, the first output module includes: a fourth capacitor and an eighth transistor; The fourth capacitor is connected between the control electrode of the eighth transistor and the first electrode of the eighth transistor; The control electrode of the eighth transistor is electrically connected to the first control terminal, and the second electrode of the eighth transistor is connected to the output terminal; And / or, the second output module includes a ninth transistor; the control electrode of the ninth transistor is electrically connected to the second control terminal, the first electrode of the ninth transistor is connected to the second voltage signal, and the second electrode of the ninth transistor is the output terminal of the gate drive circuit.

10. A display panel, characterized in that, include: The gate drive circuit according to any one of claims 1-9.

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