Memory device and its multi-pass programming operation

Abstract

In certain aspects, a memory device includes an array of memory cells having a plurality of rows of memory cells, word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the array of memory cells by the word lines. Each memory cell is configured to store a segment of N bits of data in one of 2 N levels, where N is an integer greater than 1. The level corresponds to one of 2 N segments of N bits of data. The peripheral circuit is configured to program a row of target memory cells in a first pass to each of the row of target memory cells to one of 2 N / m intermediate levels based on a segment of N bits of data to be stored in the target memory cells, where m is an integer greater than 1. The peripheral circuit is further configured to program the row of target memory cells in a second pass after the first pass to each target memory cell to one of 2 N levels based on the segment of N bits of data to be stored in the target memory cells.

Description

[0001] This application is a divisional application of the same patent application, filed on March 30, 2021, with application number 202180001045.9. Background Technology

[0002] This disclosure relates to storage devices and methods of operating thereof.

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as reading, programming (writing), and erasing, thereby changing the threshold voltage of each memory cell to a desired level. For NAND flash memory, erase operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0004] In one aspect, a storage device includes: a memory cell array having multiple rows of memory cells; multiple word lines respectively coupled to the multiple rows of memory cells; and peripheral circuitry coupled to the memory cell array via the word lines. Each memory cell is configured to store an N-bit data segment in 2... N In the levels of , where N is an integer greater than 1, level 2 corresponds to 2. N The peripheral circuitry is configured to program one row of target memory cells in a multi-row memory cell in the first pass, thereby programming each of the target memory cells in that row to 2 bits based on the N-bit data segment stored in the target memory cell. N / m intermediate levels, where m is an integer greater than 1. The peripheral circuitry is also configured to program the target memory cell in the row in a second pass after the first pass, thereby programming each of the target memory cells in the row to 2 based on the N-bit data segment stored in the target memory cell. N The level within the level.

[0005] In another aspect, a system includes a storage device configured to store data and a storage controller coupled to the storage device and configured to control the storage device. The storage device includes: a storage cell array having multiple rows of storage cells; multiple word lines respectively coupled to the multiple rows of storage cells; and peripheral circuitry coupled to the storage cell array via the word lines. Each storage cell is configured to store an N-bit data segment in 2... N In the level of , N is an integer greater than 1. This level corresponds to 2. NThe peripheral circuitry is configured to program one target memory cell in a row of multiple rows of memory cells in the first pass, thereby programming each of the target memory cells in that row to 2 bits based on the N-bit data segment stored in the target memory cell. N / m intermediate levels, where m is an integer greater than 1. The peripheral circuitry is also configured to program the target memory cell in the row in a second pass after the first pass, thereby programming each of the target memory cells in the row to 2 based on the N-bit data segment stored in the target memory cell. N The level within the level.

[0006] In another aspect, a method for operating a storage device is provided. The storage device includes a memory cell array having multiple rows of memory cells and multiple word lines respectively coupled to the multiple rows of memory cells. In a first pass, a target memory cell in one row of the multiple rows of memory cells is programmed, thereby based on 2... N The N-bit data segment to be stored in the target memory cell will be programmed into 2 bits for each of the N-bit data segments in the target memory cell. N In the intermediate levels of / m intermediate levels, where N and m are both integers greater than 1. In the second pass after the first pass, the target memory unit of the row is programmed, thereby programming each of the target memory units in the row to 2 based on the N-bit data segment stored in the target memory unit. N Within each level. 2 N Each level corresponds to 2 N N-bit data segments. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0008] Figure 1 A block diagram of an exemplary system having storage devices according to some aspects of this disclosure is shown.

[0009] Figure 2A An illustration of an exemplary memory card having a storage device according to some aspects of this disclosure is shown.

[0010] Figure 2B An illustration of an exemplary solid-state drive (SSD) having a storage device according to some aspects of this disclosure is shown.

[0011] Figure 3 A schematic diagram of an exemplary storage device including peripheral circuitry according to some aspects of this disclosure is shown.

[0012] Figure 4A side view of a cross section of an exemplary memory cell array including NAND memory strings is shown, according to some aspects of this disclosure.

[0013] Figure 5 A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0014] Figure 6 The threshold voltage distribution of memory cells during programming operations is shown according to some aspects of this disclosure.

[0015] Figure 7 A block diagram of an exemplary page buffer in programming operation is shown, according to some aspects of this disclosure.

[0016] Figure 8A and Figure 8B The waveform of the word line voltage applied to a selected word line during multiple programming operations is shown.

[0017] Figure 9 The threshold voltage distribution of memory cells during multiple programming operations is shown.

[0018] Figure 10 An exemplary waveform of the word line voltage applied to a selected word line during a multi-pass programming operation is shown, according to some aspects of this disclosure.

[0019] Figure 11 An exemplary threshold voltage distribution of a memory cell in a multi-pass programming operation is shown according to some aspects of this disclosure.

[0020] Figure 12 A flowchart of an exemplary method for operating a storage device according to some aspects of this disclosure is shown.

[0021] Figure 13 A flowchart is shown for another exemplary method for operating a storage device according to some aspects of this disclosure.

[0022] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0023] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Accordingly, other constructions and arrangements may be used without departing from the scope of this disclosure. Moreover, this disclosure may be used in a wide variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with each other, and may be combined, adjusted, and modified in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0024] Generally, terms can be understood at least in part based on their use in context. For example, at least in part based on context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, at least in part based on context, terms such as "a" or "described" can also be understood to express either a singular or a plural usage. Additionally, at least in part based on context, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily clearly described.

[0025] Storage devices (e.g., NAND flash memory devices) can store more than one bit of information across multiple levels (aka states) of memory cells to increase storage capacity and reduce cost per bit. In programming operations, data can be programmed (written) into xLCs such as Multi-Level Cell (MLC), Three-Level Cell (TLC), Quadruple-Level Cell (QLC), etc. For xLCs (e.g., for QLCs), multi-pass programming operations can be used to reduce programming time and increase read margin. These multi-pass programming operations involve a coarse programming pass that programs the xLC to one of the intermediate levels, and a fine programming pass that programs the xLC from the intermediate level to the final level. For example, for QLC, there are two schemes with two-pass programming operations: the 8-16 scheme, in which the memory cells are first programmed into 8 stages in coarse programming, and then programmed into 16 stages in fine programming; and the 16-16 scheme, in which the memory cells are first programmed into 16 stages in coarse programming, and then the memory cells are reprogrammed in fine programming to form 16 stages with a smaller threshold voltage range.

[0026] Compared to the 8-16 scheme, the 16-16 scheme typically offers a larger read margin and shorter read time. However, the 16-16 scheme requires 15 coarse verification voltages in the coarse programming pass to verify 16 stages individually, making it slower than the 8-16 scheme with a similar number of programming cycles, since the 8-16 scheme only needs to verify 8 stages in the coarse programming pass. In other two... N -2 N The same problem may arise in the scheme, where N represents the number of data bits stored in each storage unit (e.g., N=4, for a 16-16 scheme for QLC).

[0027] To address one or more of the aforementioned problems, the present disclosure introduces a solution in which multiple intermediate levels in the coarse programming pass of a multi-pass programming operation can be merged into one intermediate level, so that the number of required verification voltages and the associated duration in the coarse programming pass can be reduced, thereby increasing the programming speed. In some implementations, memory cells programmed with different data segments (e.g., having different Gray code values) are grouped and verified simultaneously using the same verification voltage, which is in contrast to using multiple verification voltages at different times. Therefore, the multi-pass programming operation scheme disclosed herein can improve the known 2 N -2 N scheme (e.g., a 16-16 scheme, where N=4 for QLC) in terms of programming speed, while maintaining a larger read margin and shorter read time compared to the corresponding 2 n -2 N scheme (where n<N, for example, n=N-1).

[0028] Figure 1 shows a block diagram of an exemplary system 100 having a memory device in accordance with some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As Figure 1 shown in, the system 100 may include a host 108 and a storage system 102, and the storage system 102 has one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of the electronic device, for example, a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104.

[0029] The memory device 104 may be any memory device disclosed in the present disclosure. As disclosed in detail below, the memory device 104 (e.g., a NAND flash memory device) may perform a multi-pass programming operation, in which multiple intermediate levels in the coarse programming pass can be grouped and merged into one intermediate level, thereby reducing the verification duration and increasing the programming speed. Consistent with the scope of the present disclosure, in the multi-pass programming operation, according to some implementations, memory cells programmed with different data segments (e.g., having different Gray code values) are grouped and verified simultaneously using the same verification voltage, which is in contrast to using multiple verification voltages at different times.

[0030] According to some embodiments, a storage controller 106 is coupled to a storage device 104 and a host 108 and is configured to control the storage device 104. The storage controller 106 can manage data stored in the storage device 104 and communicate with the host 108. In some embodiments, the storage controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the storage controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. The storage controller 106 can be configured to control the operation of the storage device 104, such as read, erase, and program operations. Storage controller 106 may also be configured to manage various functions related to data stored or to be stored in storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, storage controller 106 is also configured to process error correction codes (ECC) related to data read from or written to storage device 104. Storage controller 106 may also perform any other suitable functions, such as formatting storage device 104. Storage controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, storage controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), Firewire, etc.

[0031] The storage controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the storage controller 106 and a single storage device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2B In another example shown, storage controller 106 and multiple storage devices 104 can be integrated into SSD 206. SSD 206 may also include a connection between SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is higher than that of the memory card 202.

[0032] Figure 3 A schematic circuit diagram of an exemplary storage device 300 including peripheral circuitry according to some aspects of this disclosure is shown. The storage device 300 may be... Figure 1 An example of memory device 104 is shown. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, all extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0033] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a threshold voltage within a first range, and a second storage state "1" may correspond to a threshold voltage within a second range. In some implementations, each storage cell 306 is an xLC capable of storing more than one bit of data in four or more storage states (levels). For example, an xLC may be capable of storing two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC may be programmed to assume a range of possible nominal storage values ​​(i.e., 2). N (A segment of N-bit data, e.g., Gray code). In one example, an MLC can be programmed from an erased state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erased state.

[0034] like Figure 3 As shown, each NAND flash memory string 308 may further include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate a selected NAND flash memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND flash memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 308 is coupled to a corresponding bit line 316, enabling data to be read from or written to the corresponding bit line 316 via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection or deselection voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a selection or deselection voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0035] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, each of which may have a common source line 314, for example, coupled to an ACS (Acoustic Processing Unit). In some embodiments, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block 304, the source lines 314 coupled to the selected block 304 and unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers) (e.g., a high positive bias voltage (e.g., 20V or higher)). Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for read and program operations. The bit-sized size of a page 320 can involve the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0036] Figure 4 A side view of a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0037] The memory stack 404 may include alternating gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306, the gate of a DGS transistor 312, or the gate of an SSG transistor 310, and may extend laterally as a DSG line 313 at the top of the memory stack 404, an SSG line 315 at the bottom of the memory stack 404, or a word line 318 between DSG lines 313 and SSG lines 315.

[0038] like Figure 4 As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack layer 404. In some embodiments, the channel structure 412 includes channel vias filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, for example, polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a memory layer 424 (also referred to as a "charge trap / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a columnar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, memory layer 424, and barrier layer 422 are arranged radially from the center of the column toward the outer surface. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 424 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0039] According to some implementation methods, such as Figure 4As shown, a well 414 (e.g., a P-well and / or an N-well) is formed in substrate 402, and the source terminal of the NAND memory string 308 contacts the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that, although Figure 4 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line slits / source contacts, local contacts, interconnect layers, etc.

[0040] Re-reference Figure 3 Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0041] Page buffer / sensor amplifier 504 can be configured to read and program (write) data from and to memory cell array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal representing a data bit stored in memory cell 306 from bit line 316 during a read operation and amplify a small voltage swing to a recognizable logic level. As detailed below and consistent with the scope of this disclosure, during a programming operation, page buffer / sensor amplifier 504 may include a storage module (e.g., latch, cache, register, etc.) for temporarily storing a segment of N-bit data (e.g., in Gray code form) received from data bus 518 and using 2 N -2 N In each programming pass of the multi-pass programming operation, the N-bit data segment is provided to the corresponding target storage unit 306 via the corresponding bit line 316.

[0042] The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and to select one or more NAND memory strings 308 by applying bit line voltages generated by the voltage generator 510. The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect block 304 of the memory cell array 301 and to select / deselect word lines 318 of block 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated by the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 301.

[0043] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer data from the host (e.g., ...). Figure 1 The interface 516 receives control commands from the control logic unit 512 and forwards them to the control logic unit 512, and buffers status information received from the control logic unit 512 and forwards it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory cell array 301.

[0044] Figure 6 The threshold voltage distribution of memory cells during programming operation is shown according to some aspects of this disclosure. As described above, each memory cell 306 can be configured to... N One level in a series of levels stores an N-bit data segment, where N is an integer greater than 1 (e.g., N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). Each level can correspond to 2 of the storage units 306. N One of the threshold voltage (Vth) ranges. When considering a multi-pass programming operation where memory cell 306 can be programmed into an intermediate level starting in a coarse programming pass, the "level" mentioned herein can be considered as the final level after the fine programming pass of the multi-pass programming operation, in contrast to the intermediate level. Taking a QLC (where N = 4) as an example, as... Figure 6 As shown, memory cell 306 can be programmed into one of 16 levels, including one level for an erase state and 15 levels for a programmed state. Each level can correspond to a specific threshold voltage (Vth) range for memory cell 306. For example, corresponding to the lowest threshold voltage range (Vth). Figure 6 The leftmost threshold voltage distribution in the diagram can be considered level 0, corresponding to the second lowest threshold voltage range. Figure 6 The level of the second-leftmost threshold voltage distribution in the diagram can be considered level 1, and so on up to the level corresponding to the highest threshold voltage range ( Figure 6 Level 15 of the rightmost threshold voltage distribution in the model.

[0045] On the other hand, each level can correspond to 2 N The N-bit data segment from the N-bit data segments will be stored in the target storage unit 306. In some embodiments, 2 NAn N-bit data segment can be represented by Gray code (in Gray code form). Gray code (also known as reflected binary code (RBC) or reflected binary code (RB)) is an ordering of binary numbers such that successive values ​​differ only in one bit (binary digit). For example, Table 1 below shows the representation of... Figure 6 The example uses a binary code illustrating a one-to-one mapping between 16 levels (Lvl 0 to Lvl 15) and 16 4-bit data segments. As shown in Table 1, each 4-bit data segment can consist of bits (b1, b2, b3, and b4) of four binary values. In one example, level 1 could correspond to a 4-bit data segment with the value 1111. In another example, level 15 could correspond to another 4-bit data segment with the value 1110.

[0046] Table 1

[0047] b1 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 b2 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 b3 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 b4 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0

[0048] Also refer to Figure 5 In programming operations, N pages of N-bit data transmitted via data bus 518 can be temporarily stored in page buffer / sensor amplifier 504, and page buffer / sensor amplifier 504 can be configured to provide the corresponding N-bit data segment to each target memory cell 306 via the corresponding bit line 316. For example, Figure 7 A block diagram of an exemplary page buffer / sensor amplifier 504 in programming operation according to some aspects of this disclosure is shown. In some embodiments, the page buffer / sensor amplifier 504 includes N memory modules (e.g., latches and / or caches), each memory module being configured to temporarily store one page of data from N pages of data. That is, N bits of data (with 2^N bits) of data stored in page 320 of the target memory cell 306 coupled to the selected word line 318. N In programming operations, a single value can be transmitted, stored, and provided as N pages of N bits of data.

[0049] Still using QLC (where N=4) as an example, such as Figure 7As shown therein, the page buffer / sense amplifier 504 may include 4 storage modules 702 (P1, P2, P3, and P4), each configured to temporarily store 4-bit data of one page among 4 pages of 4-bit data. Each storage module 702 may include i storage units 704 (e.g., registers) corresponding to i target storage units 306 of the page 320 of the storage units 306 coupled to the selected word line 318 in a programming operation. That is, each target storage unit 306 may be coupled to a corresponding set of four storage units 704 from each of the four storage modules 702 (P1, P2, P3, and P4) via a respective bit line 316 (BL_1, BL_2, ..., BL_i-1, or BL_i). For each target storage unit 306 in a programming operation, four bits of binary values in the corresponding 4-bit data segment (e.g., b1, b2, b3, and b4 according to the Gray code in Table 1) may be temporarily stored in the four storage units 704 of the corresponding set respectively, such that the corresponding 4-bit data segment may be provided to the target storage unit 306 via the page buffer / sense amplifier 504.

[0050] In a multi-pass programming operation, in a fine programming pass (e.g., the last programming pass that programs each target storage unit 306 to the final level), each target storage unit 306 may be programmed to 2 based on the corresponding N-bit data to be stored in the target storage unit 306 N one of the levels. As for a coarse programming pass (e.g., any non-final programming pass that programs each target storage unit to an intermediate level), according to some embodiments, each target storage unit 306 is programmed to 2 based on the corresponding n-bit data to be stored in the target storage unit 306 n one of the levels (where n<N). For example, for the 8-16 scheme described above, in a coarse programming pass, the target storage unit 306 may be programmed to 8 levels (where n=3<4) based on 3 bits of the 4-bit data to be stored in each target storage unit 306, which is in contrast to 16 levels. In other words, for an 8-16 scheme or any 2 n -2 N scheme, in a coarse programming pass (e.g., a non-final programming pass), the target storage unit 306 may be programmed using only some pages (n pages) of the N pages of N-bit data.

[0051] On the contrary, as described herein in connection with the 2 N -2 N scheme, according to some embodiments, in a coarse programming pass (e.g., a non-final programming pass), the target storage unit 306 may be programmed to 2 based on the corresponding N-bit data to be stored in each target storage unit 306 NIn one of the levels. For example, for the 16-16 scheme described above, in the coarse programming pass, the target memory cell 306 can be programmed into 16 levels (where N=4) based on all the 4 bits of data to be stored in each target memory cell 306, which contrasts with 8 levels. In other words, for the 16-16 scheme or any 2 N -2 N The scheme allows programming of target memory cell 306 using all pages of N pages of N-bit data in a coarse programming pass (e.g., not the final programming pass). (Compared to 2) n -2 N Compared to the previous plan, 2 N -2 N The solution can increase read margin and reduce read time.

[0052] To perform the programming operation, in addition to the page buffer / sensor amplifier 504 providing the corresponding N-bit data segment to each target memory cell 306, the row decoder / word line driver 508 can be configured to apply programming and verification voltages to selected word lines 318 coupled to a row of target memory cells 306 in one or more programming / verification cycles, thereby raising the threshold voltage of each target memory cell 306 to a desired level (entering the desired threshold voltage range) based on the corresponding N-bit data segment. For example, Figure 8A and Figure 8B The waveform of the word line voltage applied to a selected word line during multiple programming operations is shown. For example... Figure 8A As shown, the multi-pass programming operation includes at least a first pass 802a (also known as a coarse programming pass, e.g., a non-last programming pass) and a second pass 802b (also known as a fine programming pass, e.g., a last programming pass) following the first pass 802a. The first pass 802a includes one or more programming / verification loops 804a, and the second pass 802b also includes one or more programming / verification loops 804b.

[0053] like Figure 8B As shown, in each programming / verification cycle 804, whether in the first pass 802a or the second pass 802b, a programming voltage (Vpgm) is applied to the selected word line, followed by several verification voltages (Vvf) with increasing voltage levels. For 2 N -2 N In the first pass of 802a, the number of verification voltages in each programming / verification loop 804 is the same as in the second pass of 802b, i.e., 2. N -1, thus verifying the 2 corresponding to N bits of data. N All 2 possible values N A possible intermediate level. Still using QLC (where N = 4) as an example, such as... Figure 9As shown, in the first pass 802a, the target memory cell is first programmed into one of the 16 intermediate stages by applying 15 verification voltages between two adjacent intermediate stages. In the second pass 802b, the threshold voltage of the target memory cell in each stage (e.g., in the programmed state) is shifted upwards to the corresponding final stage with a reduced threshold voltage distribution width (i.e., a narrower range) by applying a larger programming voltage. The number of verification voltages (and corresponding verification processes) in each programming / verification cycle 804 in each of the first pass 802a and the second pass 802b is the same, i.e., 15. As a contrast, for 2 n -2 N In the first pass of 802a, the number of verification voltages in each programming / verification loop of 804 is smaller than that in the second pass of 802b, i.e., 2. n -1, thus verifying the 2 corresponding to the n bits in N-bit data. n There are two possible intermediate stages. Therefore, due to the increased verification voltage in the first pass of 802a, thus 2 N -2 N Option 2 n -2 N The solution involves longer programming time and slower programming speed.

[0054] Exploit 2 N -2 N The scheme features a large read margin, short read time, and 2 n -2 N The fast programming speed of the scheme is consistent with the scope of this disclosure. In multi-pass programming operations, according to some embodiments, target memory cells programmed with different data segments (e.g., different values ​​of Gray code) are grouped and verified simultaneously using the same verification voltage, which contrasts with using different verification voltages at different times. Therefore, multiple intermediate stages in coarse programming passes can be grouped and merged into one intermediate stage, thereby achieving the same fast programming speed as known 2 N -2 N The proposed solution reduces verification time and increases programming speed. Furthermore, it can still be based on 2... N N-bit data segments (e.g., 16 Gray code values ​​for QLC, where N=4) are used to program each target memory cell, which contrasts with a subset (n out of N) (e.g., 8 values ​​of 3-bit data for QLC, where n=3), thus compared with the known 2 n -2 N The plan still allows you to enjoy 2 N -2 N The solution offers advantages such as large read margin and short read time.

[0055] refer to Figure 3-5 According to some implementations, each storage unit 306 is configured to store an N-bit data segment in 2... N In one of the levels (final levels), where N is an integer greater than 1, this level can correspond to 2^N. N N-bit data segments in an N-bit data segment, for example, N-bit Gray code 2 N One of the values. To perform a multi-pass programming operation, the peripheral circuitry 302 can be configured to program a row of target memory cells 306 coupled to the selected word line 318 in the first pass (also known as a coarse programming pass, e.g., a non-final programming pass), thereby programming the target memory cells 306 to 2 based on the N-bit data segment to be stored in each target memory cell 306. N In one of m intermediate levels, where m is an integer greater than 1 (e.g., 2, 3, 4, 5, etc.). That is, the known 2... N -2 N Each of the m intermediate levels in the scheme is grouped into one intermediate level of the scheme disclosed herein. In some embodiments, the m intermediate levels are adjacent intermediate levels. An intermediate level may correspond to 2 of the target storage unit 306. N / m of the intermediate threshold voltage ranges, and 2 N Each of the m intermediate levels can correspond to 2 N m N-bit data segments out of N-bit data segments. That is, the number of intermediate levels (and corresponding intermediate threshold voltage ranges) can be reduced by a factor of m. In some implementations, target storage cells 306 corresponding to m different Gray code values ​​are programmed into the same intermediate level in a coarse programming pass, contrasting with m different intermediate levels. In one example, target storage cells 306 for storing values ​​1111 and 0111 in Table 1 can be programmed into the same intermediate level in a coarse programming pass, instead of being programmed into two different intermediate levels. In another example, target storage cells 306 for storing values ​​1001, 1101, 1100, and 1110 in Table 1 can be programmed into the same intermediate level in a coarse programming pass, instead of being programmed into four different intermediate levels.

[0056] In the known 2 n -2 N In the proposed scheme, the reduction in the number of intermediate levels stems from a reduction in the total data values ​​(and bits) used in the coarse programming pass (e.g., from N to n), unlike the scheme disclosed herein where the total data values ​​(and bits) used in the coarse programming pass remain the same (N), while the number of intermediate levels is 2. N The mapping relationship between N-bit data segments changes from one-to-one to one-to-m. Taking QLC (where N=4) as an example again, such as... Figure 11As shown in Table 2 below, two (m=2) intermediate levels can be grouped into one intermediate level, i.e., having the same intermediate level (Int Lvl) (the same intermediate threshold voltage range), so that the target memory cell 306 is initially programmed into one of eight intermediate levels (Int Lvl 0 to Int Lvl 7). As shown in Table 2, each intermediate level can correspond to a different value of a 4-bit Gray code, which contrasts with the known 16-16 scheme that corresponds to only one value of a 4-bit Gray code. Moreover, unlike the known 8-16 scheme where all eight intermediate levels correspond to one value of a 3-bit Gray code, as shown in Table 2, each of the eight intermediate levels can correspond to two values ​​of a 4-bit Gray code.

[0057] Table 2

[0058]

[0059] Figure 10 Exemplary waveforms of word line voltages applied to selected word lines during multiple programming operations, according to some aspects of this disclosure, are shown. Also, refer to... Figure 3-5 In some implementations, in order to program the target memory cell 306 in the first pass 1001, the row decoder / word line driver 508 is configured to apply a first programming voltage Vpgm 1 to the selected word line 318 in each programming / verification cycle 1002. It should be understood that the first pass 1001 may include one or more programming / verification cycles 1002 with different first programming voltages Vpgm 1, for example, using an incremental step pulse programming (ISPP) scheme. For ease of description, Figure 10 Only one programming / verification loop 1002 is shown. According to some implementations, in order to program the target memory cell 306 in the first pass 1001, the page buffer / sensor amplifier 504 is configured to pass the corresponding N-bit data segment (e.g., 2^N Gray code of N bits). N One of the values) is provided to each target storage unit 306. For example, when N=4, such as Figure 7 As shown, for each QLC under coarse programming, the page buffer / sensor amplifier 504 can provide a corresponding 4-bit data segment (e.g., 4-bit Gray code b1b2b3b4 in Table 2) from a corresponding set of 4 memory cells 704 in each of the 4 memory modules 702.

[0060] In some implementations, in order to program the row target memory unit 306 in the first pass 1001, the row decoder / word line driver 508 is configured to use a 2D-based... N / m intermediate levels (2 N / m)-1 verification voltage is used to verify the target memory cell 306 in this row. To verify 2 N / m intermediate level target storage unit 306, can use (2 N / m) - 1 verification voltage. For example, a target memory cell 306 in 8 intermediate stages (N=4 and m=2) can be verified using 7 verification voltages. By grouping m intermediate stages into one intermediate stage, for example, by changing the one-to-one mapping between intermediate stages and Gray code values ​​to a pair of m mappings, the number of verification voltages (and the number of verification processes) in each programming / verification loop 1002 in the first pass 1001 can be reduced from 2 N -1 (for example, Figure 8B (in) reduced to (2) N / m)-1 (For example, Figure 10 (in the middle).

[0061] like Figure 10 As shown, to verify the target memory cell 306, the row decoder / word line driver 508 can be configured to sequentially (2 N / m)-1 verification voltage (Vvf) is applied to the selected word line 318. In some implementations, (2 N Each of the / m)-1 verification voltages in 2 N Between two adjacent intermediate levels in a set of m intermediate levels. For example, when N=4, such as Figure 11 As shown, for each QLC undergoing coarse programming, only seven verification voltages, each between two adjacent intermediate stages, are needed to verify the target memory cell 306 in one of the eight intermediate stages. The target memory cells 306 corresponding to m N-bit data segments (e.g., different values ​​of Gray code but within the same intermediate stage) can be verified under the same or different conditions. The conditions may include, for example, specific programming / verification loops in multiple programming / verification loops 1002 within the first pass 1001, and conditions for determining whether verification passes (e.g., failure bit count specifications). In one example, the target memory cells 306 corresponding to different values ​​of Gray code but within the same intermediate stage can be verified within the same programming / verification loop 1002, or verification can begin in different programming / verification loops 1002. In another example, the target memory cells 306 corresponding to different values ​​of Gray code but within the same intermediate stage may have the same or different failure bit count specifications to determine whether verification passes (and thus stop programming those target memory cells 306 in the first pass 1001). In yet another example, target memory cells 306, which correspond to different values ​​of Gray code but are in the same intermediate level, can be configured to complete verification (and thus complete coarse programming of those target memory cells 306) in the same programming / verification cycle 1002 determined according to any appropriate conditions or in different programming / verification cycles 1002.

[0062] To perform multi-pass programming, the peripheral circuitry 302 can also be configured to program the row of target memory cells 306 in a second pass (also known as a fine-programming pass, e.g., the final programming pass), thereby programming the target memory cells 306 to 2 based on the N-bit data segments to be stored in each target memory cell 306. N In one of the levels (final levels). The level (final level) may correspond to the second level of the target storage unit 306. N One of the threshold voltage ranges (final threshold voltage ranges), and this final threshold voltage range can be higher than the intermediate threshold voltage range. That is, the threshold voltage range of the target memory cell 306 in the same intermediate level can be shifted upwards and split into m different final threshold voltage ranges through a second pass. The m N-bit data segments corresponding to the same intermediate level in the first pass can correspond to the 2 in the second pass. N There are m final stages out of 1 final stage. In some implementations, m final stages are 2^m. N Adjacent levels in each final level. Still using QLC (where N = 4) as an example, such as... Figure 11 As shown, the threshold voltage range of the target memory cell 306 in the same intermediate level can be shifted upwards and split into two adjacent final threshold voltage ranges (two adjacent final levels) through fine programming, thereby increasing the number of levels from 8 intermediate levels to 16 final levels. It should be understood that the final level in the erase state can be the same as the corresponding intermediate level.

[0063] In some implementations, in order to program the target memory cell 306 in the second pass 1003, the row decoder / word line driver 508 is configured to apply a second programming voltage Vpgm 2 to the selected word line 318 in each programming / verification cycle 1004. It should be understood that the second pass 1003 may also include one or more programming / verification cycles 1004 with different second programming voltages Vpgm 2 (e.g., also using an ISPP scheme). For ease of description, Figure 10 Only one programming / verification loop 1004 is shown. The second programming voltage Vpgm 2 can be higher than the first programming voltage Vpgm 1, thereby shifting the threshold voltage distribution upward as described above. According to some embodiments, in order to program the target memory cell 306 in the second pass 1003, the page buffer / sensing amplifier 504 is configured to pass the corresponding N-bit data segment (e.g., 2^N Gray code of the N-bit target memory cell 306) to the target memory cell 306 in the second pass 1003. N One of the values) is provided to each target storage unit 306. For example, when N=4, such as Figure 7As shown, for each QLC under coarse programming, the page buffer / sensor amplifier 504 can provide a corresponding 4-bit data segment (e.g., 4-bit Gray code b1b2b3b4 in Table 2) from a corresponding set of 4 memory cells 704 in each of the 4 memory modules 702.

[0064] In some implementations, in order to program the row target memory unit 306 in the second pass 1003, the row decoder / word line driver 508 is configured to use a 2D-based... N 2 of the final level N -1 verification voltage is used to verify the target memory cell 306 in this row. To verify 2 N The target storage unit 306 in the final stage can use 2 N -1 verification voltage. For example, 15 verification voltages can be used to verify target memory cell 306 (N=4) in 16 final stages. Figure 10 As shown, to verify the target memory cell 306, the row decoder / word line driver 508 can be configured to sequentially output 2... N -1 verification voltage (Vvf) is applied to the selected word line 318. In some implementations, 2 N -1 of the verification voltages in 2 N Between two adjacent final stages in a series of final stages. For example, when N=4, such as Figure 11 As shown, for each QLC that undergoes fine programming, 15 verification voltages, each located between two adjacent final stages, may be required to verify the target memory cell 306 in one of the 16 final stages.

[0065] Figure 12 A flowchart of a method 1200 for operating a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 300. Method 1200 can be implemented by peripheral circuitry 302, such as a line decoder / word line driver 508 and a page buffer / sensor amplifier 504. It should be understood that the operations shown in method 1200 may not be exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a manner different from... Figure 12 The sequence shown is executed.

[0066] refer to Figure 12 Method 1200 begins with operation 1202, in which, in the first pass, a target memory cell of one row of multiple memory cells is programmed, thereby based on 2 NThe N-bit data segment to be stored in the target memory cell will be programmed into 2 bits for each of the N-bit data segments in the target memory cell. N In one of the m intermediate levels, where N and m are both integers greater than 1, this intermediate level can correspond to 2 of the target memory unit. N / m is one of the intermediate threshold voltage ranges. 2 N Each of the m intermediate levels corresponds to 2 N m N-bit data segments out of N-bit data segments. For example, in a coarse programming pass in a multi-pass programming operation, the peripheral circuit 302 can program a row of QLCs, thereby programming each QLC to one of eight intermediate stages (where N = 4 and m = 2) based on the 4-bit data segments to be stored in each QLC out of 16 4-bit data segments.

[0067] like Figure 13 As shown, at 1302, in some embodiments, a first programming voltage is applied to a selected word line coupled to the row of memory cells in order to program the row of memory cells in the first pass. For example, in each programming / verification loop in a coarse programming pass, the row decoder / word line driver 508 may apply the first programming voltage Vpgm 1 to the selected word line 318 coupled to the QLC. At 1304, a corresponding N-bit data segment is provided for each target memory cell. For example, in each programming / verification loop of a coarse programming pass, the page buffer / sensor amplifier 504 may provide a corresponding 4-bit data segment to each QLC.

[0068] To program the row of memory cells in the first pass, use a 2-based approach. N / m intermediate levels (2 N / m)-1 verification voltage is used to verify the row of memory cells. (2) can be used under the same or different conditions. N The same verification voltage from the 1 verification voltages ( / m)-1 is used to verify the corresponding 2. N The target storage unit for m N-bit data segments out of N-bit data segments. For example... Figure 13 As shown, at 1306, in some embodiments, for verification purposes, (2) N / m)-1 verification voltages are applied sequentially to the selected word lines. (2 N Each of the / m)-1 verification voltages can be in 2 N Between two adjacent intermediate stages in / m intermediate stages. For example, in each programming / verification loop in a coarse programming pass, the line decoder / word line driver 508 can sequentially apply 7 verification voltages to the selected word line 318 (where N=4 and m=2).

[0069] Method 1200 proceeds to operation 1204, such as... Figure 12 As shown, in this operation, the target memory cell in the row is programmed in a second pass after the first pass, thereby programming each of the target memory cells in the row to 2 bits based on the N-bit data segment to be stored in the target memory cell. N In one of the levels. 2 N The level can correspond to 2. N N-bit data segments. The level can correspond to 2 of the target storage unit. N One of several threshold voltage ranges. This threshold voltage range can be higher than the middle threshold voltage range. M N-bit data segments correspond to 2 N There are m levels in a set of levels. The m levels can be 2... N Adjacent levels within a level.

[0070] like Figure 13 As shown, at 1308, in some embodiments, a second programming voltage is applied to a selected word line in order to program the row memory cell in the second pass. For example, in each programming / verification loop of a fine-programming pass, the row decoder / word line driver 508 may apply the second programming voltage Vpgm 2 to the selected word line 318 coupled to the QLC. At 1310, a corresponding N-bit data segment is provided for each target memory cell. For example, in each programming / verification loop of a fine-programming pass, the page buffer / sensor amplifier 504 may provide a corresponding 4-bit data segment to each QLC.

[0071] To program the row of memory cells in the second pass, use a 2-based approach. N The final 2 N -1 verification voltage is applied to verify the row of memory cells. For example... Figure 13 As shown, at 1312, in some embodiments, for verification purposes, 2 N -1 verification voltage is applied sequentially to the selected word line. 2 N -1 verification voltage, each of which can be 2 N Between two adjacent final stages in a final stage. For example, in each programming / verification loop in a fine programming pass, the line decoder / word line driver 508 can sequentially apply 15 verification voltages to the selected word line 318 (where N=4).

[0072] According to one aspect of this disclosure, a storage device includes: a memory cell array having multiple rows of memory cells; multiple word lines respectively coupled to the multiple rows of memory cells; and peripheral circuitry coupled to the memory cell array via the word lines. Each memory cell is configured to store an N-bit data segment in 2... N In one of the levels, where N is an integer greater than 1. Level 2 corresponds to 2. NThe peripheral circuitry is configured to program one target memory cell in a row of multiple rows of memory cells in the first pass, thereby programming each of the target memory cells in that row to 2 bits based on the N-bit data segment stored in the target memory cell. N In one of the m intermediate stages, where m is an integer greater than 1. The peripheral circuitry is also configured to program the target memory cell in the row in a second pass after the first pass, thereby programming each of the target memory cells in the row to 2 based on the N-bit data segment stored in the target memory cell. N In one of the levels.

[0073] In some implementations, the intermediate level corresponds to 2 of the target storage unit. N / m is one of the intermediate threshold voltage ranges, and this level corresponds to 2 of the target memory cell. N One of the threshold voltage ranges. This threshold voltage range can be higher than the intermediate threshold voltage range.

[0074] In some implementations, 2 N Each of the m intermediate levels corresponds to 2 N m N-bit data segments out of N-bit data segments, and the m N-bit data segments correspond to 2 N There are m levels in a given number of levels.

[0075] In some implementations, m levels are 2 N Adjacent levels within a level.

[0076] In some implementations, in order to program the target memory cell in the first pass, the peripheral circuitry includes: a word line driver configured to apply a first programming voltage to a selected word line coupled to the target memory cell in the row; and a page buffer configured to provide a corresponding N-bit data segment to each target memory cell.

[0077] In some implementations, in order to program the target memory cell in the first pass, the peripheral circuitry is also configured to use a 2D-based... N / m intermediate levels (2 N A verification voltage of ( / m)-1 is used to verify the row of memory cells.

[0078] In some implementations, to verify the row of memory cells, the peripheral circuitry includes components configured to sequentially apply (2) to selected word lines in the word lines. N / m)-1 word line driver with verified voltage, selecting the word line coupled to the target memory cell of that row.

[0079] In some implementations, (2) N Each of the / m)-1 verification voltages in 2 NBetween two adjacent intermediate levels in / m intermediate levels.

[0080] In some implementations, in order to program the target memory cell in the second pass, the peripheral circuitry is also configured to use a 2D-based... N 2 at the individual level N -1 verification voltage is used to verify the row of memory cells.

[0081] In some implementations, to verify the row of memory cells, the peripheral circuitry is configured to use (2 N The same verification voltage from the 1 verification voltages ( / m)-1 is used to verify the corresponding 2. N The target storage unit for m N-bit data segments out of N-bit data segments.

[0082] In some implementations, the target storage unit corresponding to m N-bit data segments is verified under different conditions.

[0083] According to another aspect of this disclosure, a system includes a storage device configured to store data and a storage controller coupled to the storage device and configured to control the storage device. The storage device includes: a storage cell array having multiple rows of storage cells; multiple word lines respectively coupled to the multiple rows of storage cells; and peripheral circuitry coupled to the storage cell array via the word lines. Each storage cell is configured to store an N-bit data segment in 2... N In one of the levels, where N is an integer greater than 1, this level corresponds to 2. N The peripheral circuitry is configured to program one target memory cell in a row of multiple rows of memory cells in the first pass, thereby programming each of the target memory cells in that row to 2 bits based on the N-bit data segment stored in the target memory cell. N In one of the m intermediate stages, where m is an integer greater than 1. The peripheral circuitry is also configured to program the target memory cell in the row in a second pass after the first pass, thereby programming each of the target memory cells in the row to 2 based on the N-bit data segment stored in the target memory cell. N In one of the levels.

[0084] In some implementations, the intermediate level corresponds to 2 of the target storage unit. N / m is one of the intermediate threshold voltage ranges, and this level corresponds to 2 of the target memory cell. N One of the threshold voltage ranges. This threshold voltage range can be higher than the intermediate threshold voltage range.

[0085] In some implementations, 2 N Each of the m intermediate levels corresponds to 2 Nm N-bit data segments out of N-bit data segments, and the m N-bit data segments correspond to 2 N There are m levels in a given number of levels.

[0086] In some implementations, m levels are 2 N Adjacent levels within a level.

[0087] In some implementations, in order to program the target memory cell in the first pass, the peripheral circuitry includes: a word line driver configured to apply a first programming voltage to a selected word line coupled to the target memory cell in the row; and a page buffer configured to provide a corresponding N-bit data segment to each target memory cell.

[0088] In some implementations, in order to program the target memory cell in the first pass, the peripheral circuitry is also configured to use a 2D-based... N / m intermediate levels (2 N A verification voltage of ( / m)-1 is used to verify the row of memory cells.

[0089] In some implementations, to verify the row of memory cells, the peripheral circuitry includes components configured to sequentially apply (2) to selected word lines in the word lines. N / m)-1 word line driver with verified voltage, selecting the word line coupled to the target memory cell of that row.

[0090] In some implementations, (2) N Each of the / m)-1 verification voltages in 2 N Between two adjacent intermediate levels in / m intermediate levels.

[0091] In some implementations, in order to program the target memory cell in the second pass, the peripheral circuitry is also configured to use a 2D-based... N 2 at the individual level N -1 verification voltage is used to verify the row of memory cells.

[0092] In some implementations, to verify the row of memory cells, the peripheral circuitry is configured to use (2 N The same verification voltage from the 1 verification voltages ( / m)-1 is used to verify the corresponding 2. N The target storage unit for m N-bit data segments out of N-bit data segments.

[0093] In some implementations, the target storage unit corresponding to m N-bit data segments is verified under different conditions.

[0094] In some implementations, the system also includes a host coupled to the storage controller and configured to send or receive data.

[0095] According to another aspect of this disclosure, a method for operating a storage device is provided. The storage device includes a memory cell array having multiple rows of memory cells and multiple word lines respectively coupled to the multiple rows of memory cells. In a first pass, a target memory cell in one row of the multiple rows of memory cells is programmed, thereby based on 2 N The N-bit data segment to be stored in the target memory cell will be programmed into 2 bits for each of the N-bit data segments in the target memory cell. N In one of the m intermediate levels, where N and m are both integers greater than 1. In the second pass after the first pass, the target memory cell in that row is programmed, thereby programming each of the target memory cells in that row to 2 based on the N-bit data segment stored in the target memory cell. N In one of the levels. 2 N Each level corresponds to 2 N N-bit data segments.

[0096] In some implementations, the intermediate level corresponds to 2 of the target storage unit. N / m is one of the intermediate threshold voltage ranges, and this level corresponds to 2 of the target memory cell. N One of the threshold voltage ranges. This threshold voltage range can be higher than the intermediate threshold voltage range.

[0097] In some implementations, 2 N Each of the m intermediate levels corresponds to 2 N m N-bit data segments out of N-bit data segments, and the m N-bit data segments correspond to 2 N There are m levels in a given number of levels.

[0098] In some implementations, m levels are 2 N Adjacent levels within a level.

[0099] In some implementations, in order to program in the first pass, a first programming voltage is applied to a selected word line in the word line, the selected word line is coupled to the target memory cell of that row; and the corresponding N-bit data segment is provided to each target memory cell.

[0100] In some implementations, in order to program the target memory cell for that row in the first pass, a 2-based method is used. N / m intermediate levels (2 N A verification voltage of ( / m)-1 is used to verify the row of memory cells.

[0101] In some implementations, to verify the row of memory cells, a (2) is applied sequentially to selected word lines in the word lines. N / m)-1 verification voltage, select word line coupled to the target memory cell of that row.

[0102] In some implementations, (2) N Each of the / m)-1 verification voltages in 2 N Between two adjacent intermediate levels in / m intermediate levels.

[0103] In some implementations, in order to program the target memory cell of the row in the second pass, a 2-based method is used. N 2 at the individual level N -1 verification voltage is used to verify the row of memory cells.

[0104] In some implementations, to verify the row storage cell, (2) N The same verification voltage from the 1 verification voltages ( / m)-1 is used to verify the corresponding 2. N The target storage unit for m N-bit data segments out of N-bit data segments.

[0105] In some implementations, the target storage unit corresponding to m N-bit data segments is verified under different conditions.

[0106] The foregoing description of specific implementations can be readily modified and / or adapted for various applications. Therefore, based on the teachings and guidance provided herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations.

[0107] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A storage device, comprising: A storage cell array having multiple storage cells, each storage cell being configured to store... N The bit data segment is stored in 2 N In one of the levels, the level corresponds to 2 N indivual N One of the bit data segments N Bit data segment, in which N It is an integer greater than 1; Word lines, which are coupled to the plurality of memory cells; and Peripheral circuitry, coupled to the memory cell array via the word lines, and configured as follows: In the first pass, the target storage cell among the plurality of storage cells is programmed, based on the storage to be stored in the target storage cell. N All of the bit data segments N Bit data to program the target storage unit to 2 N / m There are several intermediate levels, among which... m It is an integer greater than 1; and In the second pass following the first pass, the target storage unit is programmed based on the data stored in the target storage unit. N All of the bit data segments N Bit data to program the target storage unit to 2 N The final level.

2. The storage device according to claim 1, wherein, The intermediate level corresponds to the 2nd of the target storage unit. N / m One of the intermediate threshold voltage ranges; and The final stage corresponds to the 2nd of the target storage unit. N One of a threshold voltage ranges, wherein the threshold voltage range is higher than or equal to the intermediate threshold voltage range.

3. The storage device according to claim 1 or 2, wherein, The 2 N / m Each of the intermediate levels corresponds to the 2 N indivual N In the bit data segment m indivual N Bit data segment; and The m indivual N The bit data segment corresponds to the 2 N In the final level m The final level.

4. The storage device according to claim 3, wherein, The m The final level is the 2 mentioned above. N Adjacent levels in a final level.

5. The storage device according to any one of claims 1-4, wherein, In order to program the target memory cell in the first pass, the peripheral circuitry includes: A word line driver configured to apply a first programming voltage to a selected word line among the word lines, the selected word line being coupled to the target memory cell; and A page buffer, configured to provide a corresponding page buffer to each target storage unit. N Bit data segment.

6. The storage device according to any one of claims 1-4, wherein, In order to program the target memory cell in the first pass, the peripheral circuitry is also configured to use a method based on the 2 N / m Two intermediate levels (2) N / m A verification voltage is used to verify the target memory cell.

7. The storage device according to claim 6, wherein, The (2) N / m Each of the 1 verification voltages in the 2 N / m Between two adjacent intermediate levels in a series of intermediate levels.

8. The storage device according to any one of claims 6-7, wherein, In order to program the target memory cell in the second pass, the peripheral circuitry is also configured to use a method based on the 2 N The final 2 N -1 verification voltage is used to verify the target memory cell.

9. The storage device according to any one of claims 6-8, wherein, To verify the target storage cell, the peripheral circuitry is configured to use the (2) N / m The same verification voltage in one of the verification voltages is used to verify the voltage corresponding to the 2. N indivual N In the bit data segment m indivual N The target storage unit for a bit data segment.

10. The storage device according to claim 9, wherein, Verification under different conditions corresponds to the above. m indivual N The target storage unit of the bit data segment.

11. A system comprising: The storage device according to any one of claims 1-10; A storage controller, coupled to the storage device, is configured to control the storage device.

12. A method of operating a storage device, the storage device comprising a memory cell array having a plurality of memory cells and word lines respectively coupled to the plurality of memory cells, the method comprising: In the first pass, the target memory cell among the plurality of memory cells is programmed, based on 2 N indivual N The bit data segment to be stored in the target storage unit N All of the bit data segments N Bit data to program the target storage unit to 2 N / m There are several intermediate levels, among which... N and m All are integers greater than 1; and In the second pass following the first pass, the target storage unit is programmed, thereby based on the data stored in the target storage unit. N All bit data segments N Bit data to program the target storage unit to 2 N The final level, the 2 N Each final level corresponds to the 2 N indivual N Bit data segment.

13. The method according to claim 12, wherein, The intermediate level corresponds to the 2nd of the target storage unit. N / m One of the intermediate threshold voltage ranges; and The final stage corresponds to the 2nd of the target storage unit. N One of a threshold voltage ranges, wherein the threshold voltage range is higher than or equal to the intermediate threshold voltage range.

14. The method according to claim 12 or 13, wherein, The 2 N / m Each of the intermediate levels corresponds to the 2 N indivual N In the bit data segment m indivual N Bit data segment; and The m indivual N The bit data segment corresponds to the 2 N In the final level m The final level.

15. The method according to claim 14, wherein, The m The final level is the 2 mentioned above. N Adjacent levels in a final level.

16. The method according to any one of claims 12-15, wherein, Programming the target storage unit in the first pass includes: A first programming voltage is applied to a selected word line among the word lines, the selected word line being coupled to the target memory cell; and Provide corresponding to each target storage unit N Bit data segment.

17. The method according to any one of claims 12-16, wherein, Programming the target storage unit in the first pass includes: using the 2 N / m Two intermediate levels (2) N / m A verification voltage is used to verify the target memory cell.

18. The method according to claim 17, wherein, The (2) N / m Each of the 1 verification voltages in the 2 N / m Between two adjacent intermediate levels in a series of intermediate levels.

19. The method according to any one of claims 17-18, wherein, The second pass of programming the target storage unit includes: using the 2 N The final 2 N -1 verification voltage is used to verify the target memory cell.

20. The method according to any one of claims 17-19, wherein, Verifying the target storage unit includes: using the (2) N / m The same verification voltage in one of the verification voltages is used to verify the voltage corresponding to the 2. N indivual N In the bit data segment m indivual N The target storage unit for a bit data segment.

21. The method according to claim 20, wherein, Verification under different conditions corresponds to the above. m indivual N The target storage unit of the bit data segment.

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