A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The application relates to a semiconductor device manufacturing method and a semiconductor device, and belongs to the technical field of semiconductor devices. The application solves the problems of low etching efficiency, complex process, poor groove uniformity and high groove morphology adjustment difficulty of the prior art. The manufacturing method comprises the following steps: providing a SiC substrate; etching a through hole in the thickness direction of the SiC substrate; epitaxially forming a P-type SiC on the through hole and the SiC substrate; forming a buffer layer and a drain at the bottom of the SiC substrate; forming an N+ type SiC layer for contact on the P-type epitaxial layer; and forming a groove, a gate, a source and a metal layer. The process for preparing the semiconductor device is easy to control, and the efficiency of forming the groove is obviously increased.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] Power devices are among the most important components in power electronics technology, playing a crucial role in power conversion. Currently, the operating voltage of Si-based power devices is insufficient for high-voltage transmission. SiC, as a third-generation semiconductor material, possesses characteristics such as a high critical breakdown electric field and high thermal conductivity, enabling it to withstand higher voltages. However, when the reverse voltage of SiC devices is very high, the thickness of the epitaxial layer also needs to be increased. Superjunction structures, due to the uniform distribution of the electric field drift region during reverse operation, allow for a reduction in thickness.

[0003] However, superjunction structures require more precise control of the P- and N-regions, necessitating the etching of trench morphologies with high aspect ratios and high uniformity. Traditional plasma etching methods for SiC are inefficient, complex, produce poor trench uniformity, and are difficult to adjust in terms of trench morphology. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a method for fabricating a semiconductor device and a semiconductor device, in order to solve the problems of poor trench uniformity, high difficulty in adjusting trench morphology, and high difficulty in process control in existing fabrication processes.

[0005] The objective of this invention is mainly achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0007] Provide a substrate that can be used as an epitaxial layer;

[0008] Through holes are etched on the substrate;

[0009] Then, an epitaxial buffer layer is added to the bottom of the substrate.

[0010] Based on a further improvement of the above manufacturing method, the manufacturing method includes the following steps:

[0011] Step 1: Provide a SiC substrate;

[0012] Step 2: Etch vias along the thickness direction of the SiC substrate;

[0013] Step 3: Epitaxially grow P-type SiC inside and outside the through-hole to obtain P-pillars, and continue to epitaxially grow P-type SiC on the upper surface of the SiC substrate to obtain a P-type epitaxial layer for contact;

[0014] Step 4: Form a buffer layer and drain at the bottom of the SiC substrate;

[0015] Step 5: Form an N+ type SiC layer for contact on the P-type epitaxial layer.

[0016] Step 6: Form the trench;

[0017] Step 7: Form the gate and source;

[0018] Step 8: Form a metal layer.

[0019] Based on further improvements to the above fabrication method, the SiC substrate is N-type 4H-SiC.

[0020] Based on a further improvement to the above manufacturing method, laser etching is used in step 2.

[0021] Based on further improvements to the above manufacturing method, laser etching is performed using a laser.

[0022] Based on a further improvement of the above manufacturing method, step 6 includes forming a gate trench and a source trench.

[0023] Based on further improvements to the above manufacturing method, in step 4, an epitaxial method is used to form a buffer layer.

[0024] Based on further improvements to the above fabrication method, in step 4, the drain electrode is formed by ion implantation, diffusion, or epitaxy.

[0025] Based on further improvements to the above manufacturing method, the drain electrode is made of N+ type 4H-SiC.

[0026] Based on further improvements to the above manufacturing method, in step 6, dry etching or wet etching is used to form the trench.

[0027] Secondly, the present invention also provides a semiconductor device. This semiconductor device is obtained using the above-described fabrication method and includes:

[0028] SiC substrate;

[0029] A P-type epitaxial layer disposed on the front side of a SiC substrate;

[0030] N+ type SiC layer for contact on P-type epitaxial layer

[0031] A buffer layer, a drain electrode, and a drain metal layer are disposed on the back side of a SiC substrate;

[0032] Source pole;

[0033] Source metal layer;

[0034] The SiC substrate has through holes along the thickness direction of the substrate.

[0035] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0036] (1) Existing semiconductor device fabrication processes typically involve sequentially forming a buffer layer and an epitaxial layer on a substrate, followed by etching to stop the etching at the buffer layer to form a trench. Since the process for thick epitaxial layers is difficult to control, and the etching must be stopped at the buffer layer, process control is challenging. This invention innovatively proposes first providing a substrate suitable as an epitaxial layer (avoiding the process of creating thick epitaxial layers), then etching vias on this substrate to form a trench, and finally epitaxially forming a buffer layer at the bottom of the substrate. On one hand, because vias are etched on the substrate, there is no need to control the etching to stop at a specific layer as in existing technologies. Therefore, the etching depth and epitaxial layer thickness can be better controlled, greatly reducing the difficulty of etching process control and facilitating control of the trench length (since it is a via, the depth of the via is the length of the trench). On the other hand, this invention directly uses a substrate suitable as an epitaxial layer, avoiding the process of creating thick epitaxial layers. Therefore, the process of this invention is simple and easy to control.

[0037] (2) Existing technologies use plasma etching to etch trenches, while the present invention uses a combination of laser and through-hole etching to etch channels, which significantly increases the efficiency of channel formation, improves the aspect ratio, facilitates charge balance, and enables the device to withstand higher voltage. At the same time, laser etching has the advantages of good uniformity, smooth trench sidewalls, simple process, and strong operability.

[0038] (3) Since the buffer layer is not extended during the etching of the channel in the process of the present invention, there is no situation where improper etching control leads to etching of the buffer layer. Therefore, the thickness of the buffer layer is easy to control.

[0039] (4) In this invention, a buffer layer is obtained by etching a channel on the epitaxial layer before epitaxial layer is obtained at the bottom. Compared with the top epitaxial layer of the prior art, the bottom epitaxial layer of this invention can better control the thickness.

[0040] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages will become apparent from the description or may be learned by practicing the invention. Attached Figure Description

[0041] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0042] Figure 1 This is a process flow diagram for fabricating semiconductor devices according to the present invention;

[0043] Figure 2The diagram shows the device structure corresponding to each step in the fabrication of the semiconductor device according to the present invention.

[0044] Figure label:

[0045] 1-SiC substrate; 2-Through hole; 3-P pillar; 4-P-type epitaxial layer; 5-Buffer layer; 6-Drain; 7-N+ type SiC layer; 8-Source trench; 9-Gate trench; 10-Source; 11-Gate; 12-Source metal layer; 13-Drain metal layer. Detailed Implementation

[0046] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of the present invention and, together with the embodiments of the present invention, serve to illustrate the principles of the invention, but are not intended to limit the scope of the invention. Unless otherwise specified, some specific process methods in the semiconductor device fabrication process of the present invention can employ existing methods.

[0047] Firstly, the present invention provides a method for fabricating a semiconductor device. This method first provides a substrate suitable for use as an epitaxial layer (avoiding the process of creating thick epitaxial layers), etches vias on the substrate to form channels, and then epitaxially extends a buffer layer at the bottom of the substrate. On one hand, because vias are etched on the substrate, it is not necessary to control the etching stop at a specific layer as in existing technologies. Therefore, the etching depth and epitaxial layer thickness can be better controlled, greatly reducing the difficulty of etching process control and facilitating the control of the channel length (since it is a via, the depth of the via is the same as the length of the channel). On the other hand, the present invention directly uses a substrate suitable for use as an epitaxial layer, avoiding the process of creating thick epitaxial layers. Therefore, the process of the present invention is simple and easy to control.

[0048] The following reference Figure 1 and Figure 2 It provides a detailed introduction to the fabrication methods of semiconductor devices.

[0049] First, a SiC substrate 1 is provided. The SiC substrate 1 has a concentration of 1×10⁻⁶. 16 cm -3 Specifically, the substrate is 4H-SiC. More specifically, it is N-type 4H-SiC.

[0050] Next, vias 2 with a diameter of 8-10 μm are laser-etched on the SiC substrate 1. For example, 8 μm, 9 μm, or 10 μm. Specifically, the vias 2 are along the thickness direction of the SiC substrate 1. The laser etching is performed using a laser, including but not limited to microsecond lasers, nanosecond lasers, picosecond lasers, and femtosecond lasers.

[0051] Continue to refer to Figure 1 and Figure 2P-type SiC is epitaxially grown inside and outside the via 2 to obtain P-pillar 3. P-type SiC is then epitaxially grown on the upper surface of the SiC substrate 1 to obtain a P-type epitaxial layer 4 for contact.

[0052] The p-type SiC material is p-type 4H-SiC with a concentration of 1×10⁻⁶. 16 cm -3 Next, the bottom of the SiC substrate 1 was smoothed. Specifically, a chemical mechanical polishing (CMP) process was used for surface smoothing.

[0053] Then, a buffer layer 5 and a drain electrode 6 are sequentially formed at the bottom of the SiC substrate 1. Specifically, the buffer layer 5 is formed epitaxially, and its material is N-type 4H-SiC. The thickness of the buffer layer 5 is 0.5 μm, and its concentration is 1 × 10⁻⁶. 18 cm -3 The drain electrode 6 is made of N+ type 4H-SiC, with a thickness of 2 μm and a concentration of 1 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 The drain electrode can be formed by ion implantation, or by diffusion, epitaxy, or other methods.

[0054] Then, an N+ type SiC layer 7 for contact is formed on the P-type epitaxial layer 4. The N+ type SiC layer 7 can be formed by epitaxy or ion implantation. Specifically, the N+ type SiC layer 7 is made of N+ type 4H-SiC with a concentration of 1×10⁻⁶. 18 cm -3 -1×10 19 cm -3 The thickness of the N+ type SiC layer 7 is 1-2 μm, for example, 1 μm, 1.5 μm, 2 μm.

[0055] Subsequently, a gate trench 9 and a source trench 8 are formed, and trench material is filled into the gate trench 9 and the source trench 8, respectively, to form the gate electrode 11 and the source electrode 10. The methods for forming the gate trench 9 and the source trench 8 include, but are not limited to, dry etching and wet etching. The depth of the gate trench 9 and the source trench 8 is 3-5 μm, for example, 3 μm, 4 μm, or 5 μm.

[0056] Finally, metal layers are deposited on the front and back sides of the SiC substrate to form source metal layer 12 and drain metal layer 13, respectively.

[0057] Example 1

[0058] Step 1: Provide an N-type 4H-SiC substrate with a concentration of 1×10⁻⁶. 16 cm -3 .

[0059] Step 2: Etch via 2 with a diameter of 8 μm along the thickness direction of SiC substrate 1 on the N-type 4H-SiC substrate. The etching is performed using a microsecond laser.

[0060] Step 3: The epitaxial material inside and outside through-hole 2 is P-type 4H-SiC with a concentration of 1×10⁻⁶. 16 cm -3 P-type SiC; Further epitaxial growth of P-type 4H-SiC with a concentration of 1×10⁻⁶ was carried out on the upper surface of SiC substrate 1. 16 cm -3 P-type 4H-SiC was used to obtain a P-type epitaxial layer 4 for contact.

[0061] Step 4: The bottom of SiC substrate 1 is smoothed using a chemical mechanical polishing (CMP) process.

[0062] Step 5: An epitaxial layer with a thickness of 0.5 μm, N-type 4H-SiC material, and a concentration of 1×10⁻⁶ is formed on the bottom of SiC substrate 1. 18 cm -3 Buffer layer 5.

[0063] Step 6: An N+ type 4H-SiC layer with a thickness of 2 μm and a concentration of 1×10⁻⁶ is formed on buffer layer 5 by ion implantation. 18 cm -3 Drain electrode 6.

[0064] Step 7: Form an N+ type 4H-SiC layer with a thickness of 1 μm and a concentration of 1 × 10⁻⁶ on the p-type epitaxial layer 4 using ion implantation. 18 cm -3 7. N+ type SiC layer used for contact.

[0065] Step 8: Use dry etching to form gate trench 9 and source trench 8 with a depth of 3μm.

[0066] Step 9: Fill the gate trench 9 and source trench 8 with trench material to form the gate 11 and source 10, respectively.

[0067] Step 10: Deposit metal layers on the front and back sides of the SiC substrate to form source metal layer 12 and drain metal layer 13, respectively.

[0068] Example 2

[0069] Step 1: Provide an N-type 4H-SiC substrate with a concentration of 1×10⁻⁶. 16 cm -3 .

[0070] Step 2: Etch via 2 with a diameter of 10 μm along the thickness direction of SiC substrate 1 on the N-type 4H-SiC substrate. Etching is performed using a femtosecond laser.

[0071] Step 3: The epitaxial material inside and outside through-hole 2 is P-type 4H-SiC with a concentration of 1×10⁻⁶. 16 cm -3 P-type SiC; Further epitaxial growth of P-type 4H-SiC with a concentration of 1×10⁻⁶ was carried out on the upper surface of SiC substrate 1. 16 cm -3 P-type SiC was used to obtain a P-type epitaxial layer 4 for contact.

[0072] Step 4: The bottom of SiC substrate 1 is smoothed using a chemical mechanical polishing (CMP) process.

[0073] Step 5: An epitaxial layer with a thickness of 0.5 μm, N-type 4H-SiC material, and a concentration of 1×10⁻⁶ is formed on the bottom of SiC substrate 1. 18 cm -3 Buffer layer 5.

[0074] Step 6: Form a 2μm thick N+ type 4H-SiC with a concentration of 1×10⁻⁶ on the buffer layer 5 using a diffusion method. 19 cm -3 Drain electrode 6.

[0075] Step 7: On the p-type epitaxial layer 4, a 2μm thick N+ type 4H-SiC material with a concentration of 1×10⁻⁶ is formed using an epitaxial method. 19 cm -3 7. N+ type SiC layer used for contact.

[0076] Step 8: Use wet etching to form gate trench 9 and source trench 8 with a depth of 5μm.

[0077] Step 9: Fill the gate trench 9 and source trench 8 with trench material to form the gate 11 and source 10, respectively.

[0078] Step 10: Deposit metal layers on the front and back sides of the SiC substrate to form source metal layer 12 and drain metal layer 13, respectively.

[0079] Example 3

[0080] Step 1: Provide an N-type 4H-SiC substrate with a concentration of 1×10⁻⁶. 16 cm -3 .

[0081] Step 2: Etch a 9μm diameter via 2 on the N-type 4H-SiC substrate along the thickness direction of the SiC substrate 1. The etching is performed using a nanosecond laser.

[0082] Step 3: The epitaxial material inside and outside through-hole 2 is P-type 4H-SiC with a concentration of 1×10⁻⁶.16 cm -3 P-type SiC; Further epitaxial growth of P-type 4H-SiC with a concentration of 1×10⁻⁶ was carried out on the upper surface of SiC substrate 1. 16 cm -3 P-type 4H-SiC was used to obtain a P-type epitaxial layer 4 for contact.

[0083] Step 4: The bottom of SiC substrate 1 is smoothed using a chemical mechanical polishing (CMP) process.

[0084] Step 5: An epitaxial layer with a thickness of 0.5 μm, N-type 4H-SiC material, and a concentration of 1×10⁻⁶ is formed on the bottom of SiC substrate 1. 18 cm -3 Buffer layer 5.

[0085] Step 6: Form a 2μm thick N+ type 4H-SiC with a concentration of 1×10⁻⁶ on the buffer layer 5 using a diffusion method. 19 cm -3 Drain electrode 6.

[0086] Step 7: An N+ type 4H-SiC layer with a thickness of 1.5 μm and a concentration of 1 × 10⁻⁶ is formed on the p-type epitaxial layer 4 using an epitaxial method. 19 cm -3 7. N+ type SiC layer used for contact.

[0087] Step 8: Use dry etching to form gate trench 9 and source trench 8 with a depth of 4μm.

[0088] Step 9: Fill the gate trench 9 and source trench 8 with trench material to form the gate 11 and source 10, respectively.

[0089] Step 10: Deposit metal layers on the front and back sides of the SiC substrate to form source metal layer 12 and drain metal layer 13, respectively.

[0090] Example 4

[0091] Step 1: Provide an N-type 4H-SiC substrate with a concentration of 1×10⁻⁶. 16 cm -3 .

[0092] Step 2: Etch a via 2 with a diameter of 8.5 μm along the thickness direction of the SiC substrate 1 on the N-type 4H-SiC substrate. The etching is performed using a nanosecond laser.

[0093] Step 3: The epitaxial material inside and outside through-hole 2 is P-type 4H-SiC with a concentration of 1×10⁻⁶. 16 cm -3P-type SiC; Further epitaxial growth of P-type 4H-SiC with a concentration of 1×10⁻⁶ was carried out on the upper surface of SiC substrate 1. 16 cm -3 P-type 4H-SiC was used to obtain a P-type epitaxial layer 4 for contact.

[0094] Step 4: The bottom of SiC substrate 1 is smoothed using a chemical mechanical polishing (CMP) process.

[0095] Step 5: An epitaxial layer with a thickness of 0.5 μm, N-type 4H-SiC material, and a concentration of 1×10⁻⁶ is formed on the bottom of SiC substrate 1. 18 cm -3 Buffer layer 5.

[0096] Step 6: Form a 2μm thick N+ type 4H-SiC with a concentration of 1×10⁻⁶ on the buffer layer 5 using a diffusion method. 19 cm -3 Drain electrode 6.

[0097] Step 7: An N+ type 4H-SiC layer with a thickness of 1.3 μm and a concentration of 1×10⁻⁶ is formed on the p-type epitaxial layer 4 using an epitaxial method. 19 cm -3 7. N+ type SiC layer for contact.

[0098] Step 8: Use dry etching to form gate trench 9 and source trench 8 with a depth of 3.5μm.

[0099] Step 9: Fill the gate trench 9 and source trench 8 with trench material to form the gate 11 and source 10, respectively.

[0100] Step 10: Deposit metal layers on the front and back sides of the SiC substrate to form source metal layer 12 and drain metal layer 13, respectively.

[0101] Secondly, the present invention also provides a semiconductor device structure obtained using the above-described fabrication process. The semiconductor device structure includes:

[0102] SiC substrate;

[0103] A P-type epitaxial layer disposed on the front side of a SiC substrate;

[0104] N+ type SiC layer for contact on P-type epitaxial layer

[0105] A buffer layer, a drain electrode, and a drain metal layer are disposed on the back side of a SiC substrate;

[0106] Source pole;

[0107] Source metal layer;

[0108] The SiC substrate has through holes along the thickness direction of the substrate.

[0109] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The manufacturing method includes the following steps: Step 1: Provide a SiC substrate; Step 2: Etch vias along the thickness direction of the SiC substrate; Step 3: Epitaxially grow P-type SiC inside and outside the through-hole to obtain P-pillars, and continue to epitaxially grow P-type SiC on the upper surface of the SiC substrate to obtain a P-type epitaxial layer for contact; Step 4: Form a buffer layer and a drain electrode sequentially at the bottom of the SiC substrate; Step 5: Form an N+ type SiC layer for contact on the P-type epitaxial layer; Step 6: Form the gate trench and source trench; Step 7: Form the gate and source; Step 8: Deposit metal layers on the front and back sides of the SiC substrate to form the source metal layer and the drain metal layer, respectively.

2. The manufacturing method according to claim 1, characterized in that, The SiC substrate is N-type 4H-SiC.

3. The manufacturing method according to claim 1, characterized in that, Laser etching is used in step 2.

4. The manufacturing method according to claim 1, characterized in that, In step 4, an epitaxial layer is formed.

5. The manufacturing method according to claim 1, characterized in that, In step 4, the drain electrode is formed by ion implantation, diffusion, or epitaxy.

6. The manufacturing method according to claim 1, characterized in that, The drain electrode is made of N+ type 4H-SiC.

7. The manufacturing method according to claim 1, characterized in that, In step 6, trenches are formed using either dry etching or wet etching.

8. A semiconductor device, characterized in that, The product is obtained by the manufacturing method according to any one of claims 1-7, comprising: SiC substrate; A P-type epitaxial layer disposed on the front side of a SiC substrate; An N+ type SiC layer for contact is disposed on a P-type epitaxial layer; A buffer layer, a drain electrode, and a drain metal layer are disposed on the back side of a SiC substrate; Source pole; Source metal layer; The SiC substrate has through holes along the thickness direction of the substrate.

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