High electron mobility transistor and method of making the same

Abstract

The present application discloses a high electron mobility transistor and a manufacturing method thereof. The manufacturing method of the high electron mobility transistor (HEMT) mainly comprises the following steps: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a P-type semiconductor layer on the barrier layer; forming a hole injection buffer layer (HIBL) on the P-type semiconductor layer; and forming a gate electrode on the HIBL.

Description

Technical Field

[0001] This invention relates to a high electron mobility transistor and a method for manufacturing the same. Background Technology

[0002] High electron mobility transistors based on gallium nitride (GaN) materials possess numerous advantages in electronic, mechanical, and chemical properties, such as wide bandgap, high breakdown voltage, high electron mobility, high elastic modulus, high piezoelectricity and piezoresistive coefficients, and chemical passivation. These advantages enable GaN-based materials to be used in the fabrication of components for applications such as high-brightness light-emitting diodes, power switching devices, regulators, battery protectors, panel display drivers, and communication components. Summary of the Invention

[0003] One embodiment of the present invention discloses a method for fabricating a high electron mobility transistor (HEMT), which mainly includes forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a P-type semiconductor layer on the barrier layer, forming a hole injection buffer layer (HIBL) on the P-type semiconductor layer, and then forming a gate electrode on the hole injection buffer layer.

[0004] Another embodiment of the present invention discloses a high electron mobility transistor, which mainly includes a buffer layer disposed on a substrate, a barrier layer disposed on the buffer layer, a P-type semiconductor layer disposed on the barrier layer, a hole injection buffer layer (HIBL) disposed on the P-type semiconductor layer, and a gate electrode disposed on the hole injection buffer layer. Attached Figure Description

[0005] Figures 1 to 3 This is a schematic diagram of a method for fabricating a high electron mobility transistor according to an embodiment of the present invention.

[0006] Symbol Explanation

[0007] 12: Base

[0008] 14: Buffer layer

[0009] 16: Barrier Layer

[0010] 18: P-type semiconductor layer

[0011] 20: Protective layer

[0012] 22: Amorphous silicon layer

[0013] 24: Gate electrode

[0014] 26: Annealing process

[0015] 28: Hole injection buffer layer

[0016] 30: Source electrode

[0017] 32: Drain electrode Detailed Implementation

[0018] Please refer to Figures 1 to 3 , Figures 1 to 3 This is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate made of silicon, silicon carbide, or aluminum oxide (or sapphire), wherein the substrate 12 may be a single-layer substrate, a multilayer substrate, a gradient substrate, or a combination thereof. According to other embodiments of the present invention, the substrate 12 may further comprise a silicon-on-insulator (SOI) substrate.

[0019] A selective nucleation layer (not shown) and a buffer layer 14 are then formed on the surface of the substrate 12. In one embodiment, the nucleation layer preferably comprises aluminum nitride and the buffer layer 14 comprises a III-V semiconductor such as gallium nitride, and its thickness can be between 0.5 micrometers and 10 micrometers. In one embodiment, the buffer layer 14 can be formed on the substrate 12 using molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), or a combination thereof.

[0020] Next, an unintentionally doped buffer layer (not shown) may be optionally formed on the surface of the buffer layer 14. In this embodiment, the unintentionally doped buffer layer preferably comprises a III-V semiconductor, such as gallium nitride, or more specifically unintentionally doped gallium nitride. In one embodiment, the unintentionally doped buffer layer may be formed on the buffer layer 14 by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0021] A barrier layer 16 is then formed on the surface of the unintentionally doped buffer layer or the buffer layer 14. In this embodiment, the barrier layer 16 preferably comprises a III-V semiconductor such as N-type aluminum gallium nitride (Al x Ga 1-x N), where 0<x<1. The barrier layer 16 preferably comprises an epitaxial layer formed by an epitaxial growth process, and the barrier layer 16 may comprise a dopant of silicon or germanium. Similar to the manner of forming the buffer layer 14 described above, the barrier layer 16 may be formed on the buffer layer 14 by a molecular-beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof.

[0022] Next, a P-type semiconductor layer 18 is formed on the barrier layer 16. A portion of the P-type semiconductor layer 18 is patterned or removed using photolithography and etching processes to form a protective layer 20 on the P-type semiconductor layer 18. Another photolithography and etching process is then performed to pattern or remove a portion of the protective layer 20, exposing the surface of the P-type semiconductor layer 18. A silicon layer, or more specifically an amorphous silicon layer 22, is then formed on the surface of the P-type semiconductor layer 18, and a gate electrode 24 is formed on the amorphous silicon layer 22. In this embodiment, the amorphous silicon layer 22 and the gate electrode 24 can be formed sequentially, fully covering the protective layer 20 and the exposed P-type semiconductor layer 18. Then, a portion of the gate electrode 24 and a portion of the amorphous silicon layer 22 are removed using photolithography and etching processes to form a patterned amorphous silicon layer 22 and gate electrode 24. Preferably, the sidewalls of the patterned amorphous silicon layer 22 and the gate electrode 24 are flush with the sidewalls of the underlying P-type semiconductor layer 18.

[0023] In one embodiment, the P-type semiconductor layer 18 preferably comprises P-type gallium nitride and can be formed on the surface of the barrier layer 16 using molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), or a combination thereof.

[0024] Furthermore, although the protective layer 20 in this embodiment is a single-layer structure, it is not limited to this. Depending on product requirements, a single-layer or multi-layer protective layer 20 can be formed, such as a double-layer or triple-layer structure. The protective layer 20 may contain dielectric materials such as silicon oxide, silicon nitride, or aluminum oxide. Next, in this embodiment, the thickness of the amorphous silicon layer 22 is preferably about one-sixth to one-tenth of the overall thickness of the P-type semiconductor layer 18. For example, in this stage, the thickness of the amorphous silicon layer 22 is preferably between 2 and 10 nanometers, or preferably about 5 nanometers, while the thickness of the P-type semiconductor layer 18 is preferably between 60 and 100 nanometers.

[0025] like Figure 2As shown, an annealing process 26 is then performed to drive silicon atoms from the amorphous silicon layer 22 into the underlying P-type semiconductor layer 18, thereby forming a hole injection buffer layer (HIBL) 28 made of silicon. The silicon atoms in the hole injection buffer layer 28 may have a concentration gradient; for example, the silicon concentration near the lower surface of the hole injection buffer layer 28 is slightly lower than the silicon concentration near the top surface of the hole injection buffer layer 28. In this embodiment, the annealing process 26 may include a rapid thermal annealing (RTP) process or a furnace annealing process. The temperature of the rapid thermal annealing process is preferably between 500 and 600 degrees Celsius, while the temperature of the furnace annealing process is preferably between 200 and 600 degrees Celsius.

[0026] Furthermore, the thickness of the hole injection buffer layer 28 after annealing process 26 is preferably slightly increased compared to the aforementioned amorphous silicon layer 22. For example, the overall thickness of the hole injection buffer layer 28 in this stage is approximately one-third of the thickness of the underlying P-type semiconductor layer 18, or more preferably approximately one-half to one-third of the thickness of the P-type semiconductor layer 18. It should be noted that since the amorphous silicon layer 22 is easily oxidized to silicon oxide if it is directly processed by annealing process 26 without shielding, in this embodiment, it is preferable to perform an annealing process 26 after both the amorphous silicon layer 22 and the gate electrode 24 are deposited on the surface of the P-type semiconductor layer 18 to convert the amorphous silicon layer 22 into a hole injection buffer layer 28 composed of silicon.

[0027] Subsequently, as Figure 3As shown, a photolithography and etching process can be performed to remove a portion of the protective layer 20 on both sides of the gate electrode 24 to form two grooves (not shown). Conductive or metallic materials are then filled into the two grooves, and a source electrode 30 and a drain electrode 32 are formed on both sides of the gate electrode 24 using a photolithography and etching process. In this embodiment, the gate electrode 24, source electrode 30, and drain electrode 32 are preferably made of metal, wherein the gate electrode 24 is preferably made of Schottky metal, and the source electrode 30 and drain electrode 32 are preferably made of ohmic contact metal. According to an embodiment of the present invention, the gate electrode 24, source electrode 30, and drain electrode 32 may each comprise gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, conductive materials can be formed within the aforementioned groove using electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), or a combination thereof. Then, the electrode materials are patterned using one or more etching operations to form the gate electrode 24, source electrode 30, and drain electrode 32. This completes the fabrication of a high electron mobility transistor according to an embodiment of the present invention.

[0028] In summary, this invention primarily involves first forming an amorphous silicon layer on the surface of a P-type semiconductor layer, then forming a gate electrode on the amorphous silicon layer. An annealing process is then performed to drive silicon atoms from the amorphous silicon layer into the underlying P-type semiconductor layer, thereby forming a hole injection buffer layer (HIBL). According to a preferred embodiment of this invention, the silicon atoms in the hole injection buffer layer can act as donors and neutralize acceptors such as magnesium (Mg) on ​​the surface of the P-type semiconductor layer, making it more difficult for holes to inject into the P-type semiconductor layer and the barrier layer, thus reducing gate leakage. Furthermore, the hole injection buffer layer can also aid in the high-temperature gate bias (HTGB) reliability testing of HEMT devices and improve the device's Vg operating range, giving designers greater flexibility in circuit design.

[0029] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for fabricating a high electron mobility transistor (HEMT), characterized in that, Include: A buffer layer is formed on the substrate; A barrier layer is formed on the buffer layer; A P-type semiconductor layer is formed on the barrier layer; Pattern the P-type semiconductor layer; A protective layer is formed on the P-type semiconductor layer; The protective layer is patterned to expose the P-type semiconductor layer; A silicon layer is formed on the P-type semiconductor layer; A gate electrode is formed on the silicon layer; The silicon layer is converted into a hole injection buffer layer by an annealing process. as well as A source electrode and a drain electrode are formed on both sides of the gate electrode.

2. The method of claim 1, wherein the silicon layer comprises an amorphous silicon layer.

3. The method of claim 1, wherein the annealing process includes a rapid heating annealing process.

4. The method of claim 1, wherein the thickness of the silicon layer is less than the thickness of the hole injection buffer layer.

5. The method of claim 1, wherein the buffer layer comprises gallium nitride (GaN).

6. The method of claim 1, wherein the barrier layer comprises aluminum gallium nitride (Al₂O₃). x Ga 1-x N).

7. The method of claim 1, wherein the P-type semiconductor layer comprises P-type gallium nitride.

8. The method of claim 1, wherein the hole injection buffer layer comprises a silicon concentration gradient.

9. A high electron mobility transistor (HEMT) fabricated using the method described in claim 1, characterized in that, Include: A buffer layer is provided on the substrate; A barrier layer is provided on the buffer layer; A P-type semiconductor layer is disposed on the barrier layer; A hole injection buffer layer (HIBL) is disposed on the P-type semiconductor layer; and The gate electrode is disposed on the hole injection buffer layer.

10. The high electron mobility transistor of claim 9, wherein the hole injection buffer layer thickness is less than the P-type semiconductor layer thickness.

11. The high electron mobility transistor of claim 9, wherein the buffer layer comprises gallium nitride (GaN).

12. The high electron mobility transistor of claim 9, wherein the barrier layer comprises aluminum gallium nitride (Al₂O₃). x Ga 1-x N).

13. The high electron mobility transistor of claim 9, wherein the P-type semiconductor layer comprises P-type gallium nitride.

14. The high electron mobility transistor of claim 9, wherein the hole injection buffer layer comprises silicon.

15. The high electron mobility transistor of claim 9, wherein the hole injection buffer layer comprises a silicon concentration gradient.

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