Method for manufacturing a semiconductor device

Abstract

A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer on a substrate; forming a feature opening to expose the substrate; performing a pre-clean process on the feature opening, the pre-clean process including a pre-clean solution; performing a cleaning process on the feature opening; and forming a conductive feature in the feature opening. The pre-clean solution includes a chelating agent and a corrosion inhibitor.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 708,146 (i.e., priority date "March 30, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor device; more specifically, this disclosure relates to a method for fabricating a semiconductor device using a pre-cleaning process. Background Technology

[0003] Semiconductor devices are used in a wide range of electronic devices, such as personal computers, mobile phones, digital cameras, and others. To meet the ever-increasing demand for computing power, the size of semiconductor devices is constantly shrinking. However, this shrinkage process introduces various problems, and these problems are increasing. Therefore, improving the performance, quality, yield, efficiency, and reliability of semiconductor devices remains a challenge.

[0004] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One aspect of this disclosure provides a method for fabricating a semiconductor device, comprising forming a first dielectric layer on a substrate; forming a feature opening to expose the substrate; performing a pre-cleaning process on the feature opening, the pre-cleaning process including a pre-cleaning solution; performing a cleaning process on the feature opening; and forming a conductive feature in the feature opening. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor.

[0006] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a feature opening to expose the substrate; performing a pre-cleaning process on the feature opening, the pre-cleaning process including a pre-cleaning solution; performing a cleaning process on the feature opening; conformally forming a barrier layer on the feature opening; conformally forming an auxiliary barrier layer on the barrier layer; and forming a conductive feature on the auxiliary barrier layer. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor. The barrier layer includes tantalum. The auxiliary barrier layer includes a copper-manganese alloy.

[0007] Another aspect of this disclosure provides a pre-cleaning solution used prior to a cleaning process of a feature opening in a semiconductor device, comprising: a chelating agent including ethylenediaminetetraacetic acid, polyacrylate, carbonate, phosphonate, gluconate, N,N'-bis(2-hydroxyphenyl)ethylenediiminodiacetic acid, triethylenetetraaminohexaacetic acid, deferaferroamine B, N,N',N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-phenyltricarboxamide and / or ethylenediaminedi-o-hydroxyphenylacetic acid; a corrosion inhibitor comprising a fatty alcohol compound having at least one thiol group; a fluorinated amine including methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, hydrofluoroethanolamine, methylethanolamine hydrofluoride, dimethylethanolamine hydrofluoride and / or triethylenediamine hydrofluoride; a surfactant comprising polyoxyethylene butylphenyl ether, polyoxyethylene alkylphenyl sulfate, or combinations thereof; and a solvent comprising deionized water.

[0008] Due to the design of the semiconductor device fabrication method of the present invention, the underlying conductive layer exposed through the feature opening can be protected by the chelating agent and / or corrosion inhibitor contained in the pre-cleaning solution, thereby reducing or avoiding contour defects or electron migration. Therefore, the yield and reliability of the resulting semiconductor device can be improved.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0011] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present disclosure;

[0012] Figures 2 to 8 For illustrative purposes, a cross-sectional view is provided to illustrate the process of fabricating a semiconductor device according to one embodiment of the present disclosure;

[0013] Figure 9 This is a flowchart of a method for fabricating a semiconductor device according to another embodiment of the present disclosure;

[0014] Figures 10 to 22 For illustrative purposes, a cross-sectional view is provided to illustrate the process of fabricating a semiconductor device in another embodiment of this disclosure.

[0015] The reference numerals in the attached figures are explained as follows:

[0016] 1A: Semiconductor device

[0017] 1B: Semiconductor Device

[0018] 10: Preparation method

[0019] 101: Base

[0020] 103: First etch stop layer

[0021] 105: First dielectric layer

[0022] 105-1: Characteristic opening

[0023] 105-3: Through-hole opening

[0024] 107: Second dielectric layer

[0025] 107-1: Ditch opening

[0026] 109: First hard mask layer

[0027] 109-1: Hard mask opening

[0028] 111: Barrier Layer

[0029] 113: Auxiliary blocking layer

[0030] 115: Electrical conductivity characteristics

[0031] 117: Through hole

[0032] 119: Ditch

[0033] 20: Preparation method

[0034] 200: Light Mask

[0035] 201: Masking base

[0036] 201BS: Bottom

[0037] 201LS: Side View

[0038] 203: Opaque layer

[0039] 203O: Masking opening

[0040] 205: Semi-transparent layer

[0041] 205O: Mask opening

[0042] 301: Processing the front mask layer

[0043] 303: Image-based mask layer

[0044] 303M: Masking Area

[0045] 303T: Ditch area

[0046] 303V: Through-hole

[0047] 401: First mask layer

[0048] 403: Second masking layer

[0049] 405: Third masking layer

[0050] 501: First conductive material

[0051] 503: Second conductive material

[0052] 505: Third conductive material

[0053] ER: Etching Residue

[0054] SK: Device stacking

[0055] T1: Thickness

[0056] T2: Thickness

[0057] T3: Thickness

[0058] T4: Thickness Detailed Implementation

[0059] The following description of this disclosure, accompanied by drawings incorporated in and forming part of this specification, illustrates embodiments of the disclosure; however, the disclosure is not limited to these embodiments. Furthermore, the following embodiments may be appropriately integrated to complete another embodiment.

[0060] Terms such as "an embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," and "another embodiment" refer to embodiments described in this disclosure that may include specific features, structures, or characteristics; however, not every embodiment must include that specific feature, structure, or characteristic. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0061] To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0062] In this disclosure, a semiconductor device generally refers to a component that can function by utilizing the properties of a semiconductor, and electro-optical components, light-emitting display components, semiconductor circuits, and electronic components are all included in the category of semiconductor devices.

[0063] It should be noted that in the description of this invention, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0064] It should be noted that the term "formation" refers to any method of creating, establishing, patterning, implanting, or depositing an element, a dopant, or a material. Examples include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, crystal growth, implantation, lithography, dry etching, and wet etching.

[0065] It should be noted that, in the description of this invention, the functions or steps mentioned herein may appear in a different order than that shown in the accompanying drawings. For example, depending on the functions or steps involved, two consecutively displayed figures may actually be performed substantially simultaneously or sometimes in reverse order.

[0066] Figure 1 For illustrative purposes, a flowchart is used to illustrate a method 10 for fabricating a semiconductor device 1A disclosed in one embodiment. Figures 2 to 8 For illustrative purposes, a cross-sectional view is provided to illustrate the process of fabricating a semiconductor device 1A according to one embodiment of the present disclosure.

[0067] Reference Figures 1 to 3 In step S11, a substrate 101 is provided, a first etch stop layer 103 is formed on the substrate 101, a first dielectric layer 105 is formed on the first etch stop layer 103, a first hard mask layer 109 is formed on the first dielectric layer 105, and the first hard mask layer 109 is patterned to form a hard mask opening 109-1.

[0068] Reference Figure 2The substrate 101 includes a bulk semiconductor substrate entirely composed of at least one semiconductor material, a plurality of device elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). The bulk semiconductor substrate may be formed of elemental semiconductors such as silicon and germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0069] In some embodiments, substrate 101 includes a semiconductor-on-insulator structure comprising, from bottom to top, a processing substrate, an insulating layer, and a topmost semiconductor material layer. The processing substrate and the topmost semiconductor material layer are formed of the same material as the bulk semiconductor substrate described above. The insulating layer is a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer comprises a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulating layer has a thickness between about 10 nm and about 200 nm.

[0070] It should be noted that the term "about" refers to a change in the amount of a component, element, or reactant in this disclosure, meaning a numerical change that may occur, for example, through typical measurement and liquid handling procedures used in its preparation, in a concentrate or solution. Furthermore, changes may also arise from unintentional errors in the measurement procedure, differences in the preparation, source, or purity of the components used in the preparation of the composition, or in the implementation of the method. In some aspects, the term "about" refers to a change of up to 10% of the indicated value. In other aspects, the term "about" refers to a change of up to 5% of the indicated value. In still other aspects, the term "about" refers to a change of up to 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the indicated value.

[0071] Reference Figure 2 Device elements can be formed on a bulk semiconductor substrate or the topmost semiconductor material layer. Some portions of the device element can be formed within the bulk semiconductor substrate or the topmost semiconductor material layer. The device element can be a transistor, such as a complementary metal-oxide-semiconductor transistor, a metal-oxide-semiconductor field-effect transistor, a fin field-effect transistor, or a combination thereof.

[0072] Reference Figure 2The dielectric layer can be formed on a bulk semiconductor substrate or the topmost semiconductor material layer and cover device elements. In some embodiments, the dielectric layer can be formed of, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-dielectric-constant dielectric materials, or combinations thereof. The low-dielectric-constant dielectric material has a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-dielectric-constant dielectric material may have a dielectric constant of less than 2.0. The dielectric layer can be formed by deposition processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, etc. A planarization process is performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0073] Reference Figure 2 The conductive features may include interconnect layers and conductive vias. The interconnect layers are separated from each other and horizontally disposed in the dielectric layer along the Z direction. The conductive vias connect adjacent interconnect layers along the Z direction and connect adjacent device elements and interconnect layers. In some embodiments, the conductive vias can improve heat dissipation and provide structural support. In some embodiments, the conductive features may be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal-forming nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The conductive features may be formed during the formation of the dielectric layer.

[0074] In some embodiments, device elements and conductive features together constitute a plurality of functional units in substrate 101. In the description herein, a functional unit generally refers to functionally related circuitry that has been divided into different units for functional purposes. In some embodiments, a functional unit may typically be a highly complex circuit, such as a processor core, memory controller, or accelerator unit. In some other embodiments, the complexity and utility of the functional unit may be determined according to actual needs.

[0075] Reference Figure 2 A first etch stop layer 103 is formed on the substrate 101. The first etch stop layer 103 may preferably be formed of a dielectric material having a different etch selectivity than the top layer (e.g., dielectric layer) of the substrate 101. For example, the first etch stop layer 103 may be formed of silicon nitride, silicon carbonitride, silicon carbide, etc., and may be deposited by chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0076] Reference Figure 2The first dielectric layer 105 is formed on the substrate 101 and is made of materials such as silicon dioxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, spin-coated low dielectric constant dielectric layer, chemical vapor deposition low dielectric constant dielectric layer, or combinations thereof. In some embodiments, the first dielectric layer 105 may include a self-planarizing material such as spin-coated glass or such as SiLK. TM Spin-coating a low-dielectric-constant dielectric material. Using a self-planarizing dielectric material avoids the need for subsequent planarization processes. In some embodiments, the first dielectric layer 105 can be formed by a deposition process, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, a planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent processing steps.

[0077] When low-dielectric-constant materials are used in dielectric layers (e.g., the first dielectric layer 105), it is difficult to produce features with few or no surface defects or feature deformation. It has been observed that low-dielectric-constant dielectric materials are typically porous and easily scratched and damaged during fabrication, leading to surface defects. Furthermore, low-dielectric-constant materials are often brittle and may deform under conventional polishing processes. One solution to limit or reduce surface defects and deformation is to deposit a hard mask layer on the exposed low-dielectric-constant material before patterning and etching features. The hard mask layer resists damage and deformation. The hard mask layer also protects the underlying low-dielectric-constant material during subsequent material deposition and planarization or material removal processes (e.g., chemical mechanical polishing or etching), thereby reducing defect formation and feature deformation. The hard mask layer can then be removed by a subsequent planarization process before further processing.

[0078] Reference Figure 2 A first hard mask layer 109 is formed on the first dielectric layer 105. In some embodiments, the first hard mask layer 109 may be formed of, for example, silicon, silicon germanium, tetraethyl orthosilicate, silicon nitride, silicon oxynitride, silicon oxynitride, silicon carbide, or combinations thereof. The first hard mask layer 109 may be formed by a deposition process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, etc. The process temperature for forming the first hard mask layer 109 may be less than 400°C.

[0079] Alternatively, in some embodiments, the first hard masking layer 109 may be formed of, for example, boron nitride, silicon boron nitride, boron phosphorus nitride, silicon boron carbon nitride, etc. The first hard masking layer 109 may be formed by a film deposition process and a processing process. Specifically, in the film deposition process, a first precursor may be introduced over the first dielectric layer 105 to form a boron substrate, the first precursor being a boron-based precursor. Subsequently, in the processing process, a second precursor may be introduced to react with the boron substrate and transform the boron substrate into the first hard masking layer 109, the second precursor being a nitrogen-based precursor. In some embodiments, the first precursor is, for example, diborane, cycloborane, or an alkyl-substituted boron derivative of cycloborane. In some embodiments, the second precursor is, for example, ammonia or hydrazine.

[0080] Reference Figure 2 A first mask layer 401 is formed on the first hard mask layer 109. The first mask layer 401 may be a photoresist layer. The first mask layer 401 may be patterned to define the location of the feature opening 105-1, as will be explained later. During the patterning of the first mask layer 401, the first hard mask layer 109 may be used as an anti-reflective coating to improve the quality of image transfer from the photomask (not shown) to the first hard mask layer 109.

[0081] Reference Figure 3 A hard mask etching process can be performed to remove a portion of the first hard mask layer 109, and the pattern of the first mask layer 401 can be transferred to the first hard mask layer 109 to form a hard mask opening 109-1 along the first hard mask layer 109. The etching rate of the first hard mask layer 109 in the hard mask etching process can be faster than the etching rate of the first dielectric layer 105 in the hard mask etching process. For example, during the hard mask etching process, the etching rate ratio of the first hard mask layer 109 to the first dielectric layer 105 is between about 100:1 and about 1.05:1. As another example, during the hard mask etching process, the etching rate ratio of the first hard mask layer 109 to the first dielectric layer 105 is between about 100:1 and about 10:1. The first dielectric layer 105 can be exposed through the hard mask opening 109-1.

[0082] Reference Figure 1 and 4 In step S13, a feature opening 105-1 is formed to expose the substrate 101.

[0083] Reference Figure 4An etching process is performed using a first hard mask layer 109 and / or a first mask layer 401 as a mask to remove a portion of the first dielectric layer 105 and a portion of the first etch stop layer 103. The etching process may include multiple stages, such as two stages. For example, during a first stage of the etching process, the etch rate ratio of the first dielectric layer 105 to the first hard mask layer 109 is between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. During a second stage of the etching process, the etch rate ratio of the first etch stop layer 103 to the first hard mask layer 109 is between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. During the second stage of the etching process, the etching rate ratio of the first etch stop layer 103 to the substrate 101 is between about 100:1 and about 1.05:1, or between about 100:1 and about 10:1. After the etching process, a feature opening 105-1 is formed along the first dielectric layer 105 and the first etch stop layer 103.

[0084] In some embodiments, the first masking layer 401 may be removed before forming the feature opening 105-1. In some embodiments, the first masking layer 401 may be removed after the etching process forming the feature opening 105-1. The removal of the first masking layer 401 may be achieved by an ashing process or other suitable process. Some etching residue ER may remain after the removal of the first masking layer 401. The etching residue ER may be residual material on the inner surface of the feature opening 105-1 after the etching process of the feature opening 105-1 or after the ashing process. For example, the etching residue ER may be incompletely ashed material remaining on the inner surface of the feature opening 105-1 after the ashing process, polymers (also known as sidewall protective films or rabbit ears) remaining as byproducts on the inner surface of the feature opening 105-1, and / or organometallic polymers and metal oxides remaining on the inner surface of the feature opening 105-1. Depending on the material to be etched or ashed, the etching residue may have different compositions.

[0085] Reference Figure 5 In step S15, a pre-cleaning process and a cleaning process are sequentially performed on the feature opening 105-1.

[0086] Reference Figure 5 During the pre-cleaning process, Figure 4The semiconductor device semi-finished product shown can be rotated at a speed between approximately 10 rpm and approximately 2000 rpm, or between approximately 100 rpm and 1000 rpm. A pre-cleaning solution is sprayed onto the semiconductor device semi-finished product to cover its entire front side. While the pre-cleaning solution is applied to the front side of the semiconductor device semi-finished product, water or other suitable solution can be applied to the back side of the semiconductor device semi-finished product to clean it.

[0087] In some embodiments, the pre-cleaning solution includes a chelating agent, a corrosion inhibitor, an amine fluoride, a surfactant, or a solvent. In some embodiments, the amine fluoride and the surfactant are optional.

[0088] Chelating agents are also commonly referred to as complexing agents or chelating agents. Chelating agents have negatively charged ions called ligands that combine with free metal ions to form soluble complexes. Chelating agents can be used to remove metal ions from semiconductor device semi-finished products. Without adhering to any particular theory, chelating agents can also reduce or prevent corrosion of the conductive layer exposed below through the feature opening 105-1.

[0089] In some embodiments, the chelating agent of the pre-cleaning solution includes ethylenediaminetetraacetic acid, polyacrylate, carbonate, phosphonate, gluconate, N,N'-bis(2-hydroxyphenyl)ethylenediiminodiacetic acid, triethylenetetraaminohexaacetic acid, deferaferroamine B, N,N',N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzenetricarboxamide and / or ethylenediamine di-o-hydroxyphenylacetic acid. In some embodiments, the concentration of the chelating agent is between about 0.001 mg / L and about 300 mg / L, or between about 0.01 mg / L and about 3 mg / L. In some embodiments, alternatively, the concentration of the chelating agent is between 1 ppm and about 400 ppm of the pre-cleaning solution, or preferably about 40 ppm of the pre-cleaning solution.

[0090] The corrosion inhibitor in the pre-cleaning solution is used to reduce or prevent metal corrosion during subsequent cleaning processes. In some embodiments, the corrosion inhibitor comprises a fatty alcohol compound having at least one thiol group in its molecule. The alcohol compound has two or more carbon atoms, with the carbon atom bonded to the thiol group and another carbon atom bonded to the hydroxyl group adjacent to each other. For example, the corrosion inhibitor may be 2-mercaptoethanol and / or thioglycerol. In some embodiments, the concentration of the corrosion inhibitor in the pre-cleaning solution is between about 0.0001 wt% and about 10 wt%, or about 0.001 wt% and about 1 wt%. When the concentration is too low, the corrosion inhibition effect may be limited to an unsatisfactory level. However, excessively high concentrations do not always provide a further increase in corrosion inhibition effect and will make the compound difficult to handle due to the characteristic odor of the thiol-containing compound.

[0091] Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes aromatic compounds, such as benzotriazole and / or 5-methylbenzimidazole. Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes uric acid, adenine, caffeine, and / or purine. Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes glyoxylic acid. Due to the presence of glyoxylic acid as a reducing agent, even if the metal material is exposed during the pre-cleaning process, the electron transfer between the pre-cleaning solution and the exposed metal material can be controlled by adjusting the redox potential of the pre-cleaning solution through adjusting the concentration of glyoxylic acid, thus preventing corrosion of the metal material. Alternatively, in some embodiments, the corrosion inhibitor of the pre-cleaning solution includes 2-mercaptoethanol, thioglycerol, benzotriazole, 5-methylbenzimidazole, uric acid, adenine, caffeine, purine, and / or glyoxylic acid.

[0092] In some embodiments, the amine fluoride in the pre-cleaning solution includes methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, hydrofluoroethanolamine, methylethanolamine hydrofluoride, dimethylethanolamine hydrofluoride, and / or triethylenediamine hydrofluoride. The amine fluoride can be used to remove etching residues (ER).

[0093] In some embodiments, the concentration of amine fluoride in the pre-cleaning solution can be determined based on the composition of the etching residue ER. For example, the concentration of amine fluoride can be between about 0.1% by mass and about 5% by mass of the overall composition of the pre-cleaning solution, or between about 0.2% by mass and about 3% by mass of the overall composition of the pre-cleaning solution. By setting the concentration of amine fluoride within the above range, it can be ensured that the amine fluoride in the pre-cleaning solution can remove the etching residue ER, while preventing the amine fluoride from corroding the metal material exposed through the feature opening 105-1 and inhibiting the etching of the dielectric layer exposed through the feature opening 105-1. That is, if the concentration of amine fluoride in the pre-cleaning solution is too low, the ability to remove residues will be insufficient; if the concentration is too high, the metal material may be corroded, and the exposed dielectric layer may be etched or undergo structural changes.

[0094] The purpose of surfactants is to prevent particles from reattaching or redepositing onto semiconductor device semi-finished products after they have been removed from them. Preventing particle reattachment is crucial because it increases the overall processing time. Surfactants also impart affinity to waterproofing layers. Typically, surfactants are long hydrocarbon chains, usually containing hydrophilic (polar, water-soluble groups) and hydrophobic (non-polar, water-insoluble groups). The surfactant attaches its non-polar groups to the particles and the front side of the semiconductor device semi-finished product. Consequently, the polar groups of the surfactant will point away from the wafer and particles toward the pre-cleaning solution covering the front side of the semiconductor device semi-finished product. Due to the polar groups of the surfactant on the particles and the front side of the semiconductor device semi-finished product, particles bound to the surfactant in the solution will be electrostatically repelled by the front side of the semiconductor device semi-finished product.

[0095] In some embodiments, the surfactant in the pre-cleaning solution comprises nonionic, anionic, or a mixture of nonionic and anionic compounds. Nonionic refers to the surfactant having a static, nonionic charge at its polar end, while anionic refers to the surfactant having a negative ionic charge at its polar end. Nonionic surfactants may be, for example, polyoxyethylene butylphenyl ether, and anionic surfactants may be, for example, polyoxyethylene alkylphenyl sulfate. In some embodiments, the concentration of one or more surfactants in the pre-cleaning solution is between about 1 ppm and about 100 ppm. In some embodiments, the concentration of the nonionic surfactant in the pre-cleaning solution is about 30 ppm, and the concentration of the anionic surfactant in the pre-cleaning solution is about 30 ppm. In some embodiments, the concentration of the surfactant in the pre-cleaning solution is from 0.0001% by mass to 10% by mass of the overall composition of the pre-cleaning solution, or from about 0.001% by mass to about 5% by mass of the overall composition of the pre-cleaning solution. By setting the concentration within the above ranges, it can be ensured that the wettability of the front side of the semiconductor device semi-finished product is commensurate with the concentration of the surfactant.

[0096] In some embodiments, the solvent for the pre-cleaning solution may be deionized water.

[0097] In some embodiments, Figure 4 The front side of the semiconductor device semi-finished product shown can be covered (or immersed) with a pre-cleaning solution for approximately 2 minutes. Next, the semiconductor device semi-finished product can be rinsed with deionized water to remove the pre-cleaning solution.

[0098] In some embodiments, a drying process may be performed after the pre-cleaning treatment. The drying process is performed by rotating the semiconductor device semi-finished product for about 20 seconds at a speed between about 100 rpm and about 6000 rpm, or about 3000 rpm, using an airflow to dry it. In some embodiments, nitrogen or isopropanol may be used to facilitate the drying process. In some embodiments, the drying process is optional, i.e., the cleaning process may be performed directly after rinsing with the pre-cleaning solution.

[0099] In some embodiments, the cleaning process may include three stages with inter-stage rinsing between the stages. Specifically, in the first stage of the cleaning process, a first cleaning solution may be applied to the semiconductor device semi-finished product after a pre-cleaning treatment (or drying process). The first cleaning solution may be rinsed off by a first-stage inter-rinse. During the second stage of the cleaning process, a second cleaning solution may be applied to the semiconductor device semi-finished product, and subsequently rinsed off by a second-stage inter-rinse. During the third stage of the cleaning process, a third cleaning solution may be applied to the semiconductor device semi-finished product, and then rinsed off by a post-stage rinsing.

[0100] In some embodiments, during the first stage of the cleaning process, the pre-cleaned semiconductor device semi-finished product may be rotated at a rate between about 10 rpm and about 2000 rpm, or between about 100 rpm and 1000 rpm. A first cleaning solution is sprayed onto the semiconductor device semi-finished product to cover its entire front side. While the first cleaning solution is applied to the front side of the semiconductor device semi-finished product, water or other suitable solution may be applied to the back side of the semiconductor device semi-finished product to clean it.

[0101] In some embodiments, the first cleaning solution comprises diluted hydrofluoric acid. The concentration of the first cleaning solution is between about five parts deionized water to one part hydrofluoric acid and about one thousand parts deionized water to one part hydrofluoric acid, or about three hundred parts deionized water to one part hydrofluoric acid, or about fifty parts deionized water to one part hydrofluoric acid. Typically, the front side of the semiconductor device semi-finished product will be exposed to the first cleaning solution for a sufficient time to etch sacrificial oxide (typically about 50 to 200 angstroms) or native oxide (typically about 10 angstroms). In some embodiments, the process time of the first stage of the cleaning process is between about 20 seconds and about 50 seconds, or about 40 seconds, or about 30 seconds. In some embodiments, the process time of the first stage of the cleaning process is between about 1 minute and about 5 minutes.

[0102] In some embodiments, the first cleaning solution may further include fluoride compounds(s), organic acid salts, and / or glyoxylic acid.

[0103] Fluorine compounds may be included in the first cleaning solution as a component for removing residues (e.g., etching residues ER). Examples of fluorine compounds include hydrofluoric acid and ammonium fluoride, or fluorinated amine salts, such as ammonium fluoride, ammonium hydrogen fluoride, methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrofluoride, methylethanolamine hydrofluoric acid, dimethylethanolamine hydrofluoric acid, and triethylenediamine hydrofluoric acid. In some embodiments, the concentration of the fluorine compound in the pre-cleaning solution may be determined based on the composition of the etching residue ER. For example, the concentration of the fluorine compound may be between about 0.1% by mass and about 5% by mass of the overall composition of the first cleaning solution, or between about 0.2% by mass and about 3% by mass of the overall composition of the first cleaning solution.

[0104] Organic acid salts may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. Organic acid salts may act as pH adjusters or buffers in the first cleaning solution. The concentration of the organic acid salt is between about 0.1% by mass and about 10% by mass of the overall composition of the first cleaning solution, or between about 0.3% by mass and about 5% by mass of the overall composition of the first cleaning solution.

[0105] Glyoxylic acid contained in the first cleaning solution can be used as a corrosion inhibitor.

[0106] In some embodiments, the first cleaning solution may further include a photoresist removal component. Examples of photoresist removal components include tetramethylammonium hydroxide and / or monomethylamine.

[0107] An inter-stage rinse is performed after the first stage of the cleaning process. During the inter-stage rinse, the semiconductor device semi-finished product following the first stage of the cleaning process can be rotated at a speed between approximately 10 rpm and approximately 1000 rpm while being rinsed with deionized water. In some embodiments, the rinse temperature is between approximately 19°C and approximately 23°C. In some embodiments, the inter-stage rinse duration is between approximately 20 seconds and approximately 50 seconds, or approximately 30 seconds.

[0108] In some embodiments, the deionized water used for the first-stage inter-rinse may be oxidized or ozonated by dissolved oxygen or ozone gas before rinsing the semiconductor device semi-finished product. Dissolved oxygen or ozone may be added to the deionized water at a concentration greater than 1 ppm as an oxidant. For example, the concentration of dissolved oxygen or ozone may be between about 1 ppm and about 200 ppm, or between about 2 ppm and about 20 ppm. Alternatively, the dissolved oxygen or ozone in the deionized water may be saturated. Alternatively, hydrogen peroxide at a concentration greater than 100 ppm may be added to the deionized water as an oxidant. Regardless of the oxidant used, it should have an oxidation potential sufficient to oxidize the most inert metal in the solution. Copper (Cu) 2+The standard reduction potential of metal ions is 0.3V, and it is typically the most inert metal among them. Therefore, a standard reduction potential greater than 0.5V is required. Oxygen or ozone dissolves metal ions and prevents precipitation by oxidizing them in the solution. This helps to reduce processing time by making the first-stage rinsing more efficient.

[0109] In some embodiments, the deionized water used for the first-stage inter-rinse may contain dissolved carbon dioxide to dissipate static electricity accumulated in the deionized water. This static electricity may originate from the rotation of a semiconductor device semi-finished product. The dissolved carbon dioxide may also increase the acidity of the deionized water, thereby reducing metal contamination. In some embodiments, carbon dioxide is dissolved in the deionized water in an amount sufficient to dissipate static electricity; for example, the amount of carbon dioxide dissolved in the deionized water may be sufficient to reduce the resistivity of the deionized water to less than 5 megohm-cm.

[0110] In some embodiments, the deionized water used for the first-stage inter-rinse may contain isopropanol or any other liquid with a surface tension lower than that of deionized water. Isopropanol can help remove chemicals more quickly by spreading the deionized water across the front side of the semiconductor device semi-finished product. Isopropanol can also help remove rinsing fluid from the semiconductor device semi-finished product during rotation. Alternatively, isopropanol vapor can be blown onto the front side of the semiconductor device semi-finished product while rinsing to assist the first-stage inter-rinse.

[0111] In some embodiments, the deionized water used to remove the pre-cleaning solution may have a similar treatment to the deionized water used during the inter-stage rinsing.

[0112] In some embodiments, during the second stage of the cleaning process, the semiconductor device semi-finished product after rinsing between the first and second stages can be rotated at a rate between about 10 rpm and about 2000 rpm, or between about 100 rpm and 1000 rpm. A second cleaning solution is sprayed onto the semiconductor device semi-finished product to cover its entire front side. While the second cleaning solution is being applied to the front side of the semiconductor device semi-finished product, water or other suitable solution can be applied to the back side of the semiconductor device semi-finished product to clean it.

[0113] In some embodiments, the second cleaning solution may be an alkaline solution, including, for example, aqueous solutions of inorganic compounds such as sodium hydroxide, potassium hydroxide, and ammonium hydroxide, and aqueous solutions of organic compounds such as tetramethylammonium hydroxide and choline. The second cleaning solution may also include hydrogen peroxide. The role of ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particulate matter and residual organic contaminants from the front side of the semiconductor device semi-finished product.

[0114] For example, in this embodiment, the second cleaning solution comprises ammonium hydroxide, hydrogen peroxide, and water. The concentrations of ammonium hydroxide, hydrogen peroxide, and water can be defined by dilution ratios between 5 / 1 / 1 and 1000 / 1 / 1, respectively. In some embodiments, the ratio of ammonium hydroxide to hydrogen peroxide can vary between 0.05 / 1 and 5 / 1. In some embodiments, hydrogen peroxide may be omitted entirely. The ammonium hydroxide in the second cleaning solution will be derived from a solution with an ammonia-to-water ratio between 28% w / w and 29% w / w. The hydrogen peroxide in the second cleaning solution will be derived from a solution with a hydrogen peroxide-to-water ratio between 31% w / w and 32% w / w. Due to the ammonium hydroxide and hydrogen peroxide, the pH of the second cleaning solution can be between about 9 and about 12, or between about 10 and about 11.

[0115] In some embodiments, the second cleaning solution may further comprise a chelating agent. The chelating agent in the second cleaning solution may have a similar compound and concentration to the chelating agent in the pre-cleaning solution, which will not be elaborated further here.

[0116] In some embodiments, the second cleaning solution may further comprise a surfactant. The surfactant in the second cleaning solution may have similar compounds and concentrations to those in the pre-cleaning solution, and will not be elaborated further here.

[0117] In some embodiments, the second cleaning solution may further comprise dissolved hydrogen. The dissolved hydrogen in the second cleaning solution can provide porosity (bubble generation) to the second cleaning solution. Providing porosity to the second cleaning solution can enhance the cleaning process. In some embodiments, the concentration of dissolved hydrogen is between about 0.01 mg / L and about 5 mg / L, or between about 0.1 mg / L and about 5 mg / L. In some embodiments, other suitable porosiforming gases, such as nitrogen, helium, argon, or oxygen, may also be used. For example, dissolved oxygen having a concentration of about 1 mg / L to about 20 mg / L can be used in the second cleaning solution.

[0118] In some embodiments, the process time of the second stage of the cleaning process is between about 30 seconds and about 100 seconds, between about 30 seconds and 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning solution is between about 40°C and about 85°C.

[0119] The second-stage rinse will be performed after the second stage of the cleaning process. The second-stage rinse can be performed using a similar procedure to the first-stage rinse, and will not be described in detail here.

[0120] In some embodiments, during the third stage of the cleaning process, the semiconductor device semi-finished product after rinsing between the second and third stages may be rotated at a rate between about 10 rpm and about 2000 rpm, or between about 100 rpm and 1000 rpm. A third cleaning solution is sprayed onto the semiconductor device semi-finished product to cover its entire front side. While the third cleaning solution is applied to the front side of the semiconductor device semi-finished product, water or other suitable solution may be applied to the back side of the semiconductor device semi-finished product to clean it.

[0121] In some embodiments, the third cleaning solution may be an acidic solution, including, for example, aqueous solutions of inorganic acids such as hydrochloric acid, hydrofluoric acid, sulfuric acid, and nitric acid, and aqueous solutions of organic acids such as oxalic acid, citric acid, malonic acid, malic acid, fumaric acid, and maleic acid. In some embodiments, the third cleaning solution may also include hydrogen peroxide. The concentration of the acidic solution may be from about 0.001 wt% to about 10 wt%, or from about 0.01 wt% to about 5 wt%. When the concentration is too low, sufficient cleaning effect may not be achieved. When the concentration is too high, metal corrosion of the cleaning equipment or other related equipment may occur.

[0122] A post-cleaning rinse can be performed after the third stage of the cleaning process. The post-cleaning rinse can be performed using a procedure similar to that between the first and second stages, which will not be elaborated here.

[0123] In some embodiments, the second and third stages of the cleaning process are optional; in other words, only the first stage of the cleaning process may be performed. In some embodiments, the third stage of the cleaning process is optional; in other words, only the first and second stages of the cleaning process may be performed.

[0124] Traditionally, cleaning processes are performed using diluted hydrofluoric acid alone without any pre-cleaning treatment. After the conductive material is filled into the feature opening 105-1, the underlying conductive layer may be damaged, causing contour defects (e.g., undercut) or electron migration. In contrast, in this embodiment, the underlying conductive layer can be protected by chelating agents and / or corrosion inhibitors contained in the pre-cleaning solution, resulting in reduced or avoided contour defects or electron migration. Therefore, the yield and reliability of the resulting semiconductor device 1A can be improved.

[0125] Reference Figure 1 and Figures 6 to 8 In step S17, a barrier layer 111, an auxiliary barrier layer 113, and a conductive feature 115 are sequentially formed in the feature opening 105-1.

[0126] Reference Figure 6The layer of the first conductive material 501 is conformally formed on the first hard mask layer 109 and in the inner surface of the feature opening 105-1 (i.e., the sidewalls and bottom surface of the feature opening 105-1). For example, the first conductive material 501 may be tantalum. The layer of the first conductive material 501 may be formed by, for example, atomic layer deposition or other suitable deposition processes.

[0127] Reference Figure 6 The second conductive material 405 layer is conformally formed on the first conductive material 501 layer. The second conductive material 503 may be manganese. The second conductive material 503 layer may be formed by, for example, atomic layer deposition or other suitable deposition processes.

[0128] Reference Figure 7 A layer of third conductive material 505 is formed on top of the layer of second conductive material 503 and can completely fill the feature opening 105-1. The third conductive material 505 can be copper. The layer of third conductive material 505 can be formed by, for example, chemical vapor deposition, physical vapor deposition, sputtering, or other suitable deposition processes. An annealing process can be performed after the formation of the layer of third conductive material 505. The annealing process can convert the manganese in the layer of second conductive material 503 into a copper-manganese alloy. The copper-manganese alloy layer can prevent copper from diffusing to the first dielectric layer 105 or the substrate 101. As a result, electron migration of the resulting semiconductor device 1A can be reduced.

[0129] Reference Figure 8 A planarization process, such as chemical mechanical polishing, is performed until the top surface of the first dielectric layer 105 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. After the planarization process, the layer of the first conductive material 501 can be transformed into a barrier layer 111, the layer of the second conductive material 503 can be transformed into an auxiliary barrier layer 113, and the layer of the third conductive material 505 can be transformed into a conductive feature 115.

[0130] Reference Figure 8 The substrate 101, the first etch stop layer 103, the first dielectric layer 105, the barrier layer 111, the auxiliary barrier layer 113, and the conductive feature 115 together constitute the semiconductor device 1A.

[0131] Figure 9 For illustrative purposes, a flowchart is used to illustrate a method 20 for fabricating a semiconductor device 1B according to another embodiment of the present disclosure. Figures 10 to 22 For illustrative purposes, a cross-sectional view is provided to illustrate the process of fabricating semiconductor device 1B in another embodiment of this disclosure.

[0132] Reference Figures 9 to 11In step S21, a masking substrate 201 is provided, and an opaque layer 203 is formed on the masking substrate 201. The opaque layer 203 is patterned to form a masking opening 203O with a trench feature in the opaque layer 203.

[0133] Reference Figure 10 The masking substrate 201 can be formed of, for example, quartz, glass, or any other substantially transparent material. The glass can be, for example, aluminosilicate glass, calcium fluoride or magnesium fluoride, or soda-lime glass. In some embodiments, the thickness of the masking substrate 201 is between approximately 0.125 inches and approximately 0.25 inches.

[0134] Reference Figure 10 An opaque layer 203 is formed on a mask substrate 201. The opaque layer 203 can be formed from, for example, chromium, or other suitable materials that are sufficiently opaque to the incident wavelength of the energy source for the lithography process, as will be described later. In some embodiments, the opaque layer 203 can be formed by, for example, chemical vapor deposition, radio frequency sputtering, or other suitable deposition processes. In some embodiments, the thickness T1 of the opaque layer 203 is between about 500 angstroms and about 1000 angstroms. In some embodiments, the opacity of the opaque layer 203 can be 100% or substantially about 100%.

[0135] In some embodiments, alternatively, the opaque layer 203 can be formed by an electroplating process. Specifically, a cover layer (not shown) can be coated on the bottom surface 201BS and side surface 201LS of the mask substrate 201. The mask substrate 201 covered with the cover layer can then be soft-baked to enhance the adhesion between the mask substrate 201 and the cover layer and to remove all solvents from the cover layer. Subsequently, the mask substrate 201 coated with the cover layer can be immersed in a chemical chromium plating activator for surface activation. A suitable chemical chromium plating activator can be an alkaline solution of chromium chloride and 2-propanol. The activated mask substrate 201 coated with the cover layer can then be immersed in a chemical chromium plating solution to coat the opaque layer 203. After the opaque layer 203 is formed on the mask substrate 201 covered with the cover layer, the cover layer can be peeled off from the mask substrate 201.

[0136] Reference Figure 10 A second masking layer 403 can be formed on the opaque layer 203 using a photolithography process. The second masking layer 403 will include a pattern of masking openings 203O with trench features. In some embodiments, the second masking layer 403 can be a photoresist, such as the commercially available photoresist OCG895i or other suitable photoresist.

[0137] Reference Figure 11A trench etching process is performed using a second masking layer 403 as a mask to remove a portion of the opaque layer 203. After the trench etching process, a masking opening 203O with trench features can be formed in the opaque layer 203. A first portion of the top surface of the masking substrate 201 can be exposed through the masking opening 203O with trench features. In some embodiments, during the trench etching process, the etching rate ratio of the opaque layer 203 to the masking substrate 201 is between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After forming the masking opening 203O with trench features, the second masking layer 403 is removed.

[0138] Reference Figure 9 and Figures 12 to 14 In step S23, a semi-transparent layer 205 is formed in the mask opening 203O of the trench feature, and the semi-transparent layer 205 is patterned to form a mask opening 205O with a through hole feature, wherein the mask substrate 201, the opaque layer 203 and the semi-transparent layer 205 together constitute a photomask 200.

[0139] Reference Figure 12 The semi-transparent layer 205 may include, for example, molybdenum silicide or silicon nitride. In some embodiments, the semi-transparent layer 205 may be formed by, for example, chemical vapor deposition, sputtering or other suitable deposition processes. In some embodiments, the second masking layer 403 may be removed after the semi-transparent layer 205 has been formed.

[0140] In some embodiments, the thickness T2 of the translucent layer 205 is substantially the same as the thickness T1 of the opaque layer 203. In some embodiments, the thickness T2 of the translucent layer 205 and the thickness T1 of the opaque layer 203 may be different. For example, the thickness T2 of the translucent layer 205 may be greater than or less than the thickness T1 of the opaque layer 203. In some embodiments, the opacity ratio of the translucent layer 205 to the opacity of the opaque layer 203 is between about 5% and about 95%. In some embodiments, the opacity ratio of the translucent layer 205 to the opacity of the opaque layer 203 is between about 45% and about 75%. It should be noted that the first exposed portion of the top surface of the masking substrate 201 is currently completely covered by the translucent layer 205.

[0141] Reference Figure 13 A third masking layer 405 is formed through a photolithography process to cover the opaque layer 203 and a portion of the semi-transparent layer 205. The third masking layer 405 may include a pattern of masking openings 205O with via features. In some embodiments, the third masking layer 405 may be a photoresist, such as commercially available photoresist OCG895i or other suitable photoresist.

[0142] Reference Figure 14 A via etching process using a third masking layer 405 as a mask is performed to remove the exposed portion of the semi-transparent layer 205. After the via etching process, a masking opening 205O with via characteristics can be formed in the semi-transparent layer 205. A second portion of the top surface of the masking substrate 201 can be exposed through the masking opening 205O with via characteristics. In some embodiments, during the via etching process, the etching rate ratio of the semi-transparent layer 205 to the masking substrate 201 is between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the masking opening 205O with via characteristics is formed, the third masking layer 405 is removed. The surface area S1 of the first portion of the top surface of the masking substrate 201 is greater than the surface area S2 of the second portion of the top surface of the masking substrate 201.

[0143] Reference Figure 9 and Figures 15 to 18 In step S25, a device stack SK is provided, a pre-processing mask layer 301 is formed on the device stack SK, the pre-processing mask layer 301 is patterned using a photomask 200 to form an imaged mask layer 303, and a damascene etching process is performed to form a via opening 105-3 and a trench opening 107-1 on the device stack SK.

[0144] Reference Figure 15 The device stack SK may include a substrate 101, a first dielectric layer 105, and a second dielectric layer 107. The substrate 101 may have a dielectric layer 107. Figure 2 The structure of the substrate 101 shown is similar and will not be described further here. A first dielectric layer 105 can be formed on the substrate 101. The first dielectric layer 105 can be constructed using a method similar to... Figure 2 The process for forming the first dielectric layer 105 shown is not described in detail here. The second dielectric layer 107 can be formed on the first dielectric layer 105. The second dielectric layer 107 can be formed using a method similar to... Figure 2 The process for forming the first dielectric layer 105 shown is not described in detail here. In some embodiments, the thickness of the second dielectric layer 107 may be greater than the thickness of the first dielectric layer 105.

[0145] Reference Figure 15 The pre-processing mask layer 301 can be formed, for example, by spin coating onto the second dielectric layer 107. A soft baking process can be performed to remove any solvent remaining in the pre-processing mask layer 301. In some embodiments, the pre-processing mask layer 301 can be a photoresist, such as the commercially available photoresist OCG895i or other suitable photoresist.

[0146] Reference Figure 16The photomask 200 can be located above and aligned with the device stack SK. An exposure process can be performed using the photomask 200. A radiation source can be used to perform the exposure process. The radiation source can be, for example, ultraviolet radiation, deep ultraviolet radiation (typically 193 nm or 248 nm), or extreme ultraviolet radiation (typically 13.5 nm). A post-exposure baking process can be performed immediately after the exposure process. Subsequently, a development process can be performed. In the development process, an alkaline aqueous solution can be added to the pre-processing mask layer 301 after exposure and baking, and can dissolve a portion of the pre-processing mask layer 301. After the exposure process, the post-exposure baking process, and the development process, the pre-processing mask layer 301 can be transformed into an imaged mask layer 303.

[0147] Reference Figure 16 The imaged masking layer 303 includes a masking region 303M, a trench region 303T, and a via 303V. The masking region 303M may surround the trench region 303T. The masking region 303M may correspond to the opaque layer 203. That is, the masking region 303M and the opaque layer 203 may completely overlap in a top view (not shown). The trench region 303T may correspond to the translucent layer 205. That is, the masking region 303M and the opaque layer 203 may completely overlap in a top perspective view (not shown). The space surrounded by the trench region 303T is called the via 303V. A portion of the top surface of the second dielectric layer 107 can be exposed through the via 303V. The via 303V may correspond to the masking opening 205O of ​​the via feature. That is, the via 303V and the masking opening 205O of ​​the via feature may completely overlap in a top perspective view (not shown).

[0148] In some embodiments, the thickness T3 of the masking region 303M may be greater than the thickness T4 of the trench region 303T. In some embodiments, the thickness ratio of the trench region 303T thickness T4 to the thickness T3 of the masking region 303M is between about 25% and about 85%. In some embodiments, the thickness ratio of the trench region 303T thickness T4 to the thickness T3 of the masking region 303M is between about 45% and about 65%.

[0149] Reference Figure 17A patterned mask layer 303 can be used as a mask to perform a damascene etching process. In some embodiments, the etching rate of the first dielectric layer 105 and the second dielectric layer 107 may be substantially the same during the damascene etching process. In some embodiments, the etching rate ratio of the second dielectric layer 107 to the substrate 101 during the damascene etching process is between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, the etching rate ratio of the first dielectric layer 105 to the substrate 101 during the damascene etching process is between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0150] During the décor etching process, the first dielectric layer 105 and the second dielectric layer 107 beneath the trench region 303T can be temporarily protected by the trench region 303T of the patterned mask layer 303. Specifically, at the start of the décor etching process, the trench region 303T of the patterned mask layer 303 can act as an etching buffer layer to protect the underlying second dielectric layer 107. However, the trench region 303T of the patterned mask layer 303 will be continuously consumed during the décor etching process. After the trench region 303T of the patterned mask layer 303 is completely consumed, the second dielectric layer 107 corresponding to the trench region 303T will be removed.

[0151] Conversely, the first dielectric layer 105 and the second dielectric layer 107 corresponding to the via 303V of the patterned mask layer 303 do not have the patterned mask layer 303 as a temporary etch buffer layer. Therefore, at the start of the damascene etching process, the second dielectric layer 107 corresponding to the via 303V will be removed, while the second dielectric layer 107 corresponding to the trench region 303T will still be protected by the trench region 303T of the patterned mask layer 303. Thus, after the damascene etching process, both the first dielectric layer 105 and the second dielectric layer 107 corresponding to the via 303V will be removed, while only the second dielectric layer 107 corresponding to the trench region 303T will be removed. The first dielectric layer 105 corresponding to the trench region 303T will remain intact or be only slightly removed.

[0152] After the décor etching process, via openings 105-3 can be formed in the first dielectric layer 105. A portion of the substrate 101 can be exposed through via openings 105-3. Trench openings 107-1 can be formed in the second dielectric layer 107. A portion of the first dielectric layer 105 and a portion of the substrate 101 can be exposed through trench openings 107-1. After forming via openings 105-3 and trench openings 107-1, the patterned masking layer 303 will be removed.

[0153] Traditionally, via opening 105-3 and trench opening 107-1 can be formed separately using multiple etching steps. In contrast, in this embodiment, since a photomask 200 with a semi-transparent layer 205 is used, via opening 105-3 and trench opening 107-1 can be formed using a single damascene etching process.

[0154] Reference Figure 18 The patterned mask layer 303 can be removed after the etching process that forms the via openings 105-3 and the trench openings 107-1. The removal of the patterned mask layer 303 can be achieved through an ashing process or other suitable processes. After removing the patterned mask layer 303, some etching residue ER may remain.

[0155] Reference Figure 9 and Figure 19 In step S27, a pre-cleaning treatment and a cleaning process are sequentially performed on the through hole opening 105-3 and the ditch opening 107-1.

[0156] Reference Figure 19 It can be used with Figure 5 A similar procedure is used to perform the pre-cleaning process, which will not be described in detail here. The cleaning process can be performed through... Figure 5 A similar procedure will be used to execute it, which will not be described in detail here.

[0157] Reference Figure 9 and Figures 20 to 22 In step S29, a barrier layer 111 and an auxiliary barrier layer 113 are sequentially formed in the through hole opening 105-3 and the ditch opening 107-1, a through hole 117 is formed in the through hole opening 105-3, and a ditch 119 is formed in the ditch opening 107-1.

[0158] Reference Figure 20 It can be done through something like Figure 6 The process shown conformally forms a layer of the first conductive material 501 in the through-hole opening 105-3 and the trench opening 107-1, which will not be described in detail here. A layer of the second conductive material 503 is conformally formed on the layer of the first conductive material 501, and the process is similar to... Figure 6 The process shown will not be repeated here.

[0159] Reference Figure 21 A third conductive material 505 layer is formed on the second conductive material 503 layer, completely filling the through-hole opening 105-3 and the trench opening 107-1. The third conductive material 505 layer can be similar to... Figure 7 The procedure shown is as described, and will not be repeated here.

[0160] Reference Figure 22A planarization process, such as chemical mechanical polishing, is performed until the top surface of the second dielectric layer 107 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. After the planarization process, the layer of the first conductive material 501 can be transformed into a barrier layer 111, the layer of the second conductive material 503 can be transformed into an auxiliary barrier layer 113, and the layer of the third conductive material 505 can be transformed into a via 117 in the via opening 105-3 and a trench 119 in the trench opening 107-1.

[0161] Reference Figure 22 The substrate 101, the first dielectric layer 105, the second dielectric layer 107, the barrier layer 111, the auxiliary barrier layer 113, the via 117, and the trench 119 together constitute the semiconductor device 1B.

[0162] One aspect of this disclosure provides a method for fabricating a semiconductor device, comprising forming a first dielectric layer on a substrate; forming a feature opening to expose the substrate; performing a pre-cleaning process on the feature opening, the pre-cleaning process including a pre-cleaning solution; performing a cleaning process on the feature opening; and forming a conductive feature in the feature opening. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor.

[0163] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a feature opening to expose the substrate; performing a pre-cleaning process on the feature opening, the pre-cleaning process including a pre-cleaning solution; performing a cleaning process on the feature opening; conformally forming a barrier layer on the feature opening; conformally forming an auxiliary barrier layer on the barrier layer; and forming a conductive feature on the auxiliary barrier layer. The pre-cleaning solution includes a chelating agent and a corrosion inhibitor. The barrier layer includes tantalum. The auxiliary barrier layer includes a copper-manganese alloy.

[0164] Another aspect of this disclosure provides a pre-cleaning solution used prior to a cleaning process of a feature opening in a semiconductor device, comprising: a chelating agent including ethylenediaminetetraacetic acid, polyacrylate, carbonate, phosphonate, gluconate, N,N'-bis(2-hydroxyphenyl)ethylenediiminodiacetic acid, triethylenetetraaminohexaacetic acid, deferaferroamine B, N,N',N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-phenyltricarboxamide and / or ethylenediaminedi-o-hydroxyphenylacetic acid; a corrosion inhibitor comprising a fatty alcohol compound having at least one thiol group; a fluorinated amine including methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, hydrofluoroethanolamine, methylethanolamine hydrofluoride, dimethylethanolamine hydrofluoride and / or triethylenediamine hydrofluoride; a surfactant comprising polyoxyethylene butylphenyl ether, polyoxyethylene alkylphenyl sulfate, or combinations thereof; and a solvent comprising deionized water.

[0165] Due to the design of the semiconductor device fabrication method of the present invention, the underlying conductive layer exposed through the feature opening 105-1 can be protected by the chelating agent and / or corrosion inhibitor contained in the pre-cleaning solution, thereby reducing or avoiding contour defects or electron migration. Therefore, the yield and reliability of the resulting semiconductor device 1A can be improved.

[0166] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0167] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: A first dielectric layer is formed on a substrate; A distinctive opening is formed to expose the substrate; A pre-cleaning process is performed on the feature opening, the pre-cleaning process including a pre-cleaning solution; Perform a cleaning process on the feature opening; and A conductive feature is formed in the opening of this feature; The pre-cleaning solution contains a chelating agent and a corrosion inhibitor; The pre-cleaning process takes approximately 2 minutes. The chelating agents include ethylenediaminetetraacetic acid, polyacrylate, carbonate, phosphonate, gluconate, N,N'-bis(2-hydroxyphenyl)ethylenediiminodiacetic acid, triethylenetetraaminohexaacetic acid, deferasamine B, N,N',N"-tris[2-(N-hydroxycarbonyl)ethyl]-1,3,5-benzenetricarboxamide, or ethylenediamine di-o-hydroxyphenylacetic acid.

2. The method for preparing a semiconductor device as claimed in claim 1, wherein the concentration of the chelating agent is between 0.001 mg / L and 300 mg / L.

3. The method for preparing a semiconductor device as claimed in claim 2, wherein the corrosion inhibitor comprises a fatty alcohol compound having at least one thiol group.

4. The method for preparing a semiconductor device as claimed in claim 3, wherein the concentration of the corrosion inhibitor is between about 0.0001% and about 10% by weight.

5. The method for fabricating a semiconductor device as claimed in claim 4, wherein performing the cleaning process includes spraying a first cleaning solution over the feature opening, and the first cleaning solution includes diluted hydrofluoric acid.

6. The method for preparing a semiconductor device as claimed in claim 5, wherein the pre-cleaning solution comprises fluorinated amine.

7. The method for preparing a semiconductor device according to claim 6, wherein the fluorinated amine comprises methylamine hydrofluoric acid, ethylamine hydrofluoric acid, propylamine hydrofluoric acid, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrofluoric acid, methylethanolamine hydrofluoric acid, dimethylethanolamine hydrofluoric acid and / or triethylenediamine hydrofluoric acid.

8. The method for preparing a semiconductor device as claimed in claim 7, wherein the concentration of the fluorinated amine is between about 0.1% by mass and about 5% by mass of the overall composition of the pre-cleaning solution.

9. The method for preparing a semiconductor device as claimed in claim 8, wherein the pre-cleaning solution comprises a surfactant.

10. The method for preparing a semiconductor device as claimed in claim 9, wherein the surfactant comprises polyoxyethylene butylphenyl ether, polyoxyethylene alkylphenyl sulfate, or a combination thereof.

11. The method for preparing a semiconductor device as claimed in claim 10, wherein the concentration of the surfactant is between about 1 ppm and about 100 ppm.

12. The method of fabricating a semiconductor device as claimed in claim 11, further comprising performing a rinsing step between performing the cleaning process and forming the conductive feature, wherein the rinsing step includes applying deionized water to the feature opening.

13. The method for preparing a semiconductor device as claimed in claim 12, wherein the concentration of hydrofluoric acid diluted in the first cleaning solution is between 5 parts deionized water to 1 part hydrofluoric acid and 1000 parts deionized water to 1 part hydrofluoric acid.

14. The method for preparing a semiconductor device as claimed in claim 13, wherein the first cleaning solution comprises a fluorine compound, an organic acid salt, and glyoxylic acid.

15. The method for preparing a semiconductor device according to claim 14, wherein the fluorine compound includes ammonium fluoride, ammonium hydrogen fluoride, methylamine hydrofluoric acid, ethylamine hydrofluoric acid, propylamine hydrofluoric acid, tetramethylammonium hydrofluorate, tetraethylammonium hydrofluorate, ethanolamine hydrofluoric acid, methylethanolamine hydrofluoric acid, dimethylethanolamine hydrofluoric acid, or triethylenediamine hydrofluoric acid.

16. The method for preparing a semiconductor device as claimed in claim 15, wherein the concentration of the fluorine compound is from about 0.1% by mass to about 5% by mass of the overall composition of the first cleaning solution.

17. The method for preparing a semiconductor device as claimed in claim 15, wherein the organic acid salt includes ammonium oxalate, ammonium tartrate, ammonium citrate, or ammonium acetate.

18. The method for preparing a semiconductor device as claimed in claim 17, wherein the concentration of the organic acid salt is between about 0.1% by mass and about 10% by mass of the overall composition of the first cleaning solution.

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