Wafer level chip scale grain interface signal fan-out substrate and layout design method thereof

Abstract

The application discloses a wafer-level chip-in-die interface signal fan-out substrate and a layout design method thereof. The signal fan-out substrate comprises a plurality of substrate units arranged in an array. Each substrate unit comprises a pad in contact with an I / O port of a die, a row of first pins and a row of second pins arranged along a first edge and a second edge of the substrate unit respectively, and a row of first bumps located in the middle region of the substrate unit. The first edge is opposite to the second edge. The contact pad is connected with the first pin. The second pin is connected with the first bump one by one. The nth second pin is connected with the (n+1)th first pin to realize staggered connection. In the direction perpendicular to the first edge, the first edge and the second edge of the adjacent two substrate units are adjacent, and the first pin arranged along the first edge is connected with the second pin arranged along the second edge one by one. Each die on the signal fan-out substrate has a separate fan-out path to fan out to the edge of the signal fan-out substrate.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a signal fan-out substrate for a wafer-level chip die interface and its layout design method. Background Technology

[0002] In chip manufacturing, due to limitations in mask size, multiple isomorphic circuit patterns must be reused and spliced ​​to form a wafer before production. In wafer-level chip manufacturing, functional dies (DIEs) are placed on the surface of an interposer layer. Interposers enable die-to-die connections, allowing signals from dies in the middle region to be transmitted to the outside. However, for dies located in the middle region, their ports (I / O) cannot be fanned out to the overall edge through a single path.

[0003] Figure 1 This is a schematic diagram showing the position coordinates of contact pads connected to die I / O ports in the interposer layer, as provided in the prior art. Figure 1 As shown, the I / O ports located at coordinates D(1,1), D(1,2), D(1,3), D(2,1), D(2,2), and D(2,3) cannot reach the boundary via a single path. For example, D(1,1) cannot form a single signal path that does not overlap with D(0,1) to reach D(-1,1). The method of transmitting information from intermediate chips to the outside through inter-chip interconnects relies heavily on the completeness of the chips and their interconnects. This is especially true for interfaces required for software debugging and hardware signal observation, which require the use of peripheral chip paths. This places high demands on chip design, inter-chip interconnect architecture, and manufacturing processes. Summary of the Invention

[0004] This invention provides a signal fan-out substrate for wafer-level chip die interface and its layout design method, so as to realize that each die's I / O port has a separate fan-out path to the edge of the chip, reducing the additional design required for interconnects on the die.

[0005] According to one aspect of the present invention, a signal fan-out substrate is provided, comprising a plurality of substrate units arranged in an array and having the same structure; wherein each substrate unit comprises:

[0006] The substrate unit includes a contact pad that contacts the I / O port of the corresponding die, a row of first pins along a first side of the substrate unit, a row of second pins along a second side of the substrate unit, and a row of first bumps located in the middle region of the substrate unit; the first side is the opposite side of the second side.

[0007] Wherein, the number of the first pins is the same as the number of the second pins and the number of the first bumps; the contact pad is connected to the first first pin; the second pins are connected to the first bumps in a one-to-one correspondence; the nth second pin is connected to the (n+1)th first pin to achieve a staggered connection, where n is an integer greater than 0;

[0008] In the direction perpendicular to the first side, the first side and the second side of two adjacent substrate units are adjacent, and the first pin provided along the first side and the second pin provided along the second side are connected in a one-to-one correspondence, so that the I / O port of each die located on the signal fan-out substrate has a separate fan-out path to the edge of the signal fan-out substrate.

[0009] Optionally, the first side and the second side are parallel to each other; the second side is parallel to the row where the first protrusion is located.

[0010] The nth first pin, the nth second pin, and the nth first bump are located on the same straight line, and the straight line is perpendicular to the first side.

[0011] Optionally, the signal fan-out substrate includes opposing first and second sides;

[0012] The contact pad is located on the first side of the signal fan-out substrate; the first bump is located on the second side of the signal fan-out substrate; the first pin and the second pin are located inside the signal fan-out substrate.

[0013] Optionally, the distance between two adjacent substrate units is less than a preset value; the substrate unit is rectangular in shape.

[0014] Optionally, the signal fan-out substrate includes a first bonding area and a second bonding area located at the edge of the first bonding area;

[0015] The array of identical substrate units is located in the first bonding region; the first bonding region is used to bond the die.

[0016] The second bonding area includes a row of second bumps, the second bumps and the first bumps are located on the same side of the signal fan-out substrate; the second bumps are arranged along the first side of the outermost substrate unit and are connected one-to-one with the first pin of the outermost substrate unit, so that the I / O port of each die in the signal fan-out substrate fans out to the second bump of the second bonding area; the second bonding area is used to bond the adapter substrate.

[0017] Optionally, the number of second bonding regions is one, and it is arranged along an entire side of the first bonding region; the I / O ports of each die in the signal fan-out substrate fan out to the same side of the signal fan-out substrate;

[0018] Alternatively, there may be multiple second bonding regions; at least two second bonding regions may be located on different sides of the first bonding region; and the I / O ports of the die in the signal fan-out substrate may fan out to at least two sides of the signal fan-out substrate.

[0019] According to another aspect of the present invention, a method for designing a signal fan-out substrate layout is provided, for designing the layout of the wafer-level chip-die interface signal fan-out substrate as described in any embodiment of the present invention; the design method includes:

[0020] The substrate unit pattern is designed based on the preset structure of the substrate unit; the substrate unit pattern includes contact pad coordinate points corresponding to the I / O ports of the die, a row of first pin coordinate points arranged along a first side of the substrate unit pattern, a row of second pin coordinate points arranged along a second side of the substrate unit pattern, and a row of bump coordinate points located in the middle region of the substrate unit pattern; the first side is the opposite side of the second side; the number of first pin coordinate points is the same as the number of second pin coordinate points and the number of bump coordinate points;

[0021] Connect the coordinate point of the contact pad to the coordinate point of the first first pin, connect the coordinate point of the second pin to the coordinate point of the bump in a one-to-one correspondence, and connect the coordinate point of the nth second pin to the left point of the (n+1)th first pin to achieve a staggered connection, where n is an integer greater than 0;

[0022] The substrate unit patterns are reused and spliced ​​to form a preliminary layout of a signal fan-out substrate having multiple arrayed substrate unit patterns; wherein, in the direction perpendicular to the first side, the first side and the second side of two adjacent substrate unit patterns are adjacent, and the first pin coordinate point set along the first side and the second pin coordinate point set along the second side are connected one-to-one, so that each contact pad coordinate point located in the preliminary layout of the signal fan-out substrate has a separate fan-out path to the edge of the preliminary layout of the signal fan-out substrate.

[0023] Based on the number of substrate units in the signal fan-out substrate, a preliminary layout of the signal fan-out substrate is extracted to form a signal fan-out substrate layout that meets the quantity requirements.

[0024] Optionally, reusing the substrate unit patterns and splicing them together to form a preliminary layout of a signal fan-out substrate having multiple substrate unit patterns arranged in an array includes:

[0025] The substrate unit pattern is reused and spliced ​​along the column direction to form a first array pattern; wherein the column direction is perpendicular to the first side, and the difference between the number of substrate unit patterns included in the first array pattern and the number of substrate unit patterns in a column of the signal fan-out substrate layout is greater than or equal to 2.

[0026] The first array pattern is reused and spliced ​​along the row direction to form the preliminary layout of the signal fan-out substrate; wherein the row direction is parallel to the first side; the difference between the number of substrate unit patterns in a row of the preliminary layout of the signal fan-out substrate and the number of substrate unit patterns in a row of the layout of the signal fan-out substrate is greater than or equal to 2.

[0027] Optionally, based on the number of substrate units in the signal fan-out substrate, a preliminary layout of the signal fan-out substrate is extracted to form a signal fan-out substrate layout that meets the quantity requirements, including:

[0028] The first bonding area in the signal fan-out substrate layout is determined based on the number of substrate units in the signal fan-out substrate.

[0029] The second bonding area in the signal fan-out substrate layout is determined based on the area in the signal fan-out substrate that is connected to the adapter substrate.

[0030] The project cut-off area is determined based on the first binding area and the second binding area;

[0031] The preliminary layout of the signal fan-out substrate is cut out according to the engineering cut-out area to form a signal fan-out substrate layout that meets the quantity requirements.

[0032] Beneficial Effects: This invention provides a signal fan-out substrate for a die interface in a wafer-level chip and its layout design method. The signal fan-out substrate includes multiple substrate units arranged in an array and having the same structure. Each substrate unit includes: a contact pad that contacts the I / O port of the corresponding die, a row of first pins along a first side of the substrate unit, a row of second pins along a second side of the substrate unit, and a row of first bumps located in the middle region of the substrate unit. The first side is the opposite side of the second side. The number of first pins is the same as the number of second pins and the number of first bumps. The contact pad is connected to the first first pin. The second pins are connected to the first bumps in a one-to-one correspondence. The nth second pin is connected to the (n+1)th first pin to achieve a staggered connection, where n is an integer greater than 0. In the direction perpendicular to the first side, the first and second sides of two adjacent substrate units are adjacent, and the first pins along the first side are connected to the second pins along the second side in a one-to-one correspondence, so that the I / O port of each die located on the signal fan-out substrate has a separate fan-out path to the edge of the signal fan-out substrate. The technical solution provided by this invention can fan out I / O to the wafer edge through a simple path design of the signal fan-out substrate, eliminating the need to develop complex DIE2DIE interconnect protocols and sampling designs, reducing development costs, improving system yield and robustness, and greatly enriching testing and positioning methods.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram showing the position coordinates of a contact pad connected to a die I / O port in the interposer layer, as provided in the prior art.

[0036] Figure 2 This is a schematic diagram of the structure of a signal fan-out substrate for a wafer-level chip-die interface provided in an embodiment of the present invention;

[0037] Figure 3 yes Figure 2 Top perspective view of the substrate unit in the structure shown;

[0038] Figure 4This is a side view of a substrate unit provided in an embodiment of the present invention;

[0039] Figure 5 This is a flowchart of a design method for a signal fan-out substrate layout provided in an embodiment of the present invention;

[0040] Figures 6-9 This is a schematic diagram of the layout during steps S110 to S140 of a signal fan-out substrate layout design method provided in an embodiment of the present invention. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] This invention provides a signal fan-out substrate for a wafer-level chip-die interface. Figure 2 This is a schematic diagram of the signal fan-out substrate for a wafer-level chip-die interface provided in an embodiment of the present invention. Figure 3 yes Figure 2 Top perspective view of the substrate unit in the structure shown. Figure 2 and Figure 3 This only illustrates the relative positions of various structures within the substrate unit in a top-view orientation; it does not show the film layer relationships of these structures. (Reference) Figure 2 and Figure 3 The signal fan-out substrate 1 includes multiple substrate units 100 arranged in an array and having the same structure; wherein each substrate unit 100 includes:

[0044] The contact pad Q is in contact with the I / O port of the corresponding die, a row of first pins FP is provided along the first side L1 of the substrate unit 100, a row of second pins SP is provided along the second side L2 of the substrate unit 100, and a row of first bumps FB is located in the middle region of the substrate unit 100; the first side L1 is the opposite side of the second side L2.

[0045] In this configuration, the number of first pins FP is the same as the number of second pins SP and the number of first bumps FB; the contact pad Q is connected to the first first pin FP; the second pins SP are connected to the first bumps FB in a one-to-one correspondence; the nth second pin SP is connected to the (n+1)th first pin FP to achieve a staggered connection, where n is an integer greater than 0.

[0046] In the direction perpendicular to the first side L1, the first side L1 and the second side L2 of two adjacent substrate units 100 are adjacent, and the first pin FP provided along the first side L1 and the second pin SP provided along the second side L2 are connected in a one-to-one correspondence, so that the I / O port of each die located on the signal fan-out substrate 1 has a separate fan-out path to the edge of the signal fan-out substrate 1.

[0047] Specifically, the signal fan-out substrate 1 is used to carry the die, and the I / O ports of the die are connected to the contact pads Q in a one-to-one manner, thereby forming a wafer-level chip. The signal fan-out substrate 1 is also used to fan out the I / O ports of each die to the edge of the signal fan-out substrate 1, so that electronic devices that transmit signals to the I / O ports of the die can be placed around the wafer-level chip. Compared with placing the electronic devices at the bottom of the wafer-level chip, fanning out the I / O ports of each die to the edge of the signal fan-out substrate 1 eliminates the need to limit the size of the electronic devices and facilitates the connection with the electronic devices. The number of first pins FP, the number of second pins SP, and the number of first bumps FB depend on the size of the array composed of substrate units 100.

[0048] Figure 2 and Figure 3In the example, the number of first pins (FP), second pins (SP), and first bumps (FB) are all 7. The contact pad Q is connected to the first first pin (FP1). Second pins (SP) are connected one-to-one with first bumps (FB), i.e., the first second pin (SP1) is connected to the first first bump (FB1), the second second pin (SP2) is connected to the second first bump (FB2), the third second pin (SP3) is connected to the third first bump (FB3), and so on. The nth second pin (SP) is connected to the (n+1)th first pin (FP) in a staggered connection manner, where n is a positive integer; i.e., the first second pin (SP1) is connected to the second first pin (FP2), the second second pin (SP2) is connected to the third first pin (FP3), and so on, until the sixth second pin (SP6) is connected to the seventh first pin (FP7).

[0049] Figure 2 and Figure 3 In the diagram, the first side is shown as the upper edge of the substrate unit 100, and the second side is shown as the lower edge of the substrate unit 100. The direction perpendicular to the first side L1 is the column direction Y of the arrayed substrate units 100. In the direction perpendicular to the first side L1, the first side L1 and the second side L2 of two adjacent substrate units 100 are adjacent, that is, the first side of one substrate unit 100 is adjacent to the second side of another substrate unit 100; and the first pin FP provided along the first side L1 and the second pin SP provided along the second side L2 are connected one-to-one, so that the I / O port of each die located on the signal fan-out substrate 1 has a separate fan-out path to the edge of the signal fan-out substrate 1.

[0050] The technical solution provided by this invention forms the signal fan-out substrate 1 of this invention by setting a staggered connection method when designing the interposer of the wafer-level chip. This achieves the effect that each computing die's I / O port in the wafer-level chip has a separate fan-out path to the edge. This eliminates the need to develop complex DIE2DIE interconnect protocols and sampling designs, reduces development costs, improves system yield and robustness, and greatly enriches testing and positioning methods.

[0051] Optional, please continue to refer to Figure 2 and Figure 3 The first side L1 and the second side L2 are parallel to each other; the second side L2 is parallel to the row where the first protrusion FB is located.

[0052] The nth first pin FP, the nth second pin SP, and the nth first bump FB are located on the same straight line, and the line is perpendicular to the first side L1. That is, the first first pin FP1, the first second pin SP1, and the first first bump FB1 are located on the same straight line; the second first pin FP2, the second second pin SP2, and the second first bump FB1 are located on the same straight line; the third first pin FP3, the third second pin SP3, and the third first bump FB3 are located on the same straight line, and so on; and the line is perpendicular to the first side L1 in all cases.

[0053] Specifically, the row containing the first bump FB is parallel to both the first side L1 and the second side L2, and the nth first pin FP, the nth second pin SP, and the nth first bump FB are located on the same straight line, with the line perpendicular to the first side L1. This facilitates the connection between the first pin FP, the second pin SP, and the first bump FB, preventing cross-connection issues. The first bump FB is formed of a metal material on the surface of the substrate unit 100; the contact pad Q is also formed of a metal material on the surface of the substrate unit 100. The first pin FP and the second pin SP are both formed of a metal material inside the substrate unit 100. The signal fan-out substrate 1 can be composed of multiple layers of stacked silicon or organic layers and a redistribution layer (RDL). The material of the redistribution layer can include conductive materials such as metals. The second pin SP is connected to the first bump FB through metal lines and connecting holes in the substrate unit 100. The second pin SP and the first pin FP are connected at least through metal lines in the substrate unit 100. The contact pad Q is connected to the first pin FP1 through a metal line and a connection hole in the substrate unit 100.

[0054] Optionally, the signal fan-out substrate 1 includes a first side and a second side opposite to each other. Figure 4 This is a side view of a substrate unit provided in an embodiment of the present invention, with reference to... Figure 4 Taking a substrate unit 100 in a signal fan-out substrate 1 as an example, the contact pad Q is located on the first side of the signal fan-out substrate 1; the first bump FB is located on the second side of the signal fan-out substrate 1. By positioning the contact pad Q and the first bump FB on two opposite sides of the signal fan-out substrate 1, it prevents the second pin SP and the first pin FP located inside the substrate from converging towards one side of the signal fan-out substrate 1, thereby increasing the distance between the metal lines inside the substrate and preventing short circuits caused by defects inside the substrate. Furthermore, since the die is typically located on the side of the signal fan-out substrate 1 with the contact pad Q, placing the first bump FB on the other side of the signal fan-out substrate 1 avoids the influence of the first bump FB on the die placement.

[0055] Optionally, the distance between two adjacent substrate units 100 is less than a preset value; in this embodiment of the invention, the distance between two adjacent substrate units 100 is equal to zero. The substrate unit 100 is rectangular in shape.

[0056] Optional, please continue to refer to Figure 2 and Figure 3 The signal fan-out substrate 1 includes a first bonding region 01 and a second bonding region 02 located at the edge of the first bonding region 01; wherein, a plurality of substrate units 100 arranged in an array and having the same structure are located in the first bonding region 01; the first bonding region 01 is used to bond the die;

[0057] The second bonding area 02 includes a row of second bumps SB, which are located on the same side of the signal fan-out substrate 1 as the first bumps FB. The second bumps SB are disposed along the first side L1 of the outermost substrate unit 100 of the first bonding area 01 and are connected one-to-one with the first pins FP of the outermost substrate unit 100 of the first bonding area 01, so that the I / O ports of each die in the signal fan-out substrate 1 fan out to the second bumps SB of the second bonding area 02. The second bonding area 02 is used to bond the adapter substrate.

[0058] Specifically, the I / O ports of each die are fanned out to the second bump SB corresponding to the second bonding area 02 via a staggered connection of the first pin FP and the second pin SP. The second bump SB is used to connect to the adapter substrate, which is equipped with various electronic devices, thereby enabling communication between the die's I / O ports and the electronic devices. In other words, each die's I / O port has a separate second bump SB to output signals or receive external signals.

[0059] In one embodiment of the present invention, there is one second bonding region 02, which is arranged along an entire side of the first bonding region 01; the I / O ports of each die in the signal fan-out substrate 1 fan out to the same side of the signal fan-out substrate 1.

[0060] For example, refer to Figure 2 and Figure 3 The first side L1 can be the upper edge of the substrate unit 100, and the second side L2 is the lower edge of the substrate unit 100; the I / O ports of each die in the signal fan-out substrate 1 fan out to the upper side of the signal fan-out substrate 1.

[0061] Alternatively, the first side L1 can be the lower edge of the substrate unit 100, and the second side L2 can be the upper edge of the substrate unit 100; the I / O ports of each die in the signal fan-out substrate 1 fan out to the lower side of the signal fan-out substrate 1 (not shown).

[0062] Alternatively, the first side L1 can be the left edge of the substrate unit 100, and the second side L2 can be the right edge of the substrate unit 100; the I / O ports of each die in the signal fan-out substrate 1 fan out to the left side of the signal fan-out substrate 1 (not shown), and the direction perpendicular to the first side L1 is the row direction.

[0063] Alternatively, the first side L1 can be the right edge of the substrate unit 100, and the second side L2 can be the left edge of the substrate unit 100; the I / O ports of each die in the signal fan-out substrate 1 fan out to the right side of the signal fan-out substrate 1 (not shown), and the direction perpendicular to the first side L1 is the row direction.

[0064] The embodiments of the present invention can enable the I / O ports of the die to fan out in any direction.

[0065] In another embodiment of the present invention, there are multiple second bonding regions 02; at least two second bonding regions 02 are located on different sides of the first bonding region 01; the I / O ports of the die in the signal fan-out substrate 1 fan out to at least two sides of the signal fan-out substrate 1.

[0066] For example, the substrate unit 100 is still arranged in an array of four rows and five columns.

[0067] In the odd-numbered column of substrate units 100, the first side L1 can be the upper edge of the substrate unit 100, and the second side L2 is the lower edge of the substrate unit 100; the I / O ports of each die in the odd-numbered column of the signal fan-out substrate 1 fan out to the upper side of the signal fan-out substrate 1. In the even-numbered column of substrate units 100, the first side L1 can be the lower edge of the substrate unit 100, and the second side L2 is the upper edge of the substrate unit 100; the I / O ports of each die in the even-numbered column of the signal fan-out substrate 1 fan out to the lower side of the signal fan-out substrate 1.

[0068] For example, in the first two rows of substrate units 100, the first edge L1 can be the upper edge of the substrate unit 100, and the second edge L2 is the lower edge of the substrate unit 100; the I / O ports of each die in the first two rows of the signal fan-out substrate 1 fan out to the upper side of the signal fan-out substrate 1. In the last two rows of substrate units 100, the first edge L1 can be the lower edge of the substrate unit 100, and the second edge L2 is the upper edge of the substrate unit 100; the I / O ports of each die in the last two rows of the signal fan-out substrate 1 fan out to the lower side of the signal fan-out substrate 1. It should be noted that there is no pin connection between the first two rows of substrate units 100 and the last two rows of substrate units 100.

[0069] For example, in the first two columns of substrate units 100, the first side L1 can be the left edge of the substrate unit 100, and the second side L2 can be the right edge of the substrate unit 100; the I / O ports of each die in the first two columns of the signal fan-out substrate 1 fan out to the left side of the signal fan-out substrate 1. In the last three columns of substrate units 100, the first side L1 can be the right edge of the substrate unit 100, and the second side L2 can be the left edge of the substrate unit 100; the I / O ports of each die in the last three columns of the signal fan-out substrate 1 fan out to the right side of the signal fan-out substrate 1. It should be noted that there is no pin connection between the first two columns of substrate units 100 and the last three columns of substrate units 100.

[0070] The embodiments of the present invention can fan out the I / O ports of the die in multiple directions.

[0071] This invention also provides a method for designing a signal fan-out substrate layout, used to design the layout of the signal fan-out substrate for the wafer-level chip-die interface as described in any embodiment of this invention; Figure 5 This is a flowchart illustrating a design method for a signal fan-out substrate layout provided in an embodiment of the present invention. Figures 6-9 This is a schematic diagram of the layout during steps S110 to S140 of a signal fan-out substrate layout design method provided in an embodiment of the present invention. (Refer to...) Figures 5-9 The design methods include:

[0072] S110. Design the substrate unit pattern based on the preset structure of the substrate unit.

[0073] refer to Figure 6 The substrate unit pattern 101 includes contact pad coordinate points q corresponding to the I / O ports of the die, a row of first pin coordinate points set along the first side L1 of the substrate unit pattern 101, a row of second pin coordinate points set along the second side L2 of the substrate unit pattern, and a row of bump coordinate points located in the middle region of the substrate unit pattern. Figure 6 The example shows the coordinates of the first pin (fp1) to the seventh pin (fp7), the first second pin (sp1) to the seventh second pin (sp7), and the first bump (b1) to the seventh bump (b7). The first edge L1 is the opposite edge of the second edge L2; the number of first pin coordinates is the same as the number of second pin coordinates and the number of bump coordinates.

[0074] S120: Connect the contact pad coordinate point to the first pin coordinate point, connect the second pin coordinate point to the bump coordinate point in a one-to-one correspondence, and connect the nth second pin coordinate point to the left point of the (n+1)th first pin to achieve a staggered connection, where n is an integer greater than 0. (See details) Figure 6 )

[0075] S130. Reuse substrate unit patterns and splice them together to form a preliminary layout of a signal fan-out substrate with multiple arrayed substrate unit patterns.

[0076] For details, please refer to Figures 7-8 The following example demonstrates how to construct a 4x5 array with an upward fan-out interface. A 6x7 matrix is ​​required to ensure engineering reliability, meaning that the shortest path needs 6 redundant paths to ensure that the same coordinates of each multiplexed substrate unit pattern do not intersect or repeat at the boundary.

[0077] The preliminary layout of a signal fan-out substrate is formed by reusing substrate unit patterns and splicing them together to create a series of substrate unit patterns arranged in an array. Specifically, this includes:

[0078] refer to Figure 7 The substrate unit patterns are reused and spliced ​​along the column direction Y to form a first array pattern; wherein the column direction Y is perpendicular to the first side L1, and the difference between the number of substrate unit patterns included in the first array pattern and the number of substrate unit patterns in a column of the signal fan-out substrate layout is greater than or equal to 2.

[0079] refer to Figure 8 The first array pattern is reused and spliced ​​along the row direction to form a preliminary layout of the signal fan-out substrate; wherein the row direction is parallel to the first side; the difference between the number of substrate unit patterns in a row of the preliminary layout of the signal fan-out substrate and the number of substrate unit patterns in a row of the signal fan-out substrate layout is greater than or equal to 2.

[0080] In the preliminary layout of the signal fan-out substrate, in the direction perpendicular to the first side, the first side L1 and the second side L2 of two adjacent substrate unit patterns are adjacent, and the first pin coordinate point set along the first side L1 and the second pin coordinate point set along the second side L2 are connected in a one-to-one correspondence, so that each contact pad coordinate point located in the preliminary layout of the signal fan-out substrate has a separate fan-out path to the edge of the preliminary layout of the signal fan-out substrate.

[0081] S140. Based on the number of substrate units in the signal fan-out substrate, cut out the preliminary layout of the signal fan-out substrate to form a signal fan-out substrate layout that meets the quantity requirements.

[0082] Optional, see reference Figure 9 Based on the number of substrate units in the signal fan-out substrate, a preliminary layout of the signal fan-out substrate is extracted to form a signal fan-out substrate layout that meets the quantity requirements, including:

[0083] The first bonding area 01 in the signal fan-out substrate layout is determined based on the number of substrate units in the signal fan-out substrate.

[0084] The second bonding area 02 in the signal fan-out substrate layout is determined based on the area in the signal fan-out substrate that is connected to the adapter substrate.

[0085] The engineering cut-off area 03 is determined based on the first binding area 01 and the second binding area 02;

[0086] According to the preliminary layout of the signal fan-out substrate in the interception area 03 of the project, a signal fan-out substrate layout that meets the quantity requirements is formed.

[0087] Wherein, the convex coordinate point in the first binding area 01 is the coordinate position of the first convex in any of the above embodiments; the convex coordinate point in the second binding area 02 is the coordinate position of the second convex in any of the above embodiments.

[0088] The technical solution provided by the embodiments of the present invention can fan out I / O to the edge of the wafer through a simple path design of the signal fan-out substrate, without the need to develop complex DIE2DIE interconnect protocols and sampling designs, thereby reducing development costs, improving system yield and robustness, and greatly enriching test and positioning methods.

[0089] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A signal fan-out substrate for a die-interface in a wafer-level chip, characterized in that, It includes multiple substrate units arranged in an array and having the same structure; wherein each substrate unit includes: The substrate unit includes a contact pad that contacts the I / O port of the corresponding die, a row of first pins along a first side of the substrate unit, a row of second pins along a second side of the substrate unit, and a row of first bumps located in the middle region of the substrate unit; the first side is the opposite side of the second side. Wherein, the number of the first pins is the same as the number of the second pins and the number of the first bumps; the contact pad is connected to the first first pin; the second pins are connected to the first bumps in a one-to-one correspondence; the nth second pin is connected to the (n+1)th first pin to achieve a staggered connection, where n is an integer greater than 0; In the direction perpendicular to the first side, the first side and the second side of two adjacent substrate units are adjacent, and the first pin provided along the first side and the second pin provided along the second side are connected in a one-to-one correspondence, so that the I / O port of each die located on the signal fan-out substrate has a separate fan-out path to the edge of the signal fan-out substrate.

2. The signal fan-out substrate for the die interface in a wafer-level chip according to claim 1, characterized in that, The first side and the second side are parallel to each other; the second side is parallel to the row containing the first protrusion. The nth first pin, the nth second pin, and the nth first bump are located on the same straight line, and the straight line is perpendicular to the first side.

3. The signal fan-out substrate for the die interface in a wafer-level chip according to claim 1, characterized in that, Including the opposing first and second sides; The contact pad is located on the first side of the signal fan-out substrate; the first bump is located on the second side of the signal fan-out substrate; the first pin and the second pin are located inside the signal fan-out substrate.

4. The signal fan-out substrate for the die interface in a wafer-level chip according to claim 1, characterized in that, The distance between two adjacent substrate units is less than a preset value; the substrate unit is rectangular in shape.

5. The signal fan-out substrate for the die interface in a wafer-level chip according to claim 1, characterized in that, Includes a first binding area and a second binding area located at the edge of the first binding area; The array of identical substrate units is located in the first bonding region; the first bonding region is used to bond the die. The second bonding area includes a row of second bumps, the second bumps and the first bumps are located on the same side of the signal fan-out substrate; the second bumps are disposed along the first side of the outermost substrate unit of the first bonding area, and are connected one-to-one with the first pin of the outermost substrate unit, so that the I / O port of each die in the signal fan-out substrate fans out to the second bump of the second bonding area; the second bonding area is used to bond the adapter substrate.

6. The signal fan-out substrate for the die interface in a wafer-level chip according to claim 5, characterized in that, The number of second bonding regions is one, and it is arranged along a whole side of the first bonding region; the I / O ports of each die in the signal fan-out substrate fan out to the same side of the signal fan-out substrate; Alternatively, there may be multiple second bonding regions; at least two second bonding regions may be located on different sides of the first bonding region; and the I / O ports of the die in the signal fan-out substrate may fan out to at least two sides of the signal fan-out substrate.

7. A method for designing a signal fan-out substrate layout, characterized in that, A layout for designing the signal fan-out substrate of the die interface in the wafer-level chip according to any one of claims 1 to 6; the design method includes: The substrate unit pattern is designed based on the preset structure of the substrate unit; the substrate unit pattern includes contact pad coordinate points corresponding to the I / O ports of the die, a row of first pin coordinate points arranged along a first side of the substrate unit pattern, a row of second pin coordinate points arranged along a second side of the substrate unit pattern, and a row of bump coordinate points located in the middle region of the substrate unit pattern; the first side is the opposite side of the second side; the number of first pin coordinate points is the same as the number of second pin coordinate points and the number of bump coordinate points; Connect the coordinate point of the contact pad to the coordinate point of the first first pin, connect the coordinate point of the second pin to the coordinate point of the bump in a one-to-one correspondence, and connect the coordinate point of the nth second pin to the left point of the (n+1)th first pin to achieve a staggered connection, where n is an integer greater than 0; The substrate unit patterns are reused and spliced ​​to form a preliminary layout of a signal fan-out substrate having multiple arrayed substrate unit patterns; wherein, in the direction perpendicular to the first side, the first side and the second side of two adjacent substrate unit patterns are adjacent, and the first pin coordinate point set along the first side and the second pin coordinate point set along the second side are connected one-to-one, so that each contact pad coordinate point located in the preliminary layout of the signal fan-out substrate has a separate fan-out path to the edge of the preliminary layout of the signal fan-out substrate. Based on the number of substrate units in the signal fan-out substrate, a preliminary layout of the signal fan-out substrate is extracted to form a signal fan-out substrate layout that meets the quantity requirements.

8. The method for designing the signal fan-out substrate layout according to claim 7, characterized in that, Reusing the aforementioned substrate unit patterns and splicing them together to form a preliminary layout of a signal fan-out substrate having multiple substrate unit patterns arranged in an array, includes: The substrate unit pattern is reused and spliced ​​along the column direction to form a first array pattern; wherein the column direction is perpendicular to the first side, and the difference between the number of substrate unit patterns included in the first array pattern and the number of substrate unit patterns in a column of the signal fan-out substrate layout is greater than or equal to 2. The first array pattern is reused and spliced ​​along the row direction to form the preliminary layout of the signal fan-out substrate; wherein the row direction is parallel to the first side; the difference between the number of substrate unit patterns in a row of the preliminary layout of the signal fan-out substrate and the number of substrate unit patterns in a row of the layout of the signal fan-out substrate is greater than or equal to 2.

9. The method for designing the signal fan-out substrate layout according to claim 7, characterized in that, Based on the number of substrate units in the signal fan-out substrate, a preliminary layout of the signal fan-out substrate is extracted to form a signal fan-out substrate layout that meets the quantity requirements, including: The first bonding area in the signal fan-out substrate layout is determined based on the number of substrate units in the signal fan-out substrate. The second bonding area in the signal fan-out substrate layout is determined based on the area in the signal fan-out substrate that is connected to the adapter substrate. The project cut-off area is determined based on the first binding area and the second binding area; The preliminary layout of the signal fan-out substrate is cut out according to the engineering cut-out area to form a signal fan-out substrate layout that meets the quantity requirements.

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