A multi-chip stacked package structure and a method of forming the same

Abstract

The present application relates to a kind of multi-chip stack package structure and its forming method, wherein the multi-chip stack package structure includes: substrate;Main chip, which is electrically connected with the substrate;And chip stack module, which is electrically connected with the substrate, the chip stack module includes: a plurality of sequentially connected stack package units;And top layer stack package unit, which is located at the top of the chip stack module.Using wafer level fan-out packaging process and the method of copper pillar planting, the stack of multiple DDR chips and the interconnection of main chip can be realized in limited package size.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a multi-chip stacked packaging structure and its formation method. Background Technology

[0002] With the rapid development of the semiconductor industry, people are placing increasingly higher demands on digital products, such as miniaturization and functional complexity. As a result, the number of chips and I / Os is increasing daily, while package sizes are becoming smaller and smaller. Traditional packaging can no longer meet the needs of high I / O counts. Wafer-level fan-out packaging (FOWLP) technology complements wafer-level chip-scale packaging technology by reconstructing the wafer to bring out the chip's I / Os, forming solder balls or bumps on the reconstructed molded package.

[0003] Conventional SIP (System-in-Package) multi-chip packages have an excessively large package area due to the flat chip layout, which cannot meet the miniaturization problem of today's digital products. Summary of the Invention

[0004] To address at least some of the problems mentioned above in the prior art, the present invention provides a multi-chip stacked package structure, comprising:

[0005] substrate;

[0006] The main chip, which is electrically connected to the substrate; and

[0007] A chip stacking module electrically connected to the substrate, the chip stacking module comprising:

[0008] Multiple stacked package units connected in sequence; and

[0009] The top-level stacked packaging unit is located on top of the chip stacking module.

[0010] Furthermore, the stacked packaging unit includes:

[0011] One or more interconnect layers;

[0012] The first chip is flip-chip disposed on the first side of the interconnect layer;

[0013] A first conductive pillar is disposed on the first surface of the interconnect layer;

[0014] A first molding layer is used to encapsulate the first chip and the first conductive post, with the end of the first conductive post exposed.

[0015] A second chip is flip-chip disposed on the second side of the interconnect layer, wherein the second side is opposite to the first side;

[0016] A second conductive pillar is disposed on the second surface of the interconnect layer; and

[0017] A second molding layer is used to encapsulate the second chip and the second conductive post, with the end of the second conductive post exposed.

[0018] Furthermore, the top-level stacked packaging unit includes:

[0019] One or more interconnect layers;

[0020] The first chip is flip-chip disposed on the first side of the interconnect layer;

[0021] A first conductive pillar is disposed on the first surface of the interconnect layer;

[0022] A first molding layer is used to encapsulate the first chip and the first conductive post, with the end of the first conductive post exposed.

[0023] A second chip, flip-chip disposed on the second side of the interconnect layer, wherein the second side is opposite to the first side; and

[0024] The second molding layer encapsulates the second chip.

[0025] Furthermore, a bump of one of the stacked package units is connected to the surface of the second molding layer and the end of the second conductive post of the other stacked package unit; and

[0026] The bumps of the top-level stacked packaging unit are connected to the surface of the second molding layer of the stacked packaging unit and the end of the second conductive post.

[0027] Furthermore, the main chip and the chip stacking module are disposed on the front side of the substrate; and

[0028] The substrate has internal connection lines, and the main chip and the chip stack module are electrically interconnected through the connection lines.

[0029] Furthermore, it also includes:

[0030] A heat sink, disposed on the front side of the substrate, and surrounding the chip stack module and the main chip; and

[0031] Solder balls are disposed on the back side of the substrate.

[0032] The present invention also provides a method for forming a multi-chip stacked package structure, comprising:

[0033] Forming stacked package units and top-level stacked package units;

[0034] Multiple stacked packaging units are stacked sequentially, with the top stacked packaging unit positioned on top to form a chip stacking module; and

[0035] The chip stacking module is disposed on the front side of the substrate, and the main chip is flip-chip disposed on the front side of the substrate; the chip stacking module and the main chip are electrically interconnected through the substrate; and

[0036] A heat sink is attached to the front side of the substrate to surround the chip stack module and the main chip, and solder balls are arranged on the back side of the substrate.

[0037] Furthermore, the formation of the stacked packaging unit includes:

[0038] One or more interconnect layers are formed, and a first chip and a first conductive pillar are disposed on the surface of the interconnect layers;

[0039] A first molding layer is formed to encapsulate the first chip and the first conductive pillar, and the first molding layer is thinned to expose the first conductive pillar;

[0040] A second chip and a second conductive pillar are disposed on the surface of the interconnect layer opposite to the first molding layer;

[0041] A second molding layer is formed to encapsulate the second chip and the second conductive pillar, and the second molding layer is thinned to expose the second conductive pillar; and

[0042] Protrusions are arranged on the surface of the first molding layer and at the end of the first conductive post.

[0043] Furthermore, the formation of the top-level stacked packaging unit includes:

[0044] One or more interconnect layers are formed, and a first chip and a first conductive pillar are disposed on the surface of the interconnect layers;

[0045] A first molding layer is formed to encapsulate the first chip and the first conductive pillar, and the first molding layer is thinned to expose the first conductive pillar;

[0046] A second chip is disposed on the surface of the interconnect layer that is away from the first molding layer;

[0047] The second molding layer forming the second molding layer for molding the second chip; and

[0048] Protrusions are arranged on the surface of the first molding layer and at the end of the first conductive post.

[0049] Furthermore, the bumps of one of the stacked packaging units are connected to the surface of the second molding layer and the end of the second conductive post of the other stacked packaging unit; and

[0050] The bumps of the top-level stacked packaging unit are connected to the surface of the second molding layer and the end of the second conductive post of the stacked packaging unit.

[0051] The present invention has at least the following beneficial effects: The multi-chip stacked packaging structure and its formation method disclosed in the present invention utilize wafer-level fan-out packaging technology and copper pillar method to first package DDR chips and then stack them. Within a limited package size, multiple DDR chips can be stacked and interconnected with the main chip, solving the problem of excessive package area caused by the flat layout of conventional SIP multi-chip packaging; Compared with TSV technology to achieve vertical stacking interconnection of chips, the present invention uses copper pillars and rewiring to achieve vertical stacking interconnection of chips, reducing costs. Attached Figure Description

[0052] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0053] Figure 1 A cross-sectional schematic diagram of a multi-chip stacked package structure according to an embodiment of the present invention is shown; and

[0054] Figures 2 to 5 A schematic diagram illustrating the process of forming a multi-chip stacked package structure according to an embodiment of the present invention is shown. Detailed Implementation

[0055] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0056] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0057] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0058] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0059] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0060] It should also be noted that in the description of this invention, the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not explicitly or implicitly suggest that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0061] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0062] Figure 1 A cross-sectional schematic diagram of a multi-chip stacked package structure according to an embodiment of the present invention is shown.

[0063] like Figure 1 As shown, a multi-chip stacked packaging structure includes a substrate 101, a chip stacking module, a main chip 102, a heat sink 103, and solder balls 104.

[0064] The substrate 101 has a connection line 105 inside, and both ends of the connection line 105 are exposed on the substrate.

[0065] Both the chip stacking module and the main chip 102 are disposed on the front side of the substrate 101, and both the chip stacking module and the main chip 102 are electrically connected to the connection line 105, thereby interconnecting the chip stacking module and the main chip 102.

[0066] The heat sink 103 is mounted on the front side of the substrate 101 and surrounds the chip stack module and the main chip 102. The edge of the front side of the heat sink 103 is bonded to the substrate 101.

[0067] The heat sink 103 has a first groove and a second groove on its front side, with the first groove being deeper than the second groove. After the heat sink 103 is attached to the front side of the substrate 101, the chip stacking module is located in the first groove, and the main chip 102 is located in the second groove. The back side of the main chip 102 and the top of the chip stacking module are respectively connected to the heat sink 103 by thermally conductive adhesive 114.

[0068] Solder balls 104 are disposed on the back side of substrate 101.

[0069] The chip stacking module includes multiple stacked packaging units connected in sequence and a top-level stacked packaging unit located on top. Each stacked packaging unit includes one or more interconnect layers 106, a first chip 107, a first conductive pillar 108, a first molding compound 109, a second chip 110, a second conductive pillar 111, a second molding compound 112, and bumps 113. The interconnect layer 106 includes a dielectric layer and a redistribution layer located within the dielectric layer.

[0070] A first chip 107 and a first conductive post 108 are disposed on the first surface of an interconnect layer 106. Pins 1071 of the first chip 107 are electrically connected to the interconnect layer 106. A first molding compound 109 encapsulates the first chip 107 and the first conductive post 108. The first conductive post 108 penetrates the first molding compound 109, with its end exposed above the first molding compound 109.

[0071] A second chip 110 and a second conductive post 111 are disposed on a second surface of an interconnect layer 106, wherein the second surface is opposite to the first surface. Pins 1101 of the second chip 110 are electrically connected to the interconnect layer 106. A second molding compound 112 encapsulates the second chip 110 and the second conductive post 111. The second conductive post 111 penetrates the second molding compound 112, with its end exposed above the second molding compound 112.

[0072] The bumps 113 are arranged on the surface of the first molding layer 109 away from the interconnect layer 106 and at the end of the first conductive post 108.

[0073] The bump 113 of the upper stacked package unit is connected to the surface of the second molding layer 112 and the end of the second conductive post 111 of the lower stacked package unit, so that the two stacked package units are connected, and so on, to connect multiple stacked package units.

[0074] The top-level stacked package unit lacks the second conductive pillar 111 compared to the stacked package unit, but its structure is the same. The top-level stacked package unit includes one or more interconnect layers 106, a first chip 107, a first conductive pillar 108, a first molding compound 109, a second chip 110, a second molding compound 112, and bumps 113.

[0075] The bump 113 of the top stacked package unit is connected to the surface of the second molding layer 112 and the end of the second conductive post 111 of the lower stacked package unit.

[0076] Figures 2 to 5 A schematic diagram illustrating the process of forming a multi-chip stacked package structure according to an embodiment of the present invention is shown.

[0077] A method for forming a multi-chip stacked package structure includes:

[0078] Step 1, as follows Figure 2As shown, one or more interconnect layers 201 are formed on the substrate. A first chip 202 and a first conductive pillar 203 are arranged on the surface of the interconnect layer 201. The first chip 202 and the first conductive pillar 203 are encapsulated to form a first encapsulation layer 204. The first encapsulation layer 204 is thinned to expose the first conductive pillar 204, and the substrate is removed.

[0079] Specifically, interconnect layer 201 includes a dielectric layer and a redistribution layer. A first dielectric layer is formed on a substrate, and the first dielectric layer is etched to form a circuit pattern. After filling with metal, a redistribution layer is obtained. This process can be repeated multiple times to form a multi-layer interconnect layer 201. A first chip 202 is flip-chip disposed on the surface of interconnect layer 201, and the pins 2021 of the first chip 202 are electrically connected to interconnect layer 201. A first conductive post 203 is disposed on the surface of interconnect layer 201, next to the first chip 202. A first molding compound 204 is formed to encapsulate the first chip 202 and the first conductive post 203, and the first molding compound 204 is thinned away from the surface of interconnect layer 201 to expose the first conductive post 203. A UBM opening is formed on the surface of the first molding compound 204 facing the first chip 202, for example, by etching the opening, so that bumps can be arranged at the UBM opening later.

[0080] Step 2, as follows Figure 3 As shown, a second chip 205 and a second conductive post 206 are disposed on the surface of the interconnect layer 201 opposite to the first molding compound layer 204, forming a second molding compound layer 207 that encapsulates the second chip 205 and the second conductive post 206. The second molding compound layer 207 is then thinned to expose the second conductive post 206. Bumps 208 are then disposed on the surface of the first molding compound layer 204 and at the ends of the first conductive post 203. The pins 2051 of the second chip 205 are electrically connected to the interconnect layer 201.

[0081] Steps 1 and 2 form a stacked packaging unit.

[0082] When preparing the top-level stacked package unit located on top after stacking, the difference from the stacked package unit is that there is no need to arrange the second conductive pillar 206 and thin the second molding layer 207, and there is no need to reserve a UBM opening on the surface of the first molding layer 204.

[0083] The first chip 202 and the second chip 205 are memory chips, such as double-rate synchronous dynamic random access memory.

[0084] Step 3, as follows Figure 4 As shown, multiple stacked package units are stacked sequentially, with the top stacked package unit positioned on top to obtain a chip stacking module. The bumps of the upper stacked package unit are connected to the surface of the second molding layer 207 and the end of the second conductive post 206 of the lower stacked package unit, thus connecting the two stacked package units. This process is repeated to connect multiple stacked package units.

[0085] Step 4, as follows Figure 5 As shown, a chip stacking module is arranged on the front side of substrate 209, and a main chip 210 is flip-chip disposed on the front side of substrate 209. A heat sink 211 is attached to the front side of substrate 209 to surround the chip stacking module and the main chip 210, and solder balls 212 are arranged on the back side of substrate 209. The bumps 208 of the chip stacking module are electrically connected to the internal connection lines 213 of substrate 209, and the pins of the main chip 210 are electrically connected to the internal connection lines 213 of substrate 209, thereby interconnecting the chip stacking module and the main chip 210. The main chip 210 may be, for example, a logic chip.

[0086] The heat sink 211 has a first groove and a second groove, with the first groove being deeper than the second groove. After the heat sink 211 is attached to the front side of the substrate 209, the chip stacking module is located in the first groove, and the main chip 210 is located in the second groove. The back side of the main chip 210 and the top of the chip stacking module are respectively connected to the heat sink 211 by thermally conductive adhesive 214.

[0087] While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A multi-chip stacked packaging structure, characterized in that, include: substrate; The main chip is electrically connected to the substrate, and the main chip is a logic chip. as well as A chip stacking module electrically connected to the substrate, the chip stacking module comprising: Multiple stacked package units connected in sequence; and Top-level stacked packaging unit, which is located on top of the chip stacking module; A heat dissipation cover is disposed on the front side of the substrate and surrounds the chip stack module and the main chip; The stacked package unit includes: one or more interconnect layers; a first chip, with its front side facing upward, disposed on a first side of the interconnect layer, the pins of the first chip being electrically connected to the interconnect layer; a first conductive pillar, disposed on the first side of the interconnect layer; a first molding compound layer, which encapsulates the first chip and the first conductive pillar, with the ends of the first conductive pillar exposed; a second chip, flip-chip disposed on a second side of the interconnect layer, the pins of the second chip being electrically connected to the interconnect layer, wherein the second side is opposite to the first side; a second conductive pillar, disposed on the second side of the interconnect layer; and a second molding compound layer, which encapsulates the second chip and the second conductive pillar, with the ends of the second conductive pillar exposed. The top-layer stacked package unit includes: one or more interconnect layers; a first chip flip-chip disposed on a first side of the interconnect layer; a first conductive pillar disposed on the first side of the interconnect layer; a first molding compound layer that encapsulates the first chip and the first conductive pillar, with the ends of the first conductive pillar exposed; a second chip flip-chip disposed on a second side of the interconnect layer, wherein the second side is opposite to the first side; and a second molding compound layer that encapsulates the second chip. The first and second chips are memory chips.

2. The multi-chip stacked packaging structure according to claim 1, characterized in that, A bump in one of the stacked package units is connected to the surface of the second molding layer and the end of the second conductive post of the other stacked package unit. as well as The bumps of the top-level stacked packaging unit are connected to the surface of the second molding layer of the stacked packaging unit and the end of the second conductive post.

3. The multi-chip stacked packaging structure according to claim 1, characterized in that, The main chip and the chip stacking module are disposed on the front side of the substrate; as well as The substrate has internal connection lines, and the main chip and the chip stack module are electrically interconnected through the connection lines.

4. The multi-chip stacked packaging structure according to claim 1, characterized in that, Also includes: Solder balls are disposed on the back side of the substrate.

5. A method for forming a multi-chip stacked package structure, characterized in that, include: Forming stacked package units and top-level stacked package units; Multiple stacked packaging units are stacked sequentially, and the top stacked packaging unit is arranged on top to form a chip stacking module; as well as The chip stacking module is arranged on the front side of the substrate, and the main chip is flip-chip arranged on the front side of the substrate. The chip stacking module and the main chip are electrically interconnected through the substrate. as well as A heat sink is attached to the front side of the substrate to surround the chip stack module and the main chip, and solder balls are arranged on the back side of the substrate. The stacked packaging unit includes: One or more interconnect layers are formed, and a first chip and a first conductive pillar are disposed on the surface of the interconnect layers; A first molding layer is formed to encapsulate the first chip and the first conductive pillar, and the first molding layer is thinned to expose the first conductive pillar; A second chip and a second conductive pillar are disposed on the surface of the interconnect layer opposite to the first molding layer; A second molding layer is formed to encapsulate the second chip and the second conductive pillar, and the second molding layer is thinned to expose the second conductive pillar; and Protrusions are arranged on the surface of the first molding layer and at the end of the first conductive post; The formation of the top-level stacked packaging unit includes: One or more interconnect layers are formed, and a first chip and a first conductive pillar are disposed on the surface of the interconnect layers; A first molding layer is formed to encapsulate the first chip and the first conductive pillar, and the first molding layer is thinned to expose the first conductive pillar; A second chip is disposed on the surface of the interconnect layer that is away from the first molding layer; The second molding layer forming the second molding layer for molding the second chip; and Protrusions are arranged on the surface of the first molding layer and at the end of the first conductive post; The first and second chips are memory chips; The main chip is a logic chip.

6. The method for forming a multi-chip stacked package structure according to claim 5, characterized in that, A bump in one of the stacked package units is connected to the surface of the second molding layer and the end of the second conductive post of the other stacked package unit; and The bumps of the top-level stacked packaging unit are connected to the surface of the second molding layer and the end of the second conductive post of the stacked packaging unit.

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