Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a substrate, a dielectric layer and a barrier structure. The dielectric layer is disposed on the substrate, and the dielectric layer has a patterned topography. The barrier structure covers inner walls of the patterned topography, and the barrier structure comprises a first barrier layer, a sandwich layer and a second barrier layer which are disposed in a stack. The present disclosure can improve the hardness of the barrier structure to avoid sidewall damage of the barrier structure due to a grinding process, thereby reducing barrier defects and improving the reliability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. After semiconductor technology entered the deep submicron stage, Dynamic Random Access Memory (DRAM), a commonly used semiconductor structure in computers and other electronic devices, is becoming increasingly smaller in size. Correspondingly, the size of each component in DRAM and the spacing between adjacent components are also becoming smaller.

[0003] Currently, in the back-end of line (BEOL) processes of semiconductor structures, high aspect ratio ion etching technology is widely used to form vias, and then barrier layers and interconnect structures are formed within these vias. However, the integrity of the barrier layer is crucial. During the fabrication of the barrier layer, a polishing process is unavoidable, which can easily lead to defects such as damaged sidewalls. These defects can then allow metal ions from other interconnect structures beneath the barrier layer to migrate, affecting the reliability of the semiconductor structure.

[0004] Therefore, how to effectively avoid damage to the barrier layer has become a pressing problem to be solved in related technologies. Summary of the Invention

[0005] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can effectively improve the hardness of the barrier structure, thereby reducing the risk of damage to the barrier structure due to the polishing process, thus reducing barrier defects and effectively improving the reliability of the semiconductor structure.

[0006] In one aspect, embodiments of this disclosure provide a semiconductor structure, including: a substrate, a dielectric layer, and a barrier structure. The dielectric layer is disposed on the substrate and has a patterned morphology. The barrier structure covers the inner wall of the patterned morphology; the barrier structure includes: a first barrier layer, a sandwich layer, and a second barrier layer stacked together.

[0007] In some embodiments, the semiconductor structure further includes a first conductive structure. The first conductive structure is located between the substrate and the dielectric layer, and the patterned topography of the dielectric layer exposes a portion of the first conductive structure; wherein the first barrier layer or the second barrier layer further covers the first conductive structure.

[0008] In some embodiments, the semiconductor structure further includes a second conductive structure. The second conductive structure covers the second barrier layer and is located within the patterned topography of the dielectric layer.

[0009] In some embodiments, the thickness of any one of the first barrier layer, the sandwich layer, and the second barrier layer ranges from 2 nm to 30 nm.

[0010] In some embodiments, the first barrier layer and the second barrier layer are both tungsten nitride layers, and the sandwich layer is a tungsten metal layer.

[0011] On the other hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, used to fabricate the semiconductor structure described in the above embodiments. The method for fabricating the semiconductor structure includes the following steps.

[0012] A substrate is provided, on which a dielectric material layer is formed.

[0013] The dielectric material layer is patterned to form a dielectric layer; the dielectric layer has a patterned morphology.

[0014] A barrier structure is formed, the barrier structure covering the inner wall of the patterned morphology. The formation of the barrier structure includes: forming a first barrier layer, a sandwich layer, and a second barrier layer stacked together, such that the first barrier layer, the sandwich layer, and the second barrier layer together constitute the barrier structure.

[0015] In some embodiments, before forming the dielectric material layer on the substrate, the fabrication method further includes forming a first conductive structure on the substrate. Wherein, after patterning the dielectric material layer, the first conductive structure is exposed at the bottom of the patterned morphology; the first barrier layer or the second barrier layer further covers the first conductive structure.

[0016] In some embodiments, the preparation method further includes: forming a second conductive structure; the second conductive structure covers the second barrier layer and is located within the patterned morphology of the dielectric layer.

[0017] In some embodiments, forming the stacked first barrier layer, sandwich layer, and second barrier layer, as well as forming the second conductive structure, includes the following steps.

[0018] A first barrier material layer, a support material layer, a second barrier material layer, and a conductive material layer are deposited sequentially; wherein, the first barrier material layer covers the inner wall of the patterned morphology and the surface of the dielectric layer facing away from the substrate, the support material layer covers the first barrier material layer, the second barrier material layer covers the support material layer, and the conductive material layer covers the second barrier material layer and fills the patterned morphology.

[0019] The conductive material layer is ground to expose the second barrier material layer above the dielectric layer.

[0020] The second barrier material layer, the support material layer, and the first barrier material layer are ground to expose the surface of the dielectric layer facing away from the substrate, so that the first barrier material layer retained in the patterned morphology forms the first barrier layer, the support material layer retained in the patterned morphology forms the sandwich layer, the second barrier material layer retained in the patterned morphology forms the second barrier layer, and the conductive material layer retained in the patterned morphology forms the second conductive structure.

[0021] In some embodiments, the supporting material layer and the conductive material layer are made of the same material.

[0022] In some embodiments, the first barrier material layer and the second barrier material layer are made of the same material, and the grinding rate of the first barrier material layer and the second barrier material layer is the same as or similar to the grinding rate of the conductive material layer.

[0023] In some embodiments, the gas used for depositing the first barrier material layer and / or the second barrier material layer includes: diborane, tungsten hexafluoride, and ammonia. The gas used for depositing the support material layer and / or the conductive material layer includes: diborane and tungsten hexafluoride.

[0024] In some embodiments, the flow rate of diborane used for depositing the first barrier material layer and / or the second barrier material layer ranges from 100 sccm to 300 sccm; the flow rate of tungsten hexafluoride used for depositing the first barrier material layer and / or the second barrier material layer ranges from 200 sccm to 400 sccm; and the flow rate of ammonia used for depositing the first barrier material layer and / or the second barrier material layer ranges from 100 sccm to 400 sccm.

[0025] In some embodiments, the pressure of the gas used to deposit the first barrier material layer and / or the second barrier material layer ranges from 1 torr to 10 torr. The temperature of the gas used to deposit the first barrier material layer and / or the second barrier material layer ranges from 250°C to 400°C.

[0026] In some embodiments, the flow rate of diborane used for depositing the support material layer and / or the conductive material layer ranges from 200 sccm to 500 sccm; the flow rate of tungsten hexafluoride used for depositing the support material layer and / or the conductive material layer ranges from 300 sccm to 400 sccm.

[0027] In some embodiments, the pressure of the gas used to deposit the support material layer and / or the conductive material layer ranges from 20 torr to 60 torr. The temperature of the gas used to deposit the support material layer and / or the conductive material layer ranges from 250°C to 400°C.

[0028] In some embodiments, the preparation method further includes preheating the resulting structure after forming the dielectric layer before depositing the first barrier material layer.

[0029] In some embodiments, the preheating time ranges from 5s to 40s.

[0030] In this embodiment, a barrier structure is formed by stacking a first barrier layer, a sandwich layer, and a second barrier layer. For example, the barrier structure is a sandwich structure of tungsten nitride / tungsten / tungsten nitride. By reasonably selecting the thickness of each layer of the first barrier layer, the sandwich layer, and the second barrier layer, the hardness of the barrier structure can be effectively improved, thereby reducing the risk of damage to the barrier structure due to the grinding process. This ensures the formation of a barrier structure with a complete outline, reduces barrier defects, and effectively improves the reliability of the semiconductor structure.

[0031] Furthermore, in this embodiment, the first barrier layer, the sandwich layer, and the second barrier layer are stacked together to form a barrier structure. The parallel connection between the first barrier layer, the sandwich layer, and the second barrier layer can be used to effectively reduce the contact resistance of the barrier structure, thereby improving the electrical performance of the semiconductor structure.

[0032] Furthermore, in this embodiment, the first barrier layer, the sandwich layer, and the second barrier layer adopt a tungsten nitride / tungsten / tungsten nitride sandwich structure, which facilitates one-time molding using the same vacuum chamber on the same machine. That is, by adjusting parameters such as the type, flow rate, pressure, and temperature of the input gas, the barrier structure can be fabricated without changing the machine chamber. This facilitates fabrication and improves production efficiency. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a semiconductor structure provided in related technologies;

[0035] Figure 2 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0036] Figure 3 This is a schematic diagram of another semiconductor structure provided in one embodiment;

[0037] Figure 4 This is a schematic diagram illustrating the relationship between the thickness and hardness of different blocking structures provided in one embodiment;

[0038] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure as provided in one embodiment;

[0039] Figure 6 This is a flowchart of a method for fabricating another semiconductor structure provided in one embodiment;

[0040] Figure 7 This is a schematic diagram of the structure of a substrate provided in one embodiment;

[0041] Figure 8 This is a schematic diagram of a structure obtained after forming a mask layer, as provided in one embodiment.

[0042] Figure 9 This is a schematic diagram of a structure obtained after forming a photoresist layer in one embodiment;

[0043] Figure 10 This is a schematic diagram of a structure obtained after forming vias in the fifth and sixth dielectric layers in one embodiment;

[0044] Figure 11 This is a schematic diagram of a structure obtained after forming a barrier material layer in one embodiment;

[0045] Figure 12 Figures (a) and (b) are enlarged schematic diagrams of a barrier material layer formed in one embodiment.

[0046] Figure 13 This is a schematic diagram of a structure obtained after forming a barrier structure in one embodiment;

[0047] Figure 14 Figures (a) and (b) are enlarged schematic diagrams of a barrier structure formed in one embodiment.

[0048] Figure 15 This is a schematic diagram of a structure obtained after forming a pad layer, as provided in one embodiment.

[0049] Figure 16 This is a schematic diagram of the structure obtained after forming an encapsulation layer in one embodiment.

[0050] Explanation of reference numerals in the attached figures:

[0051] 10-Substrate, 11-First conductive structure, 12-Dielectric layer, 2'-Barrier layer, 2-Barrier structure, 3-Second conductive structure, F-Sidewall defect,

[0052] 21-First barrier layer, 22-Sandwich layer, 23-Second barrier layer, 20-Barrier material layer, 30-Conductive material layer

[0053] 210 - First barrier material layer, 220 - Support material layer, 230 - Second barrier material layer, C - Storage capacitor region.

[0054] B1 - First blocking part, L1 - First interconnection structure, B2 - Second blocking part, L2 - Second interconnection structure, B3 - Third blocking part

[0055] L3 - Third interconnect structure, B4 - Fourth blocking section, K1 - First dielectric layer, K2 - Second dielectric layer, K3 - Third dielectric layer

[0056] K4 - Fourth dielectric layer, K5 - Fifth dielectric layer, K6 - Sixth dielectric layer, K5A - Fifth dielectric material layer, K6A - Sixth dielectric material layer

[0057] Y1 - Hard mask layer, Y2 - Anti-reflective layer, PR - Photoresist layer, V1 - Via, 4 - Pad layer, 5 - Planarization layer, 6 - Encapsulation layer. Detailed Implementation

[0058] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0060] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0061] It should be understood that although the terms first, second, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0062] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0063] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0064] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0065] Currently, in the back-end of line (BEOL) process of semiconductor structures, high aspect ratio ion etching technology can be widely used to etch and form vias, and then barrier layers and interconnect structures are formed in the vias. However, the integrity of the barrier layer is very important.

[0066] In some embodiments, please refer to Figure 1 The barrier layer 2' is located between the first conductive structure 11 and the second conductive structure 3. Since the barrier layer 2' and the second conductive structure 3 are formed within the vias of the dielectric layer 12, they can be formed using a polishing process. Based on this, when the polishing rates of the barrier layer 2' and the second conductive structure 3 are the same or similar, the sidewall of the barrier layer 2' is easily damaged by the polishing of the second conductive structure 3, for example, resulting in… Figure 1 The sidewall defect F shown in Figures (a) and (b) indicates that part of the material in the sidewall of the barrier layer 2' has been hollowed out, forming pores. As a result, metal ions in the first conductive structure 11 can easily migrate through this sidewall defect F, adversely affecting the reliability of the semiconductor structure.

[0067] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can effectively improve the hardness of the barrier structure, thereby reducing the risk of damage to the barrier structure due to the grinding process, thus ensuring the formation of a barrier structure with a complete outline, reducing barrier defects, and effectively improving the reliability of the semiconductor structure.

[0068] Please see Figure 2 Figures (a) and (b) illustrate some embodiments of a semiconductor structure disclosed herein, including a substrate 10, a dielectric layer 12, and a barrier structure 2. The dielectric layer 12 is disposed on the substrate 10 and has a patterned morphology. The barrier structure 2 covers the inner wall of the patterned morphology; the barrier structure 2 includes a first barrier layer 21, a sandwich layer 22, and a second barrier layer 22 stacked together.

[0069] For example, substrate 10 may be made of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 10 may be a single-layer structure or a multi-layer structure. For example, substrate 10 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 10 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0070] Furthermore, transistors and other electronic components may be disposed within the substrate 10. Storage structures and interconnect structures connected to the transistors may also be disposed on the substrate 10.

[0071] For example, dielectric layer 12 includes, but is not limited to, silicon oxide layer (SiO2), silicon nitride layer (Si3N4), hydrogenated silicon oxide carbon layer (SiCOH), or other types of silicon-based low-k dielectric layers (e.g., dielectric layers with k less than 4.0). Dielectric layer 12 can be a single-layer structure or a stacked structure (i.e., including multiple layers of sub-dielectric layers).

[0072] For example, the patterned topography of the dielectric layer 12 includes, but is not limited to, holes. The patterned topography of the dielectric layer 12 may be, for example, a circular hole, an elliptical hole, a polygonal hole, or a stepped hole.

[0073] Accordingly, it can be understood that the barrier structure 2 covering the inner wall of the patterned morphology can be represented as covering the inner wall of the hole in the dielectric layer 12. Thus, the first barrier layer 21, the sandwich layer 22, and the second barrier layer 22 are stacked in a direction away from the inner wall of the hole in the dielectric layer 12.

[0074] In some embodiments, please refer to Figure 2 Figure (a) and Figure 3 The semiconductor structure further includes a first conductive structure 11. The first conductive structure 11 is located between the substrate 10 and the dielectric layer 12, and the patterned topography of the dielectric layer 12 exposes a portion of the first conductive structure 11.

[0075] Here, the first conductive structure 11 is disposed on the substrate 10, and can be an interconnect structure or the like connected to a transistor. The first conductive structure 11 can be, for example, a copper metal layer. After the patterned topography of the dielectric layer 12 exposes part of the first conductive structure 11, the connection relationship between the barrier structure 2 and the first conductive structure 11 can be implemented in the following two specific ways.

[0076] In one possible implementation, such as Figure 2As shown in Figure (a), the second barrier layer 23 also covers the first conductive structure 11. That is, the second barrier layer 23 in the barrier structure 2 also includes a portion located at the bottom of the patterned morphology of the dielectric layer 12, so as to be directly connected to the first conductive structure 11.

[0077] In another possible implementation, such as Figure 3 As shown, the first barrier layer 21 also covers the first conductive structure 11. That is, the first barrier layer 21, the sandwich layer 22 and the second barrier layer 23 in the barrier structure 2 all include a portion located at the bottom of the patterned morphology of the dielectric layer 12, and are directly connected to the first conductive structure 11 through the first barrier layer 21.

[0078] Please continue reading. Figure 2 Figure (a) and Figure 3 The semiconductor structure further includes a second conductive structure 3. The second conductive structure 3 covers the second barrier layer 23 and is located within the patterned topography of the dielectric layer 12.

[0079] In some embodiments, the sandwich layer 22 and the second conductive structure 3 are made of the same material. For example, the sandwich layer 22 and the second conductive structure 3 are made of tungsten (W). In some embodiments, the first barrier layer 21 and the second barrier layer 22 are made of the same material. For example, the first barrier layer 21 and the second barrier layer 22 are made of tungsten nitride (WN). Thus, the first barrier layer 21 and the second barrier layer 23 are both tungsten nitride (WN) layers, the sandwich layer 22 is a tungsten metal (W) layer, and the barrier structure 2 adopts a sandwich structure of tungsten nitride / tungsten / tungsten nitride.

[0080] It is understood that both the barrier structure 2 and the second conductive structure 3 are located within the patterned morphology of the dielectric layer 12, and can be prepared by a polishing process after the formation of the corresponding material layers. In the example where both the first barrier layer 21 and the second barrier layer 23 are tungsten nitride (WN) layers and both the sandwich layer 22 and the second conductive structure 3 are tungsten metal (W) layers, the polishing rate of the tungsten nitride material layer can be, for example, 3.17 nm / s, and the polishing rate of the tungsten material layer can be, for example, 3.47 nm / s. The polishing rates of the tungsten nitride material layer and the tungsten material layer are quite similar. In this embodiment, the barrier structure 2 adopts a sandwich structure of tungsten nitride / tungsten / tungsten nitride, which can utilize the sandwich layer 22 to support the first barrier layer 21 and the second barrier layer 23, effectively improving the hardness of the barrier structure 2 and preventing damage to the barrier structure 2 due to the polishing of the second conductive structure 3. This ensures the formation of a barrier structure 2 with a complete outline, reduces the barrier defects of the barrier structure 2, and effectively improves the reliability of the semiconductor structure.

[0081] It is understood that the thicknesses of the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23 can be selected and set according to actual needs. For example, please refer to... Figure 4 Compared to a single tungsten layer or a single tungsten nitride layer of the same thickness, the barrier structure 2 provided in this embodiment adopts a stacked structure of a first barrier layer 21, a sandwich layer 22, and a second barrier layer 23. The relationship between its hardness and thickness can be obtained through experiments with different thicknesses. For example, the relationship curve between the hardness and thickness of the barrier structure 2 can be fitted using the Hall-Petch equation, as shown below. Figure 4 As shown in the figure. The Hall-Petch equation is: H = H0 + K × T -1 / 2 Where H is the hardness of the barrier structure 2, T is the thickness of the barrier structure 2, and H0 and K are constants.

[0082] Based on this, by reasonably selecting the thickness of the first barrier layer 21, the sandwich layer 22 and the second barrier layer 23, the hardness of the corresponding barrier structure 2 can be increased by up to 35% or more, thereby effectively improving the hardness of the barrier structure 2.

[0083] In some embodiments, the thickness of any one of the first barrier layer 21, the sandwich layer 22 and the second barrier layer 23 may range from 2nm to 30nm; for example, from 2nm to 10nm, 10nm to 20nm or 20nm to 30nm.

[0084] Optionally, the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23 have the same thickness.

[0085] Optionally, the thickness of the first barrier layer 21, the sandwich layer 22, or the second barrier layer 23 is 2nm, 5nm, 10nm, 15nm, 20nm, 25nm, or 30nm.

[0086] Furthermore, in this embodiment, the blocking structure 2 adopts the above structure. Considering the positional relationship between the blocking structure 2 and the first conductive structure 11 and the second conductive structure 3, the first blocking layer 21, the sandwich layer 22, and the second blocking layer 23 in the blocking structure 2 are stacked, that is, the first blocking layer 21, the sandwich layer 22, and the second blocking layer 23 are connected in parallel. Therefore, the resistance R of the blocking structure 2 is... total The resistance R1 of the first barrier layer 21, the resistance R2 of the sandwich layer 22, and the resistance R3 of the second barrier layer 23 satisfy the formula: 1 / R total = 1 / R1 + 1 / R2 + 1 / R3.

[0087] For example, R1 and R3 are the resistances of the corresponding tungsten nitride layers, with a resistivity of 1980 μΩ·cm.

[0088] For example, R2 is the resistance of the corresponding tungsten layer, which has a resistivity of 60 μΩ·cm.

[0089] In this embodiment, the resistivity of the barrier structure 2 is calculated to be 56.5 μΩ·cm. This represents a 91.5% reduction in resistivity compared to a single layer of tungsten nitride; that is, the resistance of the barrier structure 2 in this embodiment can be reduced by 91.5% relative to the resistance of a single layer of tungsten nitride of the same length, effectively reducing the contact resistance of the barrier structure 2.

[0090] As described above, in this embodiment of the present disclosure, the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23 are stacked together to form the barrier structure 2. For example, the barrier structure 2 can be a sandwich structure of tungsten nitride / tungsten / tungsten nitride. By reasonably selecting the thickness of each layer of the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23, the hardness of the barrier structure 2 can be effectively improved, thereby reducing the risk of damage to the barrier structure 2 due to the grinding process. This ensures the formation of a barrier structure with a complete outline, reduces barrier defects, and effectively improves the reliability of the semiconductor structure.

[0091] Furthermore, in this embodiment, the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23 are stacked together to form the barrier structure 2. The parallel connection relationship between the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23 can be used to effectively reduce the contact resistance of the barrier structure 2, thereby improving the electrical performance of the semiconductor structure.

[0092] Furthermore, in this embodiment, the first barrier layer 21, the sandwich layer 22, and the second barrier layer 23 adopt a tungsten nitride / tungsten / tungsten nitride sandwich structure, which also facilitates one-time molding using the same vacuum chamber of the same machine. That is, by adjusting parameters such as the type, flow rate, pressure, and temperature of the input gas, the barrier structure 2 can be fabricated without changing the machine chamber. This facilitates fabrication and improves production efficiency.

[0093] Please see Figure 5 On the other hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, used to fabricate the semiconductor structure described in the above embodiments. The method for fabricating this semiconductor structure includes the following steps.

[0094] S100 provides a substrate.

[0095] S200, a dielectric material layer is formed on the substrate.

[0096] S300, patterning the dielectric material layer to form a dielectric layer; the dielectric layer has a patterned morphology.

[0097] S400, forming a barrier structure that covers the inner wall of the patterned morphology. The forming of the barrier structure includes: forming a first barrier layer, a sandwich layer, and a second barrier layer stacked together, such that the first barrier layer, the sandwich layer, and the second barrier layer together constitute the barrier structure.

[0098] In some embodiments, step S400, which involves forming a first barrier layer, a sandwich layer, and a second barrier layer that are stacked together, includes the following steps.

[0099] S410, a first barrier material layer, a support material layer, and a second barrier material layer are deposited sequentially; wherein, the first barrier material layer covers the inner wall of the patterned morphology and the surface of the dielectric layer away from the substrate, the support material layer covers the first barrier material layer, and the second barrier material layer covers the support material layer.

[0100] S420, grind the second barrier material layer, the support material layer and the first barrier material layer to expose the surface of the dielectric layer away from the substrate, so that the first barrier material layer retained in the patterned morphology forms a first barrier layer, the support material layer retained in the patterned morphology forms a sandwich layer, and the second barrier material layer retained in the patterned morphology forms a second barrier layer.

[0101] In this embodiment of the disclosure, by reasonably selecting the deposition thickness of the first barrier material layer, the support material layer and the second barrier material layer in the barrier material layer, the total hardness of the barrier material layer can be effectively improved, thereby reducing the risk of damage to the barrier structure when the barrier structure is formed by grinding the barrier material layer. This ensures the formation of a barrier structure with a complete outline, reduces the barrier defects of the barrier structure, and effectively improves the reliability of the semiconductor structure.

[0102] Please see Figure 6 In some embodiments, before performing step S200 to form a dielectric material layer on the substrate, the preparation method further includes: S150, forming a first conductive structure on the substrate.

[0103] Accordingly, after performing step S300 to pattern the dielectric material layer, the first conductive structure is exposed at the bottom of the patterned topography. Furthermore, it matches the aforementioned... Figure 2 In the semiconductor structure shown in Figure (a), the second barrier layer 23 also covers the first conductive structure 11. Alternatively, it matches the aforementioned... Figure 3 The semiconductor structure shown has a first barrier layer 21 that also covers a first conductive structure 11.

[0104] Please continue reading. Figure 6 In some embodiments, the preparation method further includes: S500, forming a second conductive structure; the second conductive structure covers the second barrier layer and is located within the patterned morphology of the dielectric layer.

[0105] In one possible implementation, step S400 involves forming a first barrier layer, a sandwich layer, and a second barrier layer that are stacked together, and step S500 involves forming a second conductive structure, including the following steps.

[0106] S451, a first barrier material layer, a support material layer, a second barrier material layer, and a conductive material layer are deposited sequentially; wherein, the first barrier material layer covers the inner wall of the patterned morphology and the surface of the dielectric layer away from the substrate, the support material layer covers the first barrier material layer, the second barrier material layer covers the support material layer, and the conductive material layer covers the second barrier material layer and fills the patterned morphology.

[0107] S452, grind the conductive material layer to expose the second barrier material layer above the dielectric layer.

[0108] S453, grind the second barrier material layer, the support material layer and the first barrier material layer to expose the surface of the dielectric layer away from the substrate, so that the first barrier material layer retained in the patterned morphology forms a first barrier layer, the support material layer retained in the patterned morphology forms a sandwich layer, the second barrier material layer retained in the patterned morphology forms a second barrier layer, and the conductive material layer retained in the patterned morphology forms a second conductive structure.

[0109] In this embodiment of the disclosure, by reasonably selecting the deposition thickness of the first barrier material layer, the support material layer and the second barrier material layer in the barrier material layer, the total hardness of the barrier material layer can be effectively improved, thereby reducing the risk of damage to the barrier structure when the barrier structure and the second conductive structure are formed by grinding the barrier material layer and the conductive material layer. This ensures the formation of a barrier structure with a complete outline, reduces the barrier defects of the barrier structure, and effectively improves the reliability of the semiconductor structure.

[0110] In some embodiments, the support material layer and the conductive material layer are made of the same material. Optionally, the materials of the support material layer and the conductive material layer include tungsten.

[0111] In some embodiments, the first barrier material layer and the second barrier material layer are made of the same material, and the polishing rates of the first barrier material layer and the second barrier material layer are the same as or similar to the polishing rate of the conductive material layer. Optionally, the materials of the first barrier material layer and the second barrier material layer include tungsten nitride. The materials of the support material layer and the conductive material layer include tungsten.

[0112] Optionally, in the embodiments of this disclosure, the first and second barrier material layers are tungsten nitride material layers, and the support material layer and conductive material layer are tungsten metal layers. This also facilitates one-time molding using the same vacuum chamber of the same machine, meaning that by adjusting parameters such as the type, flow rate, pressure, and temperature of the input gas, the barrier structure and the second conductive structure can be fabricated without changing the machine chamber. The following embodiments provide specific implementations of the first barrier material layer, support material layer, second barrier material layer, and conductive material layer.

[0113] In some embodiments, the gases used to deposit the first barrier material layer and / or the second barrier material layer include: diborane (B2H6), tungsten hexafluoride (WF6), and ammonia (NH3).

[0114] Optionally, the flow rate of diborane used for depositing the first barrier material layer and / or the second barrier material layer ranges from 100 sccm to 300 sccm; for example, the flow rate range of diborane is 100 sccm to 200 sccm, 200 sccm to 300 sccm, 100 sccm to 150 sccm, 150 sccm to 250 sccm, or 150 sccm to 300 sccm. The flow rate of tungsten hexafluoride used for depositing the first barrier material layer and / or the second barrier material layer ranges from 200 sccm to 400 sccm; for example, the flow rate range of tungsten hexafluoride is 200 sccm to 300 sccm, 300 sccm to 400 sccm, 200 sccm to 350 sccm, 350 sccm to 400 sccm, or 250 sccm to 400 sccm. The flow rate of ammonia used for depositing the first barrier material layer and / or the second barrier material layer is in the range of 100 sccm to 400 sccm; for example, the flow rate of ammonia is in the range of 100 sccm to 200 sccm, 200 sccm to 300 sccm, 300 sccm to 400 sccm, 100 sccm to 250 sccm, or 250 sccm to 400 sccm.

[0115] In this embodiment, the flow rate of diborane is 100 sccm, 150 sccm, 200 sccm, or 300 sccm. The flow rate of tungsten hexafluoride is 200 sccm, 250 sccm, 300 sccm, 350 sccm, 380 sccm, or 400 sccm. The flow rate of ammonia is 100 sccm, 200 sccm, 300 sccm, 350 sccm, or 400 sccm.

[0116] Optionally, the pressure range of the gas used to deposit the first barrier material layer and / or the second barrier material layer includes 1 torr to 10 torr; for example, the aforementioned pressure range is 1 torr to 3 torr, 3 torr to 5 torr, 5 torr to 8 torr, 8 torr to 10 torr, 3 torr to 8 torr, or 5 torr to 10 torr. In this embodiment, the pressure of the gas used to deposit the first barrier material layer and / or the second barrier material layer is 1 torr, 3 torr, 5 torr, 8 torr, or 10 torr.

[0117] Optionally, the temperature range of the gas used to deposit the first barrier material layer and / or the second barrier material layer includes 250°C to 400°C. For example, the aforementioned temperature range is: 250°C to 300°C, 280°C to 350°C, 300°C to 350°C, 300°C to 400°C, or 350°C to 400°C. In this embodiment, the temperature of the gas used to deposit the first barrier material layer and / or the second barrier material layer is: 250°C, 280°C, 300°C, 320°C, 350°C, or 400°C.

[0118] In some embodiments, the gases used for depositing the support material layer and / or the conductive material layer include diborane (B2H6) and tungsten hexafluoride (WF6).

[0119] Optionally, the flow rate of diborane used for depositing the support material layer and / or conductive material layer ranges from 200 sccm to 500 sccm; for example, the flow rate range of diborane is 200 sccm to 300 sccm, 300 sccm to 400 sccm, 400 sccm to 500 sccm, 300 sccm to 500 sccm, or 400 sccm to 500 sccm. The flow rate of tungsten hexafluoride used for depositing the support material layer and / or conductive material layer ranges from 300 sccm to 400 sccm; for example, the flow rate range of tungsten hexafluoride is 300 sccm to 320 sccm, 320 sccm to 350 sccm, 350 sccm to 380 sccm, 380 sccm to 400 sccm, or 350 sccm to 400 sccm.

[0120] In this embodiment, the flow rate of diborane is 200 sccm, 300 sccm, 400 sccm, or 500 sccm. The flow rate of tungsten hexafluoride is 300 sccm, 320 sccm, 320 sccm, 350 sccm, 380 sccm, or 400 sccm.

[0121] Optionally, the pressure range of the gas used for depositing the support material layer and / or the conductive material layer includes 20 torr to 60 torr; for example, the aforementioned pressure range is 20 torr to 30 torr, 30 torr to 40 torr, 40 torr to 50 torr, 50 torr to 60 torr, 20 torr to 40 torr, or 40 torr to 60 torr. In this embodiment, the pressure of the gas used for depositing the support material layer and / or the conductive material layer is 20 torr, 30 torr, 40 torr, 50 torr, or 60 torr.

[0122] Optionally, the temperature range of the gas used for depositing the support material layer and / or the conductive material layer includes 250°C to 400°C; for example, the aforementioned temperature range is: 250°C to 300°C, 280°C to 350°C, 300°C to 350°C, 300°C to 400°C, or 350°C to 400°C. In this embodiment, the temperature of the gas used for depositing the support material layer and / or the conductive material layer is: 250°C, 280°C, 300°C, 320°C, 350°C, or 400°C.

[0123] In this embodiment, the first and second barrier material layers can be formed using diborane (B₂H₆), tungsten hexafluoride (WF₆), and ammonia (NH₃), while the support and conductive material layers can be formed using diborane (B₂H₆) and tungsten hexafluoride (WF₆). This facilitates one-time molding using the same vacuum chamber on a single machine. That is, by simply adjusting parameters such as the type, flow rate, pressure, and temperature of the input gas, the fabrication of each layer of the barrier structure and the corresponding material layer of the second conductive structure can be completed without changing the machine chamber. This simplifies fabrication and improves production efficiency.

[0124] It should be added that, in some embodiments, before depositing the first barrier material layer, the preparation method further includes preheating the structure obtained after forming the dielectric layer. Thus, preheating the structure obtained after forming the dielectric layer facilitates the uniform deposition of the first barrier material layer on the inner wall of the patterned morphology of the dielectric layer, and ensures that the first barrier material layer and the inner wall of the aforementioned patterned morphology have good interface quality.

[0125] Optionally, the preheating time can range from 5s to 40s; for example, the aforementioned preheating time range could be 5s to 15s, 10s to 20s, 15s to 30s, 20s to 35s, or 30s to 40s. In this embodiment, the preheating time is 5s, 10s, 15s, 20s, 30s, 35s, or 40s.

[0126] To more clearly illustrate the aforementioned preparation method provided in the embodiments of this disclosure, the following embodiments are described in detail using DRAM as an example of semiconductor structure.

[0127] It is understood that in the back-end process of DRAM, it is usually necessary to fabricate multi-layer interconnect structures to realize the fabrication and lead-out of different functional circuits through the corresponding connections of different interconnect structures. The following describes in detail the fabrication method provided in the embodiments of this disclosure, using the first conductive structure as the third interconnect structure and the second conductive structure as the fourth interconnect structure as an example, but it is not limited thereto. The barrier structure in the embodiments of this disclosure can be applied to any example that requires the setting of barrier portions.

[0128] In steps S100 and S150, please refer to Figure 7 A substrate 10 is provided, and a first conductive structure is formed on the substrate 10.

[0129] For example, transistors and other electronic components may be disposed within the substrate 10. A memory structure C connected to the transistors and interconnect structures (e.g., a first interconnect structure L1, a second interconnect structure L2, and a third interconnect structure L3), as well as interlayer dielectric layers (e.g., a first dielectric layer K1, a second dielectric layer K2, a third dielectric layer K3, and a fourth dielectric layer K4) may also be disposed on the substrate 10. The first conductive structure is, for example, the third interconnect structure L3.

[0130] Optionally, such as Figure 7 As shown, substrate 10 has a cell array region and a peripheral circuit region located beside the cell array region. The memory structure C is located within the cell array region of substrate 10 and can be connected to the transistor array within substrate 10. Furthermore, each interconnect structure on substrate 10 is disposed in a corresponding dielectric layer, and adjacent interconnect structures are connected by blocking portions (e.g., first blocking portion B1, second blocking portion B2, and third blocking portion B3).

[0131] In step S200, please refer to Figure 8 A dielectric material layer (e.g., K5A and K6A) is formed on the substrate 10.

[0132] Here, the dielectric material layer can be a stacked structure, such as a fifth dielectric material layer K5A and a sixth dielectric material layer K6A stacked together.

[0133] Optionally, the fifth dielectric material layer K5A is a silicon nitride layer. The sixth dielectric material layer K6A is a silicon oxide layer. The fifth dielectric material layer K5A covers the fourth dielectric layer K4, the third blocking portion B3, and the first conductive structure (i.e., the third interconnect structure L3). The sixth dielectric material layer K6A covers the fifth dielectric material layer K5A and can have a larger thickness.

[0134] Alternatively, please continue reading Figure 8 A hard mask layer Y1 and an anti-reflection layer Y2 are sequentially formed on the surface of the sixth dielectric material layer K6A.

[0135] Optionally, the hard mask layer Y1 can be formed using silicon nitride, pure carbon, polycrystalline silicon, or a metallic material. The antireflective layer Y2 can be a dielectric antireflective coating, for example, formed using silicon oxynitride or other nitrogen-containing compounds.

[0136] In step S300, please refer to Figure 9 and Figure 10 The dielectric material layer is patterned to form a dielectric layer; the dielectric layer has a patterned morphology.

[0137] Here, as Figure 9 As shown, a patterned photoresist layer PR can be formed on the surface of the anti-reflection layer Y2 first, so as to form a mask pattern in the hard mask layer Y1 based on the pattern of the photoresist layer PR. Then, the photoresist layer PR is stripped, and the fifth dielectric material layer K5A and the sixth dielectric material layer K6A are patterned based on the mask pattern in the hard mask layer Y1 to form the fifth dielectric layer K5 and the sixth dielectric layer K6, respectively. Figure 10 As shown in the diagram. Thus, the patterned topography in the fifth dielectric layer K5 and the sixth dielectric layer K6 is, for example, a via V1.

[0138] In step S451, please refer to Figure 11 and Figure 12 The first barrier material layer 210, the support material layer 220, the second barrier material layer 230 (i.e., barrier material layer 20) and the conductive material layer 30 are deposited sequentially.

[0139] For example, the first barrier material layer 210 covers the inner wall of the via V1 in the fifth dielectric layer K5 and the sixth dielectric layer K6 and the surface of the sixth dielectric layer K6 facing away from the substrate 10, the support material layer 220 covers the first barrier material layer 210, the second barrier material layer 230 covers the support material layer 220, and the conductive material layer 30 covers the second barrier material layer 230 and fills the via V1.

[0140] Here, matching the specific configuration of the blocking structure 2 in some of the aforementioned embodiments, the first blocking material layer 210 or the second blocking material layer 230 may also cover part of the first conductive structure (i.e., the third interconnect structure L3), for example... Figure 12 As shown in Figures (a) and (b) in the text.

[0141] In steps S452 and S453, please refer to Figure 13 and Figure 14The conductive material layer 30 is ground to expose the second barrier material layer 230 above the sixth dielectric layer K6. Then, the second barrier material layer 230, the support material layer 220, and the first barrier material layer 210 are ground to expose the surface of the sixth dielectric layer K6 away from the substrate 10. This causes the first barrier material layer 210, retained within the aforementioned via V1, to form the first barrier layer 21; the support material layer 220, retained within the aforementioned via V1, to form the sandwich layer 22; the second barrier material layer 230, retained within the aforementioned via V1, to form the second barrier layer 23; and the conductive material layer 30, retained within the aforementioned via V1, to form the second conductive structure 3.

[0142] After forming the aforementioned barrier structure 2 and the second conductive structure 3, please refer to Figure 15 The fourth barrier portion B4 and the pad layer 4 can be sequentially formed on the top surface of the sixth dielectric layer K6, the barrier structure 2, and the second conductive structure 3. Please refer to [link / reference]. Figure 16 A planarization layer 5 and a packaging layer 6 can be sequentially formed on the surfaces of the sixth dielectric layer K6 and the pad layer 4, thereby completing the fabrication of the DRAM.

[0143] It should be noted that the grinding mentioned in the embodiments of this disclosure can be chemical mechanical polishing (CMP) or other grinding and polishing processes. The barrier layers mentioned in the embodiments of this disclosure can have the same structure as barrier structure 2, or they can be titanium or titanium nitride barrier layers.

[0144] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0145] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A dielectric layer is disposed on the substrate; The dielectric layer has a patterned morphology; And, a blocking structure covering the inner wall of the patterned morphology; The barrier structure includes: a first barrier layer, a sandwich layer and a second barrier layer stacked together; Wherein, the first barrier layer and the second barrier layer are both tungsten nitride layers, and the sandwich layer is a tungsten metal layer; The barrier structure is prepared by a grinding process after the corresponding material layer is formed.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A first conductive structure is located between the substrate and the dielectric layer, wherein the patterned topography of the dielectric layer exposes a portion of the first conductive structure. The first barrier layer or the second barrier layer further covers the first conductive structure.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: A second conductive structure covers the second barrier layer and is located within the patterned morphology of the dielectric layer.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of any one of the first barrier layer, the sandwich layer, and the second barrier layer ranges from 2 nm to 30 nm.

5. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, on which a dielectric material layer is formed; The dielectric material layer is patterned to form a dielectric layer; The dielectric layer has a patterned morphology; A barrier structure is formed, which covers the inner wall of the patterned morphology; The formation of the barrier structure includes: forming a first barrier layer, a sandwich layer and a second barrier layer stacked together, so that the first barrier layer, the sandwich layer and the second barrier layer together constitute the barrier structure; Wherein, the first barrier layer and the second barrier layer are both tungsten nitride layers, and the sandwich layer is a tungsten metal layer; The barrier structure is prepared by a grinding process after the corresponding material layer is formed.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, Before forming the dielectric material layer on the substrate, the preparation method further includes: forming a first conductive structure on the substrate; Wherein, after the dielectric material layer is patterned, the first conductive structure is exposed at the bottom of the patterned morphology; The first barrier layer or the second barrier layer also covers the first conductive structure.

7. The method for preparing a semiconductor structure according to claim 5, characterized in that, The preparation method further includes: A second conductive structure is formed; the second conductive structure covers the second barrier layer and is located within the patterned morphology of the dielectric layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of the first barrier layer, the sandwich layer, and the second barrier layer, which are stacked together, and the formation of the second conductive structure, include: A first barrier material layer, a support material layer, a second barrier material layer, and a conductive material layer are deposited sequentially; wherein, the first barrier material layer covers the inner wall of the patterned morphology and the surface of the dielectric layer facing away from the substrate, the support material layer covers the first barrier material layer, the second barrier material layer covers the support material layer, and the conductive material layer covers the second barrier material layer and fills the patterned morphology. The conductive material layer is ground to expose the second barrier material layer above the dielectric layer; The second barrier material layer, the support material layer, and the first barrier material layer are ground to expose the surface of the dielectric layer facing away from the substrate, so that the first barrier material layer retained in the patterned morphology forms the first barrier layer, the support material layer retained in the patterned morphology forms the sandwich layer, the second barrier material layer retained in the patterned morphology forms the second barrier layer, and the conductive material layer retained in the patterned morphology forms the second conductive structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The supporting material layer and the conductive material layer are made of the same material.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, The first barrier material layer and the second barrier material layer are made of the same material, and the grinding rate of the first barrier material layer and the second barrier material layer is the same as or similar to the grinding rate of the conductive material layer.

11. The method for preparing a semiconductor structure according to claim 8, characterized in that, The gases used for depositing the first barrier material layer and / or the second barrier material layer include: diborane, tungsten hexafluoride, and ammonia. The gases used for depositing the support material layer and / or the conductive material layer include: diborane and tungsten hexafluoride.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The flow rate of diborane used for depositing the first barrier material layer and / or the second barrier material layer ranges from 100 sccm to 300 sccm; the flow rate of tungsten hexafluoride used for depositing the first barrier material layer and / or the second barrier material layer ranges from 200 sccm to 400 sccm; and the flow rate of ammonia used for depositing the first barrier material layer and / or the second barrier material layer ranges from 100 sccm to 400 sccm.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, The pressure of the gas used to deposit the first barrier material layer and / or the second barrier material layer ranges from 1 to 10 torr; the temperature of the gas used to deposit the first barrier material layer and / or the second barrier material layer ranges from 250°C to 400°C.

14. The method for preparing a semiconductor structure according to claim 11, characterized in that, The flow rate of diborane used for depositing the support material layer and / or the conductive material layer ranges from 200 sccm to 500 sccm; the flow rate of tungsten hexafluoride used for depositing the support material layer and / or the conductive material layer ranges from 300 sccm to 400 sccm.

15. The method for preparing a semiconductor structure according to claim 11, characterized in that, The pressure of the gas used to deposit the support material layer and / or the conductive material layer ranges from 20 to 60 torr; the temperature of the gas used to deposit the support material layer and / or the conductive material layer ranges from 250°C to 400°C.

16. The method for preparing a semiconductor structure according to claim 8, characterized in that, Before depositing the first barrier material layer, the preparation method further includes preheating the structure obtained after forming the dielectric layer.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, The preheating time ranges from 5s to 40s.

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