Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a substrate having opposite first and second surfaces; a metal pad on a side of the second surface facing away from the substrate; a through-silicon via structure penetrating the substrate along a thickness direction via the first surface and being in contact with the metal pad; a projection of the metal pad on the second surface covering a bottom surface of the through-silicon via structure; and an isolation ring structure formed in the substrate and surrounding the through-silicon via structure, wherein an inner sidewall of the isolation ring structure has a preset distance from an outer sidewall. The semiconductor structure prevents metal material sputtered from the metal pad from diffusing into the substrate during etching of the through-silicon via structure, thereby improving the isolation performance of the through-silicon via structure and reducing the risk of communication between adjacent through-silicon via structures, to improve the yield of semiconductor products.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the rapid development of integrated circuit technology, 3D packaging technology has been widely used in various high-speed circuits and miniaturized systems due to its excellent electrical performance and high reliability. Through Silicon Via (TSV) technology is an emerging 3D integrated circuit fabrication process that uses stacked chips to achieve interconnection. It achieves electrical interconnection between different chips by creating several vertically interconnecting TSV structures on a wafer. TSV technology has enabled integrated circuit layout to evolve from traditional two-dimensional side-by-side arrangement to more advanced three-dimensional stacking. It maximizes the density of chip stacking in three dimensions, minimizes the interconnect lines between chips, and reduces the overall size, thereby greatly improving the frequency and power characteristics of the circuit. It is currently a very important technology in electronic packaging.

[0003] In TSV process technology, since the thinned wafer is usually still at the micrometer level, it is necessary to create holes or trenches with high aspect ratios. For etching deep holes with high aspect ratios, the etching energy is usually increased, which causes etching byproducts to sputter onto the sidewalls of the holes or trenches and gradually accumulate and diffuse, reducing the isolation performance of adjacent through-silicon vias and posing a risk of conduction. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems mentioned in the background art, so as to avoid the sputtering and diffusion of etching attachments from interfering with adjacent semiconductor structures or electronic components, thereby improving the performance and reliability of the fabricated semiconductor products.

[0005] To achieve the above and other related objectives, one aspect of this disclosure provides a semiconductor structure, including a substrate, a metal pad, a through-silicon via (TSV) structure, and an isolation ring structure; the substrate has a first surface and a second surface facing each other; the metal pad is located on the side of the second surface away from the substrate; the TSV structure penetrates the substrate along the thickness direction through the first surface and contacts and connects with the metal pad; the orthographic projection of the metal pad on the second surface covers the bottom surface of the TSV structure; the isolation ring structure is formed in the substrate and surrounds the TSV structure, wherein the inner sidewall and the outer sidewall of the isolation ring structure have a predetermined distance.

[0006] In the above embodiments, the metal pad is located on the second surface of the substrate and on the side away from the substrate. An isolation ring structure is provided in the region surrounding the through-silicon via (TSV) structure. During the TSV etching process to form a TSV structure with a high aspect ratio, a high-energy etching material is used for etching. When the substrate is etched to form the TSV, when the etching process reaches the bottom of the substrate and approaches the upper surface of the metal pad, the high-energy etching material bombards the metal pad. When the metal material in the metal pad splashes onto the sidewall of the etched hole, the material in the metal pad diffuses into the sidewall and into the substrate. Due to the isolation ring structure, the material in the metal pad will not appear on the side of the isolation ring structure away from the TSV structure along the width direction, that is, it will not diffuse into the depth of the substrate. This avoids the situation where adjacent TSVs become connected due to the gradual diffusion of metal inside the substrate during or even after the TSV etching process. This improves the isolation performance of the TSV structure and can prevent the sputtering and diffusion of etching byproducts from interfering with adjacent semiconductor structures or electronic components, thereby improving the performance and reliability of the semiconductor products. In traditional techniques, etching deep holes with high aspect ratios typically involves increasing the energy of the etching material. This inevitably bombards the underlying metal pads, causing sputtered material to the sidewalls of the holes and gradually diffuse, reducing the isolation performance of adjacent through-silicon vias (TSVs) and posing a risk of interconnection. Compared to traditional techniques, the semiconductor structure disclosed in this invention prevents the metal material sputtered from the metal pads from diffusing into the substrate during the etching process of the TSV structure through the setting of an isolation ring structure. This improves the isolation performance of the TSV structure, reduces the risk of interconnection between adjacent TSV structures, and improves the yield of semiconductor products.

[0007] In some embodiments, the isolation ring structure extends through the substrate along the thickness direction via a first surface and extends to a second surface.

[0008] In some embodiments, an isolation protective layer is included between the inner sidewall of the isolation ring structure and the outer sidewall of the through-silicon via structure.

[0009] In some of these embodiments, the protective layer comprises an insulating material.

[0010] In some embodiments, the semiconductor structure further includes an annular barrier layer; the annular barrier layer surrounds the through-silicon via (TSV) structure and is located between the isolation protection layer and the TSV structure.

[0011] In some embodiments, the annular barrier layer extends through the substrate and to the metal pad via a first surface in the thickness direction.

[0012] In some embodiments, the minimum distance between the inner wall of the isolation ring structure and the outer wall of the through-silicon via structure is greater than or equal to 1 μm.

[0013] In some embodiments, the minimum distance between the outer walls of adjacent isolation ring structures is greater than or equal to 1 μm.

[0014] In some embodiments, the preset distance is 2μm-10μm.

[0015] In some embodiments, the material of the isolation ring structure includes a first low-dielectric-constant material layer, a metal barrier layer, and a second low-dielectric-constant material layer, wherein the first low-dielectric-constant material layer surrounds the through-silicon via structure, the metal barrier layer surrounds the first low-dielectric-constant material layer, and the second low-dielectric-constant material layer surrounds the metal barrier layer.

[0016] In some embodiments, the material of the annular barrier layer includes at least one of tantalum, tantalum nitride, and titanium nitride.

[0017] Another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:

[0018] A substrate having opposing first and second surfaces is provided, and a metal pad is formed on the side of the second surface away from the substrate;

[0019] An isolation ring structure is formed within the substrate, and the inner sidewall and outer sidewall of the isolation ring structure have a predetermined distance;

[0020] A through-silicon via (TSV) structure is formed in the substrate within the isolation ring structure. The TSV structure penetrates the substrate along the thickness direction through the first surface and is in contact with a metal pad. The orthogonal projection of the metal pad on the second surface covers the bottom surface of the TSV structure.

[0021] In the above embodiments, a metal pad is formed on the side of the second surface of the substrate away from the substrate, and an isolation ring structure is formed before the formation of the through-silicon via (TSV) structure. The isolation ring structure surrounds the TSV structure to be formed subsequently. When the TSV structure is formed in the substrate, the substrate needs to be etched with high energy. When the etching approaches the upper surface of the metal pad, it is inevitable that the metal pad will be etched, so that the metal material in the metal pad is sputtered onto the sidewall of the etched hole and gradually diffuses. Since the isolation ring structure has been formed before the etched hole, the metal material sputtered onto the sidewall stops its diffusion movement when it diffuses and contacts the isolation ring structure. The side of the isolation ring structure away from the TSV structure will not appear, so that the sputtered metal material will not diffuse into the depth of the substrate and connect with the adjacent TSV structure. This avoids the risk of conduction between different TSV structures, improves the isolation performance of the TSV structure, and improves the yield of semiconductor products.

[0022] In some embodiments, a first dielectric layer is formed between the metal pad and the second surface; the isolation ring structure includes a first low-dielectric-constant material layer, a metal barrier layer, and a second low-dielectric-constant material layer, wherein the first low-dielectric-constant material layer surrounds the through-silicon via structure, the metal barrier layer surrounds the first low-dielectric-constant material layer, and the second low-dielectric-constant material layer surrounds the metal barrier layer; the step of forming the isolation ring structure in the substrate includes:

[0023] A second dielectric layer is formed on the first surface of the substrate;

[0024] The second dielectric layer and the substrate are etched to obtain an isolation ring gap, which exposes part of the first dielectric layer.

[0025] A first low dielectric constant material layer, a metal barrier layer, and a second low dielectric constant material layer are formed within the gap of the isolation ring to obtain the isolation ring structure.

[0026] In some embodiments, the step of forming a through-silicon via structure in the substrate within the isolation ring structure includes:

[0027] The substrate within the second dielectric layer and the isolation ring structure is etched to obtain a via, which exposes part of the metal pad.

[0028] An isolation and protective layer is formed on the sidewall of the through hole;

[0029] An annular barrier layer is deposited on the sidewall of the isolation and protective layer;

[0030] A conductive material layer is filled into the through-hole, and then planarized to obtain a silicon through-hole structure.

[0031] In some embodiments, the minimum distance between the inner wall of the isolation ring structure and the outer wall of the through-silicon via structure is greater than or equal to 1 μm.

[0032] In some embodiments, the minimum distance between the outer walls of adjacent isolation ring structures is greater than or equal to 1 μm.

[0033] In some embodiments, the preset distance is 2μm-10μm. Attached Figure Description

[0034] To better describe and illustrate the disclosed embodiments and / or examples herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosures, the currently described embodiments and / or examples, or the best mode of these disclosures as currently understood.

[0035] Figures 1-2 The diagram shows a cross-sectional view of a semiconductor structure during the TSV etching process in a conventional technique provided in an embodiment of this disclosure.

[0036] Figure 3 The diagram shown is a cross-sectional schematic of a semiconductor structure provided in an embodiment of this disclosure.

[0037] Figure 4 The following is shown as an embodiment of this disclosure. Figure 3 A schematic cross-sectional view of the semiconductor structure along the AA' direction;

[0038] Figure 5 The diagram shows a flowchart of a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0039] Figure 6 The diagram shows a process flow diagram of a semiconductor structure fabrication method provided in another embodiment of this disclosure;

[0040] Figure 7 The diagram shows a flow chart of a semiconductor structure fabrication method provided in yet another embodiment of this disclosure;

[0041] Figure 8 The diagram shown is a cross-sectional schematic of a semiconductor structure provided in another embodiment of this disclosure.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10. Substrate; 10a. First surface; 10b. Second surface; 11. Metal pad; 111. Etching attachment; 12. Through-silicon via structure; 13. Isolation ring structure; 14. Isolation protective layer; 15. Annular barrier layer; 16. First dielectric layer; 17. Second dielectric layer; 131. First low dielectric constant material layer; 132. Metal barrier layer; 133. Second low dielectric constant material layer. Detailed Implementation

[0044] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] The embodiments disclosed herein are described with reference to cross-sectional views that serve as schematic representations of preferred embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. The regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this disclosure.

[0050] Please see Figures 1-8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components in the actual implementation, the form, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] With the development of integrated circuits and the changing times, people's requirements for electronic products have shifted towards smaller size, more functions, and greener designs. Therefore, people are striving to find technological directions that make electronic systems smaller, more integrated, and more functional, leading to the emergence of many new technologies, materials, and designs. Moore's Law predicts that, with a constant price, the number of components that can be placed on an integrated circuit will double approximately every 18-24 months. However, as the physical size of Complementary Metal-Oxide-Semiconductor (CMOS) transistors gradually approaches its limit, simply relying on reducing transistor size to improve integrated circuit performance is no longer reasonable. Therefore, relying on shrinking transistor size to improve integrated circuit performance and reduce power consumption has become impractical. Three-dimensional integrated circuits are considered a feasible solution to continue Moore's Law and further improve integrated circuit performance and reduce power consumption. Stacked chip packaging technology is a typical example of this. Stacked chip packaging technology, or 3D packaging technology, refers to packaging technology that stacks two or more chips vertically within the same package without changing the package size. 3D packaging has two main methods: Package-on-Package (POP) and Chip-Scale Packaging. POP technology typically achieves this through stacking Thin Small Outline Packages (TSOPs) or Chip-Scale Packages (CSPs) based on traditional packaging technologies. However, the long interconnects between chips limit the high-frequency and high-speed performance of POP stacking. Currently, TSV technology, based on wafer fabrication technology, is attracting increasing attention in the semiconductor industry. TSV technology achieves electrical interconnection between upper and lower chips by creating vertical interconnect vias on the wafer, compared to wire bonding and flip-chip bonding. TSV technology can reduce the interconnect length between two nodes, thus offering several advantages over 2D integrated circuits: shorter signal delay, higher operating frequency, smaller parasitic capacitance, and lower power consumption. It can effectively realize 3D chip stacking, manufacturing more complex, higher-performance, and cost-efficient packages.

[0052] For example, please refer to Figures 1-2In the fabrication of 3D integrated circuits, TSV (Through-Slip Vessel) has been used to form electrical connections between layers in stacked arrangements or 3D arrangements of devices such as MEMS (Micro-Electro-Mechanical Systems) and semiconductor devices. As an important technology in advanced packaging platforms, TSV requires etching thinned wafers and other dielectric layers to ultimately connect with metal pads. Since the thinned wafers are typically still at the micrometer level, advanced etching processes are needed to create holes or trenches with extremely high aspect ratios in the substrate. Figure 1 In deep hole etching with a high aspect ratio, the energy of the etching material is usually increased. This inevitably bombards the underlying metal pads, causing etching deposits 111 to sputter onto the sidewalls of the hole or trench and gradually accumulate. The sputtered etching deposits 111 gradually penetrate and diffuse into the sidewalls. Figure 2 In the TSV process, although a barrier layer is formed after the TSV process is completed, the etch attachments 111 sputtered onto the sidewalls of the vias have diffused into the substrate. As the amount of etch attachments 111 diffusing deep into the substrate gradually increases, adjacent vias may become conductive, reducing their isolation performance. This TSV fabrication defect can severely impact the production yield of semiconductor products. Therefore, this disclosure addresses the problems in the above-mentioned technology by providing a semiconductor structure and its fabrication method that can prevent the etch attachments 111 from diffusing into the substrate, i.e., prevent the material in the metal pads from diffusing into the sidewalls and interfering with adjacent TSVs. This can effectively improve the reduction in TSV isolation performance caused by deep-hole etching and increase yield.

[0053] For example, please refer to Figure 3 The present disclosure provides a semiconductor structure including a substrate 10, a metal pad 11, a through-silicon via (TSV) structure 12, and an isolation ring structure 13. The substrate 10 has a first surface 10a and a second surface 10b facing each other. The metal pad 11 is located on the side of the second surface 10b away from the substrate 10. The TSV structure 12 penetrates the substrate 10 along the thickness direction through the first surface 10a and is in contact with the metal pad 11. The orthogonal projection of the metal pad 11 onto the second surface 10b covers the bottom surface of the TSV structure 12. The isolation ring structure 13 is formed in the substrate 10 and surrounds the TSV structure 12, wherein the inner sidewall and the outer sidewall of the isolation ring structure 13 have a predetermined distance.

[0054] In the above embodiment, the metal pad 11 is located on the second surface 10b of the substrate 10 and on the side facing away from the substrate 10. An isolation ring structure 13 is provided in the region surrounding the through-silicon via (TSV) structure 12. During the TSV etching process to form the TSV structure 12 with a high aspect ratio, a high-energy etching material is used. When the substrate 10 is etched to form the TSV, when the etching process reaches the bottom of the substrate 10 near the upper surface of the metal pad 11, the high-energy etching material bombards the metal pad 11. The metal material in 11 splashes onto the sidewall of the etched hole. Then, the material in the metal pad 11 diffuses into the interior of the sidewall and into the substrate 10. However, due to the setting of the isolation ring structure 13, the material in the metal pad 11 will not diffuse into the depth of the substrate 10, i.e., it will not spread to the side of the isolation ring structure 13 away from the through-silicon via structure 12. This avoids the situation where adjacent through-silicon vias are connected due to the gradual diffusion of metal inside the substrate 10 during or after the etching process of the through-silicon via structure 12, thereby improving the isolation performance of the through-silicon via structure 12. In conventional techniques, etching high aspect ratio deep holes typically involves increasing the energy of the etching material. This inevitably bombards the underlying metal pad 11, causing it to sputter onto the sidewalls of the hole and gradually diffuse, reducing the isolation performance of adjacent through-silicon vias (TSVs) and posing a risk of interconnection. Compared to conventional techniques, the semiconductor structure provided in this disclosure prevents the metal material sputtered from the metal pad 11 from diffusing into the substrate 10 during the etching of the TSV structure 12 by setting the isolation ring structure 13. This improves the isolation performance of the TSV structure 12, reduces the risk of interconnection between adjacent TSV structures 12, and improves the yield of semiconductor products.

[0055] As an example, the substrate can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the substrate type according to the type of transistors formed on the substrate 10; therefore, the type of substrate 10 should not limit the scope of this disclosure.

[0056] As an example, please continue reading Figure 3The isolation ring structure 13 extends through the substrate 10 along the thickness direction via the first surface 10a and extends to the second surface 10b to prevent the metal material in the metal pad 11 from appearing on the side of the isolation ring structure 13 away from the through-silicon via structure 12. That is, the metal material in the metal pad 11 will not diffuse into the depth of the substrate 10, thereby avoiding the situation where adjacent through-silicon vias are connected due to the gradual diffusion of metal inside the substrate 10.

[0057] As an example, please continue reading Figure 3 An isolation protective layer 14 is included between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12. The isolation protective layer 14 includes an insulating material, specifically, the material of the isolation protective layer 14 may be silicon dioxide (SiO2).

[0058] As an example, the semiconductor structure also includes an annular barrier layer 15; the annular barrier layer 15 surrounds the through-silicon via structure 12 and is located between the isolation protection layer 14 and the through-silicon via structure 12. The annular barrier layer 15 extends through the substrate 10 in the thickness direction via the first surface 10a and extends to the metal pad 11.

[0059] As an example, the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12 is greater than or equal to 1 μm. For example, the minimum distance between the inner sidewall of the isolation ring structure 13 and the outer sidewall of the through-silicon via structure 12 can be 1 μm, 1.5 μm, 2 μm, or 3 μm, etc.

[0060] As an example, the minimum distance between the outer walls of adjacent isolation ring structures 13 is greater than or equal to 1 μm. For example, the minimum distance between the outer walls of adjacent isolation ring structures 13 can be 1 μm, 1.5 μm, 2 μm, or 2.5 μm, etc.

[0061] As an example, the preset distance is 2μm-10μm. For example, the preset distance can be 2μm, 3μm, 6μm, or 10μm, etc.

[0062] For example, please refer to Figure 8 ,exist Figure 8In the isolation ring structure 13, the materials include a first low dielectric constant material layer 131, a metal barrier layer 132, and a second low dielectric constant material layer 133. The first low dielectric constant material layer 131 is located within the substrate 10 and surrounds the through-silicon via structure 12. The metal barrier layer 132 surrounds the first low dielectric constant material layer 131, and the second low dielectric constant material layer 133 surrounds the metal barrier layer 132. The first low dielectric constant material layer 131 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), and fluorocarbon compounds (aC:F), etc. The metal barrier layer 132 may include at least one of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (Ti). The second low dielectric constant material layer 133 may include fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), and fluorocarbon compounds (aC:F), etc. For example, the materials of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 can be carbon-doped silicon dioxide, and the material of the metal barrier layer 132 can be tantalum nitride. Inside the semiconductor device, parasitic capacitance inevitably exists between the filling material in the through-silicon via structure 12 and the metal barrier layer 132. Parasitic capacitance not only affects the chip speed but also poses a serious threat to operational reliability. Since reducing the dielectric constant of the dielectric can reduce the capacitance, when the metal barrier layer 132 is used as the isolation ring structure 13, forming the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133 on the inner and outer walls of the isolation ring structure 13 can effectively reduce the parasitic capacitance between the through-silicon via structure 12 and the isolation ring structure 13, thereby improving the overall performance of the semiconductor product.

[0063] As an example, please continue reading Figure 8 The thickness of the metal barrier layer 132 can be less than the sum of the thicknesses of the first low dielectric constant material layer 131 and the second low dielectric constant material layer 133, so as to simultaneously ensure the isolation performance and metal barrier performance of the isolation ring structure 13.

[0064] As an example, please continue reading Figure 8 The thickness of the metal barrier layer 132 can be 1 / 3 to 2 / 3 of the sum of the thicknesses of the first low-dielectric-constant material layer 131 and the second low-dielectric-constant material layer 133. For example, the thickness of the metal barrier layer 132 can be 1 / 3, 0.5, 0.55, or 2 / 3 of the sum of the thicknesses of the first low-dielectric-constant material layer 131 and the second low-dielectric-constant material layer 133, etc. The thickness of the metal barrier layer 132 cannot be too thin to avoid interference from the sputtering and diffusion of etching byproducts during the fabrication of the through-silicon via structure to adjacent semiconductor structures or electronic components; the thickness of the metal barrier layer 132 cannot be too thick to avoid the problem of increased parasitic capacitance due to a relative reduction in the thickness of the first low-dielectric-constant material layer 131 or the second low-dielectric-constant material layer 133.

[0065] As an example, please continue reading Figure 3 and Figure 8 The material of the annular barrier layer 15 includes at least one of tantalum, tantalum nitride and titanium nitride; the material of the isolation protection layer 14 includes an insulating material and / or a low dielectric constant material. Specifically, the material of the isolation protection layer 14 can be silicon dioxide.

[0066] For example, please refer to Figure 4 , Figure 4 This is a top view of the semiconductor structure in the above embodiments, i.e., along... Figure 3 In the cross-sectional view along the AA' direction, the annular barrier layer 15, the isolation protective layer 14, and the isolation ring structure 13 are concentric rings with the same center as the through-silicon via (TSV) structure 12. All three elements penetrate the substrate 10 along the thickness direction, with a preset distance of 2μm-10μm. The minimum distance between the inner wall of the isolation ring structure 13 and the outer wall of the TSV structure 12 is greater than or equal to 1μm. This structure prevents metal sputtering from penetrating deep into the substrate 10 during the etching of the TSV structure 12, thus avoiding interconnection between adjacent TSV structures 12 and improving the isolation performance of the TSV structure 12.

[0067] For example, please refer to Figure 5 This disclosure also provides a method for fabricating a semiconductor structure, comprising the following steps:

[0068] Step S10: Provide a substrate having a first surface and a second surface opposite to each other, and form a metal pad on the side of the second surface away from the substrate;

[0069] Step S20: An isolation ring structure is formed in the substrate, and the inner sidewall and the outer sidewall of the isolation ring structure have a predetermined distance;

[0070] Step S30: A through-silicon via (TSV) structure is formed in the substrate within the isolation ring structure. The TSV structure penetrates the substrate along the thickness direction through the first surface and is in contact with the metal pad. The orthogonal projection of the metal pad on the second surface covers the bottom surface of the TSV structure.

[0071] In step S10, please refer to Figure 3 and Figure 5 In step S10, a substrate 10 having a first surface 10a and a second surface 10b opposite to each other is provided, and a metal pad 11 is formed on the second surface 10b.

[0072] As an example, step S10 may further include the following steps: thinning the substrate 10 to a preset thickness. The thinning method may include grinding, which includes different processing steps such as rough grinding, fine grinding, and polishing. For example, the thickness of the substrate 10 after thinning is less than 100 μm. After the substrate 10 is thinned to the preset thickness, rapid wet etching is performed on the surface of the substrate 10. The isotropic nature of wet etching eliminates the stress on the substrate 10. Since there is a surface damage layer on the back side of the thinned substrate 10, the residual stress can cause the thinned epitaxial wafer to bend and easily break in subsequent processes, thus affecting the yield. Therefore, the back side of the substrate 10 can be polished after thinning. Specifically, the polishing process can employ chemical mechanical polishing (CMP).

[0073] In step S20, please refer to Figure 3 and Figure 5 In step S20, an isolation ring structure 13 is formed within the substrate 10, with a predetermined distance between the inner and outer sidewalls of the isolation ring structure 13. Since the material of the isolation ring structure 13 is chosen to block metal from the metal pads, it prevents etching attachments (i.e., metal material from the metal pads) from spreading into the side of the isolation ring structure 13 away from the silicon via structure 12 along its width direction during the subsequent formation of the through-silicon via structure 12. This prevents interconnection between adjacent silicon via structures 12 and avoids the sputtering and diffusion of etching attachments that could interfere with adjacent semiconductor structures or electronic components, thereby improving the performance and reliability of the fabricated semiconductor products.

[0074] In step S30, please refer to Figure 3 and Figure 5 In step S30, a through-silicon via (TSV) structure 12 is formed in the substrate 10 within the isolation ring structure 13. The TSV structure 12 penetrates the substrate 10 along the thickness direction via the first surface 10a and contacts and connects with the metal pad 11. The metal pad 11 covers the bottom surface of the TSV structure 12 with its orthogonal projection onto the second surface 10b. Since the isolation ring structure 13 is formed before the TSV structure 12, during the formation of the TSV structure 12, when the high-energy etching material is about to finish etching the TSV structure, the metal pad 11 in contact with the TSV structure 12 is bombarded with metal sputtering. At this time, the metal sputters to the sidewall and diffuses to the isolation ring structure 13 and stops, without diffusing into the interior of the substrate 10. That is, there is no phenomenon of adjacent TSV structures 12 being connected.

[0075] In the above embodiments, a metal pad 11 is formed on the side of the second surface 10b of the substrate 10 away from the substrate 10, and an isolation ring structure 13 is formed before the formation of the through-silicon via (TSV) structure 12. The isolation ring structure 13 surrounds the TSV structure 12 that will be formed subsequently. When the TSV structure 12 is formed in the substrate 10, the substrate 10 needs to be etched with high energy. When the etching approaches the upper surface of the metal pad 11, it is unavoidable that the metal pad 11 will be etched, so that the metal material in the metal pad 11 is sputtered onto the sidewall of the etched hole and gradually... Gradual diffusion occurs because an isolation ring structure 13 is formed before etching the via. When the sputtered metal material on the sidewall diffuses and comes into contact with the isolation ring structure 13, it stops its diffusion movement and will not appear on the side of the isolation ring structure 13 away from the through-silicon via structure 12 along the width direction. This prevents the sputtered metal material from diffusing deep into the substrate 10 and connecting with the adjacent through-silicon via structure 12, avoiding the risk of conduction between different through-silicon via structures 12, improving the isolation performance of the through-silicon via structure 12, and improving the yield of semiconductor products.

[0076] For example, please refer to Figure 6 A first dielectric layer is formed between the metal pad and the second surface; the step of forming an isolation ring structure within the substrate includes:

[0077] Step S21: Form a second dielectric layer on the first surface of the substrate;

[0078] Step S22: Etch the second dielectric layer and the substrate to obtain an isolation ring gap, which exposes part of the first dielectric layer;

[0079] Step S23: Form a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer within the gap of the isolation ring to obtain the isolation ring structure.

[0080] In step S21, please refer to Figure 8 and Figure 6 In step S21, a second dielectric layer 17 is formed on the first surface 10a of the substrate 10. The formation of the second dielectric layer 17 can be performed using a rapid thermal oxidation (RTO) process.

[0081] In step S22, please refer to Figure 8 and Figure 6 In step S22, a dry etching process can be used to etch the second dielectric layer 17 and the substrate 10 to obtain an isolation ring gap, which exposes a portion of the first dielectric layer. The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high-concentration plasma etching (HDP).

[0082] In step S23, please refer to Figure 8 and Figure 6 In step S23, an initial low-dielectric-constant material layer is deposited on the inner wall and bottom of the isolation ring gap. The deposition process may include one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD). The portion of the initial low-dielectric-constant material layer located at the bottom of the isolation ring gap is etched and removed, exposing the first dielectric layer 16, forming a first low-dielectric-constant material layer 131 surrounding the through-silicon via structure 12 and a second low-dielectric-constant material layer 133 surrounding the first low-dielectric-constant material layer 131. Then, a metal barrier layer 132 is formed in the gap between the first low-dielectric-constant material layer 131 and the second low-dielectric-constant material layer 133. The process for forming the metal barrier layer 132 may include one or more of CVD, PVD, and ALD.

[0083] As an example, please continue reading Figure 8 The isolation ring structure 13 includes a first low-dielectric-constant material layer 131, a metal barrier layer 132, and a second low-dielectric-constant material layer 133. The first low-dielectric-constant material layer 131 is located within the substrate 10 and surrounds the through-silicon via (TSV) structure 12. The metal barrier layer 132 surrounds the first low-dielectric-constant material layer 131, and the second low-dielectric-constant material layer 133 surrounds the metal barrier layer 132. When the metal barrier layer 132 is used as the isolation ring structure 13, forming the first low-dielectric-constant material layer 131 and the second low-dielectric-constant material layer 133 on the inner and outer walls of the isolation ring structure 13 can effectively reduce the parasitic capacitance between the TSV structure 12 and the isolation ring structure 13, thereby improving the overall performance of the semiconductor device.

[0084] For example, please refer to Figure 7 The step of forming a through-silicon via structure in the substrate within the isolation ring structure includes:

[0085] Step S31: Etch the substrate within the second dielectric layer and the isolation ring structure to obtain a via, which exposes part of the metal pad;

[0086] Step S32: Form an isolation protective layer on the sidewall of the through hole;

[0087] Step S33: Deposit an annular barrier layer on the sidewall of the isolation protective layer; Step S34: Fill the through-hole with a conductive material layer and planarize it to obtain a silicon through-hole structure.

[0088] In step S31, please refer to Figure 8 and Figure 7 In step S31, the substrate 10 within the second dielectric layer 17 and the isolation ring structure 13 is etched to obtain a via, which exposes a portion of the metal pad 11. Specifically, the process of etching to obtain the via can employ plasma etching technology.

[0089] As an example, before step S31 and after step S23, the following steps may also be included: spin-coating photoresist on the first surface 10b of the substrate 10 to form a patterned opening by photolithography; and removing the photoresist after step S31 is completed.

[0090] In step S32, please refer to Figure 8 and Figure 7 In step S32, an isolation protective layer 14 is formed on the sidewall of the through hole. The isolation protective layer 14 can be formed by rapid thermal oxidation (RTO), low pressure chemical vapor deposition (LPCVD), or selected area chemical vapor deposition (SACVD).

[0091] In step S33, please refer to Figure 8 and Figure 7 In step S33, an annular barrier layer 15 is deposited on the sidewall of the isolation protective layer 14. The annular barrier layer 15 can be formed using a physical vapor deposition (PVD) process. Generally, electroplating is used to fill vias in TSV processes, for example, copper electroplating. However, copper diffuses very quickly in the isolation protective layer, easily causing severe degradation of its dielectric properties. Furthermore, copper has a strong trapping effect on charge carriers in semiconductors; when copper diffuses into the semiconductor bulk material, it severely affects the electrical characteristics of the semiconductor device. The adhesion strength between copper and the isolation protective layer 14 is also poor. Therefore, depositing an annular barrier layer 15 between the through-silicon via structure 12 and the isolation protective layer 14 can prevent the diffusion of the conductive material layer filling the subsequently formed through-silicon via structure 12 and improve the performance of the semiconductor device.

[0092] In step S34, please refer to Figure 8 and Figure 7 In step S34, a conductive material layer is filled into the through hole and planarized to obtain the silicon through hole structure 12.

[0093] As an example, the method of filling the conductive material layer can be electroplating. Step S34, which involves filling the through-hole with conductive material and planarizing it, may include: First, physically removing air from the cavity, for example, using ultrasonic waves, spraying, or vacuuming to allow the electroplating solution to smoothly enter the cavity; second, filling the conductive material layer with copper electroplating. The copper electroplating process includes degreasing, micro-etching, acid immersion, and plating with conductive material. Degreasing includes removing oil and fingerprints from the board surface; micro-etching includes cleaning and roughening the copper surface, removing oxides and impurities from the board surface; and acid immersion... This includes removing the oxide film on the surface of the metal pad 11 and activating the surface of the metal pad 11, and reducing impurities. Copper plating includes depositing a conductive material layer on the surface of the metal pad 11 and inside the hole using a DC electroplating method. After electroplating, due to the excessive internal stress accumulated in the electroplated conductive material layer, many protrusion defects will be generated. A low-temperature annealing process can be used to suppress the generation of protrusion defects. In addition, after the low-temperature annealing process, the silicon through-hole structure 12 can be planarized. The planarization process can be performed using any one or more of CMP process, dry etching process, and push-through process.

[0094] It should be understood that, although Figures 5-7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Furthermore, although... Figures 5-7 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0095] As an example, the minimum distance between the inner wall of the isolation ring structure 13 and the outer wall of the through-silicon via structure 12 is greater than or equal to 1 μm. For example, the minimum distance between the inner wall of the isolation ring structure 13 and the outer wall of the through-silicon via structure 12 can be 1 μm, 1.5 μm, 2 μm or 3 μm, etc.

[0096] As an example, the minimum distance between the outer walls of adjacent isolation ring structures 13 is greater than or equal to 1 μm. For example, the minimum distance between the outer walls of adjacent isolation ring structures 13 can be 1 μm, 1.5 μm, 2 μm, or 2.5 μm, etc.

[0097] As an example, the preset distance is 2μm-10μm. For example, the preset distance can be 2μm, 3μm, 6μm or 10μm, etc.

[0098] As an example, the above-described method for forming a semiconductor structure can be combined with existing semiconductor device forming processes. For example, a semiconductor device (not shown), such as a metal oxide semiconductor transistor (MOS transistor) or dynamic random access memory (DRAM), can be formed on the substrate 10 first, and then the isolation ring structure 13 and the through-silicon via structure 12 can be formed using the steps of this disclosure.

[0099] In the semiconductor structure and its fabrication method described in the above embodiments, firstly, a substrate is provided, and a metal pad is formed on the side of the second surface of the substrate away from the substrate; then, an isolation ring structure is formed in the substrate, with a predetermined distance between the inner and outer sidewalls of the isolation ring structure; then, a through-silicon via (TSV) structure is formed in the substrate within the isolation ring structure, the TSV structure penetrating the substrate along the thickness direction via the first surface and contacting and connecting with the metal pad. During the etching of the TSV structure, since the metal pad is projected onto the bottom surface of the TSV structure from the second surface, the etching process will etch the metal pad when it approaches the metal pad, thereby causing the metal material in the metal pad to sputter into the sidewalls of the TSV structure. Since the isolation ring structure is formed before the TSV structure in the semiconductor structure disclosed herein, the metal material sputtered into the sidewalls is blocked by the isolation ring structure on the side of the isolation ring structure close to the TSV structure along the width direction, and will not diffuse into the depth of the substrate, thereby preventing adjacent TSV structures from becoming interconnected, thus improving the isolation performance of the TSV structure and improving the reliability of the semiconductor product.

[0100] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0101] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate has a first surface and a second surface opposite to each other; A metal pad is located on the side of the second surface opposite to the substrate; A through-silicon via (TSV) structure extends through the substrate along its thickness direction via the first surface and contacts and connects with the metal pad; the orthographic projection of the metal pad onto the second surface covers the bottom surface of the TSV structure. An isolation ring structure is formed within the substrate and surrounds the through-silicon via structure, wherein the inner sidewall and the outer sidewall of the isolation ring structure have a predetermined distance; An isolation protective layer is located between the inner wall of the isolation ring structure and the outer wall of the through-silicon via structure; An annular barrier layer surrounds the through-silicon via structure and is located between the isolation protective layer and the through-silicon via structure; The isolation protective layer includes an insulating material; the material of the annular barrier layer includes at least one of tantalum, tantalum nitride, and titanium nitride; the isolation ring structure includes a metal barrier layer, which includes at least one of tantalum, tantalum nitride, and titanium nitride.

2. The semiconductor structure according to claim 1, characterized in that, The isolation ring structure extends through the substrate along the thickness direction via the first surface and extends to the second surface.

3. The semiconductor structure according to claim 1, characterized in that, The annular barrier layer extends through the substrate along the thickness direction via the first surface and extends to the metal pad.

4. The semiconductor structure according to claim 1 or 3, characterized in that, The minimum distance between the inner wall of the isolation ring structure and the outer wall of the through-silicon via structure is greater than or equal to 1 μm.

5. The semiconductor structure according to any one of claims 1-3, characterized in that, The minimum distance between the outer walls of adjacent isolation ring structures is greater than or equal to 1 μm.

6. The semiconductor structure according to any one of claims 1-3, characterized in that, The preset distance is 2μm-10μm.

7. The semiconductor structure according to any one of claims 1-2, characterized in that, The isolation ring structure includes a first low dielectric constant material layer, a metal barrier layer, and a second low dielectric constant material layer, wherein the first low dielectric constant material layer surrounds the through-silicon via structure, the metal barrier layer surrounds the first low dielectric constant material layer, and the second low dielectric constant material layer surrounds the metal barrier layer.

8. A method for preparing a semiconductor structure as described in any one of claims 1-7, characterized in that, include: A substrate having opposing first and second surfaces is provided, and a metal pad is formed on the side of the second surface away from the substrate; An isolation ring structure is formed within the substrate, and the inner sidewall and outer sidewall of the isolation ring structure have a predetermined distance between them. A through-silicon via (TSV) structure is formed in the substrate within the isolation ring structure. The TSV structure penetrates the substrate along the thickness direction via the first surface and is in contact with the metal pad. The orthogonal projection of the metal pad onto the second surface covers the bottom surface of the TSV structure.

9. The preparation method according to claim 8, characterized in that, A first dielectric layer is formed between the metal pad and the second surface; the isolation ring structure includes a first low dielectric constant material layer, a metal barrier layer and a second low dielectric constant material layer, the first low dielectric constant material layer surrounds the through-silicon via structure, the metal barrier layer surrounds the first low dielectric constant material layer, and the second low dielectric constant material layer surrounds the metal barrier layer. The step of forming the isolation ring structure within the substrate includes: A second dielectric layer is formed on the first surface of the substrate; The second dielectric layer and the substrate are etched to obtain an isolation ring gap, which exposes a portion of the first dielectric layer; The first low dielectric constant material layer, the metal barrier layer, and the second low dielectric constant material layer are formed within the gap of the isolation ring to obtain the isolation ring structure.

10. The preparation method according to claim 9, characterized in that, The step of forming a through-silicon via structure in the substrate within the isolation ring structure includes: The second dielectric layer and the substrate within the isolation ring structure are etched to obtain a via, which exposes a portion of the metal pad. An isolation and protective layer is formed on the sidewall of the through hole; An annular barrier layer is deposited on the sidewall of the isolation and protective layer; A conductive material layer is filled into the through-hole, and then planarized to obtain the silicon through-hole structure.

11. The preparation method according to any one of claims 8-10, characterized in that, It also includes at least one of the following features: The minimum distance between the inner wall of the isolation ring structure and the outer wall of the through-silicon via structure is greater than or equal to 1 μm; The minimum distance between the outer walls of adjacent isolation ring structures is greater than or equal to 1 μm; The preset distance is 2μm-10μm.

Images