A shielded gate MOSFET device integrated with an ultrabarrer rectifier

Abstract

The present disclosure relates to a shield gate MOSFET device integrated with super barrier rectifier, the device comprising a substrate, an epitaxial layer, a channel region, a source region; and a plurality of trenches passing through the source region, the channel region and extending to the epitaxial layer, the trenches being filled with a dielectric layer and provided with a shield gate; the MOSFET device has a first region and a second region, wherein the dielectric layer of the first region is provided with a gate electrode, and the dielectric layer of the second region is provided with a source electrode; the dielectric layer between the gate electrode and the sidewall of the trench has a first thickness, and the dielectric layer between the source electrode and the sidewall of the trench has a second thickness, the first thickness being greater than the second thickness. The above-mentioned MOSFET device integrates a super barrier rectifier on the basis of a shield gate field effect transistor, has a lower reverse recovery current when the device is reversely conducted, and has a smaller capacitance characteristic.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular, to a shielded gate MOSFET device with an integrated super barrier rectifier. Background Technology

[0002] Shielded Gate Trench (SGT) transistors, due to their low gate-drain capacitance Cgd, very low on-resistance, and high voltage withstand capability, are beneficial for the flexible application of semiconductor integrated circuits.

[0003] A super barrier rectifier (SBR) is a rectifier device formed by integrating a rectifier diode and a MOS transistor connected in parallel between the anode and cathode. It has a small forward conduction voltage and a relatively stable temperature performance, as well as a small leakage current and a large reverse breakdown voltage, and is therefore being used more and more widely.

[0004] Existing technologies still require a MOSFET device, and there are requirements for the reverse recovery current characteristics and capacitance characteristics of the device during reverse conduction. Summary of the Invention

[0005] A brief overview of this disclosure is given below to provide a basic understanding of certain aspects thereof. However, it should be understood that this overview is not an exhaustive summary of this disclosure, nor is it intended to identify key or essential parts of this disclosure, nor is it intended to limit the scope of this disclosure. The purpose of this overview is merely to present some inventive concepts of this disclosure in a simplified form as a prelude to the more detailed description that follows.

[0006] This disclosure aims to provide a device that integrates a super-barrier rectifier and a metal-oxide-semiconductor field-effect transistor, and to enable the device to have a low reverse recovery current and the smallest possible capacitance characteristics during reverse conduction.

[0007] According to one aspect of this disclosure, a shielded gate MOSFET device with an integrated super-barrier rectifier is provided, the device specifically comprising: Substrate; An epitaxial layer is disposed on one side of the substrate; The channel region is located on the side of the epitaxial layer away from the substrate; The source region is located on the side of the channel region away from the substrate; Multiple trenches pass through the source region and the channel region and extend to the epitaxial layer. The trenches are filled with a dielectric layer and a shielded gate is provided. The shielded gate MOSFET device with integrated super-barrier rectifier has a first region and a second region, wherein, A gate electrode is disposed in the dielectric layer of the first region, and a source electrode is disposed in the dielectric layer of the second region; The dielectric layer includes an insulating dielectric layer disposed on the side of the gate electrode and source electrode away from the substrate; An angled section is provided at the bottom of the source electrode and adjacent to the dielectric layer; The channel region in the first region has a first depth; the channel region in the second region, and the channel region between the first region and the second region, have a second depth, the second depth being greater than the first depth; The depth of the bottom surface of the source electrode is greater than or equal to the depth of the bottom surface of the gate electrode.

[0008] The above-described scheme integrates a super-barrier rectifier into the shielded gate field-effect transistor, enabling it to exhibit lower reverse recovery current during reverse conduction. It also features smaller capacitance. Furthermore, because the bottom of the source electrode is angled relative to the dielectric layer, the thickness of the thin gate oxide layer in the dielectric layer increases gradually at the bottom, rather than abruptly as in existing technologies. This avoids the risk of electric field concentration at the bottom corners and subsequent oxide layer breakdown.

[0009] Meanwhile, given that the thin gate oxide layer is relatively thin in the second region, the above solution specifically sets the channel region in the second region to be deeper to prevent the bottom from being penetrated.

[0010] Optionally, the shielding gate includes an SGT shielding gate disposed within a trench in the first region; The gate electrode is located on the side of the SGT shielded gate that is away from the substrate.

[0011] Optionally, the dielectric layer includes an SGT interlayer oxide layer disposed between the gate electrode and the SGT shielding gate.

[0012] Optionally, the dielectric layer includes an SGT field oxide layer filling the trench bottom and the SGT shielding gate in the first region, and filling the trench sidewall and the SGT shielding gate.

[0013] Optionally, the shielding gate includes an SBR shielding gate disposed within a trench in the second region; The source electrode is located on the side of the SBR shield gate that is away from the substrate.

[0014] Optionally, the dielectric layer includes an SBR interlayer oxide layer disposed between the source electrode and the SBR shielding gate. The SBR interlayer oxide layer can be formed simultaneously with the SGT interlayer oxide layer in the first region during the manufacturing process, which is more convenient in terms of process.

[0015] Optionally, the dielectric layer within the trench in the second region includes a dielectric layer around the source electrode and an SBR field oxide layer filling the area around the SBR shielding gate. The thickness of the SBR field oxygen layer is greater than the thickness of the dielectric layer surrounding the source electrode.

[0016] Optionally, the bottom surface of the source electrode is closer to the substrate than the bottom surface of the gate electrode.

[0017] Optionally, the dielectric layer between the gate electrode and the trench sidewall has a first thickness, and the dielectric layer between the source electrode and the trench sidewall has a second thickness, wherein the first thickness is greater than the second thickness.

[0018] Optionally, the shielding gate, gate electrode, and source electrode are made of conductive polysilicon; the epitaxial layer and source region have heavily doped donor impurities.

[0019] The technical solution disclosed herein integrates a super-barrier rectifier on the basis of a shielded gate field-effect transistor, which can have a low reverse recovery current, at least when the device is reverse-biased. It also has smaller capacitance characteristics. Furthermore, it ensures that the BV of the second region is higher than that of the first region, thereby ensuring that the breakdown point of the device occurs in the effective region, i.e., the SGT region, and preventing the electric field from concentrating at the bottom corner of the source electrode to the point that the oxide layer is broken down. Attached Figure Description

[0020] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the following description, serve to explain the principles of the disclosure. In the drawings: Figure 1 A schematic cross-sectional view of a shielded gate MOSFET device with an integrated super-barrier rectifier according to a first embodiment of the present disclosure is shown. Figure 2 A partial schematic diagram of the trench location of the shielded gate field-effect transistor portion in a shielded gate MOSFET device with an integrated super-barrier rectifier according to a first embodiment of the present disclosure is shown. Figure 3 A partial schematic diagram of the trench location of the super-barrier rectifier portion in a shielded gate MOSFET device with an integrated super-barrier rectifier according to a first embodiment of the present disclosure is shown.

[0021] The annotations in the attached diagram are as follows: 01: Substrate, 02: Epitaxial layer, 03: Channel region, 04: Source region, 05: Trench; 11: Gate electrode, 12: SGT shielded gate, 13: Shallow channel region; 141: SGT insulating dielectric layer, 142: gate electrode peripheral dielectric layer, 143: SGT interlayer oxide layer, 144: SGT field oxide layer; 21: Source electrode, 22: SBR shielded gate, 23: Deep trench region; 211: Oblique angle; 241: SBR insulating dielectric layer, 242: Source electrode peripheral dielectric layer, 243: SBR interlayer oxide layer, 244: SBR field oxide layer. Detailed Implementation

[0022] In this specification, it will also be understood that when a component (or area, layer, section, etc.) is referred to relative to other elements, such as "on," "connected to," or "coupled to" other elements, the component may be directly disposed on / directly connected to / directly coupled to the component, or there may be an intervening third component. Conversely, when an element (or area, layer, section, etc.) is referred to relative to other elements in this specification, such as "directly" on, "directly connected to," or "directly coupled to" other elements, there is no intervening component between them.

[0023] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same elements throughout the drawings. Furthermore, in the drawings, the thickness, proportions, and dimensions of components are enlarged for clarity.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the terms “a,” “an,” “the,” and “at least one” as used herein are not intended to limit the quantity but are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0025] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one component from others. For example, a first element referred to as a first element in one embodiment may be referred to as a second element in other embodiments without departing from the scope of the appended claims.

[0026] Furthermore, terms such as "below," "below," "above," and "upper" are used to describe the relationships between the components shown in the diagram. These terms can be relative concepts and are described based on the directions presented in the diagram.

[0027] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. Terms defined in commonly used dictionaries shall be interpreted as having the same meaning as in the relevant technical context, and shall not be interpreted as having a formal meaning in an idealized or overly formal sense unless expressly specified in the specification.

[0028] The meaning of “includes” or “contains” is to specify a nature, quantity, step, operation, element, component, or combination thereof, but does not exclude other natures, quantities, steps, operations, elements, components, or combinations thereof.

[0029] This document describes embodiments with reference to cross-sectional views of schematic diagrams as idealized implementations. Thus, variations in shape relative to the illustrations are anticipated as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but should include deviations in shape due to, for example, manufacturing processes. For example, regions shown or described as flat may typically have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show precise shapes of the regions and are not intended to limit the scope of the claims.

[0030] In the following description, exemplary embodiments according to this disclosure will be described with reference to the accompanying drawings.

[0031] This disclosure presents a shielded gate (SGT) MOSFET device with an integrated super-barrier rectifier. The aim is to enable the device to have a lower reverse recovery current during reverse conduction and to exhibit smaller capacitance characteristics.

[0032] Figure 1 A cross-sectional schematic diagram of a shielded gate MOSFET device with an integrated super barrier rectifier (SBR) according to an embodiment of the present disclosure is shown. From the area indicated by the dashed box in the figure, it can be understood that the embodiment of the present disclosure includes a first region functioning as an SGT MOSFET and a second region functioning as a super barrier rectifier (SBR). That is, the SGT MOSFET and the SBR are integrated.

[0033] Those skilled in the art will recognize that the SGT MOSFET and SBR integrated in the shielded gate MOSFET device with integrated super barrier rectifier of the present disclosure are not limited to Figure 1 The form shown is not limited to Figure 1 The relative positions and proportions of the first and second regions, the number of trenches and electrodes contained in each region, and the arrangement of the dielectric layer, etc.

[0034] like Figure 1 As shown, the shielded gate MOSFET device with integrated super-barrier rectifier according to embodiments of this disclosure may include: Substrate 01, and epitaxial layer 02, channel region 03, and source region 04 stacked sequentially upwards from substrate 01.

[0035] According to embodiments of the present disclosure, the substrate 01 may be composed of a heavily doped or lightly doped semiconductor material. According to embodiments of the present disclosure, the substrate 01 may be doped with donor impurities or acceptor impurities.

[0036] Specifically, substrate 01 may include, but is not limited to, silicon substrate, gallium nitride substrate, silicon carbide substrate, diamond substrate, gallium oxide substrate, or germanium silicon substrate.

[0037] Furthermore, those skilled in the art will recognize that, in this document, the term "heavily doped region" generally refers to a doping concentration greater than or equal to 10. 18 cm -3 The region is indicated by the symbol "+". Furthermore, in this document, the term "lightly doped region" refers to a doping concentration of less than 10-1. 18 cm -3 The region is indicated by the symbol "-". For example, "n+" indicates a doping concentration greater than or equal to 10. 18 cm -3 The donor impurity heavily doped region, "n-" indicates a doping concentration of less than 10. 18 cm -3 The donor impurity lightly doped region.

[0038] According to an embodiment of this disclosure, a channel region 03 is disposed on the side of the epitaxial layer 02 facing away from the substrate 01; a source region 04 is disposed on the side of the channel region 03 facing away from the substrate 01, so as to... Figure 1 As shown in the orientation reference, source region 04 should be located on the topmost or outermost layer of the device.

[0039] In one embodiment, such as Figure 1 As shown, the depth of channel region 03 varies. As illustrated, the depth of the channel region in the first region is less than the depth of the channel region in the second region.

[0040] like Figure 1 As shown, the shielded gate MOSFET device with integrated super-barrier rectifier according to this disclosure includes trenches 05, which are multiple and located in the longitudinal direction (with...). Figure 1 (Based on the direction shown in the figure) it passes through the source region 04, the channel region 03 and extends into the epitaxial layer 02. The trench 05 is filled with a dielectric layer and the inside of the dielectric layer is covered with a shielding gate.

[0041] In a typical embodiment, such as Figure 2 As shown, the shielding gate includes an SGT shielding gate 12 disposed within a trench in the first region, and as shown in the figure. Figure 3 The SBR shielding gate 22 shown is disposed in the trench of the second region.

[0042] According to embodiments of the present disclosure, the epitaxial layer 02 may be an n-type epitaxial layer disposed on the substrate 01 by, for example, an epitaxial process, i.e., a layer doped with donor impurities. Furthermore, the epitaxial layer 02 may be an n+ type epitaxial layer.

[0043] According to embodiments of this disclosure, the epitaxial layer 02 can be one layer or multiple layers. For example, it can have a first epitaxial layer and a second epitaxial layer, and the doping concentration of the first epitaxial layer can be higher than the doping concentration of the second epitaxial layer.

[0044] According to embodiments of this disclosure, the doping concentration of substrate 01 is higher than that of epitaxial layer 02. In embodiments with two epitaxial layers, the doping concentration of substrate 01 is higher than that of the first epitaxial layer and the second epitaxial layer.

[0045] According to embodiments of the present disclosure, the channel region 03 may be a P-type doped region formed on the epitaxial layer 02 by, for example, a deposition process, i.e., a layer doped with acceptor impurities.

[0046] According to embodiments of the present disclosure, the source region 04 may be an n+ heavily doped region formed on the channel region 03 by, for example, a deposition process, i.e., a layer heavily doped with donor impurities.

[0047] According to embodiments of this disclosure, the trench 05 can be formed, for example, by photolithography, to sequentially penetrate the source region 04, the channel region 03, and extend into the epitaxial layer 02 in the longitudinal direction. Figure 1 , Figure 2 or Figure 3 As shown, according to an embodiment of this disclosure, the bottom of the trench 05 is formed with rounded corners to reduce physical damage and defects to the contents. In other words, the trench 05 can be a U-shaped trench.

[0048] According to embodiments of this disclosure, a dielectric layer can be filled in trench 05 by, for example, a deposition process.

[0049] According to embodiments of this disclosure, the dielectric layer is filled in different forms and thicknesses in a first region that functions as an SGT MOSFET and a second region that functions as a super barrier rectifier (SBR).

[0050] According to embodiments of this disclosure, the dielectric layer can be further refined into: a field oxide layer, an interlayer oxide layer, a gate oxide layer, etc.; each of the above layers can be formed from different materials. Furthermore, according to embodiments of this disclosure, since the dielectric layer needs to withstand a certain degree of high voltage during the operation of the MOSFET device, it needs to be a thin film with good density, such as an insulating film of silicon oxide or silicon nitride formed by, for example, chemical vapor deposition (CVD) process.

[0051] According to embodiments of the present disclosure, a shielding gate can be formed in the dielectric layer by, for example, a deposition process. According to embodiments of the present disclosure, the shielding gate can be formed of polycrystalline silicon or amorphous silicon.

[0052] The shielded gate MOSFET device with integrated super-barrier rectifier disclosed herein has a first region and a second region to integrate an SGT MOSFET and an SBR. A gate electrode 11 is disposed in the dielectric layer of the first region, and a source electrode 21 is disposed in the dielectric layer of the second region. The dielectric layer between the gate electrode and the trench sidewall has a first thickness, and the dielectric layer between the source electrode and the trench sidewall has a second thickness, wherein the first thickness is greater than the second thickness. In other words, the dielectric layer of the first region includes a thick gate oxide layer around the gate electrode, and the dielectric layer of the second region includes a thin gate oxide layer around the source electrode. According to embodiments of this disclosure, each of the source electrode and the gate electrode can be formed of polycrystalline silicon or amorphous silicon.

[0053] like Figure 3 As shown, the bottom of the source electrode 21, adjacent to the dielectric layer, has an angled corner 211, meaning that the thin gate oxide layer gradually thickens towards the substrate, while the source electrode 21 gradually shrinks towards the substrate. In other words, the thickness of the thin gate oxide layer increases gradually at the bottom, rather than abruptly, otherwise the electric field would concentrate at the bottom corner, making the oxide layer prone to breakdown, thus preventing breakdown.

[0054] although Figure 1 Not shown in the text, but according to embodiments of the present disclosure, the shielded gate MOSFET device with integrated super-barrier rectifier may further include an insulating layer formed, for example, on the upper surfaces of the source region 04 and the trench 05 by a deposition process, and a metal layer formed, for example, on the upper surface of the insulating layer by a sputtering process. According to embodiments of the present disclosure, metal patterns electrically connected to the source electrode, the gate electrode, the shielded gate, and the source region 04 may be formed in the metal layer to serve as the control gate electrode, the shielded gate, and the source electrode, respectively.

[0055] Furthermore, despite Figure 1 Not shown in the text, but according to embodiments of the present disclosure, the shielded gate MOSFET device with integrated super-barrier rectifier may further include a metal layer formed on the lower surface of substrate 01 by, for example, a sputtering process. According to embodiments of the present disclosure, a metal pattern electrically connected to substrate 01 may be formed in the metal layer to serve as a drain electrode.

[0056] According to embodiments of this disclosure, the metal layer may include at least one of tungsten (W), platinum (Pt), platinum nitride (PtNi), titanium (Ti), and titanium nitride (TiN).

[0057] According to embodiments of this disclosure, such as Figure 2 As shown, the trench 05 in the first region of the shielded gate MOSFET device with integrated super barrier rectifier of this disclosure also includes a gate electrode 11. According to an embodiment of this disclosure, the gate electrode 11 is disposed on the side of the SGT shielded gate 12 facing away from the substrate 01.

[0058] According to embodiments of this disclosure, such as Figure 2 As shown, the dielectric layer of the first region may specifically include an SGT interlayer oxide layer 143 disposed between the gate electrode 11 and the SGT shielding gate 12.

[0059] According to embodiments of this disclosure, such as Figure 2 As shown, the dielectric layer in the first region may specifically include a dielectric layer 142 around the gate electrode and an SGT insulating dielectric layer 141 on top of the gate electrode 11.

[0060] According to embodiments of this disclosure, such as Figure 2 As shown, the dielectric layer in the first region may specifically include an SGT field oxide layer 144 disposed around the SGT shielding gate 12.

[0061] According to embodiments of this disclosure, such as Figure 3 As shown, the trench 05 in the second region of the shielded gate MOSFET device with integrated super barrier rectifier of this disclosure also includes an active electrode 21. According to an embodiment of this disclosure, the source electrode 21 is disposed on the side of the SBR shielded gate 22 facing away from the substrate 01.

[0062] According to embodiments of this disclosure, such as Figure 3 As shown, the dielectric layer of the second region may specifically include an SBR interlayer oxide layer 243 disposed between the source electrode 21 and the SBR shielding gate 22.

[0063] According to embodiments of this disclosure, such as Figure 3As shown, the dielectric layer in the second region may specifically include a dielectric layer 242 around the source electrode and an SBR insulating dielectric layer 241 on top of the source electrode 21.

[0064] Both the SGT insulating dielectric layer 141 and the SBR insulating dielectric layer 241 are used to isolate the outside world from the electrodes. When laying metal wires on top (not shown in the figure), some areas will have holes punched in the first area layer 141 to connect to the lower electrode, and some areas will have holes punched in the second area layer 241 to connect to the lower electrode.

[0065] According to embodiments of this disclosure, such as Figure 3 As shown, the dielectric layer of the second region may specifically include an SBR field oxide layer 244 disposed around the SBR shielding gate 22.

[0066] According to embodiments of this disclosure, such as Figure 3 As shown, the dielectric layer within the trench in the second region has a bottom dielectric layer (in Figure 3 The illustrated embodiment is an SBR field oxygen layer 244 and a top dielectric layer (in Figure 3 In the illustrated embodiment, a source electrode peripheral dielectric layer 242 is provided, a top dielectric layer is disposed around the source electrode and has the second thickness; a bottom dielectric layer is filled around and at the bottom of the shielding gate and has a third thickness, the second thickness being less than the third thickness.

[0067] In the above embodiment, the thick dielectric layer at the bottom of the trench can reduce the electric field and impact ionization, thereby increasing the reverse breakdown voltage (BV). On the other hand, the thick dielectric layer at the bottom of the trench can act as a field plate, providing a good charge balance between the thick dielectric layer and the epitaxial layer O2. This enables the forward on-resistance (RDS) to be achieved. ON A good trade-off between ) and BV.

[0068] In the above embodiments, the thinner dielectric layer on the top of the trench enables the SBR formed therefrom to have a lower turn-on voltage, thereby enabling it to conduct when the device is off.

[0069] In the above embodiments, the device has a lower reverse recovery current during reverse conduction and also has smaller capacitance characteristics.

[0070] According to embodiments of this disclosure, reference is made to Figure 2 and Figure 3 The channel region in the first region has a first depth, and the channel region in the second region has a second depth, which is greater than the first depth. Specifically, the first region has a shallow channel region 13 and a deep channel region 23.

[0071] like Figure 1As shown, in a typical embodiment, the channel region 03 between the trenches 05 in the first region has a first depth, namely, the shallow channel region 13. The channel region 03 between the trenches 05 in the second region, and the channel region 03 between the trench 05 in the first region and the adjacent trench 05 in the second region, have a second depth, namely, a deep channel region 23, which is greater than the first depth. Because the thin gate oxide layer in the second region is very thin, the well region (channel region) needs to be deeper to protect the bottom from being broken down.

[0072] In one embodiment, the upper and lower electrodes (source electrode 21 and SBR shielding gate 22) in the second region are short-circuited; and the SBR interlayer oxide layer 243 between them and the SGT interlayer oxide layer 143 in the first region are generated synchronously during the manufacturing process, which can simplify the manufacturing process.

[0073] According to embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the bottom surface of the source electrode 21 is closer to the substrate 01 than the bottom surface of the gate electrode 11. In other words, there is a depth difference between the bottom surfaces of the source electrode 21 and the gate electrode 11, with the depth of the bottom surface of the source electrode 21 being greater than or equal to the depth of the bottom surface of the gate electrode 11. This ensures that the BV of the second region is higher than that of the first region, thereby ensuring that the breakdown point of the device occurs in the effective region, i.e., the first (SGT) region.

[0074] According to embodiments of this disclosure, such as Figure 3 As shown, the boundary between the dielectric layer around the source electrode 21 and the dielectric layer around the SBR shield gate 22 has a conical / tilted surface for transition, which is used to achieve a gradual increase in the bottom thickness of the thin gate oxide layer, rather than an abrupt increase. Otherwise, the electric field would be concentrated at the bottom corner, and the oxide layer would be easily broken down, thus preventing it from being broken down.

[0075] According to embodiments of this disclosure, the shielding gate, gate electrode, and source electrode described above are conductive polycrystalline silicon.

[0076] According to embodiments of this disclosure, both the epitaxial layer 02 and the source region 04 have heavily doped donor impurities, i.e., they are of the n+ conductivity type.

[0077] According to embodiments of this disclosure, in the vertical direction, the size of the SGT shielding gate 12 can be larger than the size of the gate electrode 11.

[0078] Those skilled in the art will recognize that although the semiconductor manufacturing processes used to form MOSFET devices and their components, such as photolithography, epitaxy, deposition, implantation, sputtering, etc., have been illustrated above, this disclosure is not limited thereto. Those skilled in the art, based on the teachings of this disclosure, can use other semiconductor processes to obtain the same structure as the MOSFET devices described herein, and all such variations should be covered within the scope of this disclosure.

[0079] Although this disclosure has been described with reference to exemplary embodiments thereof, those skilled in the art will understand that various modifications and variations may be made without departing from the spirit and scope of this disclosure as set forth in the claims.

Claims

1. A shielded gate MOSFET device with an integrated super-barrier rectifier, characterized in that, include: Substrate (01); An epitaxial layer (02) is disposed on one side of the substrate (01); The channel region (03) is disposed on the side of the epitaxial layer (02) facing away from the substrate (01); The source region (04) is disposed on the side of the channel region (03) facing away from the substrate (01); Multiple trenches (05) pass through the source region (04), the channel region (05) and extend to the epitaxial layer (02), the trenches (05) are filled with a dielectric layer and are provided with a shielding gate; The shielded gate MOSFET device with integrated super-barrier rectifier has a first region and a second region, wherein... A gate electrode (11) is disposed in the dielectric layer of the first region, and an active electrode (21) is disposed in the dielectric layer of the second region. The dielectric layer includes an insulating dielectric layer disposed on the side of the gate electrode (11) and the source electrode (21) away from the substrate (01); The bottom of the source electrode (21) is provided with an angle (211) adjacent to the dielectric layer. The channel region (03) in the first region has a first depth; the channel region (03) in the second region, and the channel region (03) between the first region and the second region have a second depth, the second depth being greater than the first depth; The depth of the bottom surface of the source electrode (21) is greater than or equal to the depth of the bottom surface of the gate electrode (11).

2. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 1, characterized in that, The shielding gate includes an SGT shielding gate (12) disposed within the trench (05) of the first region. The gate electrode (11) is disposed on the side of the SGT shield gate (12) away from the substrate (01).

3. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 2, characterized in that, The dielectric layer includes an SGT interlayer oxide layer (143) disposed between the gate electrode (11) and the SGT shielding gate (12).

4. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 2, characterized in that, The dielectric layer, including the first region, is an SGT field oxide layer (144) filled between the bottom of the trench (05) and the SGT shielding gate (12), and filled between the sidewall of the trench (05) and the SGT shielding gate (12).

5. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 1, characterized in that, The shielding gate includes an SBR shielding gate (22) disposed within the trench (05) of the second region; The source electrode (21) is disposed on the side of the SBR shield gate (22) away from the substrate (01).

6. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 5, characterized in that, The dielectric layer includes an SBR interlayer oxide layer (243) disposed between the source electrode (21) and the SBR shielding gate (22).

7. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 5, characterized in that, The dielectric layer in the trench of the second region includes a source electrode peripheral dielectric layer (242) and an SBR field oxide layer (244) filled around the SBR shield gate (22). The thickness of the SBR field oxygen layer (244) is greater than the thickness of the source electrode peripheral dielectric layer (242).

8. The shielded gate MOSFET device with an integrated super-barrier rectifier according to claim 1, 2, or 5, characterized in that, The bottom surface of the source electrode (21) is closer to the substrate (01) than the bottom surface of the gate electrode (11).

9. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 1, characterized in that, The dielectric layer between the gate electrode (11) and the sidewall of the trench (05) has a first thickness, and the dielectric layer between the source electrode (21) and the sidewall of the trench (05) has a second thickness, wherein the first thickness is greater than the second thickness.

10. The shielded gate MOSFET device with integrated super-barrier rectifier according to claim 1, characterized in that, The shielding gate, gate electrode, and source electrode are made of conductive polycrystalline silicon; the epitaxial layer (02) and the source region (04) have heavily doped donor impurities.

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