Delay-locked loop circuit

Abstract

This invention provides a delay-locked loop circuit, comprising a receiver, a delay line circuit, a clock signal generator, and a phase detection circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal based on the clock signal and the reference voltage. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal using a delay indication signal. The clock signal generator generates an output clock signal based on the delayed clock signal. The phase detection circuit generates a detection result by sampling the reference clock signal using a feedback clock signal generated from the output clock signal, and generates a delay indication signal based on the value of the detection result.

Description

Technical Field

[0001] The present invention generally relates to a delayed locking loop circuit, and more specifically, to a delayed locking loop circuit that can avoid delayed transitions and locking failure events. Background Technology

[0002] In conventional techniques, delay-locked loop (LLL) circuits use an analog amplifier to detect the phase difference between a reference clock signal and a feedback clock signal. The amplifier constantly generates phase detection errors due to layout mismatch, component asymmetry, and many other reasons. Furthermore, due to the amplifier's sensitivity, phase detection operation is unstable, and delay jumps and unlocking events frequently occur. Thus, the efficiency of the LLL circuit is reduced. Summary of the Invention

[0003] This invention provides a delay-locked loop circuit that can efficiently lock the phase of a reference clock signal.

[0004] The delay-locked loop circuit includes a receiver, a delay line circuit, a clock signal generator, and a phase detection circuit. The receiver receives a clock signal and a reference voltage and generates a reference clock signal based on these. The delay line circuit is coupled to the receiver and generates a delayed clock signal by delaying the reference clock signal using a delay indication signal. The clock signal generator is coupled to the delay line circuit and generates an output clock signal based on the delayed clock signal. The phase detection circuit is coupled to the receiver and the clock signal generator, samples the reference clock signal using a feedback clock signal generated from the output clock signal to produce a detection result, and generates a delay indication signal based on the value of the detection result.

[0005] In general, the delay-locked loop circuit presented in this disclosure provides a phase detection circuit to sample a reference clock signal using a feedback clock signal to obtain a detection result. The phase detection circuit further generates a delay indication signal based on the value of the detection result, and this delay indication signal can be used to indicate the locked state of the delay-locked loop circuit. Thus, the delay amount of the delay line circuit can be efficiently adjusted according to the delay indication signal, the delay-locked loop circuit can be well locked, and delay jumps can be avoided.

[0006] To make the foregoing more understandable, several embodiments are described in detail below with accompanying drawings. Attached Figure Description

[0007] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the implementation methods, serve to explain the principles of this disclosure.

[0008] Figure 1 A schematic diagram of a delay-locked loop circuit according to an embodiment of the present disclosure is shown;

[0009] Figure 2 Showing according to Figure 1 A circuit diagram of the phase detection circuit of the delay-locked loop circuit in an embodiment;

[0010] Figure 3A and Figure 3B A waveform diagram of a phase detection circuit according to an embodiment of the present disclosure is shown;

[0011] Figure 4A and Figure 4B A waveform diagram of a phase detection circuit according to another embodiment of the present disclosure is shown;

[0012] Figure 5 A circuit diagram of a phase detection circuit for a delay-locked loop circuit according to another embodiment of the present disclosure is shown;

[0013] Figure 6 A circuit diagram of a phase detection circuit for a delay-locked loop circuit according to another embodiment of the present disclosure is shown;

[0014] Figure 7 A schematic diagram of a clock signal generator according to an embodiment of the present disclosure is shown;

[0015] Figure 8 A schematic diagram of a trigger according to an embodiment of the present disclosure is shown.

[0016] Explanation of icon numbers

[0017] 100: Delay-locked loop circuit;

[0018] 110: Receiver;

[0019] 120: Delay line circuit;

[0020] 130, 700: Clock signal generator;

[0021] 140: External driver;

[0022] 150, 500, 600: Phase detection circuit;

[0023] 510, 520, 610, 620: Logic circuits;

[0024] 530, 630: Shift register circuits;

[0025] 710: Clock Tree;

[0026] 800, DFF1, DFF2, DFF3, DFF51, DFF52, DFF53, DFF54, DFF61, DFF62, DFF63, DFF64: triggers;

[0027] AMP1: Amplifier;

[0028] AN1, AN2, AN3, AN4, AN5, AN6: AND gates;

[0029] CK: Clock input;

[0030] CLK: Clock signal;

[0031] CTL1, CTL2: Control signals;

[0032] D: Data terminal;

[0033] DCLK: Delayed clock signal;

[0034] DIS, HIS: Delay indication signals;

[0035] FCLK: Feedback clock signal;

[0036] IV1, IV2, IV3, IV4: Inverters;

[0037] OCLK: Output clock signal;

[0038] OR1, OR2: OR gates;

[0039] Q: Output terminal;

[0040] QA1: First;

[0041] QA1B, QA2B, QA3B: bit;

[0042] QA2: Second position;

[0043] QA3: Third position;

[0044] QB: Inverting output terminal;

[0045] R: Reset terminal;

[0046] RB, Y, Z: signal;

[0047] RCLK: Reference clock signal;

[0048] RST: Reset signal;

[0049] S51, S52, S53, S54, S61, S62, S63, S64: shift bits;

[0050] T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15: Sampling time points;

[0051] TG1: Transmission gate;

[0052] TIV1, TIV2: Tri-state inverters;

[0053] Vref: Reference voltage;

[0054] W: Move away from the lockout sign;

[0055] X: Locking indicator;

[0056] Z1, Z2: Zones. Detailed Implementation

[0057] Reference will now be made in detail to preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and embodiments to refer to the same or similar parts.

[0058] Please refer to Figure 1 This diagram illustrates a delay-locked loop circuit according to an embodiment of the present disclosure. The delay-locked loop circuit 100 includes a receiver 110, a delay line circuit 120, a clock signal generator 130, and a phase detection circuit 150. The receiver 110 receives a clock signal CLK and a reference voltage Vref and generates a reference clock signal RCLK based on the clock signal CLK and the reference voltage Vref. In this embodiment, the receiver 110 may be an amplifier having a positive input and a negative input. The positive input of the receiver 110 receives the clock signal CLK, and the negative input of the receiver 110 receives the reference voltage Vref. The receiver 110 generates the reference clock signal RCLK by comparing the clock signal CLK with the reference voltage Vref. The receiver 110 further provides the reference clock signal RCLK to the delay line circuit 120 and the phase detection circuit 150.

[0059] Delay line circuit 120 is coupled to receiver 110. Delay line circuit 120 receives reference clock signal RCLK from receiver 110 and generates delayed clock signal DCLK by delaying reference clock signal RCLK according to delay indication signal DIS. Delay indication signal DIS may be provided by phase detection circuit 150, and delay line circuit 120 may determine the amount of delay provided for delaying reference clock signal RCLK to generate delayed clock signal DCLK.

[0060] Clock signal generator 130 is coupled to delay line circuit 120. Clock signal generator 130 receives a delayed clock signal DCLK and generates an output clock signal OCLK based on the delayed clock signal DCLK. Clock signal generator 130 can provide the output clock signal OCLK to an off-chip driver (OCD) 140. OCD 140 can be configured to drive an output buffer for output data, and OCD 140 can generate a feedback clock signal FCLK based on the output clock signal OCLK.

[0061] A phase detection circuit 150 is coupled between the receiver 110 and the OCD 140. The phase detection circuit 150 receives a reference clock signal RCLK from the receiver 110 and a feedback clock signal FCLK from the OCD 140. The phase detection circuit 150 generates a detection result by sampling the reference clock signal RCLK with the feedback clock signal FCLK, and generates a delay indication signal DIS based on the value of the detection result.

[0062] In detail, the phase detection circuit 150 can be a logic circuit. The phase detection circuit 150 samples the reference clock signal RCLK using the feedback clock signal FCLK during multiple consecutive sampling time points and records the sampling results to generate a detection result. The phase detection circuit 150 can sample the reference clock signal RCLK using either the positive or negative edge of the feedback clock signal FCLK.

[0063] Please refer to Figure 2 It shows according to Figure 1 A circuit diagram of the phase detection circuit of the delay-locked loop circuit in an embodiment. Figure 2 In this circuit, the phase detection circuit 150 includes multiple flip-flops DFF1 to DFF3. Flip-flops DFF1 to DFF3 are connected in series. Flip-flop DFF1 (the first flip-flop) has a data terminal D for receiving a reference clock signal RCLK, a clock terminal CK for receiving a feedback clock signal FCLK, and an output terminal Q for generating the first bit QA1 of the detection result. Flip-flop DFF2 (the second flip-flop) has a data terminal D coupled to the inverted output QB of flip-flop DFF1, a clock terminal CK for receiving the feedback clock signal FCLK, and an output terminal Q for generating the second bit QA2 of the detection result. Flip-flop DFF3 (the third flip-flop) has a data terminal D coupled to the inverted output of flip-flop DFF2, a clock terminal CK for receiving the feedback clock signal FCLK, and an output terminal Q for generating the third bit QA3 of the detection result.

[0064] Each of flip-flops DFF1 through DFF3 has a reset terminal R for receiving a reset signal RST. In this embodiment, flip-flops DFF1 through DFF3 are reset when the reset signal RST is logic low. When flip-flops DFF1 through DFF3 are reset, the first bit QA1 to the third bit QA3 of the detection result are logic low.

[0065] Flip-flop DFF1 is used to sample the reference clock signal RCLK by the positive edge of the feedback clock signal FCLK. If the first bit QA1 of the detection result is generated according to the first positive edge of the reference clock signal RCLK, the bit QA1B, which is inverted by the first bit QA1, can be shifted to flip-flop DFF2 at the second positive edge of the reference clock signal RCLK and stored in flip-flop DFF2. At this time, the second bit QA2 is equal to the bit QA1B. Furthermore, at the third positive edge of the reference clock signal RCLK, the bit QA2B, which is inverted by the second bit QA2 of the detection result, can be shifted and stored in flip-flop DFF3, and the third bit QA3 of the detection result can be generated. That is, flip-flops DFF2 and DFF3 are configured to form a shift register circuit, and the shift register circuit can record the sampling results generated by flip-flop FF1 using the consecutive positive edges of the feedback clock signal FCLK.

[0066] It should be noted here that bit QA1 can be the least significant bit (LSB) of the value, and bit QA3 can be the most significant bit (MSB) of the value.

[0067] Please refer to this together. Figure 2 , Figure 3A as well as Figure 3B ,in Figure 3A and Figure 3B A waveform diagram of a phase detection circuit according to an embodiment of the present disclosure is shown. Initially, all flip-flops DFF1 to DFF3 are reset according to the reset signal RST. All bits QA1 to QA3 of the detection signal are logic low. Subsequently, refer to... Figure 3A If the phase of the feedback clock signal FCLK lags behind the reference clock signal RCLK, and the first positive edge of the feedback clock signal FCLK falls within a positive pulse (zone Z2), then at the sampling time point T0 corresponding to the first positive edge of the feedback clock signal FCLK, all bits QA1 to QA3 of the detection signal are at logic high. At this time, the value of the detection signal is 7 in decimal.

[0068] At sampling time point T1 immediately following sampling time point T0, if the second positive edge corresponding to sampling time point T1 still falls within region Z2, then bits QA1 to QA3 of the detection signal can be in logic high, logic low, and logic low respectively, and the value of the detection signal in decimal is 1. At sampling time point T2 immediately following sampling time point T1, if the third positive edge corresponding to sampling time point T2 still falls within region Z2, then bits QA1 to QA3 of the detection signal can be in logic high, logic low, and logic high respectively, and the value of the detection signal in decimal is 5. Furthermore, from sampling time point T3 to sampling time point T7 immediately following sampling time point T2, if the positive edges corresponding to sampling time points T3 to T7 still fall within region Z2, then bits QA1 to QA3 of the detection signal can be in logic high, logic low, and logic high respectively, and the value of the detection signal in decimal remains 5.

[0069] In this document, the phase detection circuit 150 can detect that the number of consecutive occurrences equal to a first number (=5) is 6, and the phase detection circuit 150 can compare the number of consecutive occurrences with a first threshold, which in this embodiment may be 5. If the number of consecutive occurrences is greater than the first threshold, then the phase detection circuit 150 can generate a delay indication signal DIS to reduce the delay amount of the delay line circuit.

[0070] In this embodiment, the number of flip-flops in the phase detection circuit 150 can be adjusted by the designer according to actual needs, and is not limited to 3. Furthermore, the first threshold can also be set by the designer, and is not limited to 5.

[0071] After the delay amount of the delay line circuit has been reduced, refer to Figure 3B Furthermore, the positive edge of the feedback clock signal FCLK can fall in region Z1, which corresponds to the logic low of the reference clock signal RCLK. At this time, the logic low of the reference clock signal RCLK can be sampled by the positive edge of the feedback clock signal FCLK, and bits QA1 to QA3 of the detection signal can be in logic low, logic low, and logic high, respectively, and the value of the detection signal at sampling time point T8 remains 4 in decimal. Since bit QA1 of the detection signal is in logic low, the phase detection circuit 150 can adjust the delay indicator signal DIS to increase the delay amount of the delay line circuit. Subsequently, at sampling time point T9, immediately following sampling time point T8, the corresponding positive edge of the feedback clock signal FCLK can fall in region Z2, and all bits QA1 to QA3 of the detection signal can be in logic high, and the value of the detection signal at sampling time point T9 is 7 in decimal.

[0072] During continuous sampling time points T10 to T15, the corresponding positive edge can drift between region Z1 and region Z2, and the value of the detected signal can continuously alternate between the third number (=0) and the fourth number (=7). If the phase detection circuit 150 detects that the value of the detected signal alternates between the third number and the fourth number, then the phase detection circuit 150 can generate a delay indication signal HIS to indicate that the delay lock-in loop circuit is in a locked state.

[0073] The truth table of this embodiment can be seen as follows, where 0 represents logic low and 1 represents logic high:

[0074] Reset 0 0 0 0 T0 1 1 1 7 T1 1 0 0 1 T2 1 0 1 5 T3 1 0 1 5 T4 1 0 1 5 T5 1 0 1 5 T6 1 0 1 5 T7 1 0 1 5 T8 0 0 1 4 T9 1 1 1 7 T10 0 0 0 0 T11 1 1 1 7 T12 0 0 0 0 T13 1 1 1 7 T14 0 0 0 0 T15 1 1 1 7

[0075] Please refer to this together. Figure 2 , Figure 4A as well as Figure 4B ,in Figure 4A and Figure 4B A waveform diagram of a phase detection circuit according to another embodiment of the present disclosure is shown. Initially, all flip-flops FF1 to FF3 are reset according to the reset signal RST. All bits QA1 to QA3 of the detection signal are logic low. Subsequently, refer to... Figure 4A If the phase of the feedback clock signal FCLK leads the reference clock signal RCLK, and the first positive edge of the feedback clock signal FCLK falls within region Z1 corresponding to logic 0 of the reference clock signal RCLK, then at the sampling time point T0 corresponding to the first positive edge of the feedback clock signal FCLK, bits QA1 to QA3 of the detection signal can be at logic low, logic high, and logic high, respectively. At this time, the value of the detection signal is 6 in decimal.

[0076] At sampling time point T1 immediately following sampling time point T0, if the second positive edge corresponding to sampling time T1 still falls within region Z1, then bits QA1 and QA3 of the detection signal can be at logic low, logic high, and logic low respectively, and the value of the detection signal in decimal is 2. Furthermore, from sampling time point T2 to sampling time point T6 immediately following sampling time point T1, if the positive edges corresponding to sampling time points T2 to T6 still fall within region Z1, then bits QA1 to QA3 of the detection signal can be at logic low, logic high, and logic low respectively, and the value of the detection signal in decimal remains 2.

[0077] In this document, the phase detection circuit 150 can detect that the number of consecutive occurrences equal to a first number (=2) is 6, and the phase detection circuit 150 can compare the number of consecutive occurrences with a second threshold, which in this embodiment may be 5. If the number of consecutive occurrences is greater than the second threshold, then the phase detection circuit 150 can generate a delay indication signal DIS to increase the delay amount of the delay line circuit.

[0078] In this embodiment, the second threshold can be set by the designer and is not limited to 5. Furthermore, the second threshold and the first threshold can be the same or different.

[0079] After the delay amount of the delay line circuit has been increased, refer to Figure 4B Furthermore, the positive edge of the feedback clock signal FCLK can fall in region Z2, which corresponds to the logic high of the reference clock signal RCLK. At this time, the logic high of the reference clock signal RCLK can be sampled by the positive edge of the feedback clock signal FCLK, and bits QA1 to QA3 of the detection signal can be at logic high, logic high, and logic low, respectively, and the value of the detection signal at sampling time point T7 remains 3 in decimal. Since bit QA1 of the detection signal is at logic high, the phase detection circuit 150 can adjust the delay indicator signal DIS to reduce the delay of the delay line circuit. Subsequently, at sampling time point T8, immediately following sampling time point T7, the corresponding positive edge of the feedback clock signal FCLK can fall in region Z1, and all bits QA1 to QA3 of the detection signal can be at logic low, and the value of the detection signal at sampling time point T8 is 0 in decimal.

[0080] During the continuous sampling time points T9 to T15, the corresponding positive edge can drift between region Z2 and region Z1, and the value of the detected signal can continuously alternate between the fourth number (=7) and the third number (=0). If the phase detection circuit 150 detects that the value of the detected signal alternates between the third number and the fourth number, then the phase detection circuit 150 can generate a delay indication signal HIS to indicate that the delay lock-in loop circuit is in a locked state.

[0081] The truth table of this embodiment can be seen as follows, where 0 represents logic low and 1 represents logic high:

[0082] Reset 0 0 0 0 T0 0 1 1 6 T1 0 1 0 2 T2 0 1 0 2 T3 0 1 0 2 T4 0 1 0 2 T5 0 1 0 2 T6 0 1 0 2 T7 1 1 0 3 T8 0 0 0 0 T9 1 1 1 7 T10 0 0 0 0 T11 1 1 1 7 T12 0 0 0 0 T13 1 1 1 7 T14 0 0 0 0 T15 1 1 1 7

[0083] Please refer to Figure 5 This shows a circuit diagram of the phase detection circuit of a delay-locked loop circuit according to another embodiment of the present disclosure. Except... Figure 2In addition to flip-flops DFF1 to DFF3, the phase detection circuit 500 further includes logic circuits 510 and 520, and a shift register circuit 530. If the value equals the third number (=0) or the fourth number (=7), then logic circuit 510 performs a logical operation on the value and generates a signal Y. Shift register circuit 530 is coupled to logic circuit 510 and configured to shift the signal Y according to the feedback clock signal FCLK to generate multiple shift bits S51 to S54. Logic circuit 520 is coupled to shift register circuit 530 and performs a logical operation on shift bits S51 to S54 to generate a lock flag X, wherein the lock flag X is used to indicate that the delayed lock loop circuit is in a locked state.

[0084] In detail, the logic circuit 510 includes AND gate AN1, AND gate AN2, and OR gate OR1. AND gate AN1 receives bits QA1 to QA3 of the detection result, and AND gate AN2 receives bits QA1B to QA3B, which are respectively inverted to bits QA1 to QA3. The two inputs of OR gate OR1 are coupled to the outputs of AND gate AN1 and AND gate AN2, respectively, and OR gate OR1 is used to generate signal Y.

[0085] Regarding the operation of logic circuit 510, if the value of the detection result is 7 or 0 in decimal, then one of AND gates AN1 and AN2 can provide a logic high to one input of OR gate OR1. For example, OR gate OR1 can generate the signal Y at logic 1.

[0086] The shift register circuit 530 includes multiple flip-flops DFF51 to DFF54 connected in series. The shift register circuit 530 receives the signal Y from flip-flop DFF51, and flip-flops DFF51 to DFF54 generate shift bits S51 to S54 based on the positive edge of the feedback clock signal FCLK via the shift signal Y. If signal Y remains logic high for four or more clock cycles of the feedback clock signal FCLK, then all shift bits S51 to S54 can be logic high simultaneously.

[0087] Logic circuit 520 includes AND gate AN3. AND gate AN3 receives shift bits S51 to S54 and generates a lock flag X. If all shift bits S51 to S54 are logic high, then logic circuit 520 can generate the lock flag X at the logic high to indicate that the delayed lock loop circuit is in a locked state.

[0088] Please note that in this article, such as Figure 5As illustrated, the number of flip-flops in the shift register circuit 530 can be determined by the designer of the delay-locked loop circuit, and is not limited to 4. By using more flip-flops in the shift register circuit 530, the locking state of the delay-locked loop circuit can be determined with higher accuracy. Of course, the number of inputs to the AND gate AN3 can be adjusted according to the number of flip-flops in the shift register circuit 530.

[0089] Please refer to Figure 6 This shows a circuit diagram of the phase detection circuit of a delay-locked loop circuit according to another embodiment of the present disclosure. Except... Figure 2 and Figure 5 In addition to the components in the circuit, the phase detection circuit 600 further includes logic circuits 610 and 620, and a shift register circuit 630. If the value is equal to a first number (= 5) or a second number (= 2), then logic circuit 610 performs a logical operation on the value and generates a signal Z. Shift register circuit 630 is coupled to logic circuit 610 and configured to shift the signal Z according to the feedback clock signal FCLK to generate a plurality of shift bits S61 to S64. Logic circuit 620 is coupled to shift register circuit 630 and performs a logical operation on shift bits S61 to S64 to generate a lock-away flag W, wherein the lock-away flag W is used to indicate that the delayed lock loop circuit is out of the lock-away state.

[0090] In detail, the logic circuit 610 includes AND gate AN4, AND gate AN5, and OR gate OR2. AND gate AN4 receives bits QA1, QA2B, and QA3 of the detection result, and AND gate AN5 receives bits QA1B, QA2, and QA3B of the detection result. The two inputs of OR gate OR2 are coupled to the outputs of AND gate AN4 and AND gate AN5, respectively, and OR gate OR2 is used to generate signal Z.

[0091] Regarding the operation of logic circuit 610, if the value of the detection result is 5 or 2 in decimal, then one of AND gates AN4 and AN5 can provide a logic high to one input of OR gate OR2. In this way, OR gate OR2 can generate a logic 1 signal Z.

[0092] The shift register circuit 630 includes multiple flip-flops DFF61 to DFF64 connected in series. The shift register circuit 630 receives the signal Z from flip-flop DFF61, and flip-flops DFF61 to DFF64 generate shift bits S61 to S64 based on the positive edge of the feedback clock signal FCLK via the shift signal Z. If signal Z remains logic high for four or more clock cycles of the feedback clock signal FCLK, then all shift bits S61 to S64 can be logic high simultaneously.

[0093] Logic circuit 620 includes AND gate AN6. AND gate AN6 receives shift bits S61 to S64 and generates a remote lockout flag W. If all shift bits S61 to S64 are logic high, then logic circuit 620 can generate a logic high remote lockout flag W to indicate that the delayed lockout loop circuit is out of the lockout state.

[0094] Please note that in this article, such as Figure 6 As illustrated, the number of flip-flops in the shift register circuit 630 can be determined by the designer of the delay-locked loop circuit, and is not limited to 4. By using more flip-flops in the shift register circuit 630, the locking state of the delay-locked loop circuit can be determined with higher accuracy. Of course, the number of inputs to the AND gate AN6 can be adjusted according to the number of flip-flops in the shift register circuit 630.

[0095] Please refer to Figure 7 The diagram illustrates a clock signal generator according to an embodiment of the present disclosure. Figure 1 The clock signal generator 130 can be constructed from the clock signal generator 700. The clock signal generator 700 includes an amplifier AMP1 and a clock tree 710. The amplifier AMP1 draws from a delay line circuit (e.g., Figure 1 The delay line circuit 120 receives the delayed clock signal DCLK. The output of amplifier AMP1 is coupled to clock tree 710. Clock tree 710 can generate an output clock signal OCLK based on the output signal of amplifier AMP1.

[0096] Amplifier AMP1 can be constructed from any amplifier circuit known to those skilled in the art, and clock tree 710 can also be constructed from any clock tree circuit known to those skilled in the art, and there are no particular limitations herein.

[0097] Please refer to Figure 8 This diagram illustrates a trigger according to an embodiment of the present disclosure. Note herein that, by referring to… Figure 2 Each of the flip-flops DFF1 to DFF3 can be a D-type flip-flop with high operating speed, and each of the flip-flops DFF1 to DFF3 can be derived from... Figure 8The flip-flop 800 is constructed as follows. Flip-flop 800 has a clock input CK, a data input D, an output Q, an inverted output QB, and a reset input R. Flip-flop 800 includes inverters IV1 to IV4, a transmission gate TG1, and tri-state inverters TIV1 and TIV2. The input of inverter IV1 is coupled to the clock input CK, and inverters IV1 and IV2 are coupled in series. Inverters IV1 and IV2 generate control signals CTL1 and CTL2, respectively. Transmission gate TG1 is coupled between the data input D and the output Q. Transmission gate TG1 is controlled by control signals CTL1 and CTL2 to be turned on or off. The input of tri-state inverter TIV1 is coupled to the inverted output QB, and the output of tri-state inverter TIV1 is coupled to the output Q. The input of tri-state inverter TIV2 is coupled to the reset input R, and the output of tri-state inverter TIV2 is coupled to the output Q. The input terminal of inverter IV3 is coupled to the output terminal Q, and the output terminal of inverter IV3 is coupled to the inverting output terminal QB.

[0098] The tri-state inverter TIV1 is controlled by control signals CTL1 and CTL2. The tri-state inverter TIV2 is controlled by the signal on the reset terminal R and the signal RB generated by inverter IV4, wherein the signal RB is inverted to the signal on the reset terminal R.

[0099] If transmission gate TG1 is turned on, the signal on data terminal D can be transmitted to output terminal Q. At this time, tri-state inverter TIV1 is turned off, and inverter IV3 generates a signal on inverted output terminal QB through the signal on inverted data terminal D. If transmission gate TG1 is turned off, tri-state inverter TIV1 is turned on accordingly, and tri-state inverter TIV1 and inverter IV3 can form a latch to latch the signal on output terminal Q.

[0100] On the other hand, when the reset signal on the reset terminal R is at logic low, the tri-state inverter TIV2 can be turned on. At this time, the signal on the output terminal Q can be pulled to logic high.

[0101] The hardware structure of the tri-state inverters TIV1 and TIV2 can be constructed using any tri-state inverter well known to those skilled in the art, and there are no specific limitations herein.

[0102] In general, the delay-locked loop circuit of this disclosure provides a phase detection circuit to identify the locked state of the delay-locked loop circuit by sampling a reference clock signal with a feedback clock signal. The phase detection circuit further generates a delay indication signal based on the detection result and can operate the phase-locked loop operation efficiently.

[0103] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations that fall within the scope of the following claims and their equivalents.

Claims

1. A delay-locked loop circuit, comprising: A receiver receives a clock signal and a reference voltage, and generates a reference clock signal based on the clock signal and the reference voltage. A delay line circuit, coupled to the receiver, generates a delayed clock signal by delaying the reference clock signal according to a delay indication signal; A clock signal generator is coupled to the delay line circuit and generates an output clock signal based on the delayed clock signal. A phase detection circuit, coupled to the receiver and the clock signal generator, generates a detection result by sampling the reference clock signal with a feedback clock signal generated by the output clock signal, and generates the delay indication signal based on the value of the detection result. as well as There are M flip-flops, wherein the data terminal of the first flip-flop receives the reference clock signal, the clock terminal of the first flip-flop receives the feedback clock signal, and the inverted output terminal of the Nth flip-flop is coupled to the data terminals of the N+1 first flip-flops, where M is an integer greater than 1 and N is an integer greater than 0 and less than M.

2. The delay-locked loop circuit according to claim 1, wherein each of the M flip-flops comprises: The first inverter receives the reference clock signal and generates a control signal; The second inverter is connected in series with the first inverter and generates an inverting control signal; A transmission gate is coupled between the data terminal and the output terminal of each of the M flip-flops, and the transmission gate is controlled by the control signal and the inverting control signal; A first tri-state inverter has an input terminal coupled to the inverted output terminal of each of the M flip-flops, and an output terminal coupled to the output terminal of each of the M flip-flops, the first tri-state inverter being controlled by the control signal and the inverting control signal; as well as The third inverter has an output terminal coupled to the inverted output terminal of each of the M flip-flops, and an input terminal coupled to the output terminal of each of the M flip-flops.

3. The delay-locked loop circuit according to claim 2, wherein each of the M flip-flops further comprises: The second tri-state inverter has an input terminal coupled to the reset terminal of each of the M flip-flops and an output terminal coupled to the output terminal of each of the M flip-flops, the second tri-state inverter being turned on according to a reset signal on the reset terminal of each of the M flip-flops.

4. The delay-locked loop circuit according to claim 1, wherein when the phase detection circuit detects a number of consecutive times that the value is equal to or greater than a first threshold, the phase detection circuit generates the delay indication signal to reduce the delay amount of the delay line circuit.

5. The delay-locked loop circuit according to claim 4, wherein when the phase detection circuit detects a number of consecutive times that the value is equal to or greater than the second threshold, the phase detection circuit generates the delay indication signal to increase the delay amount of the delay line circuit.

6. The delay-locked loop circuit according to claim 5, wherein the first threshold and the second threshold are the same or different.

7. The delay-locked loop circuit according to claim 5, wherein the delay-locked loop circuit is in a locked state when the phase detection circuit detects the value that continuously alternates between the third number and the fourth number.

8. The delay-locked loop circuit according to claim 7, wherein the phase detection circuit further comprises: A first logic circuit performs a first logic operation on the value and generates a first signal if the value is equal to the third number or the fourth number. A shift register circuit, coupled to the first logic circuit, shifts the first signal according to the feedback clock signal to generate multiple shift bits; as well as A second logic circuit, coupled to the shift register circuit, performs a second logic operation on the shift bit to generate a lock flag, wherein the lock flag is used to indicate that the delayed lock loop circuit is in the locked state.

9. The delay-locked loop circuit according to claim 8, wherein the first logic circuit comprises: A first AND gate receives multiple bits of the detection result and generates a second signal; The second AND gate receives multiple bits of the inverted signal of the detection result and generates a third signal; as well as An OR gate that receives the second signal and the third signal and generates the first signal.

10. The delay-locked loop circuit according to claim 8, wherein the second logic circuit comprises: An AND gate receives the shift bit and generates the lock flag.

11. The delay-locked loop circuit according to claim 8, wherein the number of registers in the shift register circuit is greater than 1.

12. The delay-locked loop circuit according to claim 5, wherein the phase detection circuit further comprises: A first logic circuit performs a first logic operation on the value to determine whether the value is equal to the first number or the second number in order to generate a first signal. A shift register circuit, coupled to the first logic circuit, shifts the first signal according to the feedback clock signal to generate multiple shift bits; as well as A second logic circuit, coupled to the shift register circuit, performs a second logic operation on the shift bit to generate a lock-away flag.

13. The delay-locked loop circuit according to claim 12, wherein the number of registers in the shift register circuit is greater than 1.

14. The delay-locked loop circuit of claim 12, wherein the phase detection circuit generates the delay indication signal based on the distance-from-locking flag.

15. The delay-locked loop circuit according to claim 1, further comprising: An external driver is coupled to the clock signal generator, receives the output clock signal, and provides the feedback clock signal.

16. The delay-locked loop circuit according to claim 1, wherein the clock signal generator comprises: An amplifier that generates a first clock signal based on the delayed clock signal; as well as The clock tree generates the output clock signal based on the first clock signal.

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