Modulator bias locking method and soft-core-based laser communication bias control system

Abstract

The application provides a modulator bias locking method and a laser communication bias control system based on a soft core, and is used for solving the technical problems of low precision, slow bias locking, poor real-time tracking and dynamic adaptability of the existing modulator bias locking method, and the technical problems of high hardware cost, high system power consumption and large volume of the existing optical communication bias control system. The modulator bias locking method comprises the following steps: three perturbation signals with different frequencies are input into a modulator, and the three perturbation signals are frequency-mixed two by two to obtain three difference frequency signals; I / Q two local quadrature reference signal arrays corresponding to the three difference frequency signals are calculated, and inner products of the three difference frequency signals and the I / Q two local quadrature reference signal arrays are calculated, so that corresponding amplitude values are obtained; three direct current voltage values input into the modulator are adjusted according to the amplitude values; and the amplitude values of the three difference frequency signals are all minimum values, so that real-time tracking and adjustment of three bias voltages of the modulator I, Q and P are periodically completed, and the locking speed of the bias point of the modulator is effectively improved.

Description

Technical Field

[0001] This invention belongs to the field of laser communication, specifically relating to a modulator bias locking method and a laser communication bias control system based on a soft core. Background Technology

[0002] Laser communication technology, using lasers as carrier waves, has been widely applied in aerospace, wireless communication, and industrial manufacturing in recent years. In laser communication, optical modulation is mainly divided into internal modulation and external modulation. However, because internal modulation cannot meet the communication rate requirements of modern communication, external modulation is currently the primary method used for laser communication. External modulation is not limited by the output frequency; when the modulator operates at the optimal bias voltage point, it can modulate an ideal optical signal. However, due to factors such as ambient temperature and humidity, input device optical power, and device aging, the modulator bias voltage point can drift, causing a deterioration in the quality of the output optical signal and consequently an increase in the bit error rate.

[0003] Currently, to achieve the best modulation effect, feedback control using an externally applied bias voltage is required to respond in real time to changes in the modulator bias voltage point of the laser communication system. Currently, the main methods for locking the modulator bias voltage are output power detection and perturbation signal detection. However, the output power detection method has low accuracy, while the perturbation signal detection method uses Fast Fourier Transform (FFT) to obtain the amplitude of the perturbation signal for modulator operating point tracking. When using FFT to lock the operating point, the sampling of fixed points increases processing delay, and there are problems such as large computational load, long processing time, and large storage space requirements. This results in slow bias voltage locking and poor real-time tracking and dynamic adaptability. Furthermore, laser communication bias control systems typically use programmable logic devices (PLDs) to implement high-speed data transmission and ARM, DSP, or microcontroller processors to implement the modulator operating point feedback control algorithm. Using PLDs and processors together to control the modulator operating point voltage increases hardware costs, system power consumption, and overall size. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problems of low accuracy, slow bias locking, poor real-time tracking and dynamic adaptability in existing modulator bias locking methods, as well as the technical problems of high hardware cost, large system power consumption and large size in existing laser communication bias control systems. The invention provides a modulator bias locking method and a laser communication bias control system based on a soft core.

[0005] To achieve the above objectives, the technical solution provided by this invention is as follows:

[0006] A modulator bias lock-in method, characterized by comprising the following steps:

[0007] 1. Scan the characteristic curves of the I, Q, and P signals in the modulator sequentially to find the maximum, minimum, and orthogonal points of the characteristic curves of the three signals; then set the operating point voltages of the I, Q, and P signals according to the modulation method.

[0008] 2】The bias control signal processing module generates three perturbation signals fI, fQ, and fP at different frequencies, and loads these three perturbation signals fI, fQ, and fP at different frequencies onto the three DC bias input terminals of the modulator.

[0009] 3】The three perturbation signals fI, fQ, and fP of different frequencies are passed through a modulator and then beat in pairs to obtain three difference frequency signals f1, f2, and f3;

[0010] 4. Based on the set sampling frequencies fs1, fs2, fs3 and the number of sampling points N, calculate the I / Q local quadrature reference signal arrays corresponding to the three difference frequency signals f1, f2, and f3 respectively.

[0011] 5. Acquire three difference frequency signals f1, f2, and f3 to obtain three datasets corresponding to the three difference frequency signals f1, f2, and f3; perform inner product calculations on the data in the three datasets with the I / Q local quadrature reference signal arrays corresponding to the three difference frequency signals f1, f2, and f3 respectively; and calculate the amplitude values ​​of the three difference frequency signals f1, f2, and f3 based on the inner product results of the three difference frequency signals f1, f2, and f3 respectively; wherein, the sampling frequency and number of sampling points of the three difference frequency signals f1, f2, and f3 are the same as the sampling frequency fs1, fs2, fs3 and the number of sampling points N corresponding to the steps in step 4;

[0012] 6. Based on the amplitude values ​​of the three difference frequency signals f1, f2, and f3, adjust the three DC voltage values ​​of the three DC bias input terminals of the input modulator, and return to step 5 for iteration until the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are all at their minimum values, thereby realizing the real-time tracking and adjustment of the three bias voltages I, Q, and P of the modulator.

[0013] Further, in step 4], the I / Q local quadrature reference signal arrays generated by the first difference frequency signal f1 are f1R and f1I, the I / Q local quadrature reference signal arrays generated by the second difference frequency signal f2 are f2R and f2I, and the I / Q local quadrature reference signal arrays generated by the third difference frequency signal f3 are f3R and f3I; f1R, f1I, f2R, f2I, f3R, and f3I are determined by the following formulas:

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020] Where f1′ represents the frequency of the first differential frequency signal f1, f2′ represents the frequency of the second differential frequency signal f2, f3′ represents the frequency of the third differential frequency signal f3, and n takes the values ​​0, 1, 2, ... (N-1).

[0021] Further, in step 5], the data in the three datasets are multiplied by the I / Q local quadrature reference signal arrays corresponding to the three difference frequency signals f1, f2, and f3. Then, based on the results of the multiplication of the three difference frequency signals f1, f2, and f3, the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are calculated. Specifically:

[0022] The data in the dataset corresponding to the first difference frequency signal f1 are multiplied by f1R and f1I respectively to obtain the real part f1_R and the imaginary part f1_I of the first difference frequency signal f1; the data in the dataset corresponding to the second difference frequency signal f2 are multiplied by f2R and f2I respectively to obtain the real part f2_R and the imaginary part f2_I of the second difference frequency signal f2; the data in the dataset corresponding to the third difference frequency signal f3 are multiplied by f3R and f3I respectively to obtain the real part f3_R and the imaginary part f3_I of the third difference frequency signal f3;

[0023] Then, calculate the corresponding amplitude values ​​A1, A2, and A3 of the three difference frequency signals f1, f2, and f3 using the following formulas:

[0024]

[0025]

[0026]

[0027] Furthermore, step 5 also includes:

[0028] Before acquiring the three difference frequency signals f1, f2, and f3, filter the three difference frequency signals f1, f2, and f3 respectively.

[0029] Furthermore, in step 4], the sampling frequencies fs1, fs2, and fs3 are four times the frequencies of the corresponding three difference frequency signals f1, f2, and f3.

[0030] This invention also provides a soft-core-based laser communication bias control system for implementing the aforementioned modulator bias locking method. The soft-core-based laser communication bias control system includes a driving module and a laser, modulator, beam splitter, photodetector, and bias control signal processing module connected sequentially in input and output order. The driving module amplifies the high-speed data stream, and the amplified signal enters the modulator, which modulates the data onto the laser signal emitted by the laser. The beam splitter divides the optical signal output from the modulator into two paths: one path is used for subsequent optical communication, and the other path is converted into an electrical signal by the photodetector and sent to the bias control signal processing module. Its special feature is that:

[0031] The bias control signal processing module includes a programmable amplifier circuit, a fine adjustment circuit, a bandpass filter circuit, an AD conversion module, a programmable logic device, and a DA conversion module connected in sequence according to input and output.

[0032] The input terminal of the programmable amplifier circuit is connected to the output terminal of the photodetector, and is used to amplify the received electrical signal in a programmable manner.

[0033] The fine adjustment circuit is used to finely amplify or attenuate the programmed amplified electrical signal;

[0034] The bandpass filter circuit includes three filter modules with different bandwidths, which are used to filter the finely amplified or attenuated signal through the three filter modules to obtain three difference frequency signals f1, f2, and f3 with different frequencies.

[0035] The AD conversion module is used to acquire three difference frequency signals f1, f2, and f3 of different frequencies respectively and convert the acquired analog signals into digital signals.

[0036] The output of the DA conversion module is connected to the three DC bias inputs of the modulator.

[0037] The programmable logic device is equipped with a soft core. The soft core is used to perform an inner product of the three acquired difference frequency signals f1, f2, and f3 with the corresponding I / Q local quadrature reference signal arrays of the three difference frequency signals f1, f2, and f3, and calculate the amplitude values ​​of the three difference frequency signals f1, f2, and f3 based on the inner product result. Then, the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are used to adjust the three DC voltage values ​​input to the three DC bias input terminals of the modulator by the DA conversion module.

[0038] Furthermore, the programmable amplifier circuit is a two-stage programmable amplifier circuit, implemented using an AD8253 chip;

[0039] The fine-tuning circuit is implemented using an AD5450 chip.

[0040] Furthermore, the AD conversion module includes three AD converters, or the AD converters in the AD conversion module include three conversion channels;

[0041] The DA conversion module includes three DA converters, or the DA converters in the DA conversion module include three conversion channels.

[0042] Furthermore, the programmable logic device is an FPGA;

[0043] The soft core uses microblaze.

[0044] The advantages of this invention compared to the prior art are as follows:

[0045] 1. The modulator bias lockout method provided by this invention sets the corresponding operating point by scanning the modulator characteristic curve, generating three perturbation signals fI, fQ, and fP of different frequencies, and then obtaining three difference frequency signals f1, f2, and f3 by beating each pair of signals; then calculating the I / Q local quadrature reference signal arrays generated by the three difference frequency signals f1, f2, and f3. This method only needs to save three sets of I / Q local quadrature reference signal arrays, i.e., six local quadrature reference signals, into memory for subsequent use, which greatly saves system memory.

[0046] 2. The modulator bias lock-in method provided by this invention involves taking the inner product of the three acquired difference frequency signals f1, f2, and f3 with the corresponding I / Q local quadrature reference signal arrays of the three difference frequency signals f1, f2, and f3, respectively, to obtain the amplitude values ​​of the three difference frequency signals f1, f2, and f3. This method only requires calculating the inner product value of the three difference frequency signals. Compared with the traditional N-point (N is generally 1024, 2048, etc.) FFT, it greatly saves the amount of calculation, effectively improves the locking speed of the modulator bias point, and ensures the real-time performance and dynamic adaptability of bias lock-in tracking.

[0047] 3. The modulator bias locking method provided by this invention, compared to the traditional FFT where the number of sampling points must be fixed at 2, provides a method that... M M = 1, 2, ..., This invention is not limited to a fixed 2 M The number of sampling points can be set arbitrarily as needed, making the selection more flexible.

[0048] 4. The modulator bias locking method provided by this invention greatly saves computational load and occupies less system memory. Therefore, it only requires setting a soft core on the programmable logic device. By using a single programmable logic device and its internal soft core, high-speed data stream processing and modulator operating point control can be achieved without adding an additional separate processor, saving hardware resources, reducing system design complexity, and reducing cost and power consumption.

[0049] 5. To implement the above-mentioned modulator bias locking method, this invention also provides a laser communication bias control system based on a soft core. A soft core is installed on the programmable logic device. The soft core performs inner product calculations on the three acquired difference frequency signals f1, f2, and f3 with the corresponding I / Q local quadrature reference signal arrays for each of the three difference frequency signals f1, f2, and f3. Based on the inner product results, the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are calculated. Then, the amplitude values ​​of the three difference frequency signals are used to adjust the three DC voltage values ​​input to the three DC bias input terminals of the modulator via the DA conversion module. This method significantly reduces the computational load and minimizes system memory usage. Therefore, the laser communication bias control system of this invention only requires a single programmable logic device and its internal soft core to achieve high-speed data stream processing and modulator operating point control without the need for an additional processor, saving hardware resources, reducing system design complexity, and decreasing cost and power consumption.

[0050] 6. The present invention provides a laser communication bias control system based on a soft core, which has high stability and can track the modulator's operating point in real time. Attached Figure Description

[0051] Figure 1 This is a schematic flowchart of a modulator bias locking method according to the present invention;

[0052] Figure 2 This is a schematic diagram of an embodiment of a laser communication bias control system based on a soft core according to the present invention.

[0053] The specific labeling in the attached diagram is as follows:

[0054] 1-Laser; 2-Modulator; 3-Driver module; 4-Beam splitter; 5-Photodetector; 6-Bias control signal processing module; 61-Programmable amplifier circuit; 62-Fine adjustment circuit; 63-Bandpass filter circuit; 64-AD conversion module; 65-Programmable logic device; 66-DA conversion module. Detailed Implementation

[0055] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] A method for fast modulation bias locking, such as Figure 1 As shown, the specific steps are as follows:

[0057] 1】Scan the characteristic curves of the I, Q and P signals of the modulator in sequence to find the maximum point, minimum point and orthogonal point of the characteristic curves of the three signals. In this embodiment, the modulation method of the modulator is QPSK modulation method. Therefore, the operating point voltage of the I and Q signals is set as the minimum point voltage and the operating point voltage of the P signal is set as the orthogonal point voltage.

[0058] 2) In this embodiment, the programmable logic device in the bias control signal processing module is an FPGA. The FPGA outputs three PWM waves of different frequencies based on the operating point voltage set by the I, Q, and P signals. The three PWM waves of different frequencies are filtered by different low-pass filter circuits to generate three perturbation signals fI, fQ, and fP of different frequencies. The duty cycle of the PWM wave is preferably set to 50%.

[0059] Three perturbation signals fI, fQ, and fP are loaded onto the three DC bias input ports corresponding to the I, Q, and P signals of the modulator. In this embodiment, the perturbation signals are sinusoidal signals, and the signal amplitude range is set to tens to hundreds of millivolts.

[0060] 3】The three perturbation signals fI, fQ, and fP of different frequencies are passed through the modulator and then beat in pairs to obtain three difference frequency signals f1, f2, and f3, namely f1 = |fI-fQ|, f2 = abs|fI-fP|, and f3 = abs|fQ-fP|, which are used to reflect the operating point drift of the P-path, Q-path, and I-path, respectively.

[0061] 4. Based on the set sampling frequencies fs1, fs2, fs3 and the number of sampling points N, calculate the corresponding I / Q local quadrature reference signal arrays for each of the three difference frequency signals f1, f2, and f3.

[0062] Wherein, the sampling frequencies fs1, fs2, fs3 and the number of sampling points N are the sampling frequencies and the number of sampling points used to obtain the I / Q two-channel local quadrature reference signal arrays of the three difference frequency signals f1, f2, and f3. In this invention, the sampling frequencies fs1, fs2, fs3 and the number of sampling points N can be selected according to the actual design situation, provided that the Nyquist sampling theorem (greater than twice the signal frequency) is satisfied. Preferably, in this embodiment, the sampling frequencies fs1, fs2, and fs3 are set to four times the corresponding difference frequency signal frequencies. The frequency of the first difference frequency signal f1 is denoted as f1′, the frequency of the second difference frequency signal f2 is denoted as f2′, and the frequency of the third difference frequency signal f3 is denoted as f3′, that is, fs1 = 4f1′, fs2 = 4f2′, fs3 = 4f3′, and the number of sampling points N is 1024.

[0063] Let the local quadrature reference arrays for the I / Q channels generated by the first difference frequency signal f1 be denoted as f1R and f1I, the local quadrature reference arrays generated by the second difference frequency signal f2 be denoted as f2R and f2I, and the local quadrature reference arrays generated by the third difference frequency signal f3 be denoted as f3R and f3I. Then f1R, f1I, f2R, f2I, f3R, and f3I are determined by the following formulas:

[0064]

[0065]

[0066]

[0067]

[0068]

[0069]

[0070] Where n takes the values ​​0, 1, 2, ... (N-1).

[0071] For the first difference frequency signal f1, the local orthogonal reference array with 1024 points selected in this implementation is as follows:

[0072] f1R

[1024] =[1,0,-1,0,1,0,-1,0,1,0,-1,0...],

[0073] f1I

[1024] =[0,-1,0,1,0,-1,0,1,0,-1,0,1...].

[0074] For the difference frequency signal f2, the local orthogonal reference array with 1024 points is selected in this implementation as follows:

[0075] f2R

[1024] =[1,0,-1,0,1,0,-1,0,1,0,-1,0...],

[0076] f2I

[1024] =[0,-1,0,1,0,-1,0,1,0,-1,0,1...].

[0077] For the difference frequency signal f3, the local orthogonal reference array with 1024 points is selected in this implementation as follows:

[0078] f3R

[1024] =[1,0,-1,0,1,0,-1,0,1,0,-1,0...],

[0079] f3I

[1024] =[0,-1,0,1,0,-1,0,1,0,-1,0,1...].

[0080] 5. Acquire three difference frequency signals f1, f2, and f3 using an AD converter and convert them into corresponding digital signals to obtain three datasets corresponding to the three difference frequency signals f1, f2, and f3. Calculate the inner product of the data in each of the three datasets with the corresponding I / Q local quadrature reference signal arrays obtained in step 4 for each of the three difference frequency signals f1, f2, and f3. Then, calculate the amplitude values ​​of the three difference frequency signals f1, f2, and f3 based on the inner product results. The sampling frequencies fs1_AD, fs2_AD, and fs3_AD and the number of sampling points N_AD for the three difference frequency signals f1, fs2, and fs3 are the same as the sampling frequencies fs1, fs2, fs3, and the number of sampling points N when generating the I / Q local quadrature reference signals in step 4.

[0081] For the first differential frequency signal f1, the AD converter collects 1024 data points to form a dataset corresponding to the first differential frequency signal f1. The data in the dataset is stored in buffer_f1

[1024] , and the inner product is performed with f1R and f1I respectively to obtain the real part f1_R and the imaginary part f1_I of the first differential frequency signal f1, that is:

[0082] f1_R=buffer_f1[0]*f1R[0]+buffer_f1[1]*f1R[1]+buffer_f1[2]*f1R[2]+buffer_f1[3]*f1R[3]+……+buffer_f1

[1023] *f1R

[1023] ;

[0083] f1_I=buffer_f1[0]*f1I[0]+buffer_f1[1]*f1I[1]+buffer_f1[2]*f1I[2]+buffer_f1[3]*f1I[3]+……+buffer_f1

[1023] *f1I

[1023] ;

[0084] The amplitude value A1 of the first difference frequency signal f1 is then calculated using the following formula:

[0085]

[0086] For the second difference frequency signal f2, the AD converter collects 1024 data points to form a dataset corresponding to the second difference frequency signal f2. The data in the dataset is stored in buffer_f2

[1024] , and the inner products are taken with f2R and f2I respectively to obtain the real part f2_R and the imaginary part f2_I of the second difference frequency signal f2, that is:

[0087] f2_R=buffer_f2[0]*f2R[0]+buffer_f2[1]*f2R[1]+buffer_f2[2]*f2R[2]+buffer_f2[3]*f2R[3]+……+buffer_f2

[1023] *f2R

[1023] ;

[0088] f2_I=buffer_f2[0]*f2I[0]+buffer_f2[1]*f2I[1]+buffer_f2[2]*f2I[2]+buffer_f2[3]*f2I[3]+……+buffer_f2

[1023] *f2I

[1023] ;

[0089] Then calculate the amplitude value A2 of the second difference frequency signal f2 according to the following formula:

[0090]

[0091] For the third difference frequency signal f3, the AD converter collects 1024 data points to form a dataset corresponding to the third difference frequency signal f3. The data in the dataset is stored in buffer_f3

[1024] , and the inner products are taken with f3R and f3I respectively to obtain the real part f3_R and the imaginary part f3_I of the third difference frequency signal f3, that is:

[0092] f3_R=buffer_f3[0]*f3R[0]+buffer_f3[1]*f3R[1]+buffer_f3[2]*f3R[2]+buffer_f3[3]*f3R[3]+……+buffer_f3

[1023] *f3R

[1023] ;

[0093] f3_I=buffer_f3[0]*f3I[0]+buffer_f3[1]*f3I[1]+buffer_f3[2]*f3I[2]+buffer_f3[3]*f3I[3]+……+buffer_f3

[1023] *f3I

[1023] ;

[0094] Then, calculate the amplitude value A3 of the third difference frequency signal f3 according to the following formula:

[0095]

[0096] In this embodiment, since the sampling frequencies fs1, fs2, fs3, fs1_AD, fs2_AD, and fs3_AD are preferably set to four times the corresponding difference frequency signal frequencies, the control process does not require multiplication operations. It only requires inverting the corresponding positions of the original signals and then summing them, which greatly saves computational resources and improves computational speed. The four-times sampling rate selected in this embodiment is a special value. In other embodiments of the invention, when the sampling frequencies fs1, fs2, fs3, fs1_AD, fs2_AD, and fs3_AD are selected as ordinary multiples, even if multiplication operations are involved, only N multiplication operations corresponding to each of the three difference frequency signals f1, f2, and f3 need to be calculated. Compared to the traditional bias-locked FFT method, this also greatly saves system computational resources and improves computational speed.

[0097] In this embodiment, the number of sampling points N and N_AD are 1024. According to the modulator bias fast locking method of the present invention, the number of sampling points can be arbitrarily selected and is not limited to a fixed number of points.

[0098] Therefore, the four times sampling frequency and 1024 sampling points in this embodiment are only a preferred embodiment of the invention. The sampling frequency and the number of sampling points can also be adjusted appropriately, as long as the above functions can be achieved.

[0099] 6. In this invention, the bias control signal processing module inputs three DC voltage values ​​to the three DC bias input terminals of the modulator via a DA converter. Therefore, based on the amplitude values ​​of the three difference frequency signals f1, f2, and f3 obtained in step 5, the module adjusts the three DC voltage values ​​input to the modulator, i.e., the output values ​​of the DA converter, and returns to step 5 for iteration until the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are all at their minimum values. Once the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are all at their minimum values, the modulator's I, Q, and P bias voltages are tracked and adjusted in real time according to the set timer interval.

[0100] Specifically, taking the first differential frequency signal f1 as an example, based on the amplitude value A1 of the first differential frequency signal f1 obtained in step 4, the output value of the DA converter is increased, and the process returns to step 5 for iteration to obtain an updated amplitude value. The first obtained amplitude value is denoted as A1, and the new amplitude value obtained after the first iteration is denoted as A1_1. A1_1 is compared with A1; if A1_1 ≤ A1, the output value of the DA converter is increased to obtain the new amplitude value A1_2 after the second iteration. A1_1 is compared with A1_2, and so on, until A1_n > A1_(n-1). When the amplitude value is A1_(n-1), the output value of the DA converter is at its optimal value. At this point, A1_(n-1) is the minimum amplitude value, ultimately stabilizing A1_n at the minimum amplitude value. Similarly, the second differential frequency signal f2 and the third differential frequency signal f3 are controlled using the same method until the amplitude values ​​of the three differential frequency signals f1, f2, and f3 are all at their minimum values. The timing interval of the timer is set according to the actual circuit design and system testing. The timing interval must be able to complete one round of adjustment of the I, Q and P signals within one cycle, while ensuring that the cycle interval is not too long to affect the real-time tracking, and at the same time, it must ensure that the entire processing system can handle other processes.

[0101] To implement the above-mentioned modulator bias locking method, this invention also provides a laser communication bias control system based on a soft core, such as... Figure 2 As shown, it includes a drive module 3, a laser 1, a modulator 2, a beam splitter 4, a photodetector 5, and a bias control signal processing module 6.

[0102] The output of the driver module 3 is connected to the RF input of the modulator 2, and the output of the laser 1 is connected to the optical input of the modulator 2. The driver module 3 amplifies the high-speed data stream, and the amplified signal enters the modulator 2, where it modulates the data onto the carrier wave (the laser signal emitted by the laser 1). The optical output of the modulator 2 is connected to the input of the beam splitter 4, which splits the optical signal output by the modulator 2 into two paths. The first output of the beam splitter supplies one of the optical signals to subsequent optical communication, and its second output is connected to the input of the photodetector 5, which converts the other optical signal into an electrical signal and sends it to the bias control signal processing module 6.

[0103] The bias control signal processing module 6 includes a programmable amplifier circuit 61, a fine adjustment circuit 62, a bandpass filter circuit 63, an AD conversion module 64, a programmable logic device, and a DA conversion module 66, which are connected in sequence according to their input and output.

[0104] The input terminal of the programmable amplifier circuit 61 is connected to the output terminal of the photodetector 5, and is used to perform programmable amplification of the received electrical signal, i.e., coarse amplification. In this embodiment, the programmable amplifier circuit 61 is a two-stage programmable amplifier circuit. The fine adjustment circuit 62 is used to finely amplify or attenuate the programmably amplified electrical signal. The bandpass filter circuit 63 includes three filtering modules with different bandwidths, which are used to filter the finely amplified or attenuated signal through the three filtering modules to obtain three difference frequency signals f1, f2, and f3 with different frequencies. In this embodiment, the AD converter in the AD conversion module 64 includes three conversion channels, which are used to acquire the three difference frequency signals f1, f2, and f3 with different frequencies respectively and convert the acquired analog signals into digital signals. In other embodiments of the present invention, the AD conversion module 64 can also be set as three AD converters. The three DC signals output by the DA conversion module 66 are superimposed with the corresponding perturbation signals fI, fQ, and fP respectively, and are connected to the three DC bias input terminals of the modulator 2 through three interfaces respectively. Similarly, in this embodiment, the DA converter in the DA conversion module 66 includes three conversion channels. In other embodiments of the present invention, the DA conversion module 66 can also be configured as three DA converters. Before the AD converter acquires the three difference frequency signals f1, f2, and f3 of different frequencies, the amplitudes of the three difference frequency signals f1, f2, and f3 need to be within the acquisition range of the AD converter. If this is not met, coarse and fine adjustments are made by adjusting the preceding programmable amplifier circuit 61 and fine adjustment circuit 62.

[0105] The programmable logic device has a soft core, which is used to perform an inner product of the three acquired difference frequency signals f1, f2, and f3 with the corresponding I / Q local quadrature reference signal arrays of the three difference frequency signals f1, f2, and f3, and calculate the amplitude values ​​of the three difference frequency signals f1, f2, and f3 based on the inner product result. Then, the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are used to adjust the three DC voltage values ​​input to the three DC bias input terminals of the DA conversion module 66 to the modulator 2.

[0106] In one specific embodiment of the present invention, the devices may employ the following parameters:

[0107] Laser 1 is a narrow-linewidth laser, and the generated laser light serves as the carrier wave. Modulator 2 is an electro-optic modulator, specifically a LiNbO3 modulator with insertion loss <8dB and bandwidth >20G. In this embodiment, QPSK modulation is selected for modulator 2. In other embodiments of the invention, OOK modulation, BPSK modulation, M-PSK, M-QAM, and other higher-order modulation methods or dual-polarization modulation can also be used. Driver module 3 employs a high-bandwidth, high-gain, and low-insertion-loss driver. Beam splitter 4 uses a 90:10 fiber-coupled passive device, with 90% of the output optical signal used for subsequent communication and 10% of the output optical signal entering the photodetector. Photodetector 5 uses a PIN diode. The programmable amplifier circuit 61 uses an AD8253 programmable amplifier chip, supporting four amplification factors: *1, *10, *100, and *1000. The amplification factor is selected based on the measured signal magnitude. Fine adjustment circuit 62 uses a bipolar, precision AD5450 for fine amplification or reduction adjustment.

[0108] In this embodiment, the programmable logic device uses an FPGA, and the soft core employs a microblaze as an on-chip processor to flexibly control peripherals such as AD converters and DA converters. In other embodiments of the present invention, the programmable logic device may also be a PLA, CPLD, or other similar devices.

[0109] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the above embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A modulator bias lock-in method, characterized in that, Includes the following steps:

1. Scan the characteristic curves of the I, Q, and P signals in the modulator sequentially to find the maximum, minimum, and orthogonal points of the characteristic curves of the three signals; then set the operating point voltages of the I, Q, and P signals according to the modulation method. 2】The bias control signal processing module generates three perturbation signals fI, fQ, and fP at different frequencies, and loads these three perturbation signals fI, fQ, and fP at different frequencies onto the three DC bias input terminals of the modulator. 3】The three perturbation signals fI, fQ, and fP of different frequencies are passed through a modulator and then beat in pairs to obtain three difference frequency signals f1, f2, and f3; 4. Based on the set sampling frequencies fs1, fs2, fs3 and the number of sampling points N, calculate the I / Q local quadrature reference signal arrays corresponding to each of the three difference frequency signals f1, f2, and f3; wherein, the I / Q local quadrature reference signal arrays generated by the first difference frequency signal f1 are f1R and f1I, the I / Q local quadrature reference signal arrays generated by the second difference frequency signal f2 are f2R and f2I, and the I / Q local quadrature reference signal arrays generated by the third difference frequency signal f3 are f3R and f3I; f1R, f1I, f2R, f2I, f3R, and f3I are determined by the following formulas: ； ； ； ； ； ； in, This indicates the frequency of the first difference frequency signal f1. This indicates the frequency of the second difference frequency signal f2. This represents the frequency of the third difference frequency signal f3, where n takes values ​​of 0, 1, 2, ... (N-1).

5. Acquire three difference frequency signals f1, f2, and f3 to obtain three datasets corresponding to the three difference frequency signals f1, f2, and f3; perform inner product calculations on the data in the three datasets with the I / Q local quadrature reference signal arrays corresponding to the three difference frequency signals f1, f2, and f3 respectively; and calculate the amplitude values ​​of the three difference frequency signals f1, f2, and f3 based on the inner product results of the three difference frequency signals f1, f2, and f3 respectively; wherein, the sampling frequency and number of sampling points of the three difference frequency signals f1, f2, and f3 are the same as the sampling frequency fs1, fs2, fs3 and the number of sampling points N corresponding to the steps in step 4; 6. Based on the amplitude values ​​of the three difference frequency signals f1, f2, and f3, adjust the three DC voltage values ​​of the three DC bias input terminals of the input modulator, and return to step 5 for iteration until the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are all at their minimum values, thereby realizing the real-time tracking and adjustment of the three bias voltages I, Q, and P of the modulator.

2. The modulator bias lockout method according to claim 1, characterized in that: In step 5, the data from the three datasets are multiplied by the I / Q local quadrature reference signal arrays corresponding to the three difference frequency signals f1, f2, and f3. Then, based on the results of the multiplication of the three difference frequency signals f1, f2, and f3, the amplitude values ​​of the three difference frequency signals f1, f2, and f3 are calculated. Specifically: The data in the dataset corresponding to the first difference frequency signal f1 are multiplied by f1R and f1I respectively to obtain the real part f1_R and the imaginary part f1_I of the first difference frequency signal f1; the data in the dataset corresponding to the second difference frequency signal f2 are multiplied by f2R and f2I respectively to obtain the real part f2_R and the imaginary part f2_I of the second difference frequency signal f2. The data in the dataset corresponding to the third difference frequency signal f3 are multiplied by f3R and f3I respectively to obtain the real part f3_R and the imaginary part f3_I of the third difference frequency signal f3. Then, calculate the corresponding amplitude values ​​A1, A2, and A3 of the three difference frequency signals f1, f2, and f3 using the following formulas: ； ； 。 3. The modulator bias lock-in method according to claim 2, characterized in that: Step 5 also includes: Before acquiring the three difference frequency signals f1, f2, and f3, filter the three difference frequency signals f1, f2, and f3 respectively.

4. The modulator bias lockout method according to any one of claims 1-3, characterized in that: In step 4, the sampling frequencies fs1, fs2, and fs3 are four times the frequencies of the corresponding three difference frequency signals f1, f2, and f3, respectively.

5. A laser communication bias control system based on a soft core, used to implement the modulator bias locking method according to any one of claims 1-4, comprising a driving module (3) and a laser (1), a modulator (2), a beam splitter (4), a photodetector (5), and a bias control signal processing module (6) connected in sequence according to input and output; the driving module (3) is used to amplify the high-speed data stream, and the amplified signal enters the modulator (2), which modulates the data onto the laser signal emitted by the laser (1); the beam splitter (4) is used to divide the optical signal output by the modulator (2) into two paths, one path for subsequent optical communication, and the other path is converted into an electrical signal by the photodetector (5) and then sent to the bias control signal processing module (6), characterized in that: The bias control signal processing module (6) includes a programmable amplifier circuit (61), a fine adjustment circuit (62), a bandpass filter circuit (63), an AD conversion module (64), a programmable logic device (65), and a DA conversion module (66) connected in sequence from input to output. The input terminal of the programmable amplifier circuit (61) is connected to the output terminal of the photodetector (5) and is used to amplify the received electrical signal in a programmable manner. The fine adjustment circuit (62) is used to finely amplify or attenuate the programmed amplified electrical signal; The bandpass filter circuit (63) includes three filter modules with different bandwidths, which are used to filter the finely amplified or attenuated signal through the three filter modules to obtain three difference frequency signals f1, f2, and f3 with different frequencies. The AD conversion module (64) is used to acquire three different frequency difference signals f1, f2 and f3 respectively and convert the acquired analog signals into digital signals; The output of the DA conversion module (66) is connected to the three DC bias inputs of the modulator (2); The programmable logic device (65) is equipped with a soft core; the soft core is used to perform an inner product of the three difference frequency signals f1, f2, f3 and the corresponding I / Q local quadrature reference signal arrays of the three difference frequency signals f1, f2, f3, and calculate the amplitude values ​​of the three difference frequency signals f1, f2, f3 based on the inner product result, and then adjust the three DC voltage values ​​of the DA conversion module (66) input to the three DC bias input terminals of the modulator (2) through the amplitude values ​​of the three difference frequency signals f1, f2, f3.

6. The laser communication bias control system based on a soft core according to claim 5, characterized in that: The programmable amplifier circuit (61) is a two-stage programmable amplifier circuit, implemented using the AD8253 chip; The fine adjustment circuit (62) is implemented using an AD5450 chip.

7. The laser communication bias control system based on a soft core according to claim 6, characterized in that: The AD conversion module (64) includes three AD converters, or the AD converters in the AD conversion module (64) include three conversion channels; The DA conversion module (66) includes three DA converters, or the DA converters in the DA conversion module (66) include three conversion channels.

8. The laser communication bias control system based on a soft core according to any one of claims 5-7, characterized in that: The programmable logic device is an FPGA; The soft core uses microblaze.

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