Vbo communication method, vbo interface and display terminal

Abstract

The application discloses a VBO communication method, a VBO interface and a display terminal. The VBO communication method detects the working state of a receiving end, resets the transmitting circuit of a transmitting end when the working state of the receiving end is in a lockout state, so that a new delay is randomly generated between a transmitting signal and a receiving signal when the transmitting end performs sample training of clock data recovery after power-on, until the delay is within an acceptable range, thereby greatly improving the probability that the receiving end is in a locked state, and the transmitting end and the receiving end can normally communicate.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a VBO communication method, a VBO interface, and a display terminal. Background Technology

[0002] During communication using the VBO (V-by-One) transmission protocol, if the delay (Skew) between transmitted or received signals exceeds the VBO specification, or if the delay between received signals exceeds the receiver's tolerance, the receiver will be unable to lock, thus preventing normal communication between the transmitter and receiver from starting. Summary of the Invention

[0003] This application provides a VBO communication method, a VBO interface, and a display terminal to alleviate the technical problem that the receiver cannot lock due to excessive delay between the transmitted or received signals.

[0004] In a first aspect, this application provides a VBO communication method applied to a display terminal. The display terminal includes a VBO interface, which in turn includes a transmitter and a receiver. The transmitter is equipped with a transmitting circuit. The VBO communication method includes: detecting the operating state of the receiver, which includes a locked state and a unlocked state; and resetting the transmitting circuit in response to the unlocked state of the receiver.

[0005] In some embodiments, the step of detecting the operating state of the receiver includes: in response to the failure of sample training for clock data recovery at the receiver, the receiver switches the potential of the clock lock control signal from low to high; the receiver recognizes that the clock lock control signal has changed from low to high potential and switches the hot-plug detection control signal from low to high potential.

[0006] In some implementations, the step of switching the potential of the clock lock control signal from low to high in response to the failure of sample training for clock data recovery at the receiver includes: determining that the switching of the clock lock control signal from low to high potential indicates an unlocked state.

[0007] In some embodiments, the transmitting circuit further includes a phase-locked loop, wherein the step of resetting the transmitting circuit in response to a lost-lock state at the receiving end includes: resetting the phase-locked loop in response to a lost-lock state at the receiving end.

[0008] In some embodiments, the receiver includes a receiving circuit, wherein, after resetting the transmitting circuit in response to the unlocked state of the receiver, the process includes: both the transmitting and receiving ends performing a power-on procedure; and enabling the receiving circuit.

[0009] In some embodiments, after enabling the receiving circuit, the following steps are included: the receiving end switches the hot-plug detection control signal from a high potential to a low potential; and in response to the hot-plug detection control signal switching from a high potential to a low potential, performs sample training for clock data recovery.

[0010] In some embodiments, after performing sample training for clock data recovery in response to the hot-plug detection control signal switching from a high potential to a low potential, the method includes: detecting the operating state of the receiver; and, in response to the latching state of the receiver, switching the clock latching control signal from a high potential to a low potential.

[0011] Secondly, this application provides a VBO interface, which includes a receiver and a transmitter. The receiver has a working state including a locked state and a unlocked state. The transmitter includes a transmitting circuit, which resets the transmitting circuit when it detects the unlocked state of the receiver.

[0012] In some implementations, the transmitting circuit includes a phase-locked loop (PLL) that resets when the transmitting end detects a lost-lock state at the receiving end.

[0013] Thirdly, this application provides a display terminal, which includes the VBO interface in at least one of the above embodiments, a timing controller disposed in the display terminal as a receiving end, and a transmitting end for transmitting the received video data.

[0014] The VBO communication method, VBO interface, and display terminal provided in this application detect the working state of the receiver. When the receiver is in an unlocked state, the transmitting circuit of the transmitter is reset. Thus, when the transmitter performs sample training for clock data recovery after power-on, a new delay will be randomly generated between the transmitted signal and the received signal until the delay is within an acceptable range. This greatly increases the probability that the receiver is in a locked state, thereby enabling normal communication between the transmitter and the receiver. Attached Figure Description

[0015] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0016] Figure 1 This is a flowchart illustrating the VBO communication method provided in an embodiment of this application.

[0017] Figure 2 A timing diagram illustrating the VBO communication method provided in this application embodiment.

[0018] Figure 3 This is a schematic diagram of the state of the VBO communication method provided in the embodiments of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0021] In display terminals, the timing controller (Tcon) for 8K displays uses a VBO input interface. 8K & 60Hz displays have 32 lanes of VBO input, while 8K & 120Hz displays have 64 lanes. Currently, most production line fixtures in the industry use cascaded pattern generator fixtures with multiple 16-channel VBO input interfaces. For example, an 8K & 60Hz panel requires two 16-channel VBO input pattern generator fixtures, and an 8K & 120Hz panel requires four 16-channel VBO input pattern generator fixtures. However, due to incomplete synchronization among multiple pattern generator fixtures, the skew delay between different lanes within different pattern generator fixtures can become too large, exceeding the VBO protocol specifications.

[0022] In particular, when the skew between the transmit (VBO TX) signals output from different Pattern Generator fixtures exceeds the VBO specification (2UI), or the skew between the receive (VBO RX) signals exceeds the VBO specification (5UI) or exceeds the tolerance of the receiver (VBO RX device), the VBO RX device will enter a state where it cannot lock. At this time, the clock lock control signal LOCKN will go high, causing the transmitter (VBO TX device) to continuously send training patterns, and the clock lock control signal LOCKN will constantly switch between high (unlocked state) and low (locked state). Since the phase-locked loop (PLL) in the transmitter is already locked, the skew between corresponding signals remains unchanged during each training process. This will cause the delay between the transmit or receive signals to exceed the limit.

[0023] In view of the aforementioned technical problem where the receiver cannot lock due to excessive delay between the transmitted or received signals, this embodiment provides a VBO communication method applied to a display terminal. The display terminal includes a VBO interface, which in turn includes a transmitter and a receiver. The transmitter is equipped with a transmitting circuit. Please refer to [link to relevant documentation]. Figures 1 to 3 ,like Figure 1 As shown, the VBO communication method includes the following steps:

[0024] Step S10: Detect the operating status of the receiver. This operating status includes a locked state and a unlocked state.

[0025] Step S20: In response to the unlocked state of the receiver, reset the transmitting circuit.

[0026] It is understood that the VBO communication method provided in this embodiment detects the working state of the receiver and resets the transmitting circuit of the transmitter when the receiver is in a unlocked state. In this way, when the transmitter performs sample training for clock data recovery after power-on, a new delay will be randomly generated between the transmitted signal and the received signal until the delay is within an acceptable range. This greatly increases the probability that the receiver is in a locked state, and thus the transmitter and receiver can communicate normally.

[0027] It should be noted that, Figure 3 The left side shows the state of the transmitter changing over time. Figure 3 The right side of the image shows the state of the transmitter over time.

[0028] In one embodiment, such as Figure 2As shown, the steps for detecting the operating status of the receiver include: in response to the failure of sample training for clock data recovery at the receiver, the receiver switches the potential of the clock lock control signal LOCKN from low to high; the receiver recognizes that the clock lock control signal LOCKN has changed from low to high potential and switches the hot-plug detection control signal HTPDN from low to high potential.

[0029] It should be noted that the unlocked state refers to the state where the clock lock control signal LOCKN changes from a low level to a high level. The locked state refers to the state where the clock lock control signal LOCKN changes from a high level to a low level.

[0030] In one embodiment, the transmitting circuit further includes a phase-locked loop, wherein the step of resetting the transmitting circuit in response to a lost-lock state at the receiving end includes: resetting the phase-locked loop in response to a lost-lock state at the receiving end.

[0031] It should be noted that since the phase-locked loop (PLL) in the transmitter is already locked, the skew between corresponding signals remains unchanged during each transmitter training process. Therefore, in this embodiment, resetting the PLL allows for the random regeneration of the skew between transmitted or received signals, thereby altering the skew between transmitted or received signals and increasing the probability that the receiver is in a locked state.

[0032] In one embodiment, such as Figure 2 As shown, the receiving end includes a receiving circuit. After resetting the transmitting circuit in response to the unlocked state of the receiving end, the process includes: both the transmitting end and the receiving end performing a power-on procedure; and enabling the receiving circuit.

[0033] It should be noted that after the reset, both the transmitter and receiver perform the normal power-on process, and the receiver circuit can work normally after power-on.

[0034] In one embodiment, such as Figure 2 As shown, after enabling the receiving circuit, the following steps are included: the receiving end switches the hot-plug detection control signal HTPDN from a high potential to a low potential; in response to the hot-plug detection control signal HTPDN switching from a high potential to a low potential, sample training for clock data recovery is performed.

[0035] It should be noted that the sample training for clock data recovery is as follows: Figure 2 The “CDR Training” shown in the image.

[0036] In one embodiment, such as Figure 2As shown, after the step of performing sample training for clock data recovery in response to the hot-plug detection control signal HTPDN switching from a high level to a low level, the method includes: detecting the operating state of the receiver; and in response to the latching state of the receiver, switching the clock lock control signal LOCKN from a high level to a low level.

[0037] It should be noted that normal data transmission can occur between the transmitter and receiver when the receiver is in a locked state.

[0038] In one embodiment, this embodiment provides a VBO interface, which includes a receiver and a transmitter. The receiver has a working state including a locked state and a unlocked state. The transmitter includes a transmitting circuit, which resets the transmitting circuit when it detects the unlocked state of the receiver.

[0039] It is understood that the VBO interface provided in this embodiment detects the working state of the receiver and resets the transmitting circuit of the transmitter when the receiver is in a unlocked state. In this way, when the transmitter performs sample training for clock data recovery after power-on, a new delay will be randomly generated between the transmitted signal and the received signal until the delay is within an acceptable range. This greatly increases the probability that the receiver is in a locked state, and thus the transmitter and receiver can communicate normally.

[0040] In one embodiment, this embodiment provides a display terminal, which includes the VBO interface of at least one of the above embodiments, a timing controller disposed in the display terminal as a receiving end, and a transmitting end for transmitting the received video data.

[0041] It is understood that since the display terminal provided in this embodiment includes the VBO interface in at least one of the above embodiments, it can also detect the working state of the receiver and reset the transmitting circuit of the transmitter when the receiver is in a unlocked state. In this way, when the transmitter performs sample training for clock data recovery after power-on, a new delay will be randomly generated between the transmitting signal and the receiving signal until the delay is within an acceptable range. This greatly increases the probability that the receiver is in a locked state, and thus the transmitter and receiver can communicate normally.

[0042] Figure 3The diagram illustrates the VBO handshake process. The transmitter and receiver using the VBO transmission protocol have a strict handshake procedure during the power-on phase, adhering to strict timing control. VBO signal transmission requires the hot-plug detection control signal HTPDN and the clock lock control signal LOCKN. The potentials of both are controlled by the receiver. After power-on, the two pins corresponding to these two control signals are set to high level by default. When the receiver completes its reset, the hot-plug detection control signal HTPDN is pulled low; then CDR training is performed. After CDR completion, the clock lock control signal LOCKN is pulled low; then ALN ​​training is performed, the handshake is successful, and valid image information is transmitted.

[0043] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0044] The VBO communication method, VBO interface, and display terminal provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A VBO communication method applied to a display terminal, the display terminal including a VBO interface, the VBO interface further including a transmitter and a receiver, wherein, The transmitting end is equipped with a transmitting circuit, characterized in that the VBO communication method includes: The working status of the receiving end is detected, including a locked state and a unlocked state. In response to the unlocked state of the receiver, the transmitting circuit is reset; The steps for detecting the working status of the receiving end include: In response to the failure of sample training for clock data recovery at the receiving end, the potential of the clock lock control signal at the receiving end changes from low to high; The receiving end detects that the clock lock control signal changes from low to high potential, and switches the hot-plug detection control signal from low to high potential. The transmitting circuit further includes a phase-locked loop, wherein the step of resetting the transmitting circuit in response to the unlocked state of the receiving end includes: In response to the unlocked state of the receiving end, the phase-locked loop is reset.

2. The VBO communication method according to claim 1, characterized in that, The step of switching the potential of the clock lock control signal from low to high in response to the failure of sample training in response to clock data recovery at the receiving end includes: The switch of the clock lock control signal from low potential to high potential is determined as the unlocked state.

3. The VBO communication method according to claim 1, characterized in that, The receiving end includes a receiving circuit, wherein, after the step of resetting the transmitting circuit in response to the unlocked state of the receiving end, the following steps are included: Both the transmitting end and the receiving end perform a power-on procedure; Enable the receiving circuit.

4. The VBO communication method according to claim 3, characterized in that, After the step of enabling the receiving circuit, the following steps are included: The receiving end switches the hot-plug detection control signal from a high potential to a low potential; In response to the hot-plug detection control signal switching from a high potential to a low potential, the transmitter performs sample training for clock data recovery.

5. The VBO communication method according to claim 4, characterized in that, Following the step of the transmitter performing sample training for clock data recovery in response to the hot-plug detection control signal switching from a high potential to a low potential, the procedure includes: Detect the working status of the receiving end; In response to the latching state of the receiver, the receiver switches the clock latching control signal from a high potential to a low potential.

6. A VBO interface, characterized in that, The VBO interface includes: The receiving end, wherein the operating states of the receiving end include a locked state and an unlocked state; and The transmitter includes a transmitting circuit, which detects the unlocked state of the receiver and resets the transmitting circuit. The step of the transmitting end detecting the working status of the receiving end includes: In response to the failure of sample training for clock data recovery at the receiving end, the potential of the clock lock control signal at the receiving end changes from low to high; The receiving end detects that the clock lock control signal changes from low to high potential, and switches the hot-plug detection control signal from low to high potential. The transmitting circuit further includes a phase-locked loop, wherein the step of resetting the transmitting circuit in response to the unlocked state of the receiving end includes: In response to the unlocked state of the receiving end, the phase-locked loop is reset.

7. The VBO interface according to claim 6, characterized in that, The transmitting circuit includes a phase-locked loop (PLL), and the transmitting end detects the unlocked state of the receiving end and resets the PLL.

8. A display terminal, characterized in that, The display terminal includes the VBO interface as described in any one of claims 6-7, the receiving end is disposed in the timing controller of the display terminal, and the transmitting end is used to transmit the received video data.

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