Topology for IP cores and IP cores

Abstract

The embodiment of the present disclosure discloses a kind of topologies for IP core, comprising: first topology and second topology, the first topology includes drive chip, multiple first signal lines and at least two first loads, the signal output end of a previous stage first signal line is connected with the signal input end of the parallel two first signal lines of next stage, the signal input end of first stage first signal line is connected with the signal output end of the drive signal;The output end of last stage each first signal line is connected with a first load;The second topology includes multiple branch structures, each branch structure includes at least one second load, the signal input end of each branch structure is connected with the signal output end of the last stage of first topology One first signal line, provide a new topology for IP core, to realize the diversified IP core topology to adapt to different needs.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a topology and IP core for use in IP cores. Background Technology

[0002] As integrated circuits become larger and more complex, in order to design and manufacture integrated circuits with various functions more quickly, reusable IP cores can be designed as integrated circuit modules with specific functions. In integrated circuit design, an IP core refers to a verified, reusable integrated circuit design module with a specific function.

[0003] Storage integrated circuit modules with high-speed data read and write capabilities can integrate driver chips and Double Data Rate Synchronous Dynamic Random Access Memory (DDR) into IP cores for reuse in different integrated circuits. Summary of the Invention

[0004] This disclosure is provided to briefly introduce the concepts, which will be described in detail in the subsequent Detailed Description section. This disclosure is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0005] This disclosure provides a topology and an IP core for use in embodiments of an IP core.

[0006] In a first aspect, embodiments of this disclosure provide a topology for an IP core, comprising: a first topology and a second topology. The first topology includes a driver chip, multiple levels of first signal lines, and at least two first loads. The signal output terminal of a first signal line of a preceding level is connected to the signal input terminals of two first signal lines of a subsequent level connected in parallel. The signal input terminals of the first signal lines of the first level are connected to the signal output terminals of the driving signal. The output terminals of each first signal line of the last level are connected to a first load. The second topology includes multiple branch structures, each branch structure including at least one second load. The signal input terminal of each branch structure is connected to the signal output terminal of a first signal line of the last level of the first topology.

[0007] Secondly, embodiments of this disclosure provide an IP core, including a substrate, a driver chip disposed on the substrate, multiple loads, and a connection structure between the multiple loads and the driver chip; the topology connecting the multiple loads and the driver chip includes a first topology and a second topology; the first topology includes a driver chip, multiple levels of first signal lines, and at least two first loads, wherein the signal output terminal of a first signal line of a preceding level is connected to the signal input terminals of two first signal lines of a subsequent level connected in parallel, and the signal input terminals of the first signal lines of the first level are connected to the signal output terminals of the driver signal; the output terminals of each first signal line of the last level are connected to a first load; the second topology includes multiple branch structures, each branch structure includes at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of a first signal line of the last level of the first topology.

[0008] The embodiments of this disclosure provide a topology for IP cores and an IP core itself. By setting a first topology and a second topology in the topology, the first topology includes a driver chip, multiple levels of first signal lines, and at least two first loads. The signal output terminal of a first signal line of a preceding level is connected to the signal input terminals of two first signal lines of a subsequent level connected in parallel. The signal input terminals of the first signal lines of the first level are connected to the signal output terminals of the driving signal. The output terminals of each first signal line of the last level are connected to a first load. The second topology includes multiple branch structures, each branch structure including at least one second load. The signal input terminal of each branch structure is connected to the signal output terminal of a first signal line of the last level of the first topology. This allows the first and second topologies to be combined to form a topology for IP cores, providing a new topology for IP cores to achieve diverse IP core topologies to adapt to different needs. Attached Figure Description

[0009] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0010] Figure 1 This is a schematic diagram of a topology for an IP core according to the present disclosure;

[0011] Figure 2 This is another schematic diagram of a topology for an IP core according to this disclosure;

[0012] Figure 3 This is a schematic eye diagram of an IP core provided in this disclosure. Detailed Implementation

[0013] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0014] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0015] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0016] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0017] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0018] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0020] Please refer to Figure 1 This illustrates a schematic diagram of the topology for IP cores disclosed herein. For example... Figure 1As shown, the topology for the IP core includes a first topology 11 and a second topology 12. The first topology 11 includes a driver chip D, multiple first signal lines S11, S2, ..., S1M, and at least two first loads B1. The driver chip D can include various chips for generating operating signals, including but not limited to Field-Programmable Gate Arrays (FPGAs) and Systems on Chips (SoCs). The driver chip D can emit a clock signal. This clock signal can be a control signal for controlling the loads. For example, this control signal can be a controller and address (CA) signal.

[0021] In the first topology, the number of stages of the multi-stage first signal lines S11, S2, ..., S1M can be set according to the specific application scenario. The output terminal of one of the preceding stage's first signal lines is connected to the signal input terminals of two parallel first signal lines of the following stage. The input terminals of the first-stage first signal lines are connected to the output terminals of the driver chip. The output terminals of each first signal line in the final stage are connected to a first load B1.

[0022] In other words, the signal input terminals of the two first signal lines of the next stage are connected in parallel and then connected to the signal output terminal of one first signal line of the previous stage.

[0023] The first stage first signal line includes one first signal line. The signal input terminal of the first stage first signal line is connected to the signal output terminal of the driver chip D.

[0024] The output of the first signal line S1M of the last stage is connected to the first load.

[0025] If there are two levels of multi-level first signal lines, then the second level of first signal lines includes two first signal lines; the first level of first signal lines includes one first signal line. If there are three levels of multi-level first signal lines, then the first level of first signal lines in these three levels includes one first signal line, the second level includes two first signal lines, and the third level includes four first signal lines. If there are four levels of multi-level first signal lines, then the first level of first signal lines in these four levels includes one first signal line; the second level includes two first signal lines, the third level includes four first signal lines, the fourth level includes eight first signal lines, and so on.

[0026] The output of the last stage's first signal line is connected to the first load B1.

[0027] In the first topology, the number of first loads B1 can be less than or equal to the number of first signal lines in the last stage. The control signal issued by the driver chip D can be transmitted through each stage of the first signal lines to the output of the last stage of the first signal lines, and then to the first load to control the operation of the first load B1.

[0028] The first topology mentioned above can be a T-shaped topology.

[0029] The second topology 12 includes multiple branch structures 121, each branch structure 121 including at least one second load B2. The signal input terminal of each branch structure 121 is connected to the output terminal of a first signal line of the last stage of the first topology 11.

[0030] For each branch structure 121, at least one second load B2 in the branch structure 121 may be connected in series. The second loads B2 in a branch structure 121 may be connected to each other via a second signal line S22.

[0031] Since the signal input terminal of each branch structure 121 is connected to the output terminal of the first signal line of the last stage of the first topology 11, the control signal issued by the driver chip D can be transmitted to the second load B2 through the first signal line and the second signal line S22 of each stage.

[0032] The number of branch structures 121 in the second topology 12 can be less than or equal to the number of first signal lines in the last stage of the first topology.

[0033] The output of the last stage first signal line of the first topology 11 is connected to the input of a second signal line in the branch structure 121. The output of this second signal line is connected to a second load B2. In some applications, a branch structure includes two second loads. The branch structure may include multiple second signal lines. The input of the first second signal line in the branch structure is connected to the output of a first signal line in the last stage of the first topology. The output of the first second signal line is connected to a second load. Furthermore, the output of the first second signal line S22 is also connected to the input of the second second signal line S22. The output of the second second signal line S22 is connected to a second load.

[0034] The second topology 12 can be a fly_by structure.

[0035] The number of second loads in the branch structure of the second topology 12 can be determined based on the driving capability of the driver chip.

[0036] The first load B1 and the second load B2 can be electronic components that perform the same function, such as electronic components that perform data storage. Specifically, the first load and the second load can be Double Data Rate Synchronous Dynamic Random Access Memory (DDR), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR), etc.

[0037] The topology for IP cores provided in this embodiment combines a first topology with a second topology to form a new topology for IP cores, thereby enabling diverse IP core topologies to meet different needs.

[0038] In some application scenarios, in the first topology 11, the equivalent impedance formed by the two first signal lines connected in parallel in the later stage is equal to the impedance of one of the first signal lines connected in the previous stage.

[0039] The impedances of the two first signal lines connected in parallel in the next stage can be equal.

[0040] For example, in the second-stage first signal line, the equivalent impedance formed by two parallel second-stage first signal lines is equal to the impedance of the first-stage first signal line connected to the two parallel second-stage first signal lines.

[0041] For example, if the impedance of the first signal line of the first stage is 10 ohms, then the impedance of each first signal line of the second stage connected to it can be 20 ohms. The equivalent impedance of the second signal lines connected in parallel can be 10 ohms, which is equal to the impedance of the first signal line of the first stage.

[0042] In these application scenarios, since the equivalent impedance formed by the two first signal lines connected in parallel in the next stage is equal to the impedance of one of the first signal lines connected in the previous stage, and the impedances of the two first signal lines connected in parallel in the next stage are equal, the impedance of the first signal lines at each stage can be guaranteed to have good continuity.

[0043] In some alternative implementations, the branch structure of the second topology 12 includes at least one second signal line connected to the second load. This second signal line may include a second signal line S22 connected to the last stage first signal line in the first topology, and a second signal line S22 between each of the second loads B2.

[0044] In these alternative implementations, by setting the impedance of each segment of the second signal line in the branch structure 121 of the second topology 12 to be equal to the impedance of the first signal line connected to the branch structure, the impedance continuity of the signal lines in the overall topology is improved.

[0045] In some alternative implementations, the first topology 11 described above includes two levels of first signal lines and two first loads.

[0046] In other words, the first topology 11 includes one first-stage first signal line and two second-stage first signal lines. The two second-stage first signal lines are connected in parallel and then connected to the output terminal of the first-stage first signal line. The output terminals of the two second-stage first signal lines are respectively connected to the first load.

[0047] In some alternative implementations, the second topology 12 may include two branch structures. Each branch structure 121 includes a second load.

[0048] Thus, the second topology 12 can include two second loads B2.

[0049] In some application scenarios, please refer to Figure 2 This illustrates a schematic diagram of a topology for IP cores provided in this disclosure. For example... Figure 2 As shown, the first topology 11' may include two levels of first signal lines S11 and S12.

[0050] The second topology 12' includes two branch structures 121', and the input terminal of the second signal line S22' of each branch structure can be connected to the output terminal of the second-stage first signal line S12 of the first topology 11'. The output terminal of the second signal line S22' of the branch structure 121' is connected to a second load B2.

[0051] In these optional implementations, two first signal lines S11 and S12 are set in the first topology 11', and two first loads B1 are set in the first topology 11', while two branch structures 121' are set in the second topology 12'. Each branch structure 121' sets a second load B2. The output terminal of the first topology 11' is connected to the input terminal of one branch structure 121' of the second topology 12', so that the entire topology can correspond to four loads. This topology is suitable when the driver chip needs to drive four loads, and it is difficult to implement using only the first or second topology.

[0052] This disclosure also provides an IP core. The IP core includes a substrate, a driver chip disposed on the substrate, multiple loads, and connection structures between the multiple loads and the driver chip. The topology formed by the connections between the multiple loads and the driver chip includes a first topology and a second topology. The first topology includes a driver chip, multiple levels of first signal lines, and at least two first loads. The signal output terminal of a first signal line of a preceding level is connected to the signal input terminals of two first signal lines of a subsequent level connected in parallel. The signal input terminals of the first signal lines of the first level are connected to the signal output terminals of the driving signal. The output terminals of each first signal line of the last level are connected to a first load. The second topology includes multiple branch structures, each branch structure including at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of a first signal line of the last level of the first topology.

[0053] The aforementioned driver chip can be any chip capable of emitting clock signals, such as a Field Programmable Gate Array (FPGA), a System on Chip (SoC), or a Microcontroller Unit (MCU). The aforementioned load can be an electronic component that implements one or more functions. In some applications, the aforementioned load can be an electronic component that implements data storage functions. For example, the aforementioned load can be DDR, LPDDR, etc.

[0054] The driver chip, the first load, and the second load can be connected to the substrate by means of welding, gluing, etc.

[0055] The first signal lines at each of the above levels can be fabricated using substrate materials.

[0056] Furthermore, the branch structure may include a second signal line. Each of the first and second signal lines can be fabricated using a conductive material in the substrate.

[0057] The branch structure of the second topology may include a second signal line, which may include a second signal line connected between the output terminal of the first signal line of the last stage of the first topology and the second load, and may also include a second signal line connected between different second loads.

[0058] In this example, the substrate can be any substrate that is used as a driver chip, a load carrier, and in which a signal line in a second topology is fabricated for a first signal line.

[0059] As one implementation method, the aforementioned substrate can be a printed circuit board (PCB). A printed circuit board substrate includes a copper-clad layer and an insulating layer. Connecting wires and pads can be fabricated on the copper-clad layer through processes such as printing and etching.

[0060] The first topology described above includes multiple levels of first signal lines, and the second topology includes multiple branch structures, each branch structure including at least one second signal line. The first and second signal lines are formed on a printed circuit board. The signal output terminal of the driver chip can be connected to the input terminal of the first-level first signal line via solder pads. Alternatively, the output terminal of the last level of the first signal line in the first topology can be connected to the input terminal of a first load. Furthermore, the output terminal of a second signal line in the second topology can be connected to the signal input terminal of a second load.

[0061] If the PCB board is a multilayer board, the first signal line and the second signal line may include signal lines disposed in the horizontal plane of at least one copper layer, and may also include signal lines that cross different copper layers through vias.

[0062] When fabricating the first signal lines of each stage using a PCB board, the impedance of the first signal lines of each stage can be controlled so that the equivalent impedance of the two parallel first signal lines of the next stage is equal to the impedance of the first signal line of the previous stage connected to the two parallel first signal lines, thus ensuring the impedance continuity of the first signal lines of each stage.

[0063] Similarly, when fabricating the second signal lines for each branch structure on a PCB board, it is necessary to control the impedance of the second signal lines for each branch structure. For each branch structure, the impedance of each second signal line on that branch structure can be controlled to be equal. In addition, the impedance of the second signal line in that branch structure must also be controlled to be equal to the impedance of the first signal line connected to that branch structure.

[0064] It should be noted that if the signal line formed by crossing different copper layers via vias is the first signal line, then the impedance of the first signal line should be controlled according to the relationship between its impedance and the impedance of the preceding stage it is connected to. If the signal line formed by crossing different copper layers via vias is the second signal line, then the impedance of the second signal line can be controlled according to the impedance of the first signal line connected to the branch structure in which the second signal line is located. Specifically, the impedance of the first or second signal line can be adjusted by optimizing the value of the antipad to ensure better impedance continuity among the nodes of the IP core.

[0065] Various signal lines can be set up on a PCB to connect driver chips and loads. The printed circuit board (PCB) consists of an insulating base plate, connecting wires, and pads for mounting and soldering electronic components, serving the dual function of conductive lines and an insulating base plate. It can replace complex wiring to achieve electrical connections between components in a circuit.

[0066] The appropriate PCB substrate can be selected based on the impedance requirements of the first signal line. For example, a PCB substrate that can meet the impedance requirements of the final stage first signal line can be selected to fabricate the signal line. When the load corresponds to a high-speed transmission rate, the lower the Dk value of the PCB substrate, the better the quality of the high-speed transmission signal and the faster the speed. Dk is an indicator of the material's ability to store electrical properties; the lower the Dk, the faster and stronger the signal transmission speed in the medium.

[0067] Dk is the dielectric constant, also known as the relative dielectric constant, of the PCB circuit board material. Dk is not a constant; for example, the Dk of a material can vary with frequency. This disclosure selects PCB substrates with Dk values ​​less than a preset threshold for fabricating IP cores. This preset threshold can be set according to specific application scenarios and is not limited here.

[0068] The first topology can be a T-shaped topology. To ensure good impedance continuity in the first topology, when setting the first signal lines of each stage of the first topology on the PCB substrate, the equivalent impedance of each of the two first signal lines connected in parallel in the later stage is equal to twice the impedance of the first signal lines of the previous stage connected to those two first signal lines. Thus, the equivalent impedance of the two first signal lines connected in parallel in the later stage is equal to the impedance of the first signal lines of the previous stage connected to those two first signal lines.

[0069] The IP core provided in this example achieves the ability to drive multiple loads with a driver chip at a lower manufacturing cost by using a combination of a first topology and a second topology on a substrate.

[0070] In some embodiments, the first load and the second load can be storage components with high-speed data read / write capabilities. A first topology disposed in the substrate includes two levels of first signal lines and two first loads; a second topology includes two branch structures, each branch structure including a second load. Correspondingly, the IP core may include a driver chip and four loads. The driver chip may be soldered or glued to the substrate. Correspondingly, the first signal lines formed in the substrate according to the topology include two levels. The input terminal of the first-level first signal line is connected to the output terminal of the driver chip. The first-level first signal line includes one first signal line. The second-level second signal line includes two first signal lines connected in parallel. The impedance of a second-level first signal line may be twice the impedance of the first-level first signal line. The branch structures disposed in the substrate may include two branch structures. Each branch structure may include one second load. Each branch structure may include one second signal line. The impedance of the second signal line in each branch structure may be equal to the impedance of a second-level first signal line connected to that branch structure.

[0071] In these optional implementations, the first topology corresponds to a T-shaped topology, and the second topology corresponds to a fly-by topology. The substrate can be a PCB substrate. Using the topology composed of the first and second topologies to fabricate the IP core allows the driver chip within the IP core to smoothly drive four loads.

[0072] If the load is a high-speed read / write storage component, such as 64-bit LPDDR5, the driver chip is a SoC. When using a conventional T-shaped topology to implement one driver chip driving four loads, a double-T-shaped topology is required. Because this adds one more branch structure compared to a single-T-shaped topology, and the number of loads doubles, the driver chip needs stronger driving capability to achieve good eye diagram results for the IP core, while strictly adhering to the ratio that a single signal line in the later stage is twice the number of signal lines in the preceding stage it connects to. However, in practical engineering, when fabricating the first signal line on the PCB, the higher the number of stages in the first signal line of the T-shaped topology, the higher the impedance of the first signal line in that stage. Firstly, the impedance of signal lines that can be implemented on a PCB is limited and cannot be infinitely large; the impedance designed in the T-shaped structure may not be achievable on the PCB. Therefore, signal lines in a T-shaped topology with more stages are more difficult to implement. Secondly, due to manufacturing process variations, the actual impedance value implemented on the PCB may deviate significantly. This impedance deviation is related to the magnitude of the impedance value. The larger the number of stages in the T-shaped structure, the greater the deviation due to manufacturing process issues. This can lead to poor impedance continuity of the first signal line in each stage, resulting in a poor eye diagram effect.

[0073] Among these optional implementation methods, a combination of a first topology and a second topology is adopted. The first topology is a T-shaped topology, and the second topology is a fly-by topology. The two-stage first signal lines in the first topology and the second signal lines in the second topology are fabricated on the PCB board using processes such as printing and etching.

[0074] Two stages of first signal lines are fabricated on the PCB board. The signal input terminals of the first-stage signal lines can be connected to the signal output terminals of the driver chip. The output terminals of the second-stage first signal lines are connected to two first loads. Two branch structures are fabricated on the PCB board, each branch structure corresponding to one second signal line. The signal input terminal of each second signal line can be connected to the output terminal of one second-stage first signal line. The output terminal of the second signal line is connected to a second load.

[0075] Thus, in the implementation of the conductors corresponding to the first topology described above, the signal line with the highest impedance is the second-stage first signal line, whose impedance is twice that of the first-stage first signal line. If the center impedance value of the first-stage first signal line is 30 ohms, then the center impedance value of the second-stage first signal line is 60 ohms. A conductor impedance of 60 ohms is achievable with current PCB materials and manufacturing processes. The impedance of the second signal line in the branch structure corresponding to the second topology can be equal to the impedance of the second-stage first signal line. Therefore, the impedance of the second signal line is also achievable with existing PCB materials and manufacturing processes. Therefore, for driving four loads, the implementation on the PCB board... Figure 2 The topology of the illustrated embodiment, corresponding to each signal line, can reduce the requirements for the PCB substrate and lower the cost of the IP core.

[0076] Among these optional implementations, the impedance of the driver chip, the impedance of the first load and the second load can be matched with the first signal line and the second signal line to achieve a better eye diagram effect.

[0077] Taking a first-stage signal line with an impedance of 30 ohms as an example, the equivalent impedance of the driver chip can be chosen to be close to the 30-ohm impedance of the first-stage signal line, for example, 35 ohms. The equivalent impedance of the first load is close to the 60-ohm impedance of a second-stage first signal line, for example, 55 ohms. The equivalent impedance of the second load is close to the 60-ohm impedance of the second signal line connected to it, for example, 55 ohms, thus achieving impedance continuity and better signal integrity.

[0078] To better ensure signal integrity, the length of the second signal line can be set according to the signal integrity requirements.

[0079] In some alternative implementations, the length of the second signal line is determined based on the maximum signal transmission rate corresponding to the load and the period of the control signal issued by the driver chip. Please refer to [reference needed]. Figure 3 , Figure 3 In the eye diagram shown, T UI It is the period of the control signal. Figure 3 The eye diagram shown is composed of the waveform of the control signal and the data transmission signal corresponding to the load.

[0080] In one implementation, the ratio of the length of the second signal line to the maximum transmission rate of the data transmission signal corresponding to the load is an integer multiple of half the period of the control signal mentioned above. That is, the transmission delay of the signal corresponding to the load on the second signal line is an integer multiple of half the period of the control signal mentioned above. This relationship can be expressed by the following formula (1).

[0081]

[0082] Here, L is the length of the second signal line; V max This represents the maximum data transmission rate of the signal corresponding to the load. K is a positive integer, and T... UI It is the period duration of the control signal.

[0083] By setting the length of the second signal line in this way, the reflection position Ed of the second load in the branch structure to the first load corresponding to the first load in the first topology is exactly pressed at the rising or falling edge of the eye diagram of the first load, so as not to affect the eye height in the eye diagram, and thus not to affect the sampling decision.

[0084] Furthermore, a low-speed range is required during the synchronization adjustment process between the control signal and the data transmission signal on the load. During this process, the load's transmission rate is used to be 1 / 4 or 3 / 4 of its maximum transmission rate to ensure that the control signal's accuracy meets the corresponding requirements.

[0085] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0086] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0087] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A topology for IP cores, comprising: A first topology and a second topology, wherein the first topology includes a driver chip, multiple first signal lines and at least two first loads, wherein the signal output terminal of a first signal line of a previous stage is connected to the signal input terminals of two first signal lines of a subsequent stage connected in parallel, the signal input terminal of the first signal line of the first stage is connected to the signal output terminal of the drive signal, and the output terminal of each first signal line of the last stage is connected to a first load; The second topology includes multiple branch structures, each branch structure includes at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of a first signal line of the last stage of the first topology.

2. The topology according to claim 1, wherein, In the first topology, the equivalent impedance of the two parallel signal lines of the next stage is equal to the impedance of one of the preceding stage signal lines connected to it.

3. The topology according to claim 1, wherein, The branch structure includes at least one second signal line connected to the second load; the impedance of the second signal line is equal to the impedance of the first signal line connected to the branch structure.

4. The topology according to claim 1, wherein, The first topology includes two levels of first signal lines and two first loads.

5. The topology according to claim 1 or 4, wherein, The second topology includes two branch structures, each of which includes a second load.

6. An IP core, comprising: A substrate, a driver chip disposed on the substrate, multiple loads, and a connection structure between the multiple loads and the driver chip; The topology connecting the multiple loads to the driver chip includes a first topology and a second topology; The first topology includes a driver chip, multiple first signal lines, and at least two first loads. The signal output terminal of a first signal line of a previous stage is connected to the signal input terminals of two first signal lines of a subsequent stage connected in parallel. The signal input terminal of the first signal line of the first stage is connected to the signal output terminal of the driving signal. The output terminal of each first signal line of the last stage is connected to a first load. The second topology includes multiple branch structures, each branch structure includes at least one second load, and the signal input terminal of each branch structure is connected to the signal output terminal of a first signal line of the last stage of the first topology.

7. The IP core according to claim 6, wherein, The second topology includes a second signal line; the first signal line and the second signal line are arranged on a PCB board.

8. The IP core according to claim 7, wherein, In the IP core, the equivalent impedance of the two first signal lines connected in parallel in the next stage is equal to the impedance of one of the first signal lines connected in the previous stage.

9. The IP core according to claim 7, wherein, In the IP core, the impedance of at least one second signal line connected to the second load in the branch structure is equal to the impedance of the first signal line connected to the branch structure.

10. The IP core according to claim 6, wherein, The first signal line disposed in the substrate has two stages and two first loads; There are two branch structures, each of which includes a second load.

11. The IP core according to claim 6, wherein, The Dk value of the substrate is less than a preset threshold.

12. The IP core according to claim 7, wherein, The length of the second signal line is determined based on the maximum signal transmission rate corresponding to the load and the period of the control signal issued by the driver chip.

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