Method of manufacturing a semiconductor structure

Abstract

The present disclosure provides a method for fabricating a semiconductor structure, comprising: providing a sacrificial structure disposed on a substrate; removing a portion of the sacrificial structure to form a plurality of central openings, at least one edge opening, and a plurality of pillars spaced apart from each other; forming a first material layer to cover the pillars, the central openings, and a portion of the at least one edge opening, wherein a thickness of the first material layer is less than a height of the pillars; and forming at least one edge word line on the substrate through the at least one edge opening, and forming a plurality of central word lines on the substrate through the central openings.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202310277509.X, filed on March 21, 2023, entitled "Semiconductor Structure and Method for Fabrication Thereof," which claims priority and benefits of U.S. Patent Application No. 17 / 879,971, filed on August 3, 2022, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a method for fabricating a semiconductor structure. More particularly, it relates to a method for fabricating a semiconductor structure including word lines. Background Technology

[0003] Semiconductor structures are used in a wide range of electronic applications, and their dimensions are constantly shrinking to meet current application demands. However, various problems arise during the miniaturization process, affecting the final electrical characteristics, quality, cost, and yield. Typical memory elements (such as dynamic random access memory (DRAM) cells) include signal lines, such as word lines and bit lines that intersect with them. As DRAM devices miniaturize and the size and / or spacing of signal lines become smaller, current leakage becomes a critical issue.

[0004] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a sacrificial structure disposed on a substrate; removing a portion of the sacrificial structure to form a plurality of central openings, at least one edge opening, and a plurality of pillars spaced apart from each other; forming a first material layer to cover a portion of the pillars, the central openings, and at least one edge opening, wherein the thickness of the first material layer is less than the height of the pillars; and forming at least one edge character line on the substrate through the at least one edge opening, and forming a plurality of central character lines on the substrate through the central openings.

[0006] The technical features and advantages of this disclosure have been broadly summarized above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages forming the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the same purpose as this disclosure can be achieved quite readily by utilizing the concepts and specific embodiments disclosed below to modify or design other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0007] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0009] Figure 2 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0010] Figure 3 A top view illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of this disclosure.

[0011] Figure 4 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0012] Figure 5 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 6 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figure 7 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figure 8 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0016] Figure 9 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0017] Figure 10 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 11 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0019] Figure 12 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0020] Figure 13 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0021] Figure 14 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0022] Figure 15 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0023] Figure 16 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0024] Figure 17 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0025] Figure 18 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0026] Figure 19 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0027] Figure 20 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0028] Figure 21 Cross-sectional views illustrating one or more stages of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0029] Figure 22 A flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure is provided.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1: Semiconductor Structure

[0032] 10: Substrate

[0033] 11: Semiconductor Section

[0034] 12: Isolation section

[0035] 13: Overlay

[0036] 14: Isolation layer

[0037] 15: Conductive materials

[0038] 16: Polycrystalline silicon layer

[0039] 17: Nitride layer

[0040] 18: Gate layer

[0041] 19: Lining layer

[0042] 20: Sacrifice Structure

[0043] 21: First Sacrifice Layer

[0044] 22: Second Sacrificial Layer

[0045] 23: The Third Sacrificial Layer

[0046] 24: Fourth Sacrifice Layer

[0047] 25: The Fifth Sacrifice Layer

[0048] 26: The Sixth Sacrifice Layer

[0049] 27: The Seventh Sacrifice Layer

[0050] 30: Mask

[0051] 31: Transparent parts

[0052] 32: Opaque portion

[0053] 51: First material layer

[0054] 52: Second material layer

[0055] 53: Third material layer

[0056] 61: First column

[0057] 62: Second column

[0058] 63: Groove

[0059] 90: Method

[0060] 100: Active Area

[0061] 102: Edge character line

[0062] 103: Central character line

[0063] 104: Middle character line

[0064] 111: Central Semiconductor Section

[0065] 112: Edge Semiconductor Section

[0066] 113: Central trench

[0067] 114: Edge groove

[0068] 115: Intermediate trench

[0069] 118: Active Area Deep Trench

[0070] 121: First Isolation Section

[0071] 122: Second Isolation Section

[0072] 201: First edge opening

[0073] 201': Trimmed first edge opening

[0074] 202: Second edge opening

[0075] 202': Trimmed second edge opening

[0076] 203: Central Opening

[0077] 203': Modified central opening

[0078] 321: The first opaque edge

[0079] 322: Second edge opaque portion

[0080] 323: The opaque part of the central government

[0081] 532: Opening

[0082] 620: Top surface

[0083] 631: Central groove

[0084] 632: Edge groove

[0085] 2011: Third edge opening

[0086] 2012: Fifth Edge Opening

[0087] 2013: Seventh Edge Opening

[0088] 2014: Ninth Edge Opening

[0089] 2021: Fourth Edge Opening

[0090] 2022: Sixth Edge Opening

[0091] 2023: Eighth Edge Opening

[0092] 2024: Perforation

[0093] 2031: First Central Opening

[0094] 2032: Second Central Opening

[0095] 2033: The Third Central Opening

[0096] d: Depth

[0097] D: Depth

[0098] D0: Depth

[0099] D': Depth

[0100] D0': Depth

[0101] H: Height

[0102] S91: Steps

[0103] S92: Steps

[0104] S93: Steps

[0105] S94: Steps

[0106] T: Thickness

[0107] w1: Width

[0108] w2: width

[0109] w3: width

[0110] W0: Width

[0111] W0': Width

[0112] W1: Width

[0113] W1': Width

[0114] W2: Width

[0115] W2': Width

[0116] W3: Width

[0117] W3': Width

[0118] W4: Width

[0119] W4': Width

[0120] W5: Width

[0121] W5': Width Detailed Implementation

[0122] The embodiments or examples of this disclosure shown in the accompanying drawings are described below using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the embodiments, and any further application of the principles set forth herein, are to be regarded as normal occurrences by those skilled in the art in relation to this disclosure. Reference numerals may be repeated in all embodiments, but this does not necessarily mean that a component of one embodiment is applicable to another embodiment, even if they use the same reference numerals.

[0123] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited to these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the conceptual guidance of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part.

[0124] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the concepts of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” also include multiple forms. It should be understood that the terms “comprises” and “comprising” as used in this specification indicate the presence of said components, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more components, integers, steps, operations, elements, components, or combinations thereof.

[0125] Figures 1 to 21 The following describes a method for fabricating a semiconductor structure 1 according to some embodiments of this disclosure. (Refer to...) Figure 1 A substrate 10 and a sacrificial structure 20 are provided. Figure 1 A cross-sectional view of the sacrificial structure 20 on the substrate 10 is shown according to some embodiments of the present disclosure. In some embodiments, the substrate 10 may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, group III-V, or group II-VI semiconductor materials.

[0126] In some embodiments, such as Figure 1 As shown, the substrate 10 may include a plurality of semiconductor portions 11, a plurality of isolation portions 12, a capping layer 13, and at least one substrate portion 19. The plurality of semiconductor portions 11 may be spaced apart from each other and arranged in an array. In some embodiments, the semiconductor portions 11 may include a plurality of central semiconductor portions 111 and at least one edge semiconductor portion 112. The plurality of central semiconductor portions 111 may be spaced apart from each other. In some embodiments, the width of the at least one edge semiconductor portion 112 may be greater than the width of the central semiconductor portions 111.

[0127] These isolation portions 12 may also be referred to as "shallow trench isolation." The isolation portions 12 may be disposed between the semiconductor portions 11. In some embodiments, the isolation portions 12 may include, for example, oxide and may be embedded in the substrate 10. In some embodiments, the isolation portions 12 may include a plurality of first isolation portions 121 and a plurality of second isolation portions 122. Each of the first isolation portions 121 may be disposed between two adjacent central semiconductor portions 111 or between at least one edge semiconductor portion 112 and one of the central semiconductor portions 111. The second isolation portions 122 may surround at least one edge semiconductor portion 112. In some embodiments, the width of the second isolation portions 122 may be greater than the width of the first isolation portions 121.

[0128] In some embodiments, from a top view, the edge semiconductor portion 112 may be annular and may surround the central semiconductor portions 111. That is, the edge semiconductor portion 112 may be the outermost portion of the semiconductor portion 11, located in the region defined by the two second isolation portions 122. The edge semiconductor portion 112 may be disposed between the outermost first isolation portion 121 and the second isolation portion 122.

[0129] The capping layer 13 may also be referred to as the "sixth sacrificial layer". The capping layer 13 may be disposed over the semiconductor portions 11 and the isolation portions 12. In some embodiments, the capping layer 13 may include, for example, a nitride.

[0130] At least one liner portion 19 may extend into the second insulating portions 122. In some embodiments, at least one liner portion 19 may contact the cover layer 13. In some embodiments, the liner portion 19 may include, for example, a nitride.

[0131] The sacrificial structure 20 may be disposed on or on the substrate 10. In some embodiments, such as Figure 1As shown, the sacrificial structure 20 may include multiple sacrificial layers (including, for example, a first sacrificial layer 21, a second sacrificial layer 22, a third sacrificial layer 23, a fourth sacrificial layer 24, a fifth sacrificial layer 25, a sixth sacrificial layer 26, and a seventh sacrificial layer 27). These sacrificial layers (e.g., the first sacrificial layer 21, the second sacrificial layer 22, the third sacrificial layer 23, the fourth sacrificial layer 24, the fifth sacrificial layer 25, the sixth sacrificial layer 26, and the seventh sacrificial layer 27) may be stacked on top of each other.

[0132] like Figure 1 As shown, a first sacrificial layer 21 may be formed on a substrate 10 (e.g., a capping layer 13). In some embodiments, the first sacrificial layer 21 may be, for example, a carbon layer. A second sacrificial layer 22 may be formed on the first sacrificial layer 21. In some embodiments, the second sacrificial layer 22 may be, for example, an anti-reflective coating. A third sacrificial layer 23 may be formed on the second sacrificial layer 22. In some embodiments, the third sacrificial layer 23 may be, for example, a carbon layer. A fourth sacrificial layer 24 may be formed on the third sacrificial layer 23. In some embodiments, the fourth sacrificial layer 24 may be, for example, an anti-reflective coating. A fifth sacrificial layer 25 may be formed on the fourth sacrificial layer 24. In some embodiments, the fifth sacrificial layer 25 may be, for example, a carbon layer. A sixth sacrificial layer 26 may be formed on the fifth sacrificial layer 25. In some embodiments, the sixth sacrificial layer 26 may be, for example, a hard mask layer. A seventh sacrificial layer 27 may be formed on the sixth sacrificial layer 26. In some embodiments, the seventh sacrificial layer 27 may be, for example, a photoresist layer.

[0133] Reference Figure 2 and Figure 3 Configure a mask 30 to cover the sacrificial structure 20. Figure 2 A cross-sectional view of a mask 30 configured to cover the sacrificial structure 20 is shown according to some embodiments of this disclosure. Figure 3 A top view of a mask 30 is shown according to some embodiments of the present disclosure. In some embodiments, the mask 30 may include a plurality of transparent portions 31 and a plurality of opaque portions 32. The transparent portions 31 may be spaced apart from each other by the opaque portions 32. The opaque portions 32 may be disposed between the transparent portions 31.

[0134] In some embodiments, the opaque portions 32 may include a plurality of central opaque portions 323, at least one first edge opaque portion 321, and at least one second edge opaque portion 322. The central opaque portions 323 may be spaced apart from each other. At least one second edge opaque portion 322 may be located between at least one first edge opaque portion 321 and the central opaque portions 323. The first edge opaque portion 321 may be the outermost opaque portion. In some embodiments, the width w2 of the second edge opaque portion 322 may be greater than the width w1 of the first edge opaque portion 321 and the width w3 of the central opaque portion 323. The width w1 of the first edge opaque portion 321 may be greater than the width w3 of the central opaque portion 323.

[0135] Reference Figures 4 to 14 Remove part of the sacrificial structure 20. (See reference...) Figure 4 The seventh sacrificial layer 27 (e.g., a photoresist layer) of the portion is removed by means of, for example, photolithography (including exposure and development), through a plurality of central opaque portions 323, at least one first edge opaque portion 321, and at least one second edge opaque portion 322, respectively, to form a plurality of central openings 203, at least one first edge opening 201, and at least one second edge opening 202. These central openings 203, at least one first edge opening 201, and at least one second edge opening 202 extend through the seventh sacrificial layer 27 and expose the sixth sacrificial layer 26 of the portion (e.g., the top surface of the portion). In some embodiments, the width W2 of the second edge opening 202 may be greater than the width W1 of the first edge opening 201 and the width W3 of the central opening 203. The width W1 of the first edge opening 201 may be greater than the width W3 of the central opening 203. The width W1 of the first edge opening 201 may be equal to the width w1 of the first edge opaque portion 321 of the mask 30. The width W2 of the second edge opening 202 can be equal to the width w2 of the second edge opaque portion 322 of the mask 30. The width W3 of the central opening 203 can be equal to the width w3 of the central opaque portion 323.

[0136] Reference Figure 4 and Figure 5 The central opening 203, at least one first edge opening 201, and at least one second edge opening 202 are trimmed and enlarged, for example, by etching. That is, the width W1' of the trimmed first edge opening 201' is greater than... Figure 4 The width W1 of the first edge opening 201 and the width W2' of the trimmed second edge opening 202' are greater than 1. Figure 4 The width W2 of the second edge opening 202 and the width W3' of the trimmed central opening 203' are greater than 1. Figure 4The width W3 of the central opening 203.

[0137] Reference Figure 5 and Figure 6 The sixth sacrificial layer 26 and the fifth sacrificial layer 25 are removed, for example, by dry etching, through a trimmed central opening 203', a trimmed first edge opening 201', and a trimmed second edge opening 202', respectively, to form a plurality of first central openings 2031, at least one third edge opening 2011, and at least one fourth edge opening 2021. In some embodiments, the first central openings 2031 may be formed through the trimmed central opening 203'. The at least one third edge opening 2011 may be formed through the trimmed first edge opening 201'. The at least one fourth edge opening 2021 may be formed through the trimmed second edge opening 202'. The first central openings 2031, at least one third edge opening 2011, and at least one fourth edge opening 2021 extend through the sixth sacrificial layer 26 and the fifth sacrificial layer 25 and expose a portion (e.g., a portion of the top surface) of the fourth sacrificial layer 24.

[0138] Reference Figure 7 The first central opening 2031, at least one third edge opening 2011, and at least one fourth edge opening 2021 are filled by, for example, coating or deposition to form a first material layer 51. In some embodiments, the first material layer 51 may be, for example, an oxide layer.

[0139] Reference Figure 8 The sixth sacrificial layer 26 and a portion of the first material layer 51 are removed, for example, by dry etching, to form a plurality of second central openings 2032, at least one fifth edge opening 2012, and at least one sixth edge opening 2022. Figure 8As shown, each of the second central openings 2032 can be formed in each of the first central openings 2031. The second central opening 2032 can be defined by the portion of the first material layer 51 remaining in the first central opening 2031. At least one fifth edge opening 2012 can be formed in at least one third edge opening 2011. At least one fifth edge opening 2012 can be defined by the portion of the first material layer 51 remaining in the third edge opening 2011. At least one sixth edge opening 2022 can be formed in at least one fourth edge opening 2021. At least one sixth edge opening 2022 can be defined by the portion of the first material layer 51 remaining in the fourth edge opening 2021. Therefore, through the first material layer 51, the first central openings 2031 can be narrowed into the second central openings 2032, at least one third edge opening 2011 can be narrowed into at least one fifth edge opening 2012, and at least one fourth edge opening 2021 can be narrowed into at least one sixth edge opening 2022.

[0140] Reference Figure 8 and Figure 9 The fifth sacrificial layer 25, a portion of the fourth sacrificial layer 24, and a portion of the third sacrificial layer 23 are removed, for example, by dry etching, to form a plurality of third central openings 2033, at least two seventh edge openings 2013, at least one eighth edge opening 2023, and a plurality of first pillars 61. The third central openings 2033, at least two seventh edge openings 2013, and at least one eighth edge opening 2023 extend through the fourth sacrificial layer 24 and the third sacrificial layer 23 and expose a portion (e.g., a portion of the top surface) of the second sacrificial layer 22. At least one eighth edge opening 2023 may be located between the at least two seventh edge openings 2013 and the third central openings 2033. The first pillars 61 may be spaced apart from each other to define the at least two seventh edge openings 2013, at least one eighth edge opening 2023, and the third central openings 2033. In some embodiments, each of the first pillars 61 may include a portion of a first material layer 51, a portion of the fourth sacrificial layer 24, and a portion of the third sacrificial layer 23. In some embodiments, the width of the eighth edge opening 2023 may be greater than the width of the seventh edge opening 2013 and the width of the third central opening 2033.

[0141] Reference Figure 9 and Figure 10 The first material layer 51 and the fourth sacrificial layer 24 are removed, for example, by wet etching, to form a plurality of second pillars 62. These second pillars 62 may be part of the third sacrificial layer 23. Figure 10 The height of these second pillars 62 can be less than Figure 9 The height of these first pillars, 61.

[0142] Reference Figure 11 A second material layer 52 is formed on the second sacrificial layer 22 by, for example, coating or deposition, to cover the second pillars 62, the third central openings 2033, portions of at least two seventh edge openings 2013, and a portion of at least one eighth edge opening 2023. The second material layer 52 may be, for example, an oxide layer. In some embodiments, the thickness T of the second material layer 52 may be less than the height H of the second pillars 62 and the depth d of the at least one eighth edge opening 2023. In some embodiments, the second material layer 52 may not fill the seventh edge openings 2013 and the eighth edge openings 2023. The second material layer 52 may fill the eighth edge opening 2023.

[0143] Reference Figure 12 The second material layer 52 is partially removed by, for example, dry etching to expose the top surface 620 of the second pillars 62 and the top surface of the second sacrificial layer 22, thereby forming at least one through-hole 2024 in at least one eighth edge opening 2023 and at least one ninth edge opening 2014 in the seventh edge opening 2013. The through-hole 2024 may be defined by the portion of the second material layer 52 remaining in the eighth edge opening 2023. The ninth edge opening 2014 may be defined by the portion of the second material layer 52 remaining in the seventh edge opening 2013. In some embodiments, the width of the at least one through-hole 2024 may be greater than the width of the at least one ninth edge opening 2014.

[0144] Reference Figure 12 and Figure 13 The second pillars 62 are removed, for example, by dry etching, to form a plurality of grooves 63. In some embodiments, the grooves 63 may include a plurality of central grooves 631 and a plurality of edge grooves 632. At least one through hole 2024 may be located between the central grooves 631 and the edge grooves 632. At least one ninth edge opening 2014 may be located between the edge grooves 632. In some embodiments, the width of the at least one through hole 2024 may be greater than the width of the grooves 63 (including, for example, the central grooves 631 and the edge grooves 632).

[0145] Reference Figure 14 A third material layer 53 is formed on the second sacrificial layer 22 using, for example, photolithography techniques (including exposure and development) to cover the edge grooves 632. In some embodiments, the third material layer 53 may be, for example, a photoresist layer. Figure 14As shown, the third material layer 53 extends into the edge grooves 632. Therefore, the third material layer 53 can be securely fixed to the second sacrificial layer 22. The third material layer 53 can define an opening 532 to expose at least one perforation 2024 and the central grooves 631. That is, the third material layer 53 may not cover the perforation 2024 and the central grooves 631.

[0146] Reference Figure 14 and Figure 15 At least one edge trench 114 is formed on at least one edge semiconductor portion 112 of the substrate 10 by means of etching, for example, through at least one through-hole 2024; a plurality of central trenches 113 are formed on the central semiconductor portions 111 of the substrate 10 by means of first portions of the central trenches 631; and a plurality of intermediate trenches 115 are formed on the first isolation portions 121 of the substrate 10 by means of second portions of the central trenches 631. Then, the third material layer 53, the second material layer 52, the second sacrificial layer 22, and the first sacrificial layer 21 are removed. Figure 15 As shown, at least one active region moat 118 can be formed between at least one edge trench 114 and a second isolation portion 122. At least one edge trench 114 extends through the capping layer 13 and into a portion of at least one edge semiconductor portion 112. Each of the central trenches 113 extends through the capping layer 13 and into a portion of each of the central semiconductor portions 111. Each of the intermediate trenches 115 extends through the capping layer 13 and into a portion of each of the first isolation portions 121. In some embodiments, the width W5' of the edge trench 114 may be greater than the width W0' of the central trench 113 and the width W4' of the intermediate trench 115. The depth D' of the edge trench 114 may be substantially equal to the depth D0' of the central trench 113. The depth of the intermediate trench 115 may be greater than the depth D' of the edge trench 114 and the depth D0' of the central trench 113.

[0147] Reference Figure 16 The cover layer 13 is thinned by, for example, dry etching.

[0148] Reference Figures 17 to 21 At least one edge character line 102, a plurality of center character lines 103, and a plurality of intermediate character lines 104 are formed on the substrate 10 to obtain the semiconductor structure 1. (Refer to...) Figure 17 An isolation layer 14 is formed, for example, by deposition, in at least one edge trench 114 and the central trenches 113. In some embodiments, the isolation layer 14 may also be referred to as a "gate oxide layer". The isolation layer 14 may include, for example, silicon oxynitride (SiON), silicon oxide, or a high-k dielectric material. Figure 17As shown, the isolation layer 14 covers the sidewalls of at least one edge groove 114 and the sidewalls of the central grooves 113.

[0149] Reference Figure 18 A conductive material 15 is formed, for example by deposition, in the central trenches 113, at least one edge trench 114, and the intermediate trenches 115 to cover a portion of the insulating layer 14. In some embodiments, the conductive material 15 may be, for example, a metallic material. The metallic material may include, for example, tungsten. In some embodiments, such as... Figure 18 As shown, the thickness of the conductive material 15 in at least one edge trench 114 may be the same as the thickness of the conductive material 15 in the central trenches 113. The height of the conductive material 15 in at least one edge trench 114 may be the same as the height of the conductive material 15 in the central trenches 113 and the height of the conductive material 15 in the intermediate trenches 115.

[0150] Reference Figure 19 A polycrystalline silicon layer 16 is formed, for example, by deposition, in the central trenches 113, at least one edge trench 114, and the intermediate trenches 115, and on the conductive material 15. In some embodiments, such as Figure 19 As shown, the thickness of the polysilicon layer 16 in at least one edge trench 114 can be the same as the thickness of the polysilicon layer 16 in the central trenches 113 and the polysilicon layer 16 in the intermediate trenches 115. The height of the polysilicon layer 16 in at least one edge trench 114 can be the same as the height of the polysilicon layer 16 in the central trenches 113 and the polysilicon layer 16 in the intermediate trenches 115. In some embodiments, the thickness of the polysilicon layer 16 can be less than the thickness of the conductive material 15.

[0151] Reference Figure 20 A nitride layer 17 is formed, for example, by deposition, on the capping layer 13, the central trenches 113, at least one edge trench 114, and the intermediate trenches 115, and on the polysilicon layer 16. Simultaneously, at least one edge character line 102, the central character lines 103, and the intermediate character lines 104 are formed. At least one edge character line 102 extends into at least one edge semiconductor portion 112. The central character lines 103 extend into the central semiconductor portions 111. The intermediate character lines 104 extend into the first isolation portions 121. The edge character line 102 may be disposed around the central character lines 103 and the intermediate character lines 104. The edge character line 102 may be disposed between the second isolation portion 122 and the intermediate character line 104. Alternatively, the edge character line 102 may be disposed between the second isolation portion 122 and the central character line 103.

[0152] In some embodiments, the width W5 of the edge character line 102 may be greater than the width W0 of the center character line 103 and the width W4 of the middle character line 104. In some embodiments, the depth D of the edge character line 102 may be substantially equal to the depth D0 of the center character line 103.

[0153] Reference Figure 21 A gate layer 18 is formed on and covers the nitride layer 17 to obtain the semiconductor structure 1. The gate layer 18 may include, for example, an oxide. In some embodiments, the semiconductor structure 1 may be a semiconductor element including circuitry, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

[0154] Furthermore, the semiconductor structure 1 may be or include part of an integrated circuit (IC) chip, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally-diffused MOS (LDMOS), high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0155] like Figure 21 As shown, at least one active region trench 118 may be adjacent to the active region 100 of the semiconductor structure 1.

[0156] like Figures 1 to 21 As shown in the embodiment, mask 30 ( Figure 2 ) Improved to achieve a sacrificial structure of 20 ( Figure 4The central opening 203, at least one first edge opening 201, and at least one second edge opening 202 are defined on the surface. Furthermore, the second material layer 52 ( Figure 11 The thickness T of ) is thinned to define at least one perforation with increased space (or width) 2024 ( Figure 12 Then, the improved edge character line 102 can be obtained through at least one perforation 2024. Figure 21 Improved edge character line 102 ( Figure 21 It has an increased width (e.g., width W) and a deeper depth (e.g., depth D) to extend the channel length of the edge transistor and prevent the formation of deep trenches 118 leading to at least one active region. Figure 21 It is a short-pass channel. Therefore, no additional leakage path will occur.

[0157] In a comparative embodiment, the word lines can be arranged in an array. However, after fabrication, the word line depth at the array edges may be less than the word line depth at the center of the array. That is, transistors adjacent to the array edges will have shorter channel lengths. Therefore, transistors adjacent to the array edges can easily turn on and create short-circuit paths to the deep trenches of the active region, resulting in additional leakage paths.

[0158] Figure 22 A flowchart illustrating a method 90 for fabricating a semiconductor structure according to some embodiments of this disclosure is provided.

[0159] In some embodiments, method 90 may include step S91, providing a sacrificial structure disposed on a substrate. For example, such as Figure 1 As shown, a substrate 10 and a sacrificial structure 20 are provided. The sacrificial structure 20 is disposed on the substrate 10.

[0160] In some embodiments, method 90 may include step S92, configuring a mask to cover the sacrificed structure. For example, as... Figure 2 As shown, mask 30 is configured to cover sacrificial structure 20.

[0161] In some embodiments, method 90 may include step S93, removing a portion of the sacrificial structure using a mask to form a plurality of central openings, at least one first edge opening, and at least one second edge opening. For example, as Figure 4 As shown, a portion of the sacrificial structure 20 is removed by a mask 30 to form a plurality of central openings 203, at least one first edge opening 201, and at least one second edge opening 202.

[0162] In some embodiments, method 90 may include step S94, forming at least one edge character line on the substrate through at least one second edge opening, and forming a plurality of central character lines on the substrate through the central character lines. For example, as Figures 4 to 20 As shown, at least one edge character line 102 is formed on the substrate 10 through at least one second edge opening 202, and the central character lines 103 are formed on the substrate 10 through the central openings 203.

[0163] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0164] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor structure, comprising: A sacrificial structure is provided on a substrate; The sacrificial structure is partially removed to form multiple central openings, at least one edge opening, and multiple columns spaced apart from each other; A second material layer is formed to cover a portion of the columns, the central openings, and the at least one edge opening, wherein a thickness of the second material layer is less than a height of the columns; as well as At least one edge character line is formed on the substrate through the at least one edge opening, and a plurality of central character lines are formed on the substrate through the central openings; After forming the second material layer, the preparation method further includes: Remove part of the second material layer to expose the top surface of the columns and form at least one perforation in the at least one edge opening; The preparation method further includes, after exposing the top surfaces of the columns: Remove the pillars to form a plurality of grooves, wherein the grooves include a plurality of central grooves and a plurality of edge grooves, and the at least one perforation is located between the central grooves and the edge grooves; The preparation method further includes, after forming these grooves: A third material layer is formed to cover these edge grooves; After forming the third material layer, the preparation method further includes: At least one edge groove is formed on the substrate through the at least one perforation, and a plurality of central grooves are formed on the substrate through the central recesses, wherein the width of the at least one edge groove is greater than the width of the central grooves.

2. The method for fabricating a semiconductor structure as claimed in claim 1, wherein the depth of the at least one edge trench is substantially equal to the depth of the central trenches.

3. The method for fabricating a semiconductor structure as claimed in claim 1, wherein after forming the at least one edge trench and the central trenches, the method further comprises: The at least one edge character line is formed in the at least one edge groove, and the central character lines are formed in the central grooves.

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