Carbon nanotube field effect transistor, three-dimensional integrated circuit, and method of manufacturing the same

Abstract

The application provides a preparation method of large-scale position-controllable carbon nanotubes, and a three-dimensional integrated circuit based on carbon nanotube field effect transistor and a preparation method thereof. Specifically, carbon nanotubes with desired properties are uniformly dispersed in a solution; the carbon nanotubes are transferred to a specially designed mold by using a special container; dry ice is used to protect and fix the carbon nanotubes, and then the carbon nanotubes are transferred to a wafer; after multiple transfers, large-scale and position-controllable carbon nanotube channels on the wafer are formed; and finally, the preparation of the integrated circuit is performed. In the above process, after the preparation of a layer of carbon nanotube integrated circuit is completed, an insulating isolation layer can be prepared on the layer, and a three-dimensional integrated circuit with multiple layers stacked can be prepared. The application solves the core problem of preparing a large-scale integrated circuit based on carbon nanotube field effect transistor, opens up a road for integrated circuits in the post-moore era, and creates a new industrial chain and business model of integrated circuits with channel material foundry.

Description

Technical Field

[0001] This invention relates to the field of carbon nanotube field-effect transistors (CNTs) and their integrated circuits, which are important candidate devices for integrated circuits in the post-Moore era. Specifically, it relates to the large-scale integration of carbon nanotubes on a substrate with controllable position, which is the biggest obstacle that CNTs must overcome in the application of large-scale integrated circuits, and their three-dimensional integrated circuits. Background Technology

[0002] The core device of current integrated circuits is the silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET). For nearly 50 years, Moore's Law has successfully guided the reduction of transistor size, making a tremendous contribution to human civilization; however, it has now reached the limits of process technology and physical properties, making further reduction difficult. Exploring the application of new semiconductor materials and devices in large-scale integrated circuits is a crucial fundamental topic in current integrated circuit science and engineering. Carbon nanotube field-effect transistors (CVTs), due to their excellent electrical properties and nanoscale size, are important candidate devices for integrated circuits in the post-Moore's Law era and are widely studied worldwide.

[0003] However, since commonly used carbon nanotubes have diameters of less than a few nanometers and lengths on the micrometer scale, the fabrication of large-scale ordered carbon nanotubes on wafers is theoretically impossible. Even with state-of-the-art methods, the uncertainty of the nanotube termination positions hinders the application of carbon nanotubes in large-scale integrated circuits.

[0004] A team from Peking University in my country has long been a world leader in this field. Their recent work (Science .368, 2020, 850) has demonstrated the fabrication of ordered, high-density carbon nanotubes on 4-inch wafers, achieving excellent electrical properties. Their method for preparing ordered carbon nanotubes involves dispersing carbon nanotubes with desired properties (purity, length, etc.) in a solution, then immersing the wafer in the solution and slowly lifting it. This allows the carbon nanotubes to be adsorbed at the wafer-solution interface and aligned in the same direction. By adjusting the wafer lifting speed and the solution composition, an ordered arrangement of carbon nanotubes can ultimately be formed on the wafer. However, this method has a drawback: because the wafer size (centimeter-scale) is much larger than the length of the carbon nanotubes (micrometer-scale), although unidirectional alignment is achieved, multiple carbon nanotubes may exist along a single line on the wafer surface, with their termination determined by their individual lengths. Therefore, the location of carbon nanotubes on the wafer is highly uncertain and unpredictable. However, the uncertainty and unpredictability of carbon nanotubes as channel materials hinder their application in large-scale integrated circuits.

[0005] To address the aforementioned problems, this invention, based on the method described by Peking University (Science .368, 2020, 850), proposes the following main innovations: First, it employs a carbon nanotube dispersion container with a concave structure, requiring the width of the concave structure to be less than 1.3 times the minimum length of the carbon nanotube, to achieve precise positional control of the carbon nanotubes on the convex structure of the mold. Second, it uses a flat mold with a convex structure, above which is a striped space for carrying carbon nanotubes, requiring the width of the convex structure to be at least 0.7 times the minimum length of the carbon nanotube and less than the width of the concave structure of the container. Then, it aligns the centers of the convex and concave portions of the mold and the container to ensure that each striped space on the mold containing carbon nanotubes has a complete and uninterrupted carbon nanotube. Finally, it uses dry ice to protect and fix the carbon nanotubes on the mold, and transfers the carbon nanotubes to a designated position on a designated substrate. This process is repeated until a wafer-level, position-controllable carbon nanotube channel is formed, achieving large-scale integration of carbon nanotubes on the wafer. This method not only solves the uncertainties and unpredictability of large-scale integration of micro- and nano-sized carbon nanotubes on centimeter-sized wafers, thus removing obstacles and paving the way for the large-scale fabrication and application of carbon nanotube field-effect transistors and their three-dimensional integrated circuits, but also creates a new industrial chain and business model for integrated circuits fabricated using transistor channel materials. Summary of the Invention

[0006] To address the existing technical problems, this invention provides a fabrication process for carbon nanotube field-effect transistors and their integrated circuits, wherein the following characteristic steps are used to achieve a positionally controllable arrangement of carbon nanotubes: (1.1) Carbon nanotubes of the required length and purity are uniformly dispersed into the solution of a container with a concave structure in the inner wall, and the width of the concave structure of the container is less than 1.3 times the minimum length of the carbon nanotubes. (1.2) A flat mold containing a convex structure and a striped space above the convex structure for supporting carbon nanotubes is used, and the width of the convex structure is required to be more than 0.7 times the minimum length of the carbon nanotubes and less than the width of the aforementioned concave structure of the container. (1.3) A coating that is insoluble in the solution of (1.1), can adsorb carbon nanotubes, can decompose, and can be separated from carbon nanotubes after decomposition is applied to the striped space on the convex structure of the above-mentioned flat mold. (1.4) Immerse the above flat mold into the above carbon nanotube dispersion solution, so that the center of the convex structure of the mold is aligned with the center of the concave and convex parts of the concave structure of the container. (1.5) Slowly pull the mold out of the above solution so that the carbon nanotubes in the solution can fill the striped space on the convex structure of the above mold that supports the carbon nanotubes. (1.6) Transfer the mold and invert it on the designated position of the designated substrate to decompose the coating in (1.3) above, so as to realize the controllable arrangement of carbon nanotubes on the substrate. (1.7) Repeat steps (1.3) to (1.6) to achieve the large-scale, position-controllable fabrication of carbon nanotubes on a substrate.

[0007] In the fabrication process of carbon nanotube field-effect transistors and their integrated circuits, the following characteristic steps are used to achieve large-scale integration of carbon nanotubes on a substrate: (2.1) First, carbon nanotubes are transferred to a mold coated with a coating that is insoluble in the carbon nanotube dispersion solution, can adsorb carbon nanotubes, can decompose, and can be separated from carbon nanotubes after decomposition. (2.2) Use dry ice to fix and protect the carbon nanotubes on the above mold for easy transportation; (2.3) Place the mold containing carbon nanotubes upside down on a designated position on a designated substrate; (2.4) Slowly heat up to remove the dry ice and decompose the above coating. Then remove the mold and place the carbon nanotubes on top of the substrate. (2.5) Repeat steps (2.1) to (2.4) above to achieve large-scale integration of carbon nanotubes on the substrate.

[0008] In the fabrication process of carbon nanotube field-effect transistors and their integrated circuits, the following characteristic steps are used to fabricate carbon nanotube integrated circuits: (3.1) First, prepare carbon nanotubes of the required length and purity; (3.2) Dispersion in solution; (3.3) Transfer carbon nanotubes onto a mold to form ordered small carbon nanotube units; (3.4) Fix and protect the positions of the above-mentioned ordered carbon nanotube small units; (3.5) Transfer the mold containing the ordered carbon nanotube miniature units to a designated position on a designated substrate. (3.6) Remove the mold and repeat the steps (3.3) to (3.5) above to achieve large-scale integration of carbon nanotubes on the substrate; (3.7) Fabrication of integrated circuits using large-scale integrated carbon nanotubes.

[0009] After completing the fabrication of a carbon nanotube field-effect transistor and its integrated circuit, an insulating isolation layer is then fabricated on top of it. Following the method described above, another carbon nanotube field-effect transistor and its integrated circuit are fabricated on top of the insulating isolation layer. As needed, multiple layers are fabricated according to the above steps to form a three-dimensional integrated circuit based on carbon nanotube field-effect transistors.

[0010] Another object of the present invention is to provide a three-dimensional integrated circuit based on carbon nanotube field-effect transistors, which has the structural feature of a multilayer structure isolated by an insulating isolation layer. Attached Figure Description

[0011] The following figures are brief descriptions of embodiments of the present invention. In specific implementation, adjustments and additions / deletions can be made according to actual circumstances. Although not all are listed here, they can all be inferred and associated with the present invention, and therefore all fall within the scope of the present invention.

[0012] Figure 1 This is a schematic diagram of the structure of a mold filled with orderly arranged carbon nanotubes, as one embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of the concave structural portion used to disperse carbon nanotube containers.

[0014] Figure 3 This is a schematic diagram of a mold with a convex structure used to arrange carbon nanotubes in an orderly manner.

[0015] Figure 4 This is a schematic diagram of a container for dispersing carbon nanotubes with three concave structures, as one embodiment of the present invention.

[0016] Figure 5 This is a schematic diagram of a mold with three convex structures used for the orderly arrangement of carbon nanotubes.

[0017] Figure 6 A schematic diagram of a mold with three convex structures for the orderly arrangement of carbon nanotubes.

[0018] Figure 7 This is a schematic diagram illustrating the large-scale ordered integration of carbon nanotubes on a wafer using the method proposed in this invention. Detailed Implementation

[0019] The present invention will now be described with reference to the accompanying drawings and examples of embodiments.

[0020] Figure 1This is a schematic diagram of a mold filled with ordered carbon nanotubes, one embodiment of the present invention. 1 represents the mold, and 2 represents the convex structure of the mold. The material of the mold is not particularly important, but it must not react physically or chemically with the solution dispersing the carbon nanotubes. Furthermore, it must not react with the coating that adsorbs carbon nanotubes in subsequent steps, and it must not undergo any physical or chemical changes when the carbon nanotubes are fixed with dry ice, when the dry ice is removed by heating, or when the coating is dissolved and removed from the mold, thus allowing for reuse. 3 represents the structure that separates the carbon nanotubes to form striped spaces. This structure can be made of the same material as 1 or 2, or a new material can be used, but its material requirements are the same as those for 1 and 2, thus allowing for reuse. 4 is a schematic diagram of the ordered carbon nanotubes being supported.

[0021] Figure 2 This is a schematic diagram of the concave structure used to disperse the carbon nanotube container. Components 1, 2, and 3 can be made of the same material or different materials, but all must not react with the solution dissolving the carbon nanotube coating. This concave structure (between 2 and 3 in the diagram) needs to have carbon nanotubes distributed within it. The width of this concave portion (the distance between 2 and 3) is less than 1.3 times the minimum length of the carbon nanotubes. This is to ensure that when extracting carbon nanotubes using a mold later, the mold surface must contain carbon nanotubes, and the ends of these nanotubes are not on the mold itself, meaning they are not broken in the channel portion. Therefore, the carbon nanotubes on the mold, after being transferred to the wafer, can serve as channel materials for field-effect transistors in the fabrication of large-scale integrated circuits.

[0022] Figure 3 This is a schematic diagram of a mold with a convex structure used for the ordered arrangement of carbon nanotubes. The material requirements for its corresponding components are as follows: Figure 1 The same applies. It's important to note that the width of the convex structure is at least 0.7 times the minimum length of the carbon nanotube, but smaller than the width of the concave portion of the mold (otherwise, the convex mold cannot be embedded in the concave portion of the container). Above the convex structure of the mold is a striped space that supports the carbon nanotubes. This striped space can be coated with a coating that is insoluble in the carbon nanotube dispersion solution, capable of adsorbing carbon nanotubes, capable of decomposing, and capable of separating from the carbon nanotubes after decomposition. It should be noted that the adsorption principle of this coating on the carbon nanotubes can be electrostatic adsorption, or physical and chemical adsorption, such as chemical bonds, van der Waals forces, electrostatics, magnetic fields, electric fields, etc. However, after the carbon nanotubes are finally transferred to the substrate through the mold, removing this coating does not affect the physical and chemical properties of the carbon nanotubes.

[0023] Figure 4 , Figure 5 , Figure 6These are all other embodiments of the present invention. Since carbon nanotubes are micrometers in size, while the actual size of the mold is typically millimeters or centimeters, multiple convex structures are usually fabricated on the same mold. Figure 4 , Figure 5 , Figure 6 It has three convex structures on the same mold. Figure 4 This is a schematic diagram of three convex structures on the same mold. Correspondingly, the container holding the carbon nanotube dispersion must also have three parallel concave structures. Figure 5 The schematic diagram after carbon nanotube extraction is as follows: Figure 6 As shown. The content represented by each figure is the same as... Figure 1-3 Correspondingly, it should be noted that in practice, the number is usually much greater than three; or it is also feasible to extract carbon nanotubes from the carbon nanotube dispersion by using multiple molds in parallel.

[0024] Figure 7 This is a schematic diagram illustrating the large-scale ordered integration of carbon nanotubes using the method proposed in this invention on a wafer.

[0025] 1 represents the substrate, typically a silicon wafer used in integrated circuits. It should be noted that insulating layers or various substrates for improving thermal, electrical, and stress properties are usually deposited on the wafer, depending on the specific situation. Alternatively, wafers of other semiconductors (such as III-V group semiconductors) can also be used. 2 represents the large-scale ordered arrangement of carbon nanotubes, usually composed of one or more carbon nanotubes transferred from a mold and arranged in an ordered manner. The distance between each unit can be adjusted during the actual process. After large-scale integration of carbon nanotubes on the wafer, integrated circuits can be fabricated simultaneously on each unit of the entire wafer using conventional semiconductor integrated circuit methods, such as those described in published papers (Science .368, 2020, 850, etc.).

[0026] It should be noted that carbon nanotube field-effect transistors can be either top-gate or gate-all-around. The method proposed in this invention is applicable to various gate types, including the two gate types mentioned above, and has strong versatility. For the top-gate type, the carbon nanotube field-effect transistor can be directly fabricated by following the steps above to prepare a large-scale, ordered arrangement of carbon nanotubes. However, for the gate-all-around type, a sacrificial layer needs to be deposited before transferring the carbon nanotubes onto the wafer. This sacrificial layer is used to etch away the sacrificial layer below the carbon nanotube channel portion during gate fabrication, allowing for the fabrication of the gate oxide and the gate structure of the all-around structure. Additionally, the ALD method is typically used for fabricating the gate oxide and the gate structure of the all-around structure.

[0027] It should be pointed out that, in Figure 1 and Figure 6 In this process, carbon nanotubes have been extracted and arranged in an orderly manner on a mold. To transfer multiple molds onto a wafer, the carbon nanotubes on the molds are typically protected and fixed first. Considering that carbon nanotubes are affected by oxygen and water vapor in the air, this invention proposes using dry ice (solid carbon dioxide) for protection and fixation. Dry ice does not readily react with carbon nanotubes and can be easily removed by heating; furthermore, dry ice has a formation temperature of approximately -78 degrees Celsius, which is higher than other gases such as nitrogen, thus saving costs.

[0028] The large-scale controllable integration of carbon nanotubes on wafers, as proposed in this invention, enables the realization of integrated circuits based on carbon nanotube field-effect transistors (CNTs). After forming a single CNT integrated circuit layer, multiple layers of stacked structures isolated by insulating layers can be fabricated on top to form a three-dimensional integrated circuit. It should be noted that the insulating layer can be a single or multiple thin films, serving both as conductive insulation between layers and as a substrate for the newly formed CNT integrated circuit layer. The devices of the three-dimensional integrated circuit proposed in this invention can be implemented within each layer, for example, using PMOS and NMOS in the first layer to form a CMOS. Alternatively, they can be implemented between layers, for example, fabricating PMOS in the first layer and NMOS in the second layer, thus allowing the PMOS in the first layer to form a CMOS with the NMOS in the second layer. Compared to traditional stacked wafer or chip-based three-dimensional integrated circuits, the above-mentioned three-dimensional integrated circuits reduce the distance between layers, thereby further reducing power consumption and increasing speed. It is precisely because of the method of this invention that the above-mentioned three-dimensional integrated circuit based on carbon nanotube field-effect transistors can be realized for the first time. It should be noted that due to the characteristics of three-dimensional integrated circuits using carbon nanotubes, logic circuits can be fabricated in one layer and memory in another, thus achieving true computing-in-memory, or expanding to system-on-chip. Alternatively, logic circuits can be fabricated in a portion of the same layer, and memory in another portion, also achieving computing-in-memory. Memory, and system on chip.

[0029] In summary, the proposal of this invention not only solves the uncertainties and unpredictability associated with the large-scale integration of micro- and nano-sized carbon nanotubes on wafers, thus removing obstacles and paving the way for the large-scale fabrication and application of carbon nanotube field-effect transistors and their three-dimensional integrated circuits, but also creates a new industrial chain and business model for integrated circuits fabricated using transistor channel materials. That is, for carbon nanotube-based integrated circuits, the integrated circuits themselves can be manufactured in traditional integrated circuit fabs without changing the traditional methods, but the carbon nanotube channels can be manufactured in specialized workshops or companies, thereby forming a new industrial chain and business model.

[0030] Finally, it should be noted that the above-described embodiments (including structures and processes) only illustrate certain implementations of the present invention, and while the descriptions are relatively specific, they should not be construed as limiting the scope of the invention patent. It should be pointed out that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A fabrication process for a carbon nanotube field-effect transistor, characterized in that, The fabrication steps include large-scale, position-controllable carbon nanotube field-effect transistors on a substrate: (1.1) The carbon nanotube field-effect transistors of the required length and purity are uniformly dispersed in the solution of a container with a concave structure in the inner wall, and the width of the concave structure of the container is less than 1.3 times the minimum length of the carbon nanotube field-effect transistor. (1.2) A flat plate mold containing a convex structure and having a striped space above the convex structure to support a carbon nanotube field-effect transistor is used, and the width of the convex structure is required to be more than 0.7 times the minimum length of the carbon nanotube field-effect transistor and less than the width of the aforementioned container concave structure. (1.3) A coating is applied to the striped space on the convex structure of the flat mold that carries the carbon nanotube field-effect transistor. The coating is insoluble in the solution of (1.1), can adsorb the carbon nanotube field-effect transistor, can decompose, and can be separated from the carbon nanotube field-effect transistor after decomposition. (1.4) Immerse the flat mold in the above-mentioned carbon nanotube field effect transistor dispersion solution, so that the center of the convex structure of the mold is aligned with the center of the concave and convex parts of the concave structure of the container. (1.5) Slowly pull the mold out of the above solution so that the carbon nanotube field-effect transistors in the solution can fill the striped space on the convex structure of the above mold that carries the carbon nanotube field-effect transistors. (1.6) Transfer the mold and invert it at a designated position on a designated substrate to decompose the coating in (1.3) above, thereby achieving a controllable arrangement of carbon nanotube field-effect transistors on the substrate. (1.7) Repeat steps (1.3) to (1.6) to achieve the fabrication of large-scale, position-controllable carbon nanotube field-effect transistors on a substrate.

2. The fabrication process of the carbon nanotube field-effect transistor according to claim 1, characterized in that, It also includes the fabrication steps of carbon nanotube field-effect transistors that are mass-integrated on a substrate: (2.1) First, the carbon nanotube field effect transistor is transferred to a mold coated with a coating that is insoluble in the carbon nanotube field effect transistor dispersion solution, can adsorb the carbon nanotube field effect transistor, can decompose, and can be separated from the carbon nanotube field effect transistor after decomposition. (2.2) Use dry ice to fix and protect the carbon nanotube field-effect transistors on the above mold for easy transportation; (2.3) The mold containing the carbon nanotube field-effect transistor is placed upside down on a designated position on a designated substrate; (2.4) Slowly heat up to remove the dry ice and decompose the above coating. Then remove the mold and place the carbon nanotube field-effect transistor on top of the substrate. (2.5) Repeat steps (2.1) to (2.4) above to achieve large-scale integration of carbon nanotube field-effect transistors on the substrate.

3. In the fabrication process of the carbon nanotube field-effect transistor according to claim 1, the characteristic is that, It also includes the step of fabricating an integrated circuit based on the carbon nanotube field-effect transistor: (3.1) First, prepare carbon nanotube field-effect transistors of the required length and purity; (3.2) Dispersion in solution; (3.3) Transfer carbon nanotube field-effect transistors onto a mold to form ordered small units of carbon nanotube field-effect transistors; (3.4) Fix and protect the positions of the ordered carbon nanotube field-effect transistor miniature units; (3.5) Transfer the mold containing the ordered carbon nanotube field-effect transistor miniature units to a specified position on a specified substrate. (3.6) Remove the mold and repeat the steps (3.3) to (3.5) above to achieve large-scale integration of carbon nanotube field-effect transistors on the substrate; (3.7) Fabrication of integrated circuits using large-scale integrated carbon nanotube field-effect transistors.

4. The fabrication process of the carbon nanotube field-effect transistor according to claim 3, characterized in that, After completing the fabrication of a carbon nanotube field-effect transistor and its integrated circuit, an insulating isolation layer is then fabricated on top of it. Following the method described above, another carbon nanotube field-effect transistor and its integrated circuit are fabricated on top of the insulating isolation layer. As needed, multiple layers are fabricated according to the above steps to form a three-dimensional integrated circuit based on carbon nanotube field-effect transistors.

5. A three-dimensional integrated circuit having a carbon nanotube field-effect transistor as described in any one of claims 1-4, characterized by a multilayer structure isolated by an insulating isolation layer.

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