Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a display area and a non-display area located at the periphery of the display area. The non-display area comprises a GOA driving circuit area, a GOA bus area, a fan-out area and a binding area which are sequentially arranged in the direction away from the display area and are located at the same side of the display area. The binding area comprises a plurality of binding lead groups. The fan-out area comprises at least one first GOA signal trace group and a plurality of source fan-out trace groups which are electrically connected with the plurality of binding lead groups one by one. The GOA driving circuit area comprises at least one GOA driving circuit. The GOA bus area comprises a first GOA bus group which is electrically connected with the GOA driving circuit. The first GOA signal trace group is located between two adjacent source fan-out trace groups. One end of the first GOA signal trace group is electrically connected with one or two adjacent binding lead groups, and the other end is electrically connected with the first GOA bus group. The first GOA signal trace group comprises at least a plurality of CK traces. The application can reduce the frame width of the source side.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate and a display panel. Background Technology

[0002] Currently, display substrates are generally fabricated using Gate Driver On Array (GOA) technology. The GOA circuit refers to the scan line driving circuit directly fabricated on the array substrate. The GOA circuit includes multiple cascaded shift registers, each driving one scan line and providing an enable signal to the next-level shift register. Thus, the GOA circuit as a whole can achieve the purpose of enabling scan lines row by row. Because the GOA circuit is located on the source side of the panel (GOAin Source, i.e., source-side panel row driving), the panel is narrow on three sides and wide on one side, which can be used for three-sided splicing. Due to its significant price advantage compared to existing products, it has attracted widespread attention in the industry in recent years.

[0003] GOA-in-Source products require a busline and GOA circuitry on the source side to reduce the width of the other three sides. Typically, a GOA-in-Source design requires first introducing the GOA signal onto the source-side bus. For example... Figure 1 In the array substrate 1' shown, the GOA timing signals, including the clock signal (CK), are introduced into the source-side bus via traces 2' from the two outermost chip-on-film (COF) layers near the frame. However, this design results in the GOA timing signal traces occupying a significant amount of frame space, leading to an increase in the width of the source-side frame and the frame widths on both sides, which is not conducive to achieving a narrow frame design. Summary of the Invention

[0004] This application provides an array substrate and a display panel that can further narrow the bezel width on the source side.

[0005] This application provides an array substrate, including a display area and a non-display area located around the display area; the non-display area includes a GOA driving circuit area, a GOA bus area, a fan-out area, and a bonding area arranged sequentially on the same side of the display area and in a direction away from the display area; the bonding area includes a plurality of bonding lead groups arranged at intervals along a first direction; the fan-out area includes a plurality of source fan-out trace groups and at least one first GOA signal trace group; the plurality of source fan-out trace groups are arranged in a one-to-one correspondence with the plurality of bonding lead groups and are electrically connected; the GOA driving circuit area includes at least one GOA driving circuit; the GOA bus area includes a first GOA bus group extending along the first direction and electrically connected to the GOA driving circuit.

[0006] The first GOA signal trace group is located only between two adjacent source fan-out trace groups; one end of the first GOA signal trace group is electrically connected to one or two adjacent bonding lead groups, and the other end is electrically connected to the first GOA bus group; the first GOA signal trace group includes at least multiple CK traces.

[0007] Optionally, a first GOA signal routing group may be provided between any two adjacent source fan-out routing groups.

[0008] Optionally, the first GOA signal trace group includes a first CK trace group and a second CK trace group; the first CK trace group and the second CK trace group in the same first GOA signal trace group are electrically connected to the two adjacent bonding lead groups in a one-to-one correspondence.

[0009] The first GOA bus group includes a first CK bus group and a second CK bus group; each of the first CK trace groups is electrically connected to the first CK bus group, and each of the second CK trace groups is electrically connected to the second CK bus group.

[0010] Optionally, the first CK routing group includes multiple first CK routing lines; the second CK routing group includes multiple second CK routing lines; the number of first CK routing lines and the number of second CK routing lines are equal.

[0011] The first CK bus group includes multiple first CK buses, and the second CK bus group includes multiple second CK buses; the multiple first CK traces are electrically connected to the multiple first CK buses in a one-to-one correspondence, and the multiple second CK traces are electrically connected to the multiple second CK buses in a one-to-one correspondence.

[0012] Optionally, the fan-out area further includes at least one second GOA signal trace group; the plurality of source fan-out trace groups include a first side and a second side disposed opposite to each other in the first direction; the second GOA signal trace group is located on the first side or the second side; the GOA bus group further includes a second GOA bus group extending along the first direction and electrically connected to the GOA driving circuit; one end of the second GOA signal trace group is electrically connected to the adjacent bonding lead group, and the other end is electrically connected to the second GOA bus group;

[0013] The second GOA signal trace group includes at least low voltage traces, start trigger signal traces, reset signal traces, and low frequency clock signal traces.

[0014] Optionally, the array substrate further includes a cutting area located on the side of the bonding area away from the display area; the cutting area includes a plurality of test pad units that are arranged at intervals along the first direction and have the same structure; each pair of adjacent bonding lead groups is correspondingly arranged with one of the test pad units and electrically connected;

[0015] The test pad unit includes a first test pad group and a second test pad group spaced apart along the first direction, a first lead group and a second lead group electrically connected to the first test pad group, and a third lead group electrically connected to the second test pad group; the first lead group extends from the side of the first test pad group closest to the bonding area; the second lead group extends from the side of the first test pad group away from the bonding area; and the third lead group extends from the side of the second test pad group closest to the bonding area.

[0016] At least one of the bonding lead groups is electrically connected to the corresponding first test pad group via an adjacent first lead group, at least one of the bonding lead groups is electrically connected to the corresponding first test pad group via an adjacent second lead group, and at least one of the bonding lead groups is electrically connected to the corresponding second test pad group via an adjacent third lead group.

[0017] Optionally, the first test pad group includes a first sub-test pad group and a second sub-test pad group; the second sub-test pad group is located between the first sub-test pad group and the second test pad group; the first lead group includes a first sub-lead group connected to the first sub-test pad group and a second sub-lead group connected to the second sub-test pad group; the second lead group includes a third sub-lead group connected to the first sub-test pad group and a fourth sub-lead group connected to the second sub-test pad group.

[0018] Each of the bonding lead groups is electrically connected to the corresponding second sub-test pad group via an adjacent second sub-lead group or the fourth sub-lead group; at least one of the bonding lead groups is electrically connected to the corresponding first sub-test pad group via an adjacent first sub-lead group or the third sub-lead group; the first sub-test pad includes at least one of a power supply voltage test pad, a low-frequency clock signal test pad, a first common electrode voltage test pad, and a start trigger signal test pad; the second sub-test pad group is used to connect to the source test signal.

[0019] Optionally, the second test pad group includes a first CK test pad group, a second common electrode voltage test pad, and a second CK test pad group arranged sequentially at intervals in the first direction; the third lead group includes a first CK lead group, a common electrode voltage lead, and a second CK lead group that are electrically connected to the first CK test pad group, the second common electrode voltage test pad, and the second CK test pad group in a one-to-one correspondence.

[0020] Each pair of adjacent bonding lead groups is electrically connected to the first CK lead group and the second CK lead group in the corresponding test pad unit.

[0021] Optionally, the plurality of source fan-out trace groups include a first side and a second side disposed opposite to each other in the first direction; the fan-out area also includes a second GOA signal trace group located on the first side and the second side respectively; the plurality of bonding lead groups include a first bonding lead group near the first side, a second bonding lead group near the second side, and a plurality of third bonding lead groups located between the first bonding lead group and the second bonding lead group;

[0022] The first bonding lead group is electrically connected to the second GOA signal trace group located on the first side, and is electrically connected to the corresponding first sub-test pad group through an adjacent first sub-lead group; the second bonding lead group is electrically connected to the second GOA signal trace group located on the second side, and is electrically connected to the corresponding first sub-test pad group through an adjacent third sub-lead group; the first bonding lead group and the plurality of third bonding lead groups are all electrically connected to the corresponding second sub-test pad group through an adjacent second sub-lead group; the second bonding lead group is electrically connected to the corresponding second sub-test pad group through an adjacent fourth sub-lead group.

[0023] This application also provides a display panel, including an opposing substrate and the array substrate described above; the opposing substrate and the array substrate are disposed opposite to each other.

[0024] The array substrate and display panel provided in this application can improve the utilization rate of WOA space by setting the CK trace only between two adjacent source fan-out trace groups, which is beneficial to further narrowing the bezel width, especially the bezel width on the source side; at the same time, it can also improve the temperature rise problem of the WOA area on both sides of the array substrate. Attached Figure Description

[0025] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0026] Figure 1 This is a partial structural schematic diagram of an exemplary array substrate.

[0027] Figure 2 This is a partial structural schematic diagram of another exemplary array substrate.

[0028] Figure 3 This is a top view of an array substrate provided in an embodiment of this application.

[0029] Figure 4 for Figure 3 A schematic diagram of the structure of the non-display area in the middle.

[0030] Figure 5 for Figure 4 A magnified view of a portion of region A in the middle.

[0031] Figure 6 This is a top view of the array substrate before the cutting area is cut, as shown in the embodiment of this application.

[0032] Figure 7 This is a schematic diagram of the structure of a test pad unit provided in an embodiment of this application.

[0033] Figure 8 This is a schematic diagram showing the connection between adjacent first and third binding lead groups and the test pad unit, as provided in an embodiment of this application.

[0034] Figure 9 This is a schematic diagram showing the connection between adjacent second and third binding lead groups and the test pad unit, provided in an embodiment of this application.

[0035] Figure 10 This is a schematic diagram showing the connection between two adjacent third binding lead groups and the test pad unit provided in an embodiment of this application.

[0036] Figure 11 This is a schematic cross-sectional view of a display panel provided in an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0039] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0040] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0041] like Figure 2As shown, in an exemplary array substrate 1”, in order to reduce the delay (RC loading) problem on the bus, a set of CK traces 2” are led out from both sides of each COF to the bus. However, in this design, two sets of CK traces 2” are located near the left and right edges, which still occupy a lot of space of the array substrate traces (WOA, wire on array), making the edge width on the source side larger, which is not conducive to achieving the goal of reducing the edge width.

[0042] To further reduce the width of the panel bezel, this application provides a new array substrate and display panel, as described in the following embodiments.

[0043] like Figures 3 to 10 As shown, this application embodiment provides an array substrate 1. As... Figure 3 As shown, the array substrate 1 includes a display area 2 and a non-display area 3 located around the display area 2. The non-display area 3 includes a GOA driving circuit area 4, a GOA bus area 5, a fan-out area 6, and a bonding area 7, which are located on the same side of the display area 2 (e.g., the upper side of the display area 2) and arranged sequentially in a direction away from the display area 2. The bonding area 7 includes a plurality of bonding lead groups 8 arranged at intervals in a first direction; the fan-out area 6 includes a plurality of source fan-out trace groups 9 and at least one first GOA signal trace group 10; the plurality of source fan-out trace groups 9 are arranged one-to-one with the plurality of bonding lead groups 8 and are electrically connected. The GOA driving circuit area 4 includes at least one GOA driving circuit 11; the GOA bus area 5 includes a first GOA bus group 12 extending in the first direction and electrically connected to the GOA driving circuit 11. The first GOA signal trace group 10 is located only between two adjacent source fan-out trace groups 9; one end of the first GOA signal trace group 10 is electrically connected to one or two adjacent bonded lead groups 8, and the other end is electrically connected to the first GOA bus group 12; the first GOA signal trace group 10 includes at least a plurality of clock signal (CK) traces.

[0044] Specifically, the display area 2 includes multiple scan lines 13 extending in parallel along a first direction (e.g., horizontal) and multiple data lines (not shown in the figure) extending in parallel along a second direction (e.g., vertical), with the first and second directions perpendicular to each other. The multiple scan lines 13 and the data lines are insulated from each other and intersect to form multiple pixel areas. Each pixel area forms a pixel circuit (not shown in the figure) for driving the display. The data lines and scan lines 13 provide data signals and scan signals to the corresponding pixel circuits, respectively.

[0045] For ease of description, the following explanation will use the example of the first direction being horizontal and the second direction being vertical.

[0046] Specifically, the number of bonding lead groups 8 includes, but is not limited to, 4, 6, 9, 12, 16, or 24. Understandably, each bonding lead group 8 includes multiple bonding leads, and the area containing each bonding lead group 8 is used for soldering driver chips (e.g., COF). Specifically, the driver chip is soldered (electrically connected) to multiple bonding leads in the bonding lead group 8.

[0047] Specifically, in this embodiment of the application, a driver chip, such as a COF, can be soldered onto each bonding lead group 8; and the driver chip can access or output electrical signals through the bonding lead group 8.

[0048] Specifically, such as Figure 5 As shown, each source fan-out trace group 9 includes multiple source fan-out traces 14 arranged in a fan shape. These multiple source fan-out traces 14 extend towards the display area 2 and are electrically connected to multiple data lines in a one-to-one correspondence, providing data signals (source signals) to the data lines. It can be understood that the multiple data lines can be divided into multiple data line groups corresponding one-to-one with the multiple source fan-out trace groups 9, and each bonding lead group 8 outputs data signals to the data lines in the corresponding multiple data line groups through the corresponding source fan-out trace group 9.

[0049] Specifically, the GOA driving circuit 11 includes multiple cascaded GOA units (shift registers), for example, each GOA driving circuit 11 includes 2160 GOA units, but is not limited to this. Multiple GOA units are electrically connected one-to-one with multiple scan lines 13 to provide scan signals to the scan lines 13. It can be understood that the GOA driving circuit 11 can control the scan lines 13 in the entire display area 2 to be turned on line by line.

[0050] It should be noted that the number of GOA drive circuits 11 in the GOA drive circuit area 4 is not limited in the embodiments of this application. For example, a two-drive GOA, a three-drive GOA, or a four-drive GOA design can be adopted, but it is not limited to this.

[0051] Figure 3 The array substrate 1 shown is a four-drive GOA design, meaning that the GOA drive circuit area 4 has four GOA drive circuits 11 (GOA1, GOA2, GOA3, and GOA4). Multiple GOA units in each GOA drive circuit 11 are electrically connected one-to-one with multiple scan lines 13 in the entire display area 2. Specifically, the four GOA drive circuits 11 are arranged sequentially along a first direction, and the dashed arrows in the figure represent the scanning direction.

[0052] Specifically, the number of first GOA signal trace groups 10 can be one or more. When the number of first GOA signal trace groups 10 is one, the first GOA signal trace group 10 is located between any pair of adjacent source fan-out trace groups 9; when the number of first GOA signal trace groups 10 is multiple, only one GOA signal trace group is set between each pair of adjacent source fan-out trace groups 9.

[0053] like Figure 3 As shown, this embodiment of the application will be described using the example of a first GOA signal trace group 10 located between any two adjacent source fan-out trace groups 9. Specifically, the first GOA signal trace group 10 is used to transmit a first GOA signal, such as a CK signal. This design allows the first GOA signal to be accessed at different locations of the first GOA bus group 12, which can effectively reduce the signal delay of the first GOA bus group 12 and improve the display effect. At the same time, placing the first GOA signal trace group 10 between two adjacent source fan-out trace groups 9 can improve the utilization rate of the WOA space, which is beneficial to further narrowing the bezel width, especially the bezel width on the source side.

[0054] Specifically, such as Figures 3 to 5 As shown, the first GOA signal trace group 10 includes a first CK trace group 15 and a second CK trace group 16; the first CK trace group 15 and the second CK trace group 16 in the same first GOA signal trace group 10 are electrically connected to two adjacent bonding lead groups 8 in a one-to-one correspondence. Correspondingly, the first GOA bus group 12 includes a first CK bus group 19 and a second CK bus group 20; each first CK trace group 15 is electrically connected to the first CK bus group 19, and each second CK trace group 16 is electrically connected to the second CK bus group 20.

[0055] Specifically, such as Figure 5 As shown, the first CK trace group 15 includes multiple first CK traces 17; the second CK trace group 16 includes multiple second CK traces 18; the number of first CK traces 17 is equal to the number of second CK traces 18. The first CK bus group 19 includes multiple first CK buses 21, and the second CK bus group 20 includes multiple second CK buses 22; the multiple first CK traces 17 are electrically connected to the multiple first CK buses 21 in a one-to-one correspondence, and the multiple second CK traces 18 are electrically connected to the multiple second CK buses 22 in a one-to-one correspondence.

[0056] It should be noted that each first GOA signal trace group 10 includes 2N CK traces, where N is a positive integer; the first CK trace group 15 includes N first CK traces 17, and the second CK trace group 16 includes N second CK traces 18. In this embodiment, taking each first GOA signal trace group 10 as an example with 12 CK traces, the number of first CK traces 17 and second CK traces 18 is 6; correspondingly, the number of first CK buses 21 and second CK buses 22 is also 6. Figure 5 As shown, the first CK bus group 19 includes buses CK1 to CK6, and the first CK bus group 20 includes buses CK7 to CK12.

[0057] Specifically, such as Figure 4 As shown, the plurality of source fan-out trace groups 9 include a first source fan-out trace group 23 and a second source fan-out trace group 24 disposed opposite to each other in a first direction and respectively close to the left and right edges of the array substrate 1, and a plurality of third source fan-out trace groups 25 located between the first source fan-out trace group 23 and the second source fan-out trace group 14. It can be understood that the first source fan-out trace group 23 is the leftmost source fan-out trace group 9, and the second source fan-out trace group 24 is the rightmost source fan-out trace group 9.

[0058] The first source fan-out routing group 23 has a first CK routing group 15 on the side near the third source fan-out routing group 25, the second source fan-out routing group 24 has a second CK routing group 16 on the side near the third source fan-out routing group 25, and each third source fan-out routing group 25 has a second CK routing group 16 on the side near the first source fan-out routing group 23, and each third source fan-out routing group 25 has a first CK routing group 15 on the side near the second source fan-out routing group 24.

[0059] Specifically, such as Figure 4 As shown, the plurality of bonding lead groups 8 include a first bonding lead group 26 and a second bonding lead group 27 disposed opposite to each other in a first direction and respectively close to the left and right edges of the array substrate 1, and a plurality of third bonding lead groups 28 located in the first bonding lead group 26 and the second bonding lead group 27. It can be understood that the first bonding lead group 26 and the second bonding lead group 27 are the leftmost and rightmost bonding lead groups 8, respectively.

[0060] Specifically, each bonding lead group 8 includes a source signal terminal group (not shown in the figure) connected to a corresponding source fan-out routing group 9; the first bonding lead group 26 also includes a first CK signal terminal group (not shown in the figure) located on the side of the source signal terminal group near the third bonding lead group 28; the second bonding lead group 27 also includes a second CK signal terminal group (not shown in the figure) located on the side of the source signal terminal group near the third bonding lead group 28; the third bonding lead group 28 also includes a second CK signal terminal group located on the side of the source signal terminal group near the first bonding lead group 26 and a first CK signal terminal group located on the side of the source signal terminal group near the second bonding lead group 27. Each first CK signal terminal group is electrically connected to a corresponding first CK routing group 15, and each second CK signal terminal group is electrically connected to a corresponding second CK routing group 16.

[0061] In one specific implementation, such as Figure 3 As shown, there are 12 source fan-out routing groups 9, 12 bonding lead groups 8, and 11 first GOA signal routing groups 10. From left to right, a first CK routing group 15 is provided on the right side of the first source fan-out routing group 9. Each of the second to eleventh source fan-out routing groups 9 has a second CK routing group 16 on its left and a first CK routing group 15 on its right. A second CK routing group 16 is provided on the left side of the twelfth source fan-out routing group 9. Correspondingly, from left to right, the first CK signal terminal group of the first bonding lead group 8 is electrically connected to the corresponding first CK trace group 15; in the second to eleventh bonding lead groups 8, the first CK signal terminal group of each bonding lead group 8 is electrically connected to the corresponding first CK trace group 15, and the second CK signal terminal group of each bonding lead group 8 is electrically connected to the corresponding second CK trace group 16; the second CK signal terminal group in the twelfth bonding lead group 8 is electrically connected to the corresponding second CK trace group 16.

[0062] Understandably, the first CK signal terminal group includes 6 CK signal terminals, and the second CK signal terminal group includes 6 CK signal terminals; each CK signal terminal is connected to a corresponding CK trace.

[0063] Specifically, such as Figure 4 As shown, the fan-out area 6 also includes at least one second GOA signal trace group 29; multiple source fan-out trace groups 9 are included on a first side 30 and a second side 31 disposed opposite each other in a first direction; the second GOA signal trace group 29 is located on the first side 30 or the second side 31. Correspondingly, the GOA bus group also includes a second GOA bus group 32 extending along the first direction and electrically connected to the GOA drive circuit 11. One end of the second GOA signal trace group 29 is electrically connected to an adjacent bonding lead group 8, and the other end is electrically connected to the second GOA bus group 32.

[0064] In one specific embodiment, there are two second GOA signal trace groups 29, and the two second GOA signal trace groups 29 are located on the first side 30 and the second side 31, respectively. Furthermore, the first bonding lead group 26 located near the first side 30 also includes a GOA signal terminal group (not shown in the figure) located on the side of the source signal terminal group away from the third bonding lead group 28, which is connected to the corresponding second GOA signal trace group 29; the third bonding lead group 28 located near the second side 31 also includes a GOA signal terminal group located on the side of the source signal terminal group away from the third bonding lead group 28, which is connected to the corresponding second GOA signal trace group 29.

[0065] Understandably, the first side 30 is the side of the first source fan-out routing group 23 that is far away from the third source fan-out routing group 25, and the second side 31 is the side of the second source fan-out routing group 24 that is far away from the third source fan-out routing group 25.

[0066] Specifically, each second GOA signal trace group 29 includes multiple GOA signal traces for transmitting the second GOA signal. In one specific embodiment, the second GOA signal trace group 29 includes at least a low voltage (VSS) trace, a start trigger signal (STV) trace, a reset signal (Reset) trace, and a low frequency clock signal (LC) trace, but is not limited to these. That is, the second GOA signal can be any GOA signal other than the CK signal.

[0067] It is understood that the array substrate 1 provided in this application embodiment is a substrate without CK design on both sides.

[0068] For a 12CK array substrate, if through Figure 2 The design method shown places the CK traces on both sides of each COF (equivalent to the bonding lead group in this application). When the GOA line width and spacing (unit: μm) L / S is 30 / 30, the WOA width required for one set of CK traces is approximately 720 μm, and the WOA width required for other signal traces is approximately 600 μm. Therefore, the width requirement on the source side of the WOA region is approximately 1320 μm. However, using... Figure 3 The design method shown, which groups the CK traces between every two adjacent bonded lead groups (specifically between two adjacent source fan-out trace groups), can save up to 720µm of space, which is beneficial for narrowing the source-side bezel width. Furthermore, it has been verified that… Figure 3 The design method shown has very little impact on bus latency and improves the temperature rise in the WOA areas on both sides of the panel.

[0069] For an 8CK array substrate, if through Figure 2The design method shown places the CK traces on both sides of each COF. When the GOA trace width and spacing (in μm) L / S is 40 / 40, the required WOA width for one set of CK traces is approximately 640 μm, and the required WOA width for other signal traces is approximately 750 μm. Therefore, the required width on the source side of the WOA region is approximately 1320 μm. However, using... Figure 3 The design method shown, which groups the CK traces between every two adjacent bonded lead groups (specifically between two adjacent source fanout trace groups), can save up to 640µm of space, which is beneficial for narrowing the source-side bezel width. This has been verified. Figure 3 The design method shown has very little impact on bus latency and improves the temperature rise in the WOA areas on both sides of the panel.

[0070] Therefore, by placing the CK trace between two adjacent source fan-out trace groups 9, the utilization rate of the WOA space can be improved, which is beneficial to further narrowing the bezel width, especially the bezel width on the source side; at the same time, it can also improve the temperature rise problem of the WOA region on both sides of the array substrate 1.

[0071] Specifically, such as Figure 6 and Figure 7 As shown, the array substrate 1 also includes a cutting area 33 located on the side of the bonding area 7 away from the display area 2; the cutting area 33 includes a plurality of test pad units 34 that are arranged at intervals along the first direction and have the same structure; each pair of adjacent bonding lead groups 8 is correspondingly arranged with a test pad unit 34 and electrically connected.

[0072] Understandably, the test pad unit 34 is used to test the GOA signal and source signal on the array substrate 1. After the test is completed, the cutting area 33 on the array substrate 1 will be cut off to further narrow the bezel.

[0073] Specifically, such as Figure 7As shown, the test pad unit 34 includes a first test pad group 35 and a second test pad group 36 spaced apart along a first direction, a first lead group 37 and a second lead group 38 electrically connected to the first test pad group 35, and a third lead group 39 electrically connected to the second test pad group 36. The first lead group 37 extends from the side of the first test pad group 35 closest to the bonding area 7; the second lead group 38 extends from the side of the first test pad group 35 furthest from the bonding area 7; and the third lead group 39 extends from the side of the second test pad group 36 closest to the bonding area 7. At least one bonding lead group 8 is electrically connected to a corresponding first test pad group 35 via an adjacent first lead group 37, at least one bonding lead group 8 is electrically connected to a corresponding first test pad group 35 via an adjacent second lead group 38, and at least one bonding lead group 8 is electrically connected to a corresponding second test pad group 36 via an adjacent third lead group 39.

[0074] Understandably, each pad in the first test pad group 35 has leads on both the top and bottom sides. The binding lead group 8 can be connected via the leads on the top or bottom sides according to the actual situation, making the wiring layout more reasonable.

[0075] Specifically, such as Figure 7 As shown, the first test pad group 35 includes a first sub-test pad group 40 and a second sub-test pad group 41; the second sub-test pad group 41 is located between the first sub-test pad group 40 and the second test pad group 36. The first lead group 37 includes a first sub-lead group 42 connected to the first sub-test pad group 40 and a second sub-lead group 43 connected to the second sub-test pad group 41. The second lead includes a third sub-lead group 44 connected to the first sub-test pad group 40 and a fourth sub-lead group 45 connected to the second sub-test pad group 41.

[0076] Specifically, the first sub-test pad group 40 includes at least one of the following: power supply voltage test pad, low-frequency clock signal test pad, first common electrode voltage test pad, and start-trigger signal test pad. For example, the first sub-test pad group 40 includes at least one of the following: operating voltage (VGH) test pad, regulated voltage (VSSG / VSSQ) test pad, low-frequency clock signal (LC) test pad, first common electrode voltage (A_COM) test pad, shield voltage (GBS / DBS) test pad, and start-trigger signal (STV) test pad, but is not limited thereto.

[0077] Specifically, the second sub-test pad group 41 includes at least one source signal test pad, such as a red data (Data_R) test pad, a green (Data_G) data test pad, and a blue (Data_B) data test pad.

[0078] Understandably, the first sub-test pad group 40 is electrically connected to the second GOA signal trace group 29 for testing the second GOA signal; the second sub-test pad group 41 is electrically connected to the source fan-out trace group 9 for testing the source signal.

[0079] Specifically, the number of test pads in the first sub-test pad group 40 can be equal to the number of traces in the second GOA signal trace group 29, but it is not limited to this, as long as the first sub-test pad group 40 can test all the second GOA signals.

[0080] Specifically, since each source fan-out trace group 9 corresponds to a bonding lead group 8, each bonding lead group 8 is electrically connected to the corresponding second sub-test pad group 41 through the adjacent second sub-lead group 43 or fourth sub-lead group 45, for testing source signals.

[0081] Specifically, at least one bonding lead group 8 (e.g., the first bonding lead group 26 and the second bonding lead group 27) is electrically connected to the corresponding first sub-test pad group 40 via an adjacent first sub-lead group 42 or third sub-lead group 44 for testing the second GOA signal. Understandably, the bonding lead group 8 electrically connected to the first sub-test pad group is also electrically connected to the second GOA signal trace group 29.

[0082] Specifically, such as Figure 7 As shown, the second test pad group 36 includes a first CK test pad group 46, a second common electrode voltage (e.g., CF_COM) test pad 47, and a second CK test pad group 48, which are sequentially spaced apart in a first direction; the third lead group 39 includes a first CK lead group 49, a common electrode voltage lead 50, and a second CK lead group 51, which are electrically connected to the first CK test pad group 46, the second common electrode voltage test pad 47, and the second CK test pad group 48 in a one-to-one correspondence. Each pair of adjacent bonding lead groups 8 is electrically connected to the first CK lead group 49 and the second CK lead group 51 in the corresponding test pad unit 34 in a one-to-one correspondence.

[0083] Specifically, the first CK test pad group 46 includes a plurality of first CK test pads 52 arranged at intervals in a first direction, and the second CK test pad group 48 includes a plurality of second CK test pads 53 arranged at intervals in a first direction; the number of the plurality of first CK test pads 52 and the plurality of second CK test pads 53 are equal, for example, 6 in each. It can be understood that the plurality of first CK test pads 52 are electrically connected one-to-one with the plurality of first CK traces 17 in the first CK trace group 15, and the plurality of second CK test pads 53 are electrically connected one-to-one with the plurality of second CK traces 18 in the second CK trace group 16.

[0084] In one specific embodiment, the plurality of bonding lead groups 8 include a first bonding lead group 26 and a second bonding lead group 27 disposed opposite to each other in a first direction and respectively close to the left and right edges of the array substrate 1, and a plurality of third bonding lead groups 28 located in the first bonding lead group 26 and the second bonding lead group 27. Figures 8 to 10 As shown, the first bonding lead group 26 is electrically connected to the corresponding first sub-test pad group 40 via an adjacent first sub-lead group 42; the second bonding lead group 27 is electrically connected to the corresponding first sub-test pad group 40 via an adjacent third sub-lead group 44; the first bonding lead group 26 and multiple third bonding lead groups 28 are all electrically connected to the corresponding second sub-test pad group 41 via an adjacent second sub-lead group 43; the second bonding lead group 27 is electrically connected to the corresponding second sub-test pad group 41 via an adjacent fourth sub-lead group 45. This design can reduce wiring crossovers and make the wiring more reasonable.

[0085] It should be noted that any two test pad units 34 in this embodiment have the same structure. Since only the first binding lead group 26 and / or the second binding lead group 27 are electrically connected to the corresponding second GOA signal trace group 29 for outputting the second GOA signal, only the first binding lead group 26 and / or the second binding lead group 27 are electrically connected to the corresponding first sub-test pad group 40 through the adjacent first sub-lead group 42 or third sub-lead group 44. It can be understood that the first sub-lead group 42 or the third sub-lead group 44 that is not connected to the binding lead group 8 is in a floating state. Similarly, the second sub-test pad group 41 used for testing the source signal is provided with a second sub-lead group 43 and a fourth sub-lead group 45 on both sides, and each binding lead group 8 is connected to the corresponding second sub-test pad group 41 through the adjacent second sub-lead group 43 or the fourth sub-lead group 45, so that the second sub-lead group 43 or the fourth sub-lead group 45 that is not connected to the binding lead group 8 is in a floating state.

[0086] Since each test pad unit 34 has the same structure, each first GOA signal trace group 10 has the same structure, each third bonding lead group 28 has the same structure, and each third source fan-out trace group 25 has the same structure, the test pad unit 34 provided in this application embodiment can also be applied to mask splicing technology when providing test pads for each bonding lead group 8, that is, it can be applied to large-size splicing design.

[0087] Specifically, during the fabrication of the array substrate 1, the area controlled by each third bonding lead group 28 can be fabricated using Mask splicing technology. For example, the area controlled by one third bonding lead group 28 can be set as a repeating area, and multiple areas controlled by the third bonding lead group 28 can be fabricated by splicing the same Mask. In this process, multiple test pad units 34 with the same structure can be formed.

[0088] For example, such as Figure 6 As shown, there are 12 bonding lead groups 8, 11 first GOA signal trace groups 10, and 11 test pad units 34. The first GOA signal trace groups 10 and test pad units 34 are correspondingly arranged, and each test pad unit 34 is correspondingly arranged with two adjacent bonding lead groups 8. The area controlled by the second to eleventh bonding lead groups 8 can be evenly divided into 10 repeating regions 54. Each repeating region 54 corresponds to one bonding lead group 8, and the structure in each repeating region 54 can be made using the same mask. That is to say, the area controlled by the second to eleventh bonding lead groups 8 is made by splicing masks, and in this process, multiple test pad units 34 with the same structure can be formed.

[0089] Therefore, the array substrate 1 provided in this application embodiment can be applied to Mask splicing technology on the basis of narrowing the width of the source side bezel, which is beneficial for manufacturing large-size source side panel row driving panel products.

[0090] This application also provides a test pad unit 34 as described in the foregoing embodiments, which will not be repeated here.

[0091] like Figure 11 As shown, this application embodiment also provides a display panel 55, which includes a counter substrate 56 and an array substrate 1 as described in the foregoing embodiment; the counter substrate 56 is disposed opposite to the array substrate 1.

[0092] Specifically, the display panel 55 is a liquid crystal display panel 55; the display panel 55 also includes a color filter and a liquid crystal layer 57, the color filter is located on the opposing substrate 56 or the array substrate 1, and the liquid crystal layer 57 is located between the array substrate 1 and the opposing substrate 56.

[0093] Specifically, the display panel 55 can be a splicing panel, for example, including multiple splicing units, each splicing unit including an opposing substrate 56 and the array substrate 1 described in the aforementioned embodiments.

[0094] In addition to the advantages of the aforementioned embodiments, the embodiments of this application also facilitate obtaining a large-size splicing display panel 55 with a narrow bezel.

[0095] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0096] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, The system includes a display area and a non-display area located around the display area. The non-display area includes a GOA driver circuit area, a GOA bus area, a fan-out area, and a bonding area, which are sequentially arranged on the same side of the display area and in a direction away from the display area. The bonding area includes a plurality of bonding lead groups that are sequentially spaced apart along a first direction. The fan-out area includes a plurality of source fan-out trace groups and at least one first GOA signal trace group. The plurality of source fan-out trace groups are arranged in a one-to-one correspondence with the plurality of bonding lead groups and are electrically connected. The GOA driver circuit area includes at least one GOA driver circuit. The GOA bus area includes a first GOA bus group that extends along the first direction and is electrically connected to the GOA driver circuit. The first GOA signal trace group is located only between two adjacent source fan-out trace groups; one end of the first GOA signal trace group is electrically connected to one or two adjacent bonding lead groups, and the other end is electrically connected to the first GOA bus group; the first GOA signal trace group includes at least multiple CK traces.

2. The array substrate according to claim 1, characterized in that, A first GOA signal routing group is provided between any two adjacent source fan-out routing groups.

3. The array substrate according to claim 1 or 2, characterized in that, The first GOA signal trace group includes a first CK trace group and a second CK trace group; the first CK trace group and the second CK trace group in the same first GOA signal trace group are electrically connected to the two adjacent bonding lead groups in a one-to-one correspondence. The first GOA bus group includes a first CK bus group and a second CK bus group; each of the first CK trace groups is electrically connected to the first CK bus group, and each of the second CK trace groups is electrically connected to the second CK bus group.

4. The array substrate according to claim 3, characterized in that, The first CK routing group includes multiple first CK routing lines; the second CK routing group includes multiple second CK routing lines; the number of first CK routing lines and the number of second CK routing lines are equal. The first CK bus group includes multiple first CK buses, and the second CK bus group includes multiple second CK buses; the multiple first CK traces are electrically connected to the multiple first CK buses in a one-to-one correspondence, and the multiple second CK traces are electrically connected to the multiple second CK buses in a one-to-one correspondence.

5. The array substrate according to claim 1, characterized in that, The fan-out area further includes at least one second GOA signal trace group; the plurality of source fan-out trace groups include a first side and a second side disposed opposite to each other in the first direction; the second GOA signal trace group is located on the first side or the second side; the GOA bus group further includes a second GOA bus group extending along the first direction and electrically connected to the GOA drive circuit; one end of the second GOA signal trace group is electrically connected to the adjacent bonding lead group, and the other end is electrically connected to the second GOA bus group; The second GOA signal trace group includes at least low voltage traces, start trigger signal traces, reset signal traces, and low frequency clock signal traces.

6. The array substrate according to claim 3, characterized in that, The array substrate further includes a cutting area located on the side of the bonding area away from the display area; the cutting area includes a plurality of test pad units that are arranged at intervals along the first direction and have the same structure; each pair of adjacent bonding lead groups is correspondingly arranged with one of the test pad units and electrically connected. The test pad unit includes a first test pad group and a second test pad group spaced apart along the first direction, a first lead group and a second lead group electrically connected to the first test pad group, and a third lead group electrically connected to the second test pad group; the first lead group extends from the side of the first test pad group closest to the bonding area; the second lead group extends from the side of the first test pad group away from the bonding area; and the third lead group extends from the side of the second test pad group closest to the bonding area. At least one of the bonding lead groups is electrically connected to the corresponding first test pad group via an adjacent first lead group, at least one of the bonding lead groups is electrically connected to the corresponding first test pad group via an adjacent second lead group, and at least one of the bonding lead groups is electrically connected to the corresponding second test pad group via an adjacent third lead group.

7. The array substrate according to claim 6, characterized in that, The first test pad group includes a first sub-test pad group and a second sub-test pad group; the second sub-test pad group is located between the first sub-test pad group and the second test pad group; the first lead group includes a first sub-lead group connected to the first sub-test pad group and a second sub-lead group connected to the second sub-test pad group; the second lead group includes a third sub-lead group connected to the first sub-test pad group and a fourth sub-lead group connected to the second sub-test pad group; Each of the bonding lead groups is electrically connected to the corresponding second sub-test pad group via an adjacent second sub-lead group or the fourth sub-lead group; at least one of the bonding lead groups is electrically connected to the corresponding first sub-test pad group via an adjacent first sub-lead group or the third sub-lead group; the first sub-test pad includes at least one of a power supply voltage test pad, a low-frequency clock signal test pad, a first common electrode voltage test pad, and a start trigger signal test pad; the second sub-test pad group is used to connect to the source test signal.

8. The array substrate according to claim 7, characterized in that, The second test pad group includes a first CK test pad group, a second common electrode voltage test pad, and a second CK test pad group arranged sequentially at intervals in the first direction; the third lead group includes a first CK lead group, a common electrode voltage lead, and a second CK lead group that are electrically connected to the first CK test pad group, the second common electrode voltage test pad, and the second CK test pad group in a one-to-one correspondence. Each pair of adjacent bonding lead groups is electrically connected to the first CK lead group and the second CK lead group in the corresponding test pad unit.

9. The array substrate according to claim 8, characterized in that, The plurality of source fan-out trace groups are included on a first side and a second side that are disposed opposite to each other in the first direction; the fan-out area also includes a second GOA signal trace group located on the first side and the second side respectively; the plurality of bonding lead groups include a first bonding lead group near the first side, a second bonding lead group near the second side, and a plurality of third bonding lead groups located between the first bonding lead group and the second bonding lead group; The first bonding lead group is electrically connected to the second GOA signal trace group located on the first side, and is electrically connected to the corresponding first sub-test pad group through an adjacent first sub-lead group; the second bonding lead group is electrically connected to the second GOA signal trace group located on the second side, and is electrically connected to the corresponding first sub-test pad group through an adjacent third sub-lead group; the first bonding lead group and the plurality of third bonding lead groups are all electrically connected to the corresponding second sub-test pad group through an adjacent second sub-lead group; the second bonding lead group is electrically connected to the corresponding second sub-test pad group through an adjacent fourth sub-lead group.

10. A display panel, characterized in that, It includes a counter substrate and an array substrate as described in claim 1; the counter substrate and the array substrate are disposed opposite to each other.

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