Display device

Abstract

A display device has a substrate, a heat dissipation layer containing aluminum nitride provided on a main surface of the substrate, a plurality of light emitting elements provided on the heat dissipation layer on the main surface side of the substrate, an insulating film covering the heat dissipation layer, and a cathode wiring provided on the insulating film on a peripheral area outside a display area of the substrate and electrically connected to cathodes of the light emitting elements, wherein the heat dissipation layer is continuously provided from an area overlapping the plurality of light emitting elements to the peripheral area, and a contact hole overlapping the cathode wiring and the heat dissipation layer when viewed from a direction perpendicular to the main surface of the substrate is provided in the insulating film.

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] Display devices that use tiny light-emitting diodes (micro LEDs) as display elements have attracted considerable attention (see, for example, Patent Documents 1 and 2). Patent Document 1 describes a display device in which the light-emitting element and the transistor driving the light-emitting element are formed on the same side of a glass substrate (represented as an LED display in Patent Document 1). In addition, Patent Document 2 describes a light-emitting element having a tunnel bonding layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2020 / 188851

[0006] Patent Document 2: Japanese Patent Publication No. 2021-508175

[0007] Non-patent literature 1: T. Wu et al., Appl. Sci. 8, 1557 (2018). Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Inorganic light-emitting diodes (LEDs) experience a decrease in luminous efficiency as temperature rises. Therefore, display devices utilizing inorganic LEDs may experience a decrease in brightness and display characteristics as temperature increases.

[0010] The purpose of this invention is to provide a display device capable of suppressing the degradation of display characteristics.

[0011] Methods for solving problems

[0012] One aspect of the present invention provides a display device comprising: a substrate, a heat dissipation layer comprising aluminum nitride disposed on a main surface of the substrate, a plurality of light-emitting elements disposed on the heat dissipation layer on the main surface side of the substrate, an insulating film covering the heat dissipation layer, and a cathode wiring disposed on the insulating film and electrically connected to the cathodes of the light-emitting elements in a peripheral region outside the display area of ​​the substrate, wherein the heat dissipation layer is continuously disposed from the region overlapping with the plurality of light-emitting elements to the peripheral region, and the insulating film is provided with a contact hole that overlaps with the cathode wiring and the heat dissipation layer when viewed from a direction perpendicular to the main surface of the substrate. Attached Figure Description

[0013] [ Figure 1 ] Figure 1A top view of the display device according to the first embodiment is shown for illustrative purposes.

[0014] [ Figure 2 ] Figure 2 This is a top view showing multiple pixels.

[0015] [ Figure 3 ] Figure 3 The circuit diagram for the pixel circuit is shown.

[0016] [ Figure 4 ] Figure 4 for Figure 1 Sectional view of IV-IV'.

[0017] [ Figure 5 ] Figure 5 A graph showing the temperature characteristics of the light-emitting element.

[0018] [ Figure 6 ] Figure 6 A cross-sectional view showing the approximate cross-sectional configuration of the display device according to the second embodiment.

[0019] [ Figure 7 ] Figure 7 A cross-sectional view showing the approximate cross-sectional configuration of the light-emitting element according to the third embodiment.

[0020] [ Figure 8 ] Figure 8 A circuit diagram of the pixel circuit according to the third embodiment is shown. Detailed Implementation

[0021] The embodiments (implementations) for carrying out the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited by the content described in the following embodiments. Furthermore, the constituent elements described below include content that is readily conceived by those skilled in the art and substantially the same. In addition, the constituent elements described below can be appropriately combined. It should be noted that the disclosed content is merely an example, and appropriate modifications that maintain the spirit of the invention and are readily conceived by those skilled in the art are of course included within the scope of the present invention. Furthermore, regarding the accompanying drawings, in order to make the description clearer, the width, thickness, shape, etc., of each part are sometimes schematically shown compared to the actual embodiment, but this is merely an example and does not limit the interpretation of the present invention. Additionally, in this specification and the figures, the same constituent elements as those described with respect to the previously mentioned figures are sometimes given the same reference numerals and detailed descriptions are appropriately omitted.

[0022] In this specification and claims, when expressing the manner in which other structures are arranged on top of a certain structure, the abbreviation "on top of" is used, unless otherwise stated, including both the case where other structures are arranged directly above a certain structure in connection with it, and the case where other structures are arranged above a certain structure with another structure in between.

[0023] (First Embodiment)

[0024] Figure 1 A top view is shown schematically of the display device according to the first embodiment. Figure 1 As shown, the display device 1 includes an array substrate 2, pixel Pixes, a driving circuit 12, a driving IC (Integrated Circuit) 210, cathode wiring 60, and a heat dissipation layer 91. The array substrate 2 is the driving circuit substrate used to drive each pixel Pix, and is also called a base plate or active matrix substrate. The array substrate 2 has a substrate 21, multiple transistors, multiple capacitors, and various wirings, etc.

[0025] like Figure 1 As shown, the display device 1 has a display area AA and a peripheral area GA. The display area AA overlaps with multiple pixels Pix and is the area for displaying images. The peripheral area GA is the area that does not overlap with the multiple pixels Pix and is disposed outside the display area AA.

[0026] Multiple pixels (Pix) are arranged along a first direction (Dx) and a second direction (Dy) in the display area AA of the substrate 21. It should be noted that the first direction (Dx) and the second direction (Dy) are parallel directions relative to the surface of the substrate 21. The first direction (Dx) and the second direction (Dy) are orthogonal. Alternatively, the first direction (Dx) may intersect the second direction (Dy) in a non-orthogonal manner. The third direction (Dz) is orthogonal to both the first direction (Dx) and the second direction (Dy). The third direction (Dz) corresponds, for example, to the normal direction of the substrate 21. It should be noted that, in the following context, "top view" refers to the positional relationship as viewed from the third direction (Dz).

[0027] The driving circuit 12 controls multiple gate lines (e.g., reset control signal line L5, output control signal line L6, pixel control signal line L7, initialization control signal line L8) based on various control signals supplied via wiring from the driver IC 210. Figure 3 The driving circuit 12 selects multiple gate lines sequentially or simultaneously and supplies gate driving signals to the selected gate lines. Thus, the driving circuit 12 selects multiple pixels (Pixes) connected to the gate lines.

[0028] Driver IC 210 is a circuit that controls the display of display device 1. Starting from driver IC 210, multiple wirings (e.g., image signal line L2, reset power line L3, and initialization power line L4) are led out towards multiple pixels (see [link to relevant documentation]). Figure 3 The driver IC210 is mounted on the peripheral area GA of the substrate 21 using a COG (Chip On Glass) mounting method. However, the driver IC210 can also be mounted on a flexible printed circuit board or a rigid substrate connected to the peripheral area GA of the substrate 21.

[0029] A cathode wiring 60 is disposed in the peripheral region GA of the substrate 21. The cathode wiring 60 is arranged such that it surrounds the multiple pixels (Pix) of the display region AA and the driving circuitry 12 of the peripheral region GA. The cathodes of the multiple light-emitting elements 3 are connected to the common cathode wiring 60 and supplied with a fixed potential (e.g., ground potential). More specifically, the cathode electrode 33 of the light-emitting element 3 (see...) Figure 7 The cathode wiring 60 is connected to the cathode connection wiring (not shown) formed on the array substrate 2. It should be noted that the cathode wiring 60 is not limited to a single wiring continuously formed along the three sides of the substrate 21, but can consist of two partial wirings separated by a slit in any one side, or it can be wiring arranged along at least one side of the substrate 21.

[0030] Heat dissipation layer 91 is disposed on the main surface S1 of substrate 21 (see Figure 4 ), located in the area that overlaps with the display area AA and the surrounding area GA when viewed from above. Figure 1 The heat dissipation layer 91 shown is provided on the entire main surface S1 of the substrate 21, and in the display area AA, it is provided in the area overlapping with multiple pixels (Pix). Furthermore, the heat dissipation layer 91 is provided in the peripheral area GA, covering the areas overlapping with the driving circuit 12 and the driving IC 210 (which are peripheral circuits) in a top view, and the areas overlapping with the cathode wiring 60 in a top view. The heat dissipation layer 91 in the peripheral area GA is connected to the cathode wiring 60 via multiple contact holes CH1. It should be noted that the detailed configuration of the heat dissipation layer 91 and the cathode wiring 60 will be described below. Furthermore, the configuration is not limited to providing the heat dissipation layer 91 on the entire main surface S1 of the substrate 21; the heat dissipation layer 91 may also be omitted from the display area AA and a portion of the peripheral area GA.

[0031] Figure 2 This is a top view showing multiple pixels. (Example) Figure 2 As shown, one pixel Pix contains multiple sub-pixels 49. For example, pixel Pix has sub-pixels 49R, 49G, and 49B. Sub-pixel 49R displays the primary color red as the first color. Sub-pixel 49G displays the primary color green as the second color. Sub-pixel 49B displays the primary color blue as the third color. Figure 2 As shown, in one pixel Pix, subpixels 49R and 49G are arranged in the first direction Dx. Additionally, subpixels 49G and 49B are arranged in the second direction Dy. It should be noted that the first, second, and third colors are not limited to red, green, and blue; any color, such as complementary colors, can be chosen. Without needing to distinguish between subpixels 49R, 49G, and 49B, they will be referred to simply as subpixel 49.

[0032] Each sub-pixel 49 has a light-emitting element 3 and an anode wiring 23. The display device 1 displays an image by emitting different light from each light-emitting element 3R, 3G, and 3B in sub-pixels 49R, 49G, and 49B. The light-emitting element 3 is an inorganic light-emitting diode (LED) chip with a size of approximately 3μm to 300μm when viewed from above, and is referred to as a micro LED. The display device 1, in which each pixel contains micro LEDs, is also called a micro LED display device. It should be noted that the "micro" in micro LED does not limit the size of the light-emitting element 3.

[0033] It should be noted that multiple light-emitting elements 3 can also emit more than four different colors of light. Furthermore, the configuration of multiple sub-pixels 49 is not limited to... Figure 2 The configuration is shown in the diagram. For example, sub-pixel 49R and sub-pixel 49B can be adjacent in the second direction Dy. Alternatively, sub-pixel 49R, sub-pixel 49G, and sub-pixel 49B can be arranged repeatedly in the first direction Dx.

[0034] Figure 3 The circuit diagram for the pixel circuit is shown. Figure 3 A pixel circuit PICA is shown, located in one sub-pixel 49, and a pixel circuit PICA is provided in each of multiple sub-pixels 49. For example... Figure 3 As shown, the pixel circuit PICA includes 3 and 5 light-emitting elements (LEDs), and 2 capacitors. Specifically, the pixel circuit PICA includes a driving transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST. The driving transistor DRT, output transistor BCT, initialization transistor IST, pixel selection transistor SST, and reset transistor RST are all composed of n-type TFTs (Thin Film Transistors). Additionally, the pixel circuit PICA includes a first capacitor Cs1 and a second capacitor Cs2.

[0035] The cathode of the light-emitting element 3 (cathode 33 (see...) Figure 7The cathode power line L10 is connected to the light-emitting element 3. Additionally, the anode (anode electrode 32) of the light-emitting element 3 is connected to the anode power line L1 via the anode wiring 23, the driving transistor DRT, and the output transistor BCT. An anode power potential PVDD is supplied to the anode power line L1. A cathode power potential PVSS is supplied to the cathode power line L10 via the cathode wiring 60 and the cathode electrode 33. The anode power potential PVDD is higher than the cathode power potential PVSS.

[0036] The anode power line L1 supplies the anode power potential PVDD, which serves as the driving potential, to the sub-pixel 49. Specifically, under ideal conditions, the light-emitting element 3 emits light by being supplied with a forward current (driving current) through the potential difference (PVDD-PVSS) between the anode power potential PVDD and the cathode power potential PVSS. That is, the anode power potential PVDD has a potential difference relative to the cathode power potential PVSS that causes the light-emitting element 3 to emit light. The anode electrode 32 of the light-emitting element 3 is electrically connected to the anode wiring 23, and the second capacitor Cs2 is formed between the anode wiring 23 and the anode power line L1.

[0037] The source electrode of the driving transistor DRT is connected to the anode electrode 32 of the light-emitting element 3 via the anode wiring 23, and the drain electrode is connected to the source electrode of the output transistor BCT. The gate electrode of the driving transistor DRT is connected to the first capacitor Cs1, the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.

[0038] The gate electrode of the output transistor BCT is connected to the output control signal line L6. An output control signal BG is supplied to the output control signal line L6. The drain electrode of the output transistor BCT is connected to the anode power supply line L1.

[0039] The source electrode of the initialization transistor IST is connected to the initialization power supply line L4. An initialization potential Vini is supplied to the initialization power supply line L4. The gate electrode of the initialization transistor IST is connected to the initialization control signal line L8. An initialization control signal IG is supplied to the initialization control signal line L8. That is, when the initialization transistor IST is turned on, the initialization power supply line L4 is connected to the gate electrode of the driving transistor DRT through the initialization transistor IST.

[0040] The source electrode of the pixel selection transistor SST is connected to the image signal line L2. An image signal Vsig is supplied to the image signal line L2. A pixel control signal line L7 is connected to the gate electrode of the pixel selection transistor SST. A pixel control signal SG is supplied to the pixel control signal line L7.

[0041] The source electrode of the reset transistor RST is connected to the reset power supply line L3. A reset power supply potential Vrst is supplied to the reset power supply line L3. The gate electrode of the reset transistor RST is connected to the reset control signal line L5. A reset control signal RG is supplied to the reset control signal line L5. The drain electrode of the reset transistor RST is connected to the anode wiring 23 (the anode electrode 32 of the light-emitting element 3) and the source electrode of the driving transistor DRT. Through the reset operation of the reset transistor RST, the voltage held by the first capacitor Cs1 and the second capacitor Cs2 is reset.

[0042] The first capacitor Cs1 is formed between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can suppress gate voltage fluctuations caused by the parasitic capacitance and leakage current of the drive transistor DRT through the first capacitor Cs1 and the second capacitor Cs2.

[0043] It should be noted that in the following description, the anode power line L1 and the cathode power line L10 are sometimes referred to as power lines. The image signal line L2, the reset power line L3, and the initialization power line L4 are sometimes referred to as signal lines. The reset control signal line L5, the output control signal line L6, the pixel control signal line L7, and the initialization control signal line L8 are sometimes referred to as gate lines.

[0044] A potential responding to the image signal Vsig (or grayscale signal) is supplied to the gate electrode of the driving transistor DRT. That is, the driving transistor DRT supplies a current responding to the image signal Vsig to the light-emitting element 3 based on the anode power supply potential PVDD supplied through the output transistor BCT. In this way, the anode power supply potential PVDD supplied to the anode power line L1 is reduced by the driving transistor DRT and the output transistor BCT, thereby supplying a potential lower than the anode power supply potential PVDD to the anode electrode 32 of the light-emitting element 3.

[0045] An anode power supply potential PVDD is supplied to one electrode of the second capacitor Cs2 via the anode power supply line L1, while a potential lower than the anode power supply potential PVDD is supplied to the other electrode of the second capacitor Cs2. That is, a potential higher than the other electrode of the second capacitor Cs2 is supplied to one electrode of the second capacitor Cs2. One electrode of the second capacitor Cs2 is, for example,... Figure 4 The opposing electrode 26 shown in the figure, the other electrode of the second capacitor Cs2 is Figure 4 The anode wiring 23 shown is connected to the source of the driving transistor DRT.

[0046] In display device 1, drive circuit 12 (see...) Figure 1 From the first line (for example, in) Figure 1The display device 1 selects multiple pixel rows sequentially, starting with the topmost pixel row in the display area AA. The driver IC 210 writes an image signal Vsig (image write potential) to the sub-pixel 49 of the selected pixel row, causing the light-emitting element 3 to emit light. During each horizontal scan, the driver IC 210 supplies the image signal Vsig to the image signal line L2, the reset power potential Vrst to the reset power line L3, and the initialization potential Vini to the initialization power line L4. The display device 1 repeats these operations for each frame of the image.

[0047] Next, the cross-sectional structure of the display device 1 will be described. Figure 4 yes Figure 1 Sectional view of IV-IV'. (See also...) Figure 4 As shown, the light-emitting element 3 is disposed on the array substrate 2. The array substrate 2 has a substrate 21, various transistors, various wirings, and various insulating films. The substrate 21 is a glass substrate used as an insulating substrate. It should be noted that the substrate 21 is not limited to a glass substrate, and may also be a resin substrate or a resin film, etc.

[0048] In this specification, the direction perpendicular to the surface of the substrate 21, from the substrate 21 toward the light-emitting element 3, is referred to as "upper side" or simply "up". The direction from the light-emitting element 3 toward the substrate 21 is referred to as "lower side" or simply "lower".

[0049] A heat dissipation layer 91 is provided to cover the main surface S1 of the substrate 21 and is continuously provided from the display area AA of the substrate 21 to the surrounding area GA. In this embodiment, the heat dissipation layer 91 is directly in contact with the main surface S1 of the substrate 21. The heat dissipation layer 91 is an inorganic insulating film containing aluminum nitride (AlN) and is formed by sputtering, vapor deposition, plasma CVD, or the like. As an example, the heat dissipation layer 91 is formed by sputtering.

[0050] The light-emitting element 3 is directly connected to the heat dissipation layer 91. That is, the light-emitting element 3 is formed by depositing a heat dissipation layer 91 containing aluminum nitride as a buffer layer on the main surface S1 of the substrate 21, which is a glass substrate, and then patterning it. In other words, the light-emitting element 3 can omit the process of forming a semiconductor layer (light-emitting element 3) on a sapphire substrate or the like, and transferring the light-emitting element 3 onto the substrate 21 using a carrier substrate or the like.

[0051] It should be noted that, Figure 4 The image shows one light-emitting element 3, but for... Figure 4 The description of the light-emitting element 3 shown can also be applied to the individual light-emitting elements 3R, 3G, and 3B of the pixel Pix described above.

[0052] The light-emitting element 3 has a semiconductor layer 31, an anode electrode 32, and a cathode electrode 33 (see [reference]). Figure 7 The light-emitting element 3 is a light-emitting element in which the anode electrode 32 (p-type electrode) and the cathode electrode 33 (n-type electrode) are arranged in the same direction as the main surface S1 of the substrate 21 (array substrate 2). It should be noted that... Figure 4 In the diagram, the cathode electrode 33 is not shown, but it is related to... Figure 7 The example shown is similarly formed in part of the n-type capping layer 37.

[0053] like Figure 4 As shown, the semiconductor layer 31 of the light-emitting element 3 is formed by stacking a high-resistivity layer 38, an n-type capping layer 37, an active layer 36, and p-type capping layers 35 and 34. In the light-emitting element 3, the high-resistivity layer 38, the n-type capping layer 37, the active layer 36, and the p-type capping layers 35 and 34 are stacked sequentially on the heat dissipation layer 91. An anode electrode 32 is provided on the p-type capping layers 35 and 34.

[0054] The semiconductor layer 31 may use compound semiconductors such as gallium nitride (GaN), aluminum indium phosphide (AlInP), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). Different materials may be used in the semiconductor layer 31 for each light-emitting element 3R, 3G, and 3B.

[0055] The high-resistivity layer 38 is directly connected to the heat dissipation layer 91. The high-resistivity layer 38 is formed of an undoped semiconductor material (e.g., gallium nitride (GaN)). The sheet resistance of the high-resistivity layer 38 is greater than the sheet resistance of the n-type capping layer 37 stacked on top.

[0056] The n-type capping layer 37 is, for example, n-type GaN. As the active layer 36, a multiple quantum well (MQW) structure, consisting of a well layer and a barrier layer comprising several atomic layers, is periodically stacked for high efficiency. Additionally, the p-type capping layer 35 is, for example, p-type GaN, and the p-type capping layer 34 is, for example, p-type aluminum gallium nitride (AlGaN). An anode electrode 32 is disposed on the p-type capping layer 34. The anode electrode 32 is, for example, formed as a stacked structure of titanium (Ti), nickel (Ni), titanium (Ti), and gold (Au).

[0057] The component insulating film 39 is provided to cover the periphery and sides of the upper surface of the light-emitting element 3. The component insulating film 39 is a protective inorganic insulating film, such as silicon oxide film (SiO2), silicon nitride film (SiN), or aluminum oxide (Al2O3). Alternatively, the component insulating film 39 can also be an organic insulating film.

[0058] The component insulating film 39 has an opening OP at the position where it overlaps with the anode electrode 32. The anode wiring 23 is disposed on the insulating film 96 and is connected to the anode electrode 32 through the opening OP. The anode electrode 32 is electrically connected to the driving transistor DRT formed on the substrate 21 (array substrate 2) through the anode wiring 23.

[0059] The anode wiring 23 may be formed, for example, as a stacked structure of titanium (Ti) and aluminum (Al). However, it is not limited to this, and the anode wiring 23 may also be made of any one or more materials including molybdenum and titanium. Alternatively, the anode wiring 23 may also be an alloy containing any one or more of molybdenum and titanium, or a light-transmitting conductive material.

[0060] It should be noted that, Figure 4 The cathode electrode 33 (not shown) is electrically connected to the cathode wiring 60 via a cathode connection wiring (not shown) disposed on the insulating film 96. The cathode electrode 33 is formed of the same material as the anode electrode 32. The connection structure between the cathode electrode 33 and the cathode wiring 60 can be arbitrary; for example, it can be configured such that the cathode connection wiring is provided extending in the first direction Dx and connected to the cathode electrodes 33 of a plurality of light-emitting elements 3 arranged along the first direction Dx.

[0061] The driving transistor DRT and the reset transistor RST are disposed on the same layer as the light-emitting element 3, above the heat dissipation layer 91. The driving transistor DRT has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and gate electrodes 64A and 64B. The reset transistor RST has a semiconductor layer 65, a source electrode 66, a drain electrode 67, and gate electrodes 68A and 68B. Furthermore, Figure 4 The diagram shows the transistor Tr included in the drive circuit 12 located in the peripheral region GA of the substrate 21.

[0062] The following description explains the stacked structure of the driving transistor DRT. Other transistors include the reset transistor RST, transistor Tr, and... Figure 3 The various transistors shown are also constructed in the same way, and the description of the driving transistor DRT can also be applied to other transistors.

[0063] Gate electrode 64A is disposed on heat dissipation layer 91. Insulating film 92 covers gate electrode 64A and is disposed on heat dissipation layer 91. Semiconductor layer 61 is disposed on insulating film 92. Insulating film 93 covers semiconductor layer 61 and is disposed on insulating film 92. Gate electrode 64B is disposed on insulating film 93. Insulating films 92 and 93 are disposed between semiconductor layer 61 and gate electrodes 64A and 64B, and are inorganic insulating films formed as gate insulating films. Insulating films 92 and 93 may be, for example, silicon nitride film or silicon oxide film.

[0064] An insulating film 94 covers the gate electrode 64B and is disposed on top of the insulating film 93. The insulating film 94 may have, for example, a laminated structure of a silicon nitride film and a silicon oxide film. The source electrode 62 and the drain electrode 63 are disposed on the insulating film 94. The source electrode 62 is electrically connected to the semiconductor layer 61 through contact holes penetrating the insulating films 93 and 94. The drain electrode 63 is electrically connected to the semiconductor layer 61 through contact holes provided in the insulating films 93 and 94.

[0065] The insulating film 95 is an organic insulating film that covers each transistor. As the insulating film 95, organic materials such as photosensitive acrylics can be used. Compared to inorganic insulating materials formed by CVD or similar methods, photosensitive acrylics and other organic materials offer superior coverage of wiring height differences and surface flatness.

[0066] Specifically, an insulating film 95 is disposed on top of an insulating film 94, covering the source electrode 62 and the drain electrode 63. The insulating film 95 also covers the side of the element insulating film 39 that covers the light-emitting element 3. An anode connection wiring 24 and a counter electrode 26 are provided on the insulating film 95. The anode connection wiring 24 is connected to the source electrode 62 at the bottom of a contact hole in the insulating film 95. The counter electrode 26 is connected to the drain electrode 63 at the bottom of a contact hole in the insulating film 95.

[0067] An insulating film 96 is provided to cover the anode connection wiring 24 and the counter electrode 26. Furthermore, the insulating film 96 is provided to cover the upper surface of the component insulating film 39. The insulating film 96 is an inorganic insulating film and can be made of the same material as the insulating films 92 and 93 described above, such as a silicon nitride film. The anode wiring 23 is connected to the anode connection wiring 24 at the bottom of the contact hole provided in the insulating film 96. With this configuration, the anode wiring 23 is electrically connected to the drive transistor DRT.

[0068] Additionally, a portion of the anode wiring 23 is positioned opposite the counter electrode 26 via an insulating film 96. A second capacitor Cs2 is formed between the opposing anode wiring 23 and the counter electrode 26, separated by the insulating film 96 (see [link]). Figure 3 ).

[0069] After the light-emitting element 3 is formed on the substrate 21 and the heat dissipation layer 91, each transistor is formed on the same substrate 21 and the heat dissipation layer 91. The element insulating film 39 covering the light-emitting element 3 can be integrally and continuously formed using the same material as the insulating film 92, which serves as the gate insulating film. In other words, the element insulating film 39 and the insulating film 92 also function as protective films for the light-emitting element 3 during the process of forming each transistor.

[0070] The cathode wiring 60 is disposed on the insulating film 96 in the peripheral area GA of the substrate 21. In addition, the heat dissipation layer 91 is continuously disposed on the main surface S1 of the substrate 21 from the area of ​​the display area AA that overlaps with the plurality of light-emitting elements 3 and the plurality of transistors (e.g., driving transistors DRT) and extends throughout the peripheral area GA, and is also disposed in the area that overlaps with the cathode wiring 60.

[0071] Contact holes CH1 and CH2 are provided in insulating films 92 and 95, overlapping the cathode wiring 60 and the heat dissipation layer 91 when viewed from a direction perpendicular to the main surface S1 of the substrate 21. More specifically, the heat transfer section 162 is provided on the insulating film 94 in the same layer as the source electrode 62 and the drain electrode 63. The heat transfer section 162 is provided to fill the interior of the contact holes CH2 that penetrate the insulating films 92, 93, and 94, and is in contact with the heat dissipation layer 91 at the bottom of the contact holes CH2.

[0072] The cathode wiring 60 is provided by filling the interior of the contact hole CH1 through which the insulating film 95 passes. Figure 4 The portion of the cathode wiring 60 located within the contact hole CH1 is shown as a heat transfer section 161. The cathode wiring 60 and the heat transfer section 161 are integrally formed using the same material. The cathode wiring 60 (heat transfer section 161) is connected to the heat transfer section 162 at the bottom of the contact hole CH1.

[0073] It should be noted that the insulating film 96 is provided to cover the inner wall surface of the contact hole CH1 of the insulating film 95, and the insulating film 96 and the cathode wiring 60 (heat transfer part 161) are stacked sequentially on the inner wall surface of the contact hole CH1.

[0074] With this configuration, the cathode wiring 60 formed on the insulating film 96 and the heat dissipation layer 91 formed on the main surface S1 of the substrate 21 are connected by contact holes CH1 and CH2. However, it is not limited to this; a single contact hole can also be formed that extends from the insulating film 92 to the insulating film 95. Alternatively, the cathode wiring 60 and the heat transfer portion 161 can be formed separately. For example, after forming the heat transfer portion 161 by filling the contact hole CH1, the cathode wiring 60 is provided by covering the contact hole CH1 and the heat transfer portion 161.

[0075] Materials used for the cathode wiring 60 (heat transfer section 161) and heat transfer section 162 may include, for example, titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), tungsten (W), niobium (Nb), copper (Cu), carbon nanotubes, graphite, graphene or carbon nanobuds, silver (Ag), and Ag alloys.

[0076] Figure 5 A graph showing the temperature characteristics of an inorganic light-emitting element. Figure 5The horizontal axis represents the temperature of the light-emitting element 3, and the vertical axis represents the light output of the light-emitting element 3. For example... Figure 5 As shown, the light-emitting element 3 tends to decrease its light output and become unstable when the temperature increases. This tendency applies to any type of light-emitting element 3, regardless of the driving current, from small to large.

[0077] like Figure 4 As shown, a heat dissipation layer 91 containing aluminum nitride is disposed between the main surface S1 of the substrate 21 and multiple light-emitting elements 3 and multiple transistors, and the peripheral area GA is connected to the cathode wiring 60 through contact holes CH1, CH2.

[0078] The thermal conductivity of the heat dissipation layer 91, which includes aluminum nitride, is higher than that of the substrate 21, which is a glass substrate. For example, the thermal conductivity of the heat dissipation layer 91 is 285 W·m. -1 ·K -1 ) above 320 (W·m -1 ·K -1 The thermal conductivity of substrate 21 is approximately 1.5 W / m². -1 ·K -1 ) or above 1.6 (W·m -1 ·K -1 The thermal conductivity of the heat dissipation layer 91, which includes aluminum nitride, is greater than that of the semiconductor layer 31 (GaN) of the light-emitting element 3. For example, the thermal conductivity of GaN is 230 W / m³. -1 ·K -1 )about.

[0079] The heat generated by the current flowing through the multiple light-emitting elements 3 is transferred to the heat dissipation layer 91, as indicated by arrow A1. The heat dissipation layer 91 has a higher thermal conductivity than the substrate 21, enabling it to efficiently conduct heat from the light-emitting elements 3 to the cathode wiring 60. As described above, the cathode wiring 60 is arranged to surround the display area AA along the outer edge of the substrate 21. Furthermore, the thermal conductivity of the cathode wiring 60 and the heat transfer portions 161 and 162 is higher than that of the insulating films 92, 93, 94, 95, and 96 covering the substrate 21. Therefore, the cathode wiring 60 and the heat transfer portions 161 and 162 can efficiently dissipate heat from the light-emitting elements 3 to the outside.

[0080] Similarly, the multiple transistors of the pixel circuit PICA are also arranged overlapping with the heat dissipation layer 91. Among the multiple transistors of the pixel circuit PICA, for example, the driving transistor DRT carries current and thus becomes a heat source. The heat generated from the driving transistor DRT is transferred to the heat dissipation layer 91 as shown by arrow A2. As described above, the cathode wiring 60 and the heat transfer sections 161 and 162 can efficiently dissipate the heat from the driving transistor DRT.

[0081] It should be noted that the above configuration is merely an example and can be modified appropriately. For example, it is not limited to the case where contact holes CH1 and CH2 penetrate through insulating films 92, 93, 94, and 95. For example, the heat dissipation layer 91 and the heat transfer part 162 do not necessarily need to be in direct contact; an insulating film can also be provided between the heat transfer part 162 and the heat dissipation layer 91. Furthermore, Figure 1 In the middle, four contact holes CH1 are shown in the surrounding area GA, but more than five contact holes CH1 can also be provided.

[0082] As described above, the display device 1 of this embodiment includes: a substrate 21; a heat dissipation layer 91 provided on the main surface S1 of the substrate 21 and comprising aluminum nitride (AlN); a plurality of light-emitting elements 3 and a plurality of transistors (e.g., driving transistors DRT) provided on the heat dissipation layer 91 on the main surface S1 side of the substrate 21; an insulating film 95 covering at least the plurality of transistors; and a cathode wiring 60 provided on the insulating film 95 and electrically connected to the cathodes of the light-emitting elements 3 in a peripheral region GA outside the display area AA of the substrate 21. The heat dissipation layer 91 is continuously provided from the area overlapping with the plurality of light-emitting elements 3 and the plurality of transistors to the peripheral region GA. The insulating film 95 has contact holes CH1 and CH2 that overlap with the cathode wiring 60 and the heat dissipation layer 91 when viewed from a direction perpendicular to the main surface S1 of the substrate 21.

[0083] (Second Implementation)

[0084] Figure 6 This is a cross-sectional view showing a schematic cross-sectional configuration of the display device according to the second embodiment. It should be noted that in the following description, components identical to those described in the above embodiments are given the same reference numerals and repeated descriptions are omitted.

[0085] like Figure 6 As shown, in the display device 1A according to the second embodiment, the light-emitting element 3A has a tunnel bonding layer TJ stacked on top of the p-type capping layer 35. In the light-emitting element 3A, a high-resistivity layer 38, an n-type capping layer 37, an active layer 36, a p-type capping layer 35, a tunnel bonding layer TJ, and an n-type capping layer 41 are sequentially stacked on top of the heat dissipation layer 91. The tunnel bonding layer TJ is formed by stacking a high-concentration p-type semiconductor layer 43 and a high-concentration n-type semiconductor layer 42, which are thinner than the p-type capping layer 35 and the n-type capping layer 41. An anode electrode 32 is provided on top of the n-type capping layer 41.

[0086] In other words, the light-emitting element 3A can also be said to be composed of a tunnel bonding layer TJ and an n-type capping layer 41 stacked in the light-emitting element 3 of the first embodiment to replace the p-type capping layer 34 formed by AlGaN.

[0087] The light-emitting element 3A has a tunnel junction layer TJ, thus achieving lower resistance compared to a structure with a p-type capping layer 34 formed of AlGaN. This is because, as disclosed in Non-Patent Document 1, in a cascaded LED structure utilizing RGB-LEDs stacked in series along the growth direction, the p-type GaN surface layer deteriorates due to plasma exposure during dry etching when forming the p-type contact of the lower LED, leading to hole injection into the LED. On the other hand, by replacing the p-type contact of each LED with a tunnel junction (TJ) contact, a structure is formed where the tunnel junction layer TJ and the n-type capping layer 41 are stacked instead of the p-type capping layer 34. The thick, low-resistance n-type capping layer is exposed to plasma, thereby solving this problem.

[0088] (Third Implementation)

[0089] Figure 7 A cross-sectional view showing the approximate cross-sectional configuration of the light-emitting element according to the third embodiment. (See attached image.) Figure 7 As shown, in the light-emitting element 3 according to the third embodiment, light-emitting element 3B (first light-emitting element) and light-emitting element 3G (second light-emitting element) are disposed adjacent to each other with a device insulating film 39 in between. More specifically, light-emitting element 3B (first light-emitting element) and light-emitting element 3G (second light-emitting element) are formed on a common high-resistivity layer 38 that is directly connected to the heat dissipation layer 91. In light-emitting element 3B and light-emitting element 3G, an n-type capping layer 37G, an active layer 36G, a p-type capping layer 35G, a tunnel bonding layer TJ-G, and an n-type capping layer 41G are sequentially stacked on the heat dissipation layer 91 and the high-resistivity layer 38, respectively.

[0090] A groove is provided between the n-type capping layer 37G, active layer 36G, p-type capping layer 35G, tunnel bonding layer TJ-G, and n-type capping layer 41G of the light-emitting element 3B, and the n-type capping layer 37G, active layer 36G, p-type capping layer 35G, tunnel bonding layer TJ-G, and n-type capping layer 41G of the light-emitting element 3G. An element insulating film 39 is formed in the groove. Thus, the light-emitting element 3B and the light-emitting element 3G are separated.

[0091] In the light-emitting element 3G, an anode electrode 32G is provided on the n-type capping layer 41G, and a cathode electrode 33G is provided on the n-type capping layer 37G.

[0092] In the light-emitting element 3B, an n-type capping layer 37B, an active layer 36B, a p-type capping layer 35B, a tunnel bonding layer TJ-B, and an n-type capping layer 41B are sequentially stacked on top of the n-type capping layer 41G. An anode electrode 32B is provided on top of the n-type capping layer 41B, and a cathode electrode 33B is provided on top of the n-type capping layer 41G.

[0093] That is, in the direction perpendicular to the main surface S1 of the substrate 21, the height and number of semiconductor layers of the light-emitting element 3B (the first light-emitting element) are different from those of the light-emitting element 3G (the second light-emitting element). More specifically, in the direction perpendicular to the main surface S1 of the substrate 21, the height between the anode electrode 32B of the light-emitting element 3B and the high-resistivity layer 38 are different from those of the anode electrode 32G of the light-emitting element 3G and the high-resistivity layer 38.

[0094] Figure 8 A circuit diagram illustrating the pixel circuit according to the third embodiment is shown. (For example...) Figure 8 As shown, light-emitting elements 3B and 3G are connected to a common pixel circuit PICA. The structure of the pixel circuit PICA is similar to... Figure 3 The above-described configuration is the same. In this embodiment, the light-emitting element 3B and the light-emitting element 3G are respectively connected to the common driving transistor DRT via switching elements SW-B and SW-G.

[0095] By operating the switching elements SW-B and SW-G in a reverse ON / OFF manner, the period during which one of the light-emitting elements 3B and 3G is connected to the driving transistor DRT (light-emitting period) is also the period during which the other of the light-emitting elements 3B and 3G is not connected to the driving transistor DRT (non-light-emitting period). Thus, the light-emitting elements 3B and 3G are driven in time-division manner using the common pixel circuit PICA.

[0096] In the third embodiment, two light-emitting elements 3G and 3B are formed adjacent to each other, and each sub-pixel 49 includes two light-emitting elements 3G and 3B and one pixel circuit PICA. This allows for a reduction in the area of ​​multiple pixels (PIX), enabling higher display resolution. Furthermore, it reduces the number of transistors and wirings formed on the array substrate 2.

[0097] The preferred embodiments of the present invention have been described above, but the present invention is not limited to these embodiments. The contents disclosed in the embodiments are merely examples, and various modifications can be made without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention are of course also within the technical scope of the present invention. At least one of the various omissions, substitutions, and modifications of the constituent elements can be made without departing from the spirit of the above-described embodiments and modifications.

[0098] Explanation of reference numerals in the attached figures

[0099] 1. 1A display device

[0100] 2 array substrates

[0101] 3, 3A, 3R, 3G, 3B light-emitting elements

[0102] 12. Drive circuit

[0103] 21 substrate

[0104] 23 Anode wiring

[0105] 24. Anode connection wiring

[0106] 26 Opposite Electrodes

[0107] 31 Semiconductor layer

[0108] 32 Anode electrode

[0109] 33 Cathode Electrode

[0110] 34 and 35p type cover layers

[0111] 36 Active Layer

[0112] 37 n-type capping layer

[0113] 38 High-resistivity layer

[0114] 39 Component Insulating Film

[0115] 60 Cathode wiring

[0116] 91 Heat dissipation layer

[0117] Heat transfer sections 161 and 162

[0118] CH1, CH2 contact holes

[0119] AA display area

[0120] GA surrounding area

[0121] S1 Main Face

Claims

1. A display device, having: substrate, A heat dissipation layer comprising aluminum nitride is disposed in direct contact with the main surface of the substrate. Multiple light-emitting elements are disposed on the heat dissipation layer and directly in contact with the heat dissipation layer on the main surface of the substrate. The insulating film covered by the heat dissipation layer, and A cathode wiring is disposed on the insulating film and electrically connected to the cathode of the light-emitting element in the peripheral region outside the display area of ​​the substrate. In the display device, the heat dissipation layer is continuously disposed from the area overlapping with the plurality of light-emitting elements to the surrounding area. The insulating film has contact holes that overlap with the cathode wiring and the heat dissipation layer when viewed from a direction perpendicular to the main surface of the substrate. The light-emitting element includes a first light-emitting element and a second light-emitting element adjacent to the first light-emitting element. The first light-emitting element and the second light-emitting element are formed on a common high-resistivity layer that is directly in contact with the heat dissipation layer. The height between the anode electrode of the first light-emitting element and the high-resistivity layer is different in a direction perpendicular to the main surface of the substrate, and the height between the anode electrode of the second light-emitting element and the high-resistivity layer is different.

2. The display device as claimed in claim 1, wherein, In the light-emitting element, a high-resistivity layer, an n-type capping layer, an active layer, and a p-type capping layer are sequentially stacked on top of the heat dissipation layer.

3. The display device as claimed in claim 2, wherein, The light-emitting element has a tunnel bonding layer stacked on top of the p-type cover layer.

4. The display device according to any one of claims 1 to 3, wherein, The substrate has a plurality of transistors disposed on the heat dissipation layer on its main surface side. The heat dissipation layer is continuously disposed in the area of ​​the display region where it overlaps with the plurality of light-emitting elements and the plurality of transistors. The insulating film covers the plurality of transistors.

5. The display device as claimed in claim 4, comprising: The gate insulating film disposed between the semiconductor layer and the gate electrode of the transistor, and An insulating film is provided to cover the periphery and sides of the upper surface of the light-emitting element. The gate insulating film and the element insulating film are integrally and continuously formed from a common material.

6. The display device as claimed in claim 1, wherein, The first light-emitting element and the second light-emitting element are connected to a common transistor via a switching element.

7. The display device according to any one of claims 1 to 3, wherein, The thermal conductivity of the heat dissipation layer is higher than that of the substrate.

8. The display device according to any one of claims 1 to 3, wherein, The substrate is a glass substrate.

Images