LDO circuit

Abstract

This invention relates to the field of integrated circuits and discloses an LDO circuit, comprising: an LDO main circuit and an overshoot clamping circuit. The LDO main circuit includes an operational amplifier, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, and a third resistor. The overshoot clamping circuit includes a second NMOS transistor; the source of the second NMOS transistor is connected to a second reference voltage, and its gate and drain are respectively connected to both sides of a second resistor, wherein the drain is connected to the connection node between the second capacitor and the second resistor; the maximum voltage at the output of the operational amplifier is greater than the sum of the second reference voltage and the threshold voltage of the second NMOS transistor. The LDO circuit of this invention can significantly reduce the overshoot voltage generated by the circuit while meeting the low-power design requirements of the operational amplifier, thus protecting circuit components.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an LDO circuit. Background Technology

[0002] LDOs (low dropout regulators) have significant advantages such as low cost, low noise, and low quiescent current. Furthermore, LDOs require very few external components, typically only one or two bypass capacitors, and are therefore widely used in the integrated circuit field.

[0003] However, because the LDO architecture requires a large capacitor to provide the capacitance needed for the dominant pole, and the capacitor is constantly charging during the process of the LDO powering on and bringing the output voltage to the target voltage, once the output voltage reaches the target voltage and no further boosting is needed, the continuously charging capacitor cannot quickly return to the normal operating voltage, and will continue to output excessive current to the output terminal, resulting in a large overshoot voltage at the output of the LDO circuit. Summary of the Invention

[0004] The purpose of this invention is to provide an LDO circuit that can meet the low-power design requirements of operational amplifiers while greatly reducing the overshoot voltage generated by the circuit and protecting circuit components.

[0005] To solve the above-mentioned technical problems, the embodiments of the present invention provide an LDO circuit, comprising an LDO main circuit and an overshoot clamping circuit;

[0006] The main circuit of the LDO includes an operational amplifier, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, and a third resistor;

[0007] The output terminal of the operational amplifier is connected to the gate of the first NMOS transistor. A second resistor and a second capacitor are connected in series between the output terminal of the operational amplifier and ground. The source of the first NMOS transistor is grounded, and its drain is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, and its gate is connected to its drain. The source of the second PMOS transistor is connected to the power supply voltage, and its gate is connected to the gate of the first PMOS transistor. The drain of the second PMOS transistor serves as one connection path between the output terminal of the LDO circuit and ground, and the first capacitor is connected in series. The first resistor and the third resistor are connected in series in another connection path between the drain of the second PMOS transistor and ground. The inverting input terminal of the operational amplifier is connected to the connection node between the first resistor and the third resistor, and the non-inverting input terminal of the operational amplifier is connected to a first reference voltage.

[0008] The overshoot clamping circuit includes a second NMOS transistor; the source of the second NMOS transistor is connected to a second reference voltage, and the gate and drain are respectively connected to both sides of the second resistor, wherein the drain is connected to the connection node between the second capacitor and the second resistor;

[0009] The maximum voltage at the output of the operational amplifier is greater than the sum of the second reference voltage and the threshold voltage of the second NMOS transistor.

[0010] In the LDO circuit described above, the second reference voltage is a fixed voltage generated on the fourth resistor by the current flowing from the power supply through the current mirror and the fourth resistor to ground.

[0011] In the LDO circuit described above, the second reference voltage is a fixed voltage generated at the drain of the third NMOS transistor by the current flowing from the power supply through the current mirror and the third NMOS transistor to ground.

[0012] In the LDO circuit described above, the second reference voltage is a fixed voltage generated at the source of the third PMOS transistor by the current flowing from the power supply through the current mirror and the third PMOS transistor to ground.

[0013] Compared with the prior art, the embodiment of the present invention clamps the voltage of the second capacitor to the second reference voltage before the output voltage of the LDO circuit reaches the target voltage by means of an overshoot clamping circuit. This prevents the second capacitor with a higher voltage from continuously supplying power after the output voltage reaches the target voltage, thus avoiding the generation of a large overshoot voltage. In other words, the LDO circuit structure in this embodiment is simple. While maintaining the low power consumption of the amplifier, it can greatly shorten the setup time of large signals and reduce the overshoot voltage of the output. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of an LDO circuit according to an embodiment of the present invention;

[0015] Figure 2 This is a circuit diagram for generating the second reference voltage Vclamp according to an embodiment of the present invention;

[0016] Figure 3 This is a circuit diagram for generating the second reference voltage Vclamp according to an embodiment of the present invention;

[0017] Figure 4 This is a circuit diagram for generating the second reference voltage Vclamp according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0019] One embodiment of the present invention relates to an LDO circuit, such as Figure 1 As shown, the LDO circuit provided in this embodiment includes: an LDO main circuit and an overshoot clamping circuit;

[0020] The main circuit of the LDO includes an operational amplifier A0, a first NMOS transistor M0, a first PMOS transistor M1, a second PMOS transistor M2, a first capacitor C1, a second capacitor C0, a first resistor R1, a second resistor R2, and a third resistor R0.

[0021] The output of operational amplifier A0 is connected to the gate of the first NMOS transistor M0. A second resistor R2 and a second capacitor C0 are connected in series between the output of operational amplifier A0 and ground. The source of the first NMOS transistor M0 is grounded, and its drain is connected to the drain of the first PMOS transistor M1. The source of the first PMOS transistor M1 is connected to the power supply voltage VDD, and its gate is connected to its drain. The source of the second PMOS transistor M2 is connected to the power supply voltage VDD, and its gate is connected to the gate of the first PMOS transistor M1. The drain of the second PMOS transistor M2 serves as one connection path between the output of the LDO circuit and ground, and a first capacitor C1 is connected in series. The other connection path between the drain of the second PMOS transistor M2 and ground is connected in series with a first resistor R1 and a third resistor R0. The inverting input of operational amplifier A0 is connected to the connection node between the first resistor R1 and the third resistor R0, and the non-inverting input of operational amplifier A0 is connected to the first reference voltage Vref.

[0022] The overshoot clamping circuit includes a second NMOS transistor M3; the source of the second NMOS transistor M3 is connected to the second reference voltage Vclamp, and the gate and drain are respectively connected to the two sides of the second resistor R2, wherein the drain is connected to the connection node between the second capacitor C0 and the second resistor R2.

[0023] Among them, the maximum voltage at the output terminal of operational amplifier A0 is greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3.

[0024] Specifically, the second capacitor C0 provides the capacitance required for the dominant pole, and its capacitance value is relatively large. Simultaneously, the second resistor R2 and the second capacitor C0 form a compensation zero point. Before power-on, the output voltage V0 at the output terminal of operational amplifier A0 and the output voltage Vout at the output terminal of the LDO circuit (the drain of the second PMOS transistor M2) are both 0. The operation of the LDO circuit can be viewed as a process of raising the output voltage Vout to the target voltage and stabilizing the output power supply.

[0025] Specifically, the target voltage value of the output voltage Vout can be determined according to actual needs. However, it should be noted that the first reference voltage Vref can only be selected after the target voltage value is determined. This is because the reference voltage (first reference voltage Vref) connected to the positive input terminal of operational amplifier A0 and the target voltage value of the output voltage Vout of the LDO circuit containing operational amplifier A0 satisfy the following relationship:

[0026] Where R0 is the resistance value of the third resistor R0, R1 is the resistance value of the first resistor R1, V1 is the target voltage value of the output voltage of the LDO circuit, and Vref is the first reference voltage value.

[0027] Specifically, in the above scheme, the first PMOS transistor M1 and the second PMOS transistor M2 form an amplification relationship. The first PMOS transistor M1 provides gate drive for the second PMOS transistor M2. The first PMOS transistor M1 can be replaced by a resistor, and this application does not impose any specific restrictions on this.

[0028] The working process of the LDO circuit in this embodiment is described below.

[0029] Upon power-up, the LDO circuit needs to charge the first capacitor C1 through the output current of operational amplifier A0. Operational amplifier A0 compares the voltage between its positive and negative input terminals and outputs current through its output terminal. As operational amplifier A0 outputs current, the loop gradually raises the gate voltage of the first NMOS transistor M0 to a very high level, far exceeding the normal operating voltage. This provides sufficient pull-down capability to fully turn on the second PMOS transistor M2 to charge the first capacitor C1, thereby increasing the voltage across the first capacitor C1 (and thus the output voltage Vout of the LDO circuit) until it reaches the target voltage. During the process of charging the first capacitor C1 and raising the output voltage Vout to the target voltage, the second capacitor C0 is also continuously charged, and the voltage across the second capacitor C0 is also continuously increasing. The output voltage V0 of operational amplifier A0 is also continuously increasing, and the voltage across the second capacitor C0 will gradually approach V0.

[0030] In the above process, the relationship between the voltage V0 at the output terminal of operational amplifier A0 and the output voltage Vout of the LDO circuit basically satisfies the following formula (2): ΔV out =G·ΔV0 3 ;

[0031] Where, ΔV out Vout is the change in the output voltage of the LDO circuit, and G is the gain of the entire LDO circuit loop. Specifically, it is determined by the capacitance values ​​of the first capacitor C1 and the second capacitor C0, as well as the maximum output current capability of the operational amplifier A0. It can be regarded as a constant. This application does not limit the specific value of G.

[0032] As the voltage V0 at the output of operational amplifier A0 continuously increases, the voltage value of V0 is related to the first reference voltage Vref, the output voltage Vout, and the amplification factor of operational amplifier A0, specifically satisfying the following relationship:

[0033]

[0034] Where A is the amplification factor of operational amplifier A0, R0 is the resistance value of the third resistor R0, R1 is the resistance value of the first resistor R1, Vout is the output voltage value of the LDO circuit, and Vref is the first reference voltage value. Vgs0 is the voltage between Vref and... When they are equal, the voltage that ensures the normal turn-on of the first NMOS transistor M0 is maintained. The value of Vgs0 is the sum of the threshold voltage of the first NMOS transistor M0 and the overdrive voltage of the first NMOS transistor M0. The magnitude of the overdrive voltage is related to the magnitude of the current flowing through M0.

[0035] When the voltage V0 at the output of operational amplifier A0 rises to a level greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3, the second NMOS transistor M3 in the overshoot clamping circuit is turned on. After it is turned on, the voltage of the second capacitor C0 will be immediately pulled up to the second reference voltage Vclamp.

[0036] In terms of timing, the action of turning on the second NMOS transistor M3 when the output voltage V0 of operational amplifier A0 rises to a level greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3 should occur before the output voltage Vout reaches the target voltage. Therefore, at least before the loop causes the gate voltage of the first NMOS transistor M0 to fall back to its normal operating voltage after the output voltage Vout reaches the target voltage, the second NMOS transistor M3 must be turned on. Since the output voltage Vout will provide feedback to operational amplifier A0 after reaching the target voltage, the current and voltage at the output of operational amplifier A0 will immediately change to pull V0 down. That is, once the output voltage V0 of operational amplifier A0 can make the output voltage Vout reach the target voltage, V0 will be pulled down immediately. Therefore, the maximum output voltage V0 of operational amplifier A0 is the voltage at which the output voltage Vout can reach the target voltage and trigger the feedback. To ensure that the voltage of the second capacitor C0 is pulled down before the output voltage Vout reaches the target voltage, the maximum output voltage of operational amplifier A0 needs to be set to be greater than the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3. The maximum value of the output voltage V0 of operational amplifier A0 can reach the power supply voltage VDD. When the LDO is turned on, the LDO output charges the large load capacitor C1. This causes the gate voltage of the first NMOS transistor M0 to rise very high, far exceeding the normal operating voltage, thus providing sufficient pull-down capability to fully turn on the second PMOS transistor M2 to charge the first capacitor C1. (During large signal establishment, due to...) V0 will become very large during the charging of the first capacitor C1, far exceeding the sum of the second reference voltage Vclamp and the threshold voltage of the second NMOS transistor M3.

[0037] After the second NMOS transistor M3 is turned on, the voltage across the second capacitor C0 becomes the second reference voltage Vclamp and remains stable. When the output voltage Vout reaches the target voltage, triggering feedback and being pulled low, the voltage across the second capacitor C0 discharges outward by the magnitude of Vclamp and quickly drops to the operating voltage. During the process of the voltage across the second capacitor C0 dropping to the operating voltage by the magnitude of Vclamp, the overshoot voltage generated by the LDO circuit output is much smaller than the overshoot voltage of the LDO circuit output before clamping the second capacitor C0.

[0038] Compared with related technologies, the above-described embodiment of this application clamps the voltage of the second capacitor to the second reference voltage before the output voltage of the LDO circuit reaches the target voltage through an overshoot clamping circuit. This prevents the second capacitor from continuously supplying power after the output voltage reaches the target voltage, thus avoiding a large overshoot voltage. Through reasonable design, the overshoot voltage can be reduced to about 1 / 27 of its original value. In other words, the LDO circuit structure in this embodiment is simple, and while maintaining low power consumption of the amplifier, it can significantly shorten the setup time of large signals and reduce the overshoot voltage at the circuit output.

[0039] Another embodiment of the present invention relates to an LDO circuit, which is a supplement to the foregoing embodiments and specifically involves the following:

[0040] In one example, the circuit for generating the second reference voltage Vclamp in the above embodiment can be as follows: Figure 2 As shown, the second reference voltage Vclamp can be: the fixed voltage generated on the fourth resistor R4 by the current flowing from the power source through the current mirror CM1 and the fourth resistor R4 to ground.

[0041] In another example, the circuit for generating the second reference voltage Vclamp in the above embodiment can be as follows: Figure 3 As shown, the second reference voltage Vclamp can be: the fixed voltage generated at the drain of the third NMOS transistor M4 by the current flowing from the power supply through the current mirror CM1 and the third NMOS transistor M4 to ground.

[0042] In this circuit, the drain of the third NMOS transistor M4 is connected to the current mirror, the source is grounded, and the gate is connected to the drain. The second reference voltage Vclamp can be a fixed voltage generated at the drain of the third NMOS transistor M4.

[0043] In another example, the circuit for generating the second reference voltage Vclamp in the above embodiment can be as follows: Figure 4 As shown, the second reference voltage Vclamp can be: a fixed voltage generated at the source of the third PMOS transistor M5 by the current flowing from the power supply through the current mirror CM1 and the third PMOS transistor M5 to ground.

[0044] In this circuit, the source of the third PMOS transistor M5 is connected to the current mirror, the drain is grounded, and the gate is connected to the drain. The second reference voltage Vclamp can be a fixed voltage generated at the source of the third PMOS transistor M5.

[0045] Compared with related technologies, the above embodiments of this application provide multiple ways to generate the second reference voltage Vclamp, so that the second reference voltage Vclamp can be selected in multiple ways, which facilitates the precise control of the value of the second reference voltage Vclamp, thereby better reducing overshoot voltage.

[0046] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. An LDO circuit, characterized by, include: LDO main circuit and overshoot clamping circuit; The main circuit of the LDO includes an operational amplifier, a first NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first capacitor, a second capacitor, a first resistor, a second resistor, and a third resistor; The output terminal of the operational amplifier is connected to the gate of the first NMOS transistor. A second resistor and a second capacitor are connected in series between the output terminal of the operational amplifier and ground. The source of the first NMOS transistor is grounded, and its drain is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to the power supply voltage, and its gate is connected to its drain. The source of the second PMOS transistor is connected to the power supply voltage, and its gate is connected to the gate of the first PMOS transistor. The drain of the second PMOS transistor serves as one connection path between the output terminal of the LDO circuit and ground, and the first capacitor is connected in series. The first resistor and the third resistor are connected in series in another connection path between the drain of the second PMOS transistor and ground. The inverting input terminal of the operational amplifier is connected to the connection node between the first resistor and the third resistor, and the non-inverting input terminal of the operational amplifier is connected to a first reference voltage. The overshoot clamping circuit includes a second NMOS transistor; the source of the second NMOS transistor is connected to a second reference voltage, and the gate and drain are respectively connected to both sides of the second resistor, wherein the drain is connected to the connection node between the second capacitor and the second resistor; The maximum voltage at the output of the operational amplifier is greater than the sum of the second reference voltage and the threshold voltage of the second NMOS transistor; The action of raising the voltage at the output terminal of the operational amplifier to a level greater than the sum of the second reference voltage and the threshold voltage of the second NMOS transistor to turn on the second NMOS transistor occurs before the output voltage of the LDO circuit reaches the target voltage; after the output voltage of the LDO circuit reaches the target voltage, it provides feedback to the operational amplifier, and the voltage at the output terminal of the operational amplifier is pulled down.

2. The circuit of claim 1, wherein, The second reference voltage is a fixed voltage generated on the fourth resistor by the current flowing from the power source through the current mirror and the fourth resistor to ground.

3. The circuit of claim 1, wherein, The second reference voltage is a fixed voltage generated at the drain of the third NMOS transistor by the current flowing from the power supply through the current mirror and the third NMOS transistor to ground.

4. The circuit according to claim 1, characterized in that, The second reference voltage is a fixed voltage generated at the source of the third PMOS transistor by the current flowing from the power supply through the current mirror and the third PMOS transistor to ground.

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