A buffer circuit, a linear voltage regulator, a display panel and a near-eye display device

Abstract

The application discloses a buffer circuit, a linear voltage stabilizer, a display panel and a head-mounted display device. The buffer circuit comprises an error amplification module, a voltage clamping module and an output module; the input end of the voltage clamping module is connected with the output end of the error amplification module, the output end of the voltage clamping module is connected with the first input end of the output module, and the voltage clamping module is used for transmitting the voltage at the output end of the error amplification module to the first input end of the output module after clamping when the load current changes; and the second input end of the output module is connected with the input end of the buffer circuit. According to the application, the voltage clamping module is arranged between the output end of the error amplification module and the first input end of the output module, so that the voltage at the output end of the error amplification module can be transmitted to the first input end of the output module after clamping when the load current changes, thereby improving the loop response speed, reducing the dynamic current and reducing the static power consumption of the circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a buffer circuit, a linear regulator, a display panel, and a near-eye display device. Background Technology

[0002] Low-voltage linear regulators (LDOs) are widely used in display panels as an important circuit module in the power management unit (PMU).

[0003] Existing low-voltage linear regulators mainly consist of a voltage reference source, an error amplification module, a buffer circuit, a power transistor, and a voltage divider output module. For the buffer circuit of existing low-voltage linear regulators, when the load is large, a direct way to reduce the buffer circuit impedance is to increase its quiescent current or increase the size of the buffer circuit. However, this approach increases the overall circuit's quiescent power consumption or increases its area, and the loop response speed is too slow. Furthermore, a larger buffer circuit combined with a larger power transistor can lead to excessive overshoot voltage in the low-voltage linear regulator when the load current changes. This can cause the power transistor to briefly enter the pinch-off region, resulting in a temporary uncontrollable state for the low-voltage linear regulator. In display devices, these problems can cause a deterioration in the visual effect, resulting in screen flickering or scrolling patterns. Summary of the Invention

[0004] This invention provides a buffer circuit, a linear regulator, a display panel, and a head-mounted display device, which have a small overshoot voltage when the load current changes, prevent the power transistor from entering the pinch-off region, improve the loop response speed, reduce dynamic current, and thus reduce the static power consumption of the circuit.

[0005] In a first aspect, embodiments of the present invention provide a buffer circuit, an error amplification module, a voltage clamping module, and an output module. The output module includes a clamping signal receiving module, an amplified signal receiving module, and a feedback module. A first input terminal of the error amplification module is connected to the feedback module, a second input terminal of the error amplification module is connected to a first reference voltage, and the output terminal of the error amplification module is connected to the input terminal of the voltage clamping module. The output terminal of the voltage clamping module is connected to the clamping signal receiving module. The clamping signal receiving module and the amplified signal receiving module are both connected to the output terminal of the output module. The amplified signal receiving module receives a first amplified signal and operates under the control of the first amplified signal. The error amplification module compares the feedback voltage of the feedback module with the first reference voltage and generates a second amplified signal. The voltage clamping module generates a clamping signal under the action of the second amplified signal. The clamping signal receiving module operates under the control of the clamping signal. The amplified signal receiving module and the clamping signal receiving module jointly control the voltage at the output terminal of the output module.

[0006] Secondly, embodiments of the present invention provide a linear regulator, including a buffer circuit provided in any embodiment of the present invention; the linear regulator further includes an operational amplifier module and a power transistor; the first input terminal of the operational amplifier module is connected to the output terminal of the linear regulator, the second input terminal of the operational amplifier module is connected to a second reference voltage, the output terminal of the operational amplifier module is connected to the amplified signal receiving module of the buffer circuit, and is used to provide the first amplified signal; the gate of the power transistor is connected to the output terminal of the buffer circuit, the first terminal of the power transistor serves as the output terminal of the linear regulator, and the second terminal of the power transistor is connected to a power supply.

[0007] Thirdly, embodiments of the present invention provide a display panel including a linear regulator provided in any embodiment of the present invention.

[0008] Fourthly, embodiments of the present invention provide a head-mounted display device, including a silicon-based OLED display panel provided in any embodiment of the present invention.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a buffer circuit provided in an embodiment of the present invention;

[0012] Figure 2 This is a voltage-current curve diagram of a low-voltage linear regulator including a voltage clamping module provided in an embodiment of the present invention when the load current changes.

[0013] Figure 3 This is a schematic diagram of another dynamic current limiting and voltage limiting buffer circuit provided in an embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of a dynamic current-limiting and voltage-limiting buffer circuit that does not include a voltage clamping module.

[0015] Figure 5 This is a schematic diagram of another buffer circuit provided in an embodiment of the present invention;

[0016] Figure 6 This is a schematic diagram of another buffer circuit provided in an embodiment of the present invention;

[0017] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0018] Figure 8 This is a schematic diagram of the structure of a near-eye display device provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0021] Figure 1 This is a schematic diagram of a buffer circuit provided in an embodiment of the present invention. The embodiment of the present invention also provides a buffer circuit including... Figure 1 The buffer circuit shown is a low-voltage linear regulator. The buffer circuit in this embodiment is a dynamic current-limiting and voltage-limiting buffer circuit, suitable for providing dynamic control voltage to the gate of the power transistor in a low-voltage linear regulator.

[0022] Continue to refer to Figure 1 The dynamic current and voltage limiting buffer circuit 20 includes an error amplification module 11, a voltage clamping module 12, and an output module 13.

[0023] Output module 13 includes a clamping signal receiving module 131, an amplified signal receiving module 132, and a feedback module 133. The clamping signal receiving module 131 receives the clamping signal provided by the voltage clamping module 12 and operates under the control of the clamping signal. The amplified signal receiving module 132 receives an external first amplified signal and operates under the control of the first amplified signal. The feedback module 133 converts the current change flowing through the amplified signal receiving module 132 into a voltage change and feeds it back to the first input terminal of the error amplification module 11. Output module 13 also includes a first input terminal O1, a second input terminal O2, an output terminal PG, and a feedback terminal FB.

[0024] The first input terminal of the error amplification module 11 is connected to the feedback terminal FB of the feedback module 133, and the second input terminal of the error amplification module 11 is connected to the first reference voltage Vref1. The error amplification module 11 compares the feedback voltage of the feedback terminal FB of the output module 13 with the first reference voltage Vref1 to generate a second amplified signal for controlling the voltage clamping module 12. A high-precision first reference voltage Vref1 can be provided to the error amplification module 11 through a reference voltage source. Figure 1 The diagram illustrates the case where the first input terminal of the error amplifier module 11 is a non-inverting input terminal and the second input terminal of the error amplifier module 11 is an inverting input terminal.

[0025] The input terminal of the voltage clamping module 12 is connected to the output terminal of the error amplification module 11, and the output terminal of the voltage clamping module 12 is connected to the first input terminal O1 of the output module 13. The first input terminal O1 is connected to the control terminal of the clamping signal receiving module 131. The voltage clamping module 12 is used to provide a clamping signal to the clamping signal receiving module 131 when the load current changes, so as to control the output module 13 to output a set of dynamic voltages, so that the low-voltage linear regulator will not output excessive current, thus clamping the current range of the low-voltage linear regulator output.

[0026] The second input terminal O2 of the output module 13 serves as the input terminal of the dynamic current limiting and voltage limiting buffer circuit 20 and is connected to the control terminal of the amplified signal receiving module 132. The output terminal PG of the output module 13 serves as the output terminal of the dynamic current limiting and voltage limiting buffer circuit 20. The output module 13 is used to control the output terminal PG to follow the first input terminal O1 and the second input terminal O2 to output voltage.

[0027] Figure 1 The diagram also schematically illustrates the connection structure between the dynamic current-limiting and voltage-limiting buffer circuit 20 and other modules of the low-voltage linear regulator 30, which also includes an operational amplifier module 10 and a power transistor MP. The second input terminal O2 of the dynamic current-limiting and voltage-limiting buffer circuit 20 is connected to the output terminal of the operational amplifier module 10, providing a first amplified signal to the amplified signal receiving module 132; the output terminal PG of the dynamic current-limiting and voltage-limiting buffer circuit 20 is connected to the gate of the power transistor MP of the low-voltage linear regulator 30; the first input terminal of the operational amplifier module 10 is connected to the output terminal OUT of the low-voltage linear regulator 30; and the second input terminal of the operational amplifier module 10 is connected to the second reference voltage Vref2. Exemplarily, in... Figure 1 In the structure shown, the power transistor MP is a P-type metal-oxide-semiconductor field-effect transistor (PMOS), the first input terminal of the operational amplifier module 10 is the non-inverting input terminal, and the second input terminal is the inverting input terminal.

[0028] The power transistor (MP), also known as a regulator transistor, primarily functions as a path to provide a large current to the load. The first terminal of the power transistor (MP) is connected to the power supply VP+, and the second terminal is connected to the output of a linear regulator. Power transistors (MP) can be, but are not limited to, NPN, PNP, PMOS, or NMPS transistors. Figure 1 The diagram illustrates the case where the power transistor MP is a PMOS transistor.

[0029] When the load current of the low-voltage linear regulator 30 changes, the voltage at the output terminal OUT changes. The output terminal OUT feeds back its voltage change to the first input terminal of the operational amplifier module 10. The output terminal of the operational amplifier module 10 generates a first amplified signal based on the signal from the first input terminal and provides it to the amplified signal receiving module 132, thereby controlling the operating state of the amplified signal receiving module 132. The feedback module 133 converts the current change flowing through the amplified signal receiving module 132 into a voltage change and feeds it back to the first input terminal of the error amplifier module 11. The error amplifier module 11 outputs a second amplified signal to the voltage clamping module 12 based on the voltage change. The voltage clamping module 12 outputs a clamping signal to the clamping signal receiving module 131 based on the second amplified signal and controls the operating state of the clamping signal receiving module 131. The clamping signal receiving module 131 and the amplified signal receiving module 132 jointly control the potential of the output terminal PG.

[0030] Specifically, the change in load current of the low-voltage linear regulator 30 can refer to a situation from light load to heavy load, such as when a high-power external circuit suddenly starts working; or it can refer to a situation from heavy load to light load, such as when a high-power external circuit suddenly stops working.

[0031] When the load current changes from light load to heavy load, firstly, the clamping signal receiving module 131 and the amplifying signal receiving module 132 jointly control the potential of the output terminal PG to enhance the driving capability of the power transistor MP, so that the power transistor MP can output a larger current to meet the operation of the external circuit; then, the clamping signal receiving module 131 and the amplifying signal receiving module 132 jointly control the potential of the output terminal PG to suppress its tendency to enhance the driving capability of the power transistor MP, so that the power transistor MP can quickly enter a stable heavy load working state.

[0032] When the load current changes from heavy load to light load, firstly, the clamping signal receiving module 131 and the amplifying signal receiving module 132 jointly control the potential of the output terminal PG to weaken the driving capability of the power transistor MP, so that the power transistor MP can reduce the output current to correspond to the light load state; then, the clamping signal receiving module 131 and the amplifying signal receiving module 132 jointly control the potential of the output terminal PG to suppress its tendency to weaken the driving capability of the power transistor MP, so that the power transistor MP can quickly enter a stable light load working state.

[0033] During the above-mentioned change process, the voltage clamping module 12 provides a clamping signal, which enables the clamping signal receiving module 131 and the amplified signal receiving module 132 to jointly and quickly control the potential of the output terminal PG, so that the low-voltage linear regulator 30 can quickly change the operating current and quickly enter a stable operating state.

[0034] Optionally, the power transistor MP is a PMOS transistor. When the output terminal PG potential decreases, the driving capability of the power transistor MP is enhanced, and the power transistor MP can provide a larger current. When the output terminal PG potential increases, the driving capability of the power transistor MP is weakened, and the output current of the power transistor MP decreases.

[0035] Optionally, the output module 13 can be a PMOS source follower. The clamping signal receiving module 131 includes an eleventh transistor MB1, and the amplifying signal receiving module 132 includes a twelfth transistor MB2. Both transistors MB1 and MB2 are PMOS transistors. Preferably, the output module 13 has a small input capacitance and a low output impedance. For example, the input capacitance of the output module 13 can be between 100fF and 1pF, and the output impedance can be between 10Ω and 200Ω.

[0036] Optionally, the feedback module 133 includes a feedback resistor RF. The clamping signal receiving module 131 is connected between the power supply VP+ and the output terminal PG, and the amplified signal receiving module 132 is connected between the output terminal PG and the feedback resistor RF, which is also grounded. However, the invention is not limited to this; in other embodiments, the structure of the output module 13 can also be other forms. Optionally, the feedback module 133 provides a lower feedback voltage, which can be set to a range less than the first reference voltage Vref1.

[0037] exist Figure 1 In this circuit, the gate of the eleventh transistor MB1 is the control terminal of the clamping signal receiving module 131, connected to the first input terminal O1 of the output module 13. The second terminal of the eleventh transistor MB1 is connected to the output terminal PG, and the first terminal of the eleventh transistor MB1 is connected to the power supply VP+. The gate of the twelfth transistor MB2 is the control terminal of the amplifying signal receiving module 132, connected to the second input terminal O2 of the output module 13. The first terminal of the twelfth transistor MB2 is connected to the output terminal PG, and the second terminal of the twelfth transistor MB2 is connected to the first terminal of the feedback resistor RF. The second terminal of the feedback resistor RF is grounded, and the first terminal of the feedback resistor RF serves as the feedback terminal FB of the output module 13.

[0038] Figure 2 This is a voltage-current curve diagram of a low-voltage linear regulator including a voltage clamping module provided in an embodiment of the present invention, showing the voltage and current curves under varying load current. Figure 1 and Figure 2 The working process of the dynamic current limiting and voltage limiting buffer circuit and the low-voltage linear regulator provided in this embodiment of the invention is as follows:

[0039] When the load current IL of the low-voltage linear regulator 30 changes from light load to heavy load, such as Figure 2During the first time period T1 shown, the output current IL at the output terminal OUT of the low-voltage linear regulator 30 increases instantaneously, and correspondingly, the output voltage V... OUT Instantaneously reduced and fed back to the first input terminal of operational amplifier module 10 ( Figure 1 (The input terminal is non-inverting). The operational amplifier module 10 outputs the first amplified signal. At this time, the first amplified signal is a low voltage signal, that is, the voltage V at the second input terminal O2 of the dynamic current limiting and voltage limiting buffer circuit 20. O2 The voltage V of the output terminal PG is reduced, which controls the twelfth transistor MB2 to turn on and pull down the voltage V. PG This increases the power transistor MP's ability to supply high current. At the output terminal PG, the transistor discharges through the twelfth transistor MB2, increasing the current Id flowing through MB2. The feedback resistor RF converts this increase in current Id into an increase in voltage V. FB And it is fed back to the first input terminal of error amplifier 11 ( Figure 1 (The middle is the non-inverting input terminal); the error amplifier 11 outputs a high-voltage second amplified signal to the voltage clamping module 12; the voltage clamping module 12 provides a first clamping signal to the first input terminal O1 according to the second amplified signal.

[0040] The first clamping signal provided by the voltage clamping module 12 is a small voltage change signal, which controls the voltage at the first input terminal O1 to change slightly, thereby controlling the eleventh transistor MB1 to disconnect. Figure 1 In the structure shown, the eleventh transistor MB1 is a PMOS transistor, and the first clamping signal is a small voltage rise signal to control the eleventh transistor MB1 to turn off; however, the present invention is not limited to this. When the eleventh transistor is an NMOS transistor, the first clamping signal is a small voltage drop signal to control the eleventh transistor to turn off.

[0041] The voltage V at the first input terminal O1 O1 A slight increase in voltage causes the eleventh transistor MB1 to disconnect. At this point, in output module 13, the eleventh transistor MB1 is disconnected and no longer charges the output terminal PG. Meanwhile, the twelfth transistor MB2 remains on, continuously pulling down the potential V of the output terminal PG. PG That is, the eleventh transistor MB1 and the twelfth transistor MB2 together control the potential of the output terminal PG to drop rapidly, thereby enhancing the ability of the power transistor MP to provide a large current.

[0042] As the output terminal potential V PG As the current Id flowing through the twelfth transistor MB2 gradually decreases, the feedback voltage V at the feedback terminal FB decreases. FBThe voltage is reduced and fed back to the non-inverting input of error amplifier 11. Error amplifier 11 outputs a low-voltage second amplified signal and transmits it to voltage clamping module 12. Voltage clamping module 12 provides a second clamping signal to the first input O1 based on this second amplified signal, controlling the eleventh transistor MB1 to quickly turn on. The second clamping signal is also a small voltage change signal, and the voltage change of the second clamping signal is opposite to that of the first clamping signal. Figure 1 In the structure shown, the second clamping signal is a small voltage drop signal.

[0043] Because in the aforementioned stage, the voltage clamping module 12 controls the voltage at the first input terminal O1 to rise slightly, but not too much, the small voltage drop signal provided by the voltage clamping module 12 can quickly pull down the voltage at the first input terminal O1, controlling the eleventh transistor MB1 to quickly turn on and charge the output terminal PG, thereby quickly pulling up the potential of the output terminal PG. At this time, both the eleventh transistor MB1 and the twelfth transistor MB2 are in the conducting state, jointly controlling the potential of the output terminal PG, suppressing its tendency to enhance the driving capability of the power transistor MP, so that the output current no longer continues to rise but quickly enters a stable state, and the sudden change in load from light to heavy of the low-voltage linear regulator 30 can quickly return to a normal and stable operating state.

[0044] During the transition from light load to heavy load, the voltage clamping module 12 first provides a first clamping signal with a small voltage increase to pull up the gate voltage of the eleventh transistor MB1 and turn it off. However, it will not further increase the gate voltage of the eleventh transistor MB1, as long as the difference between the source voltage Vs and the gate voltage Vg of the eleventh transistor MB1 is less than the critical value of its threshold voltage Vth. Then, when the eleventh transistor MB1 needs to be turned on to charge the output terminal PG, only a second clamping signal with a small voltage drop is needed to quickly turn on the eleventh transistor MB1 and speed up the control speed of the power transistor MP by the output terminal PG.

[0045] Next, refer to Figure 1 and Figure 2 In this embodiment of the invention, when the load current IL of the low-voltage linear regulator 30 changes from heavy load to light load, such as during the second time period T2, the heavy load is suddenly released, the output current IL drops instantaneously, and the output voltage VOUT rises instantaneously and is fed back to the non-inverting input terminal of the operational amplifier module 10. The operational amplifier module 10 outputs a first amplified signal. At this time, the first amplified signal is a high voltage signal, and the voltage VOUT at the second input terminal is... O2 As the voltage rises, the twelfth transistor MB2 turns off, no longer pulling down the output terminal PG's potential, and the eleventh transistor MB1 turns on to charge the output terminal PG. As the current Id flowing through the twelfth transistor MB2 decreases, the feedback voltage V... FBThe voltage is reduced and fed back to the non-inverting input of error amplifier 11. Error amplifier 11 outputs a low-voltage second amplified signal and transmits it to voltage clamping module 12. Voltage clamping module 12 provides a third clamping signal to the first input O1 based on the second amplified signal to control the eleventh transistor MB1 to remain on and continuously charge the output terminal PG, thus raising the potential of the output terminal PG. At this time, the twelfth transistor MB2 turns off and stops pulling down the output terminal PG potential. The eleventh transistor MB1 charges the output terminal PG quickly. The eleventh transistor MB1 and the twelfth transistor MB2 jointly control the output terminal PG potential to rise rapidly, weakening the driving capability of power transistor MP so that power transistor MP can reduce the output current to correspond to the light load state. The third clamping signal is the voltage signal that keeps the eleventh transistor MB1 on. When the load current IL of the low-voltage linear regulator 30 is in a stable state before the change from heavy load to light load, the eleventh transistor MB1 is on, and the third clamping signal is simply the voltage signal that keeps the eleventh transistor MB1 on.

[0046] Subsequently, the potential of the output terminal PG rises, which also raises the source potential of the twelfth transistor MB2. When the source voltage Vs of the twelfth transistor MB2 rises to a threshold voltage Vth difference from its gate voltage Vg, the twelfth transistor MB2 turns on to discharge to the output terminal PG, pulling down the potential of the output terminal PG. This enhances the output current capability of the power transistor MP, preventing the output current from continuously decreasing and instead quickly entering a smooth state. At the same time, the output voltage V... OUT The upward trend slows down as the voltage V at the output terminal OUT decreases. OUT As the load level rises, the circuit resumes stable operation, providing a stable small current to meet the needs of light load conditions. At this time, both the eleventh transistor MB1 and the twelfth transistor MB2 are in the conducting state, jointly controlling the potential of the output terminal PG, suppressing the tendency of it to weaken the driving capability of the power transistor MP, so that the output current no longer decreases but quickly enters a stable state. The low-voltage linear regulator 30 can quickly recover to a normal and stable operating state when the load changes suddenly from heavy to light.

[0047] Optionally, the first reference voltage Vref1 at the second input terminal of the error amplifier module 11 is a low reference voltage. For example, the first reference voltage Vref1 is set between 50mV and 300mV. Since the first input terminal of the error amplifier module 11 is connected to the feedback terminal FB of the output module 13, the voltage at the feedback terminal FB of the output module 13 is locked within a low reference voltage range. This means the resistance value of the feedback resistor RF can also be set relatively small to ensure that under heavy load on the low-voltage linear regulator, the increased dynamic current will not cause the twelfth transistor MB2 to enter the linear region, thus preventing circuit instability.

[0048] Optionally, the error amplification module 11 can be an operational amplifier in the form of a single-sided PMOS differential pair folded, a fully folded operational amplifier, or a single-sided NMOS differential pair folded operational amplifier.

[0049] Figure 3 This is a schematic diagram of another dynamic current-limiting and voltage-limiting buffer circuit provided in an embodiment of the present invention. The embodiment of the present invention also provides a circuit including... Figure 3 The diagram shows a low-voltage linear regulator with a dynamic current-limiting and voltage-limiting buffer circuit. See also... Figure 3 The error amplification module 11 adopts a single-sided PMOS differential pair folded operational amplifier structure. Optionally, the error amplification module 11 includes a tail current source IS, a differential pair unit 110, a resistor unit 111, a first current source 112, a bias voltage supply module 113, and also includes a fifth transistor M5 and a sixth transistor M6.

[0050] The first terminal of the tail current source IS is connected to the power supply VP+, and the second terminal of the tail current source IS is connected to the first terminal of the differential pair unit 110 to provide tail current to the differential pair unit 110. The second terminal of the differential pair unit 110 serves as the first input terminal of the error amplifier module 11 and is connected to the feedback terminal FB; the third terminal of the differential pair unit 110 serves as the second input terminal of the error amplifier module 11 and is connected to the first reference voltage Vref1; the fourth terminal of the differential pair unit 110 is connected to the first current source 112, and the resistor unit 111 is connected between the fifth terminal of the differential pair unit 110 and ground. The differential pair unit 110 is used to amplify the input differential signal.

[0051] exist Figure 3 In the structure shown, the voltage clamping module 12 includes a first transistor M1. The differential pair unit 110 includes a second transistor M2 and a third transistor M3, and the resistor unit 111 includes a first resistor R1. The first current source 112 includes a fourth transistor M4, and the fourth transistor M4, the fifth transistor M5, the first transistor M1, and the sixth transistor M6 are connected in series between ground and power supply VP+. The bias voltage providing module 113 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10, and the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are connected in series between power supply VP+ and ground.

[0052] Specifically, the gate of the second transistor M2 serves as the second terminal of the differential pair unit 110, the first terminal of the second transistor M2 serves as the first terminal of the differential pair unit 110, and the second terminal of the second transistor M2 serves as the fifth terminal of the differential pair unit 110. The gate of the third transistor M3 serves as the third terminal of the differential pair unit 110, the first terminal of the third transistor M3 is connected to the first terminal of the second transistor M2, and the second terminal of the third transistor M3 serves as the fourth terminal of the differential pair unit 110. The first resistor R1 is connected between the second terminal of the second transistor M2 and ground.

[0053] The gate of the fourth transistor M4 is connected to a fixed first bias voltage Vb1. The gate of the fourth transistor M4 serves as the control terminal of the first current source 112. The first terminal of the fourth transistor M4 is connected to the second terminal of the fifth transistor M5, and the second terminal of the fourth transistor M4 is grounded. The gate of the fifth transistor M5 is connected to a fixed second bias voltage Vb2. The first terminal of the fifth transistor M5 is connected to the second terminal of the first transistor M1. The second terminal of the first transistor M1 serves as the input terminal of the voltage clamping module 12. The first terminal of the first transistor M1 serves as the output terminal of the voltage clamping module 12 and is connected to the first input terminal O1 of the output module 13. The gate of the first transistor M1 serves as the control terminal of the voltage clamping module 12. The second terminal of the sixth transistor M6 is connected to the first terminal of the first transistor M1, and the first terminal of the sixth transistor M6 is connected to the power supply VP+.

[0054] The bias voltage providing module 113 is connected to the control terminal of the first current source 112, namely the gate of the fourth transistor M4, the gate of the first transistor M1, and the gate of the sixth transistor M6. The bias voltage providing module 113 is used to provide bias voltage for the first transistor M1 and the sixth transistor M6.

[0055] The gate of the seventh transistor M7 in the bias voltage supply module 113 is connected to the gate of the sixth transistor M6 and the second terminal of the seventh transistor M7. The first terminal of the seventh transistor M7 is connected to the power supply VP+, and the second terminal of the seventh transistor M7 is connected to the first terminal of the eighth transistor M8. The gate of the eighth transistor M8 is connected to the second terminal of the eighth transistor M8. The gate of the ninth transistor M9 is connected to the gate of the first transistor M1 and the second terminal of the ninth transistor M9. The first terminal of the ninth transistor M9 is connected to the second terminal of the eighth transistor M8, and the second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10. The gate of the tenth transistor M10 is connected to the gate of the fourth transistor M4, and the second terminal of the tenth transistor M10 is connected to ground.

[0056] For example, in Figure 3In the circuit structure shown, transistors M1, M2, M3, M6, M7, M8, and M9 are all PMOS transistors, while transistors M4, M5, and M10 are NMOS transistors. The first electrode of transistors M1, M2, M3, M6, M7, M8, and M9 is the source, and the second electrode is the drain. The first electrode of transistors M4, M5, and M10 is the drain, and the second electrode is the source.

[0057] exist Figure 3 In the circuit shown, the fourth transistor M4 and the fifth transistor M5 are in a common-source, common-gate configuration. The fourth transistor M4 is a common-source transistor, with its source-to-ground voltage remaining constant, and its gate connected to a fixed first bias voltage Vb1. The fifth transistor M5 is a common-gate transistor, with its gate connected to a fixed second bias voltage Vb2. The source and gate voltages of the fourth transistor M4 remain unchanged, and the current I flowing through it remains constant, thus the fourth transistor M4 acts as a stable first current source I12. The current flowing from the power supply VP+ through the fourth transistor M4 to ground is divided into two branches: the first branch consists of the sixth transistor M6, the first transistor M1, and the fifth transistor M5, with a current of I1; the second branch consists of the third transistor M3, with a current of I2.

[0058] The tenth transistor M10 and the fourth transistor M4 form a current mirror circuit. The current of the tenth transistor M10 and the current of the fourth transistor M4 are matched. This current matching means that the channels of the tenth transistor M10 and the fourth transistor M4 can be proportionally related. The current flowing through the tenth transistor M10 can be a proportionally amplified or reduced current of the fourth transistor M4, or the current flowing through the tenth transistor M10 can be the same as the current of the fourth transistor M4. When the current of the fourth transistor M4 remains constant, the current of the tenth transistor M10 also remains stable.

[0059] The seventh transistor M7, eighth transistor M8, ninth transistor M9, and tenth transistor M10 of the bias voltage supply module 113 are connected in series between the power supply VP+ and ground. The current flowing through the bias voltage supply module 113 is stable and constant, providing a fixed voltage to the gate of the first transistor M1, i.e., the gate voltage Vg of the first transistor M1 remains constant. During the operation of the low-voltage linear regulator 30, the bias voltage supply module 113 controls the first transistor M1 to remain continuously turned on and operate stably. Optionally, in Figure 3In the circuit shown, the first transistor M1 is a PMOS transistor. According to the condition for PMOS transistor conduction, Vs - Vg ≥ Vth, meaning the source voltage Vs of the first transistor M1 is higher than the gate voltage Vg, and at least higher than the threshold voltage of the first transistor M1. When the voltage at the first input terminal O1, i.e., the source of the first transistor M1, changes, the gate voltage Vg of the first transistor M1 remains unchanged, and the source voltage Vs1 of the first transistor M1 increases or decreases to Vs2. The absolute value of the increased or decreased source voltage Vs2 is still greater than the threshold voltage Vth, so the voltage change ΔV is very small, generally not exceeding the magnitude of the threshold voltage of the first transistor M1, and is a voltage change with a small amplitude.

[0060] Figure 3 In the structure shown, the clamping signal receiving module of the output module 13 includes an eleventh transistor MB1, the amplified signal receiving module includes a twelfth transistor MB2, and the feedback module includes a feedback resistor RF. Both the eleventh transistor MB1 and the twelfth transistor MB2 are PMOS transistors. The first input terminal O1 is connected to the gate of the eleventh transistor MB1, the second input terminal O2 is connected to the gate of the twelfth transistor MB2, and the feedback terminal FB of the feedback resistor RF is connected to the gate of the second transistor MB2.

[0061] Combination Figure 1 , Figure 2 and Figure 3 , Figure 3 The operation of the dynamic current-limiting and voltage-limiting buffer circuit and the low-voltage linear regulator provided in the illustrated embodiment is as follows:

[0062] When the load current IL of the low-voltage linear regulator 30 changes from light load to heavy load, such as Figure 2 During the first time period T1, the voltage at the output terminal OUT decreases rapidly and is fed back to the first input terminal of the operational amplifier module 10. Consequently, the voltage at the second input terminal O2 of the dynamic current-limiting and voltage-limiting buffer circuit 20 decreases. The twelfth transistor MB2 is in the conducting state, pulling up the potential of the output terminal PG, thereby increasing the power transistor MP's ability to supply output current. The dynamic current Id flowing through the twelfth transistor MB2 increases instantaneously, the voltage at the feedback terminal FB rises and is fed back to the non-inverting input terminal of the error amplifier 11, which is the gate of the second transistor M2. The second transistor M2 turns off, and the current I2 flowing through the third transistor M3 increases instantaneously, i.e., the current I2 in the second branch increases; correspondingly, the current I1 in the first branch decreases instantaneously.

[0063] On the first branch, the fifth transistor M5 is operating in the saturation region, and the current flowing through the first branch is determined by the fifth transistor M5. The source voltage Vs of the fifth transistor M5 increases. The first transistor M1 and the sixth transistor M6 are operating in the linear region. The source voltage Vs of the first transistor M1, which is also the voltage of the first output terminal O1, increases slightly, controlling the eleventh transistor MB1 to temporarily turn off. This slightly increased voltage signal is the first clamping signal.

[0064] The voltage rise at the source of the first transistor M1 is small, which can control the eleventh transistor MB1 to turn off. When the eleventh transistor MB1 needs to be turned on again, it is not necessary to discharge the first output terminal O1 for a long time to pull the potential low in order to reach the turn-on voltage of the eleventh transistor MB1.

[0065] After the eleventh transistor MB1 is turned off, it no longer charges the output terminal PG. Only the twelfth transistor MB2 discharges the output terminal PG. The potential of the output terminal PG can be reduced rapidly, which quickly enhances the ability of the driving transistor MP to provide a large current.

[0066] As the potential of the output terminal PG gradually decreases, the current flowing through the twelfth transistor MB2 decreases, the feedback voltage of the feedback terminal FB decreases and is fed back to the non-inverting input terminal of the error amplifier 11, controlling the second transistor M2 to turn on, and the current I2 in the second branch where the third transistor M3 is located decreases instantaneously; correspondingly, the current I1 in the first branch where the sixth transistor M6, the first transistor M1 and the fifth transistor M5 are located increases.

[0067] At this point, in the first branch, the fifth transistor M5 operates in the saturation region, with its gate voltage remaining unchanged and its source voltage Vs decreasing. The first transistor M1 and the sixth transistor M6 operate in the linear region. The source voltage Vs of the first transistor M1, i.e., the voltage at the first output terminal O1, decreases slightly, controlling the eleventh transistor MB1 to resume conduction. This slight decrease in voltage signal serves as the second clamping signal. The eleventh transistor MB1 pulls up the potential of the output terminal PG, preventing it from decreasing further and gradually restoring it to a stable operating state. Because the voltage rise at the first output terminal O1 was small in the previous period, it can now quickly decrease to the turn-on voltage of the eleventh transistor MB1, controlling MB1 to turn on and charge the output terminal PG, pulling up the PG potential. This weakens the ability of the output terminal PG to control the power transistor MP to output a large current, clamping the increasing trend of the power transistor MP's output current and allowing the circuit to quickly return to a stable operating state.

[0068] That is, after the first time period T1, the low-voltage linear regulator 30 recovers from the sudden change in load from light to heavy to a normal and stable working state.

[0069] When the load current IL of the low-voltage linear regulator 30 changes from heavy load to light load, such as during the second time period T2, the heavy load is suddenly released, the output current IL drops instantaneously, the output voltage VOUT rises instantaneously and is fed back to the non-inverting input of the operational amplifier module 10, and the voltage V at the second input terminal O2 rises instantaneously. The twelfth transistor MB2 turns off and no longer pulls down the potential of the output terminal PG. At this time, the eleventh transistor MB1 is still in the on state, charging the output terminal PG and pulling up the potential of the output terminal PG, reducing the ability of the output terminal PG to drive the power transistor MP to provide a large current. As the current flowing through the twelfth transistor MB2 decreases, the voltage at the feedback terminal FB drops and is fed back to the gate of the second transistor M2 to keep it in the on state. The second branch current I2 remains unchanged, and correspondingly, the first branch current I1 remains unchanged. The voltage at the first input terminal O1 remains unchanged, maintaining the charging state of the eleventh transistor MB1 on the output terminal PG. That is, at this time, the third clamping signal provided by the first transistor M1 to the first input terminal O1 is the signal to keep the eleventh transistor MB1 on.

[0070] As the eleventh transistor MB1 charges the output terminal PG, the twelfth transistor MB2 turns on when the difference between the source potential of the output terminal PG (which is also the source potential of the twelfth transistor MB2) and its gate potential (which is also the potential of the second input terminal O2) exceeds the threshold voltage of the twelfth transistor MB2. At this point, both the eleventh transistor MB1 and the twelfth transistor MB2 are turned on, and the circuit quickly returns to a stable operating state.

[0071] That is, after the second time period T2, the potential of the output terminal PG gradually recovers, and the sudden change in load from heavy load to light load of the low-voltage linear regulator 30 can quickly recover to the normal and stable working state and smoothly carry out the light load working state.

[0072] Under stable operating conditions, both the eleventh transistor MB1 and the twelfth transistor MB2 are in the on state. The current flowing through the twelfth transistor MB2 is a stable operating current, and the voltage at the feedback terminal FB keeps the second transistor MB2 in the on state as well. Only when the external load changes suddenly and the current flowing through the twelfth transistor MB2 suddenly increases will the feedback voltage control the second transistor MB2 to turn off.

[0073] Please refer to Figure 4This is a schematic diagram of a buffer circuit without a voltage clamping module. In the first branch where the first input terminal O1 is located, there is no control measure for the voltage change of the first input terminal O1, i.e., the gate of the eleventh transistor MB1. The eleventh transistor MB1 turns on very slowly. For example, when the voltage at the output terminal OUT drops instantaneously, the second input terminal O2 controls the twelfth transistor MB2 to conduct and discharge to the output terminal PG. The current flowing through the twelfth transistor MB2 increases, and the increased feedback terminal voltage turns off the second transistor M2. The current of the third transistor M3 increases instantaneously. The first input terminal O1 is connected to the output terminal of the third transistor M3, and the first input terminal O1 also rises instantaneously, controlling the eleventh transistor MB1 to turn off. At this time, the potential of the first input terminal O1 is very high, close to the power supply voltage. As the twelfth transistor MB2 discharges at the output terminal PG, the potential of the output terminal PG gradually decreases. The voltage at the feedback terminal FB decreases and controls the second transistor M2 to turn on. The instantaneous current flowing through the third transistor M3 decreases. The potential of the first input terminal O1 gradually decreases through the pull-down of the fourth transistor M4. When the potential of the first input terminal O1 drops to the level that controls the eleventh transistor MB1 to turn on, the eleventh transistor MB1 begins to pull up the potential of the output terminal PG. However, because the potential of the first input terminal O1 starts to decrease from a very high state, it takes a long time for the eleventh transistor MB1 to complete the charging of the output terminal PG. Therefore, during the long charging time, the output terminal PG still controls the power transistor MP to output a large current, and the circuit stabilization time is very long.

[0074] Comparatively, refer to Figure 3 In this embodiment of the invention, the buffer circuit includes a voltage clamping module 12. When the potential of the first input terminal O1 rises to control the eleventh transistor MB1 to turn off, the module controls the voltage rise of the eleventh transistor MB1 to not exceed the threshold voltage of the first transistor MB1. When it is necessary to lower the potential of the first input terminal O1 to control the eleventh transistor MB1 to turn on, the potential of the eleventh transistor MB1 can be quickly lowered to the turn-on voltage of the eleventh transistor MB1, and the potential of the output terminal PG can be quickly raised. This controls the power transistor MP to quickly return to a stable state, and the circuit stabilization time is greatly shortened.

[0075] Figure 5 This is a schematic diagram of another dynamic current-limiting and voltage-limiting buffer circuit provided in an embodiment of the present invention. (See also...) Figure 5The error amplification module 11 adopts a fully folded operational amplifier structure. The error amplification module 11 includes a differential pair unit 110, a first current source 122, a fifth transistor M5, a sixth transistor M6, and a bias voltage supply module 113. The first terminal of the tail current source IS is connected to the power supply voltage VP+, and the second terminal of the tail current source IS is connected to the first terminal of the differential pair unit 110 to provide tail current to the differential pair unit 110. The second terminal of the differential pair unit 110 serves as the first input terminal (non-inverting input terminal) of the error amplification module 11, the third terminal of the differential pair unit 110 serves as the second input terminal (inverting input terminal) of the error amplification module 11, the fourth terminal of the differential pair unit 110 is connected to the first current source 112, and the fifth terminal of the differential pair unit 110 is connected to the bias voltage supply module 113.

[0076] The first current source 112, the fifth transistor M5, the voltage clamping module 12, and the sixth transistor M6 are connected in series between ground and power supply VP+. The bias voltage providing module 113 is connected to the control terminals of the first current source 112, the fifth transistor M5, the voltage clamping module 12, and the sixth transistor M6, respectively, and is used to provide a fixed bias voltage.

[0077] The differential pair unit 110 includes a second transistor M2 and a third transistor M3, the first current source 112 includes a fourth transistor M4, and the voltage clamping module 12 includes a first transistor M1. Figure 5 The structure shown and Figure 3 The similarities will be reiterated, and the differences will be explained below.

[0078] Optionally, the second terminal of the second transistor M2 is connected to the bias voltage supply module 113 as the fifth terminal of the differential pair unit 110. When the output voltage decreases, the second output terminal O2 is controlled to turn on the twelfth transistor MB2 to discharge the output terminal PG. The voltage at the feedback terminal FB increases, controlling the second transistor M2 to turn off. The current flowing through the second transistor M2 decreases and is transmitted to the bias voltage supply module 113, which includes the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9. Because the bias voltage supply module 113 outputs a fixed bias voltage, the current change of the second transistor M2 does not affect the voltage or current change of the bias voltage supply module 113. Similarly, when the output voltage decreases or increases, the second output terminal O2 is controlled to turn off the twelfth transistor MB2. The voltage at the feedback terminal FB decreases, controlling the second transistor M2 to turn on. When the current flowing through the second transistor M2 increases, the current change of the second transistor M2 also does not affect the fixed bias voltage output of the bias voltage supply module 113. Figure 3 By grounding the second terminal of the second transistor M2, the influence of current changes in the second transistor M2 on the circuit is eliminated. Figure 5The second transistor M2 is connected to the bias voltage provided by module 113, and the effect is basically the same.

[0079] Optionally, the gate of the fifth transistor M5 is connected to the gate of the ninth transistor M9 to provide a voltage to the gate of the fifth transistor M5, eliminating the need for an additional bias voltage supply circuit to provide a bias voltage to the fifth transistor M5, thus simplifying the circuit structure.

[0080] Figure 6 This is a schematic diagram of another dynamic current-limiting and voltage-limiting buffer circuit provided in an embodiment of the present invention, and Figure 5 The difference is that, Figure 6 The control terminal of the voltage clamping module 12 is connected to the third bias voltage Vb3. The third bias voltage Vb3 needs to be provided by the newly added bias voltage providing circuit, and the third bias voltage Vb3 can be set to any value as required.

[0081] Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 7 The display panel 1 includes the dynamic current limiting and voltage limiting buffer circuit and the low-voltage linear regulator of any of the above embodiments. The display panel 1 is a silicon-based OLED microdisplay panel.

[0082] This invention also provides a near-eye display device. Figure 8 This is a schematic diagram of a near-eye display device provided in an embodiment of the present invention, with reference to... Figure 8 The near-eye display device 2 includes the aforementioned silicon-based display panel.

[0083] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A buffer circuit, characterized in that, include: The system includes an error amplification module, a voltage clamping module, and an output module. The output module includes a clamping signal receiving module, an amplified signal receiving module, and a feedback module. The first input terminal of the error amplification module is connected to the feedback module, the second input terminal of the error amplification module is connected to the first reference voltage, the output terminal of the error amplification module is connected to the input terminal of the voltage clamping module, and the output terminal of the voltage clamping module is connected to the clamping signal receiving module; the clamping signal receiving module and the amplified signal receiving module are both connected to the output terminal of the output module. The amplified signal receiving module is used to receive the first amplified signal and operate under the control of the first amplified signal; The error amplification module is used to compare the feedback voltage of the feedback module with the first reference voltage and generate a second amplified signal, and the voltage clamping module is used to generate a clamping signal under the action of the second amplified signal; The clamping signal receiving module is used to operate under the control of the clamping signal; The amplified signal receiving module and the clamping signal receiving module jointly control the voltage at the output terminal of the output module; The voltage clamping module includes a first transistor with a fixed gate voltage. The first terminal of the first transistor serves as the output terminal of the voltage clamping module and is connected to the control terminal of the clamping signal receiving module. The second terminal of the first transistor is connected to the output terminal of the error amplification module. The error amplification module includes a differential pair unit, a first current source, a bias voltage supply module, a fifth transistor, and a sixth transistor; The first terminal of the differential pair unit is connected to a power supply, the second terminal of the differential pair unit serves as the first input terminal of the error amplification module, the third terminal of the differential pair unit serves as the second input terminal of the error amplification module, the fourth terminal of the differential pair unit is connected to the first current source, and the fifth terminal of the differential pair unit is connected to a fixed potential terminal. The differential pair unit is used to amplify the input differential signal. The first current source, the fifth transistor, the voltage clamping module, and the sixth transistor are connected in series between ground and the power supply. The gate voltage of the fifth transistor is fixed, and the gate voltage of the sixth transistor is fixed. The differential pair unit includes a second transistor and a third transistor, and the first current source includes a fourth transistor; The gate of the second transistor serves as the first input terminal of the error amplification module, the first terminal of the second transistor is connected to the power supply, and the second terminal of the second transistor is connected to the fixed potential terminal. The gate of the third transistor serves as the second input terminal of the error amplification module, the first terminal of the third transistor is connected to the first terminal of the second transistor, and the second terminal of the third transistor is connected to the first current source; The gate of the fourth transistor is connected to a first bias voltage, and the gate of the fourth transistor serves as the control terminal of the first current source. The first terminal of the fourth transistor is connected to the second terminal of the third transistor and the second terminal of the fifth transistor, and the second terminal of the fourth transistor is grounded. The first terminal of the fifth transistor serves as the output terminal of the error amplification module. The bias voltage providing module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, which are sequentially connected between the power supply and ground; the gate of the tenth transistor is connected to the first bias voltage, and the second terminal of the tenth transistor is connected to the second terminal of the fourth transistor. The gate of the seventh transistor is connected to the gate of the sixth transistor, the second terminal of the seventh transistor, and the first terminal of the eighth transistor. The seventh transistor and the first terminal of the sixth transistor are connected to the power supply. The gate of the eighth transistor is connected to the second terminal of the eighth transistor and the first terminal of the ninth transistor. The second terminal of the sixth transistor is connected to the first terminal of the first transistor. The gate of the ninth transistor is connected to the gate of the first transistor and the second terminal of the ninth transistor, respectively. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor; the gate of the tenth transistor is connected to the gate of the fourth transistor, and the second terminal of the tenth transistor is connected to ground.

2. The buffer circuit according to claim 1, characterized in that, The error amplification module includes an operational amplifier in the form of a single-sided differential pair folded operational amplifier or an operational amplifier in the form of a fully folded operational amplifier.

3. The buffer circuit according to claim 1, characterized in that, The error amplification module further includes a tail current source and a resistor unit; the tail current source is connected to the first end of the differential pair unit, and the resistor unit is connected to the fifth end of the differential pair unit.

4. The buffer circuit according to claim 1, characterized in that, The feedback voltage change controls the second transistor to turn on or off, affecting the second current change flowing through the third transistor. The second current change affects the first current change flowing through the fifth transistor, the voltage clamping module, and the sixth transistor. The first current change corresponds to the output voltage of the voltage clamping module, and the output voltage of the voltage clamping module is the clamping signal.

5. The buffer circuit according to claim 1, characterized in that, The clamping signal receiving module includes an eleventh transistor, the amplifying signal receiving module includes a twelfth transistor, and the feedback module includes a feedback resistor; The gate of the eleventh transistor is used to receive the clamping signal, and the gate of the twelfth transistor is used to receive the first amplified signal. The first terminal of the eleventh transistor is connected to the power supply, and the second terminal of the eleventh transistor is connected to the first terminal of the twelfth transistor, serving as the output terminal of the output module. The first end of the feedback resistor is connected to the second terminal of the twelfth transistor and the first input terminal of the error amplification module, and the second end of the feedback resistor is grounded.

6. A buffer circuit, characterized in that, include: The system includes an error amplification module, a voltage clamping module, and an output module. The output module includes a clamping signal receiving module, an amplified signal receiving module, and a feedback module. The first input terminal of the error amplification module is connected to the feedback module, the second input terminal of the error amplification module is connected to the first reference voltage, the output terminal of the error amplification module is connected to the input terminal of the voltage clamping module, and the output terminal of the voltage clamping module is connected to the clamping signal receiving module; the clamping signal receiving module and the amplified signal receiving module are both connected to the output terminal of the output module. The amplified signal receiving module is used to receive the first amplified signal and operate under the control of the first amplified signal; The error amplification module is used to compare the feedback voltage of the feedback module with the first reference voltage and generate a second amplified signal, and the voltage clamping module is used to generate a clamping signal under the action of the second amplified signal; The clamping signal receiving module is used to operate under the control of the clamping signal; The amplified signal receiving module and the clamping signal receiving module jointly control the voltage at the output terminal of the output module; The voltage clamping module includes a first transistor with a fixed gate voltage. The first terminal of the first transistor serves as the output terminal of the voltage clamping module and is connected to the control terminal of the clamping signal receiving module. The second terminal of the first transistor is connected to the output terminal of the error amplification module. The error amplification module includes a differential pair unit, a first current source, a bias voltage supply module, a fifth transistor, and a sixth transistor; The first terminal of the differential pair unit is connected to a power supply, the second terminal of the differential pair unit serves as the first input terminal of the error amplification module, the third terminal of the differential pair unit serves as the second input terminal of the error amplification module, the fourth terminal of the differential pair unit is connected to the first current source, and the fifth terminal of the differential pair unit is connected to a fixed potential terminal. The differential pair unit is used to amplify the input differential signal. The first current source, the fifth transistor, the voltage clamping module, and the sixth transistor are connected in series between ground and the power supply. The gate voltage of the fifth transistor is fixed, and the gate of the fifth transistor is connected to the gate of the first transistor. The gate voltage of the sixth transistor is also fixed. The differential pair unit includes a second transistor and a third transistor, and the first current source includes a fourth transistor; The gate of the second transistor serves as the first input terminal of the error amplification module, the first terminal of the second transistor is connected to the power supply, and the second terminal of the second transistor is connected to the fixed potential terminal. The gate of the third transistor serves as the second input terminal of the error amplification module, the first terminal of the third transistor is connected to the first terminal of the second transistor, and the second terminal of the third transistor is connected to the first current source; The gate of the fourth transistor is connected to a first bias voltage, and the gate of the fourth transistor serves as the control terminal of the first current source. The first terminal of the fourth transistor is connected to the second terminal of the third transistor and the second terminal of the fifth transistor, and the second terminal of the fourth transistor is grounded. The first terminal of the fifth transistor serves as the output terminal of the error amplification module. The bias voltage providing module includes a seventh transistor, a ninth transistor, and a tenth transistor, which are sequentially connected between the power supply and ground; the gate of the tenth transistor is connected to the first bias voltage, and the second terminal of the tenth transistor is connected to the second terminal of the fourth transistor. The gate of the seventh transistor is connected to the gate of the sixth transistor, the second terminal of the seventh transistor, and the first terminal of the ninth transistor; the seventh transistor and the first terminal of the sixth transistor are connected to the power supply; the second terminal of the sixth transistor is connected to the first terminal of the first transistor. The second terminal of the ninth transistor is connected to the first terminal of the tenth transistor, and the gate of the ninth transistor is connected to the gate of the fifth transistor. The gate of the tenth transistor is connected to the gate of the fourth transistor, and the second terminal of the tenth transistor is connected to ground.

7. A linear voltage regulator, characterized in that, Includes the buffer circuit described in any one of claims 1-6; The linear regulator also includes an operational amplifier module and a power transistor; The first input terminal of the operational amplifier module is connected to the output terminal of the linear regulator, the second input terminal of the operational amplifier module is connected to the second reference voltage, and the output terminal of the operational amplifier module is connected to the amplified signal receiving module of the buffer circuit and is used to provide the first amplified signal. The gate of the power transistor is connected to the output terminal of the output module of the buffer circuit, the first terminal of the power transistor serves as the output terminal of the linear regulator, and the second terminal of the power transistor is connected to the power supply.

8. The linear regulator according to claim 7, characterized in that, The voltage clamping module is used to provide the clamping signal when the load current changes, and control the output module to output a set of dynamic voltages to clamp the current range of the linear regulator.

9. The linear regulator according to claim 7, characterized in that, When the load current of the linear regulator changes, the output voltage of the linear regulator changes and feeds the voltage change back to the first input of the operational amplifier module. The operational amplifier module generates the first amplified signal and provides it to the amplified signal receiving module and controls the current of the amplified signal receiving module. The feedback module converts the current change of the amplified signal receiving module into a voltage change and feeds it back to the first input terminal of the error amplification module. The error amplification module outputs the second amplified signal to the voltage clamping module according to the voltage change. The voltage clamping module outputs the clamping signal to the clamping signal receiving module according to the second amplified signal and controls the working state of the clamping signal receiving module; The clamping signal receiving module and the amplifying signal receiving module jointly control the gate potential of the power transistor.

10. The linear regulator according to claim 7, characterized in that, Changes in load current include changes from light load to heavy load, and also changes from heavy load to light load.

11. The linear regulator according to claim 10, characterized in that, When the load current changes from light load to heavy load, firstly, the clamping signal receiving module and the amplifying signal receiving module jointly control the gate potential of the power transistor to enhance the driving capability of the power transistor, so that the power transistor outputs a larger current to meet the operation of the external circuit. Then, the clamping signal receiving module and the amplifying signal receiving module jointly control the gate potential of the power transistor to suppress the trend of the power transistor's driving capability increasing, so that the power transistor can quickly enter a stable heavy-load working state.

12. The linear regulator according to claim 10, characterized in that, When the load current changes from heavy load to light load, firstly, the clamping signal receiving module and the amplifying signal receiving module jointly adjust the gate potential of the power transistor to weaken the driving capability of the power transistor, so that the power transistor reduces the output current to correspond to the light load state. Then, the clamping signal receiving module and the amplifying signal receiving module jointly control the gate potential of the power transistor to suppress the weakening trend of the power transistor's driving capability, so that the power transistor can quickly enter a stable light-load operating state.

13. A display panel, characterized in that, Includes the linear regulator as described in any one of claims 7-12.

14. The display panel according to claim 13, characterized in that, The display panel is a silicon-based OLED microdisplay panel.

15. A near-eye display device, characterized in that, Including the silicon-based OLED microdisplay panel as described in claim 14.

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