Biasing circuit and bandgap reference circuit

Abstract

The application relates to a bias circuit and a bandgap reference circuit. The bias circuit of the application comprises: a bias voltage circuit comprising a first current path and a second current path parallel to the first current path; the second current path is configured to determine a second current according to a mirror current of a first current in the first current path, and to determine and output a bias voltage according to a mirror current of the second current; the first current is determined according to a PN junction voltage drop in the first current path; and a starting circuit configured to provide a direct current path for the bias voltage circuit when the bias circuit is powered on, so that the bias voltage circuit is out of a zero current balance state; and the starting circuit stops working after the bias voltage circuit outputs the bias voltage when the bias circuit completes starting. The bias circuit of the application can provide a current for the bandgap reference circuit, can provide a bias current for an operational amplifier of the bandgap reference circuit, and improves robustness and stability.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a bias circuit and a bandgap reference circuit. Background Technology

[0002] Reference voltage generators are crucial components in analog circuits, power management, and RF circuits. To meet application requirements, the reference voltage and / or reference current provided by the generator must be sufficiently stable, largely unaffected by process, voltage, and temperature variations. For example, bandgap reference circuits are the most common type of reference voltage generator that meets these requirements. These bandgap reference circuits typically incorporate operational amplifiers (op-amps), and the op-amp's bias current is usually provided by "self-biasing." While this method of providing bias current eliminates the need for a separate bias circuit, saving layout area and power consumption, it suffers from low robustness and instability under PVT (process, voltage, and temperature) conditions, lacking strong stability. Summary of the Invention

[0003] In view of this, embodiments of this application provide a bias circuit and a bandgap reference circuit to solve at least one problem existing in the prior art.

[0004] In a first aspect, embodiments of this application provide a bias circuit, the bias circuit comprising:

[0005] A bias voltage circuit includes a first current path and a second current path parallel to the first current path; the second current path is configured to determine a second current based on a mirror current of a first current in the first current path, and to determine and output a bias voltage based on the mirror current of the second current; the first current is determined based on the PN junction voltage drop in the first current path; and

[0006] The startup circuit is configured to provide a DC path to the bias voltage circuit when the bias circuit power supply is powered on, so that the bias voltage circuit is removed from the zero current balance state; after the bias circuit has completed startup and outputs a bias voltage, the startup circuit stops working.

[0007] In conjunction with the first aspect, in an optional embodiment, the bias voltage circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second resistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PNP transistor, a first resistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth PMOS transistor.

[0008] The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage terminal, respectively. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor, respectively. The drain of the fourth PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the seventeenth PMOS transistor, and the first terminal of the second resistor, respectively. The second terminal of the second resistor is connected to the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the sixth NMOS transistor, respectively.

[0009] The emitter of the first PNP transistor is connected to the source of the fifth NMOS transistor, and the base and collector of the first PNP transistor are connected to the first ground terminal respectively.

[0010] The first end of the first resistor is connected to the source of the sixth NMOS transistor, and the second end of the first resistor is connected to the first ground terminal.

[0011] The source of the seventeenth PMOS transistor and the source of the twentieth PMOS transistor are respectively connected to the power supply voltage terminal. The drain of the seventeenth PMOS transistor is respectively connected to the drain of the eighteenth NMOS transistor, the gate of the eighteenth NMOS transistor, and the gate of the nineteenth NMOS transistor. The drain of the nineteenth NMOS transistor is respectively connected to the drain of the twentieth PMOS transistor and the gate of the twentieth PMOS transistor and is configured to output the bias voltage. The source of the eighteenth NMOS transistor and the source of the nineteenth NMOS transistor are respectively connected to the first ground terminal.

[0012] In conjunction with the first aspect, in an optional embodiment, the startup circuit includes a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, and a thirtieth NMOS transistor;

[0013] The source of the 27th PMOS transistor is connected to the power supply voltage terminal. The gate of the 27th PMOS transistor is connected to the drain of the 27th PMOS transistor, the drain of the 28th NMOS transistor, the gate of the 28th NMOS transistor, and the gate of the 30th NMOS transistor. The source of the 28th NMOS transistor is connected to the first ground terminal. The drain of the 30th NMOS transistor is connected to the power supply voltage terminal. The source of the 30th NMOS transistor is connected to the drain of the 5th NMOS transistor and is configured to output the first bias current.

[0014] Secondly, embodiments of this application provide a bandgap reference circuit, which includes a bandgap reference core circuit and the aforementioned bias circuit.

[0015] The bandgap reference core circuit is configured to determine a bias current based on a second current in the bias circuit, and to generate and output a reference voltage under the supply of the bias current and the bias voltage output by the bias circuit.

[0016] The startup circuit in the bias circuit is also configured to provide a DC path to the bandgap reference core circuit when the bias circuit power supply is turned on, so that the bandgap reference core circuit can leave the zero current balance state; after the bias circuit completes startup and the bandgap reference core circuit outputs a reference voltage, the startup circuit stops working.

[0017] In conjunction with the second aspect, in an optional embodiment, the bandgap reference core circuit includes an operational amplifier circuit; the operational amplifier circuit includes a second common-source cascode current mirror circuit and a first operational amplifier;

[0018] The second common-source cascode current mirror circuit includes a seventh PMOS transistor and an eighth PMOS transistor;

[0019] The source of the seventh PMOS transistor is connected to the power supply voltage terminal, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the gates of the seventh PMOS transistor and the eighth PMOS transistor are respectively connected to the bias circuit to determine the bias current according to the second current in the bias circuit.

[0020] The first operational amplifier includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor;

[0021] The source of the ninth PMOS transistor and the source of the tenth PMOS transistor are respectively connected to the drain of the eighth PMOS transistor. The gate of the ninth PMOS transistor is configured as the first input terminal of the first operational amplifier, and the gate of the tenth PMOS transistor is configured as the second input terminal of the first operational amplifier. The drain of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor, and the drain of the tenth PMOS transistor is connected to the source of the twelfth PMOS transistor. The gates of the eleventh PMOS transistor and the twelfth PMOS transistor are respectively configured to input a second control signal. The drain of the eleventh PMOS transistor is connected to the drain of the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor. The source of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor are respectively connected to the first ground terminal. The drain of the fourteenth NMOS transistor is connected to the drain of the twelfth PMOS transistor and is configured as the output terminal of the first operational amplifier.

[0022] In conjunction with the second aspect, in an optional embodiment, the bandgap reference core circuit further includes a first internal bias providing circuit;

[0023] The first internal bias providing circuitry includes a fifteenth NMOS transistor and a sixteenth PMOS transistor;

[0024] The gate of the fifteenth NMOS transistor is connected to the output of the first operational amplifier, the source of the fifteenth NMOS transistor is connected to the first ground terminal, the drain of the fifteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor and the gate of the sixteenth PMOS transistor respectively and is configured as the output of the first internal bias supply circuit, and the source of the sixteenth PMOS transistor is connected to the power supply voltage terminal.

[0025] In conjunction with the second aspect, in an optional embodiment, the bandgap reference core circuit further includes a reference voltage generation circuit;

[0026] The reference voltage generating circuit includes a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a third resistor, a fourth resistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, and a twenty-sixth PMOS transistor.

[0027] The gates of the 21st PMOS transistor, the 22nd PMOS transistor, and the 23rd PMOS transistor are respectively connected to the gate of the 16th PMOS transistor. The gates of the 24th PMOS transistor, the 25th PMOS transistor, and the 26th PMOS transistor are respectively configured as input bias voltages.

[0028] The sources of the 21st PMOS transistor, the 22nd PMOS transistor, and the 23rd PMOS transistor are respectively connected to the power supply voltage terminal. The drain of the 21st PMOS transistor is connected to the source of the 24th PMOS transistor, the drain of the 22nd PMOS transistor is connected to the source of the 25th PMOS transistor, and the drain of the 23rd PMOS transistor is connected to the source of the 26th PMOS transistor. The drain of the 24th PMOS transistor is connected to the first input terminal of the first operational amplifier and the emitter of the second PNP transistor. The drain of the 25th PMOS transistor is connected to the second input terminal of the first operational amplifier and the first terminal of the third resistor. The second terminal of the third resistor is connected to the emitter of the third PNP transistor. The emitter of the fourth PNP transistor is connected to the second terminal of the fourth resistor. The first terminal of the fourth resistor is connected to the drain of the 26th PMOS transistor and is configured to output the reference voltage.

[0029] The base, collector, base, collector, base, collector, base, and collector of the second PNP transistor are respectively connected to the second ground terminal.

[0030] In conjunction with the second aspect, in an optional embodiment, the startup circuit further includes a twenty-ninth NMOS transistor;

[0031] The gate of the 29th NMOS transistor is connected to the gate of the 28th NMOS transistor, the drain of the 29th NMOS transistor is connected to the power supply voltage terminal, and the source of the 29th NMOS transistor is configured to output the second bias current.

[0032] The source of the 27th PMOS transistor in the startup circuit is connected to the power supply voltage terminal, the gate of the 27th PMOS transistor is connected to the drain of the 27th PMOS transistor, the drain of the 28th NMOS transistor and the gate of the 28th NMOS transistor respectively, and the source of the 28th NMOS transistor is connected to the first ground terminal.

[0033] In conjunction with the second aspect, in an optional embodiment, the bandgap reference circuit further includes a MOS capacitor circuit coupled between the gate terminal of the current mirror in the bandgap reference circuit and the power supply voltage terminal or between the gate terminal and the first ground terminal.

[0034] In conjunction with the second aspect, in an optional embodiment, the bandgap reference circuit further includes a start-stop control circuit;

[0035] The start-stop control circuit includes a first inverter and a second inverter; the input terminal of the first inverter is configured to input a start-stop control signal, the output terminal of the first inverter is connected to the input terminal of the second inverter and configured to output a first control signal, and the output terminal of the second inverter is configured to output a second control signal.

[0036] The start-stop control circuit further includes at least one of the thirty-first NMOS transistor, the thirty-second NMOS transistor, the thirty-third PMOS transistor, and the thirty-fourth NMOS transistor;

[0037] The thirty-first NMOS transistor is configured to turn on or off under the control of the second control signal to control the output of the startup circuit; the thirty-second NMOS transistor is configured to turn on or off under the control of the second control signal to control the output of the bias circuit; the thirty-third PMOS transistor is configured to turn on or off under the control of the first control signal to control the output of the bias circuit; and the thirty-fourth NMOS transistor is configured to turn on or off under the control of the second control signal to control the output of the reference voltage.

[0038] The beneficial effects of the technical solution provided in this application include: providing current through an independent bias circuit, which can provide bias current to the operational amplifier of the bandgap reference circuit, improving robustness and stability; determining the second current to be provided based on the PN junction voltage drop in the first current path, realizing that the bias circuit is a current reference source independent of the power supply, which also improves current stability; and injecting a first bias current into the bias voltage circuit through the startup circuit, causing it to move out of the zero current state.

[0039] Additional aspects and advantages of the embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments of this application. Attached Figure Description

[0040] The accompanying drawings, incorporated in and forming part of this specification, illustrate embodiments conforming to this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but rather to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. In the drawings:

[0041] Figure 1 A circuit diagram of a specific example of a self-biased voltage-mode bandgap reference circuit;

[0042] Figure 2 This is a schematic block diagram of a specific example of the bias circuit in an embodiment of this application;

[0043] Figure 3 The circuit diagram is a specific example of the bias circuit in the embodiments of this application;

[0044] Figure 4 This is a schematic block diagram of a specific example of a bandgap reference circuit in an embodiment of this application;

[0045] Figure 5 This is a circuit diagram of a specific example of a bandgap reference circuit in an embodiment of this application. Detailed Implementation

[0046] To make the technical solutions and beneficial effects of the embodiments of this application more apparent and understandable, a detailed description is provided below by listing specific embodiments. The accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which the embodiments of this application pertain.

[0047] It should be noted that the terms "first," "second," etc., may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. When "first" is described, it does not imply the existence of a "second"; and when "second" is discussed, it does not imply the existence of a "first." The singular forms "a," "an," and "the" may also be intended to include the plural forms unless the context clearly indicates otherwise. The term "comprising" is used to identify the presence of included features, but does not exclude the presence or addition of one or more other features. The term "and / or" includes any and all combinations of the related listed items.

[0048] Bandgap reference circuits (hereinafter referred to as "BGRs") typically include operational amplifiers, and the bias current of these operational amplifiers is usually provided by "self-biasing". For example, as Figure 1 As shown, the bias current of the operational amplifier in the voltage-mode BGR300 is provided by self-biasing. The voltage-mode BGR300 includes a fifth PNP transistor (PNP bipolar junction transistor) Q5, a sixth PNP transistor Q6, a seventh PNP transistor Q7, a fifth resistor R5, a sixth resistor R6, a third operational amplifier U3, a thirty-eighth PMOS transistor (P-type metal-oxide-semiconductor field-effect transistor) M38, a thirty-ninth PMOS transistor M39, and a fortieth PMOS transistor M40;

[0049] The positive input terminal of the third operational amplifier U3 is connected to the first terminal of the fifth resistor R5 and the drain of the thirty-eighth PMOS transistor M38, respectively. The negative input terminal of the third operational amplifier U3 is connected to the emitter of the sixth PNP transistor Q6 and the drain of the thirty-ninth PMOS transistor M39, respectively. The second terminal of the fifth resistor R5 is connected to the emitter of the fifth PNP transistor Q5. The output terminal of the third operational amplifier U3 is connected to the gate of the thirty-eighth PMOS transistor M38, the gate of the thirty-ninth PMOS transistor M39, and the gate of the fortieth PMOS transistor M40, respectively. The drain of the fortieth PMOS transistor M40 is connected to the first terminal of the sixth resistor R6 and is configured as the output. The reference voltage Vbgr is connected to the second terminal of the sixth resistor R6, which is connected to the emitter of the seventh PNP transistor Q7. The base and collector of the fifth PNP transistor Q5, the base and collector of the sixth PNP transistor Q6, the base and collector of the seventh PNP transistor Q7 are all connected to ground GND. The sources of the thirty-eighth PMOS transistor M38, the thirty-ninth PMOS transistor M39, and the fortieth PMOS transistor M40 are all connected to the power supply VDD. The bias current input terminal of the third operational amplifier U3 is connected to the gate of the thirty-ninth PMOS transistor M39. It is evident that the bias current ibias provided by the current mirror circuit of the voltage-mode BGR300 is supplied to the third operational amplifier U3. Therefore, it suffers from low robustness and instability under PVT (process, voltage, and temperature) conditions, lacking strong stability.

[0050] Therefore, embodiments of this application provide a bias circuit that can provide current to a bandgap reference core circuit, which can be used to provide bias current to operational amplifiers in the bandgap reference core circuit. For example... Figure 2 and Figure 3 As shown, the bias circuit 01 includes:

[0051] The bias voltage circuit 12 includes a first current path and a second current path parallel to the first current path; the second current path is configured to determine and output a second current I2 based on the mirror current Im of the first current I1 in the first current path, and to determine and output a bias voltage vb based on the mirror current Iin2 of the second current I2; the first current I1 is determined based on the PN junction voltage drop in the first current path.

[0052] The startup circuit 11 is configured to provide a DC path to the bias voltage circuit 12 when the bias circuit 01 is powered on, so that the bias voltage circuit 12 is removed from the zero current balance state; after the bias circuit 01 has completed startup and the bias voltage circuit 12 outputs the bias voltage, the startup circuit 11 stops working.

[0053] In this embodiment, the device providing the PN junction can be a single bipolar junction transistor (BJT); or it can be a combination of at least two transistors, which may include at least one of a bipolar junction transistor (BJT) and a MOS transistor. For example, the device providing the PN junction can be a PNP transistor. The first preset time can be determined based on the time required for the bias voltage circuit to go from startup to normal operation, and can be set according to actual needs.

[0054] This embodiment provides current through an independent bias circuit, enabling the operational amplifier in the bandgap reference core circuit to provide bias current, thus improving robustness and stability. Furthermore, the second current to be provided is determined based on the PN junction voltage drop in the first current path, making the bias circuit a power supply-independent current reference source, which also improves current stability. Finally, through a startup circuit, a first bias current can be injected into the bias voltage circuit, causing it to move out of the zero-current state.

[0055] In an alternative implementation, such as Figure 3 As shown, the bias voltage circuit 12 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a second resistor R2, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a first PNP transistor Q1, a first resistor R1, a seventeenth PMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, and a twentieth PMOS transistor M20;

[0056] The source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 are connected to the power supply voltage terminal vdda, respectively. The drain of the first PMOS transistor M1 is connected to the source of the third PMOS transistor M3. The drain of the second PMOS transistor M2 is connected to the source of the fourth PMOS transistor M4. The drain of the third PMOS transistor M3 is connected to the drain of the fifth NMOS transistor M5, the gate of the fifth NMOS transistor M5, and the gate of the sixth NMOS transistor M6, respectively. The drain of the fourth PMOS transistor M4 is connected to the gate of the first PMOS transistor M1, the gate of the second PMOS transistor M2, the gate of the seventeenth PMOS transistor M17, and the first terminal of the second resistor R2, respectively. The second terminal of the second resistor R2 is connected to the gate of the third PMOS transistor M3, the gate of the fourth PMOS transistor M4, and the drain of the sixth NMOS transistor M6, respectively.

[0057] The emitter of the first PNP transistor Q1 is connected to the source of the fifth NMOS transistor M5, and the base and collector of the first PNP transistor Q1 are connected to the first ground terminal vssa respectively.

[0058] The first terminal of the first resistor R1 is connected to the source of the sixth NMOS transistor M6, and the second terminal of the first resistor R1 is connected to the first ground terminal vssa.

[0059] The source of the seventeenth PMOS transistor M17 and the source of the twentieth PMOS transistor M20 are connected to the power supply voltage terminal vdda, respectively. The drain of the seventeenth PMOS transistor M17 is connected to the drain of the eighteenth NMOS transistor M18, the gate of the eighteenth NMOS transistor M18, and the gate of the nineteenth NMOS transistor M19, respectively. The drain of the nineteenth NMOS transistor M19 is connected to the drain of the twentieth PMOS transistor M20 and the gate of the twentieth PMOS transistor M20, respectively, and is configured as the output bias voltage vb. The source of the eighteenth NMOS transistor M18 and the source of the nineteenth NMOS transistor M19 are connected to the first ground terminal vssa, respectively.

[0060] In this embodiment, a first current mirror circuit is formed by a fifth NMOS transistor M5 and a sixth NMOS transistor M6, which can provide a first current path and a second current path, respectively. A PN junction is provided by a first PNP transistor Q1, which is coupled in the first current path and located between the first current mirror circuit and the first ground terminal vssa.

[0061] The second current I2 can be determined based on the PN junction voltage drop of the first PNP transistor Q1 and the first resistor R1. The connection position of the first resistor R1 is not limited to being coupled into the second current path and located between the first current mirror circuit and the first ground terminal vssa; it can be set according to actual needs. For example, the first resistor R1 can also be connected in parallel between the emitter and collector of the first PNP transistor Q1 to obtain the first current I1. The first current I1 can be: I1 = V BE1 / R1, where I1 represents the current value of the first current I1, V BE1 R1 represents the base-emitter voltage drop of the first PNP transistor Q1, and R1 represents the resistance value of the first resistor R1. The current value of the second current I2 can be equal to the current value of the mirror current Im of the first current I1, and the current value of the mirror current Im of the first current I1 can be equal to the current value of the first current I1.

[0062] The drains of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 can be configured to receive current from the power supply voltage terminal vdda for normal operation. The method of injecting current into the drains of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 can be set according to actual needs. In an optional embodiment, a current mirror circuit can be used to couple between the power supply voltage terminal vdda and the drain of the fifth NMOS transistor M5, and between the power supply voltage terminal vdda and the drain of the sixth NMOS transistor M6, thereby improving the accuracy and stability of the mirrored current. For example, this current mirror circuit can be a first cascode current mirror circuit composed of a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, and a fourth PMOS transistor M4. Therefore, the output current from the power supply voltage terminal vdda can be introduced into the fifth NMOS transistor M5 and the sixth NMOS transistor M6 for normal operation. By employing a current mirror structure, the stability of the second current can be guaranteed.

[0063] In this embodiment, a first voltage vc and a second voltage vd are generated at nodes 101 and 102 respectively through the second resistor R2 and the second current I2, providing bias voltages for the first cascode current mirror circuit. The first voltage vc can provide bias for the third PMOS transistor M3 and the fourth PMOS transistor M4, and the second voltage vd can provide bias for the first PMOS transistor M1 and the second PMOS transistor M2, thereby realizing the on / off control of the first PMOS transistor M1 and the second PMOS transistor M2, as well as the third PMOS transistor M3 and the fourth PMOS transistor M4, improving the rationality of voltage margin allocation and enabling the bias voltage circuit 12 to reach the desired bias point for normal operation.

[0064] The seventeenth PMOS transistor M17, the eighteenth NMOS transistor M18, the nineteenth NMOS transistor M19, and the twentieth PMOS transistor M20 constitute a second internal bias supply circuit. This second internal bias supply circuit is configured to generate and output a bias voltage vb based on the mirror current of the second current I2. The mirror current of the second current I2 can be a second internal output current Iin2, which generates the bias voltage vb at the gate of the twentieth PMOS transistor M20 and outputs it to node 106.

[0065] In an optional embodiment, the startup circuit 11 includes a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, and a thirtieth NMOS transistor M30;

[0066] The source of the 27th PMOS transistor M27 is connected to the power supply voltage terminal vdda. The gate of the 27th PMOS transistor M27 is connected to the drain of the 27th PMOS transistor M27, the drain of the 28th NMOS transistor M28, the gate of the 28th NMOS transistor M28, and the gate of the 30th NMOS transistor M30. The source of the 28th NMOS transistor M28 is connected to the first ground terminal vssa. The drain of the 30th NMOS transistor M30 is connected to the power supply voltage terminal vdda. The source of the 30th NMOS transistor M30 is connected to the drain of the 5th NMOS transistor M5 and is configured to output the first bias current inject2.

[0067] Those skilled in the art should understand that the connection between the source of the thirtieth NMOS transistor M30 and the bias voltage circuit 12 is not limited to this and can be configured according to actual needs. During the entire power-on process of the bandgap reference circuit 100, when the reference current is at the zero equilibrium point, the thirtieth NMOS transistor M30 can provide current to the branch of the fifth NMOS transistor M5, causing the circuit to leave the zero-current state. As the source potential of the thirtieth NMOS transistor M30 rises, the bias voltage circuit 12 gradually enters the normal bias state and eventually turns off the thirtieth NMOS transistor M30, completing the startup process. The startup circuit 11 no longer affects the bias voltage circuit 12. Among them, the branch formed by the twenty-seventh PMOS transistor M27 and the twenty-eighth NMOS transistor M28 should flow a very small current after the startup process is completed, in order to save power consumption of the circuit.

[0068] This application also provides a bandgap reference circuit, such as... Figure 4 As shown, the bandgap reference circuit 100 includes a bandgap reference core circuit 02 and the aforementioned bias circuit 01;

[0069] The bandgap reference core circuit 02 is configured to determine the bias current based on the second current I2 in the bias circuit, and generate and output the reference voltage Vbgr under the supply of the bias current and the bias voltage output by the bias circuit 01.

[0070] The startup circuit 11 in the bias circuit 01 is also configured to provide a DC path to the bandgap reference core circuit 02 when the bias circuit 01 is powered on, so that the bandgap reference core circuit can get out of the zero current balance state; after the bias circuit 01 completes startup, the bandgap reference core circuit 02 outputs the reference voltage Vbgr, and the startup circuit 11 stops working.

[0071] In this embodiment, the bias current Ibias, determined according to the second current I2, is provided to the operational amplifier in the bandgap reference core circuit 02 as the bias current of the operational amplifier. The bandgap reference core circuit 02 can adopt a voltage-mode, current-mode, or other mode structure, which can be set according to actual needs. The second preset time can be determined according to the time required for the bandgap reference core circuit 02 to go from startup to normal operation, and can be set according to actual needs. In this embodiment, the bias circuit 01 provides bias current and bias voltage to the bandgap reference core circuit 02, and the startup circuit injects bias current into the bandgap reference core circuit 02 to make it leave the zero current state, so that the bandgap reference core circuit 02 can achieve normal operation and output reference voltage Vbgr, thereby improving robustness and stability.

[0072] In an alternative implementation, such as Figure 5 As shown, the bandgap reference core circuit 02 includes an operational amplifier circuit 21; the operational amplifier circuit 21 includes a second common-source cascode current mirror circuit and a first operational amplifier;

[0073] The second common-source cascode current mirror circuit includes a seventh PMOS transistor M7 and an eighth PMOS transistor M8;

[0074] The source of the seventh PMOS transistor M7 is connected to the power supply voltage terminal vdda, the drain of the seventh PMOS transistor M7 is connected to the source of the eighth PMOS transistor M8, and the gates of the seventh PMOS transistor M7 and the eighth PMOS transistor M8 are respectively connected to the bias circuit 01 to determine the bias current Ibias according to the second current in the bias circuit 01.

[0075] The first operational amplifier includes the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, the twelfth PMOS transistor M12, the thirteenth NMOS transistor M13, and the fourteenth NMOS transistor M14;

[0076] The source of the ninth PMOS transistor M9 and the source of the tenth PMOS transistor M10 are connected to the drain of the eighth PMOS transistor, respectively. The gate of the ninth PMOS transistor M9 is configured as the first input terminal of the first operational amplifier, and the gate of the tenth PMOS transistor M10 is configured as the second input terminal of the first operational amplifier. The drain of the ninth PMOS transistor M9 is connected to the source of the eleventh PMOS transistor M11, and the drain of the tenth PMOS transistor M10 is connected to the source of the twelfth PMOS transistor M12. The gate of the eleventh PMOS transistor M11 and the twelfth PMOS transistor M12 are connected to the source of the eleventh PMOS transistor M12. The gate of PMOS transistor M12 is configured to input the second control signal pd. The drain of the eleventh PMOS transistor M11 is connected to the drain of the thirteenth NMOS transistor M13, the gate of the thirteenth NMOS transistor M13, and the gate of the fourteenth NMOS transistor M14. The source of the thirteenth NMOS transistor M13 and the source of the fourteenth NMOS transistor M14 are connected to the first ground terminal vssa. The drain of the fourteenth NMOS transistor M14 is connected to the drain of the twelfth PMOS transistor M12 and is configured as the output terminal of the first operational amplifier.

[0077] In this embodiment, the second cascode current mirror circuit is configured to mirror the second current I2 to obtain and output a bias current Ibias. The second cascode current mirror circuit can be connected to the first cascode current mirror circuit disposed in the bias circuit 01, thereby forming a current mirror structure that replicates the second current I2 provided by the bias circuit 01. The bias current Ibias can be a mirror current of the second current I2. The bias current Ibias can be output through node 103 to provide power to the first operational amplifier. The first operational amplifier can operate normally with the bias current Ibias supplied, improving robustness and stability. For example, the gate of the seventh PMOS transistor M7 can be connected to the gate of the first PMOS transistor M1, and the gate of the eighth PMOS transistor M8 can be connected to the gate of the third PMOS transistor M3.

[0078] The input pair of the first operational amplifier includes the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11, and the twelfth PMOS transistor M12, forming a common-source, common-gate input pair, which can increase the internal resistance and thus the gain of the operational amplifier. Those skilled in the art should understand that the first operational amplifier can also employ other operational amplifier structures, which can be configured according to actual needs. The second control signal pd can be provided by the internal circuitry of the bandgap reference circuit 100 or by an external control device connected to the bandgap reference circuit 100. This control device can be programmable.

[0079] In an optional embodiment, the bandgap reference core circuit 02 further includes a first internal bias providing circuit 22;

[0080] The first internal bias supply circuit 22 includes a fifteenth NMOS transistor M15 and a sixteenth PMOS transistor M16;

[0081] The gate of the fifteenth NMOS transistor M15 is connected to the output of the first operational amplifier. The source of the fifteenth NMOS transistor M15 is connected to the first ground terminal vssa. The drain of the fifteenth NMOS transistor M15 is connected to the drain of the sixteenth PMOS transistor M16 and the gate of the sixteenth PMOS transistor M16, respectively, and is configured as the output of the first internal bias supply circuit 22. The source of the sixteenth PMOS transistor M16 is connected to the power supply voltage terminal vdda.

[0082] In this embodiment, the fifteenth NMOS transistor M15 can act as a current source, determining the first internal output current Iin1 based on the internal voltage at node 104 of the first operational amplifier output. Since the internal voltage of the first operational amplifier output remains stable, the first internal output current Iin1 also remains stable. Therefore, when there is power supply ripple, the gate-source voltage of the sixteenth PMOS transistor M16 remains constant to ensure it has the same current as the fifteenth NMOS transistor M15. Consequently, the voltage at node 105 changes synchronously with the power supply voltage at the power supply terminal vdda. This process ensures the stability of the first internal output current Iin1, improves the power supply ripple rejection ratio (PSRR), overcomes the influence of noise (such as power supply ripple) in the power supply voltage on the output, and improves the stability of the reference voltage Vbgr.

[0083] Those skilled in the art will understand that the fifteenth NMOS transistor M15 can be any other single transistor or a combination of at least two transistors to form a current source; the sixteenth PMOS transistor M16 can be any other single transistor or a combination of at least two transistors, and both can be configured according to actual needs. For example, the fifteenth NMOS transistor M15 can be a low-side power transistor circuit. The sixteenth PMOS transistor M16 can be a high-side power transistor circuit. The low-side power transistor circuit can be a low-side switching circuit where power transistors are combined between the low-voltage end of the load and the reference point (which can be the negative terminal of the power supply), and the high-side power transistor circuit can be a high-side switching circuit where power transistors are combined between the positive terminal of the power supply and the high-voltage end of the load. Both the low-side and high-side power transistor circuits can include a control terminal, a first signal terminal, and a second signal terminal. Their operating principle is that, under the control of the control signal input at the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off, thereby connecting or blocking the signal transmission between the first signal terminal and the second signal terminal. The power transistor combination can be at least one of NMOS transistors (N-type metal-oxide-semiconductor field-effect transistors), PMOS transistors (P-type metal-oxide-semiconductor field-effect transistors), and other transistors. For example, in a low-side power transistor circuit, the power transistor combination can include NMOS transistors, while in a high-side power transistor circuit, the power transistor combination can include PMOS transistors.

[0084] In an optional embodiment, the bandgap reference core circuit 02 further includes a reference voltage generation circuit 23;

[0085] The reference voltage generation circuit 23 includes a second PNP transistor Q2, a third PNP transistor Q3, a fourth PNP transistor Q4, a third resistor R3, a fourth resistor R4, a twenty-first PMOS transistor M21, a twenty-second PMOS transistor M22, a twenty-third PMOS transistor M23, a twenty-fourth PMOS transistor M24, a twenty-fifth PMOS transistor M25, and a twenty-sixth PMOS transistor M26.

[0086] The gates of the twenty-first PMOS transistor M21, the twenty-second PMOS transistor M22, and the twenty-third PMOS transistor M23 are respectively connected to the gate of the sixteenth PMOS transistor M16. The gates of the twenty-fourth PMOS transistor M24, the twenty-fifth PMOS transistor M25, and the twenty-sixth PMOS transistor M26 are respectively configured to the input bias voltage vb.

[0087] The sources of the twenty-first PMOS transistor M21, the twenty-second PMOS transistor M22, and the twenty-third PMOS transistor M23 are connected to the power supply voltage terminal vdda, respectively. The drain of the twenty-first PMOS transistor M21 is connected to the source of the twenty-fourth PMOS transistor M24, the drain of the twenty-second PMOS transistor M22 is connected to the source of the twenty-fifth PMOS transistor M25, and the drain of the twenty-third PMOS transistor M23 is connected to the source of the twenty-sixth PMOS transistor M26. The drain of transistor M24 is connected to the first input terminal of the first operational amplifier and the emitter of the second PNP transistor Q2. The drain of the twenty-fifth PMOS transistor M25 is connected to the second input terminal of the first operational amplifier and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the emitter of the third PNP transistor Q3. The emitter of the fourth PNP transistor Q4 is connected to the second terminal of the fourth resistor R4. The first terminal of the fourth resistor R4 is connected to the drain of the twenty-sixth PMOS transistor M26 and is configured as the output reference voltage Vbgr.

[0088] The base and collector of the second PNP transistor Q2, the base and collector of the third PNP transistor Q3, the base and collector of the fourth PNP transistor Q4 are respectively connected to the second ground terminal psub.

[0089] In this embodiment, the 21st PMOS transistor M21, 22nd PMOS transistor M22, 23rd PMOS transistor M23, 24th PMOS transistor M24, 25th PMOS transistor M25, and 26th PMOS transistor M26 form a third cascode current mirror circuit. By employing a cascode current mirror structure, the output impedance is improved. Furthermore, the bias of the 21st PMOS transistor M21, 22nd PMOS transistor M22, and 23rd PMOS transistor M23 is provided by the first internal bias providing circuit 22, which improves stability. Those skilled in the art should understand that the third cascode current mirror circuit can also adopt other structures, which can be configured according to actual needs. For example, the third cascode current mirror circuit can be stacked in multiple layers.

[0090] The second ground terminal psub, which is connected to the second PNP transistor Q2, the third PNP transistor Q3, and the fourth PNP transistor Q4, can be grounded independently. This allows the second PNP transistor Q2, the third PNP transistor Q3, and the fourth PNP transistor Q4 to obtain a relatively clean ground, thereby avoiding affecting the output and improving stability.

[0091] The bias voltage vb provided to the gates of the 24th PMOS transistor M24, the 25th PMOS transistor M25, and the 26th PMOS transistor M26 can be provided by the bias voltage circuit output within the bandgap reference circuit 100. Alternatively, it can be provided by an external control device connected to the bandgap reference circuit 100. This control device can be programmable. For example, the gate of the 20th PMOS transistor M20 is connected via node 106 to the gates of the 24th PMOS transistor M24, the 25th PMOS transistor M25, and the 26th PMOS transistor M26, respectively, to provide a bias voltage to the third cascode current mirror circuit. Therefore, this embodiment of the application achieves the provision of a bias voltage to the reference voltage generation circuit 23 through the bias circuit within the bandgap reference circuit 100, improving the rationality of voltage margin allocation and enabling the reference voltage generation circuit 23 to reach the desired bias point for normal operation.

[0092] In an optional embodiment, the startup circuit 11 further includes a twenty-ninth NMOS transistor M29;

[0093] The gate of the twenty-ninth NMOS transistor M29 is connected to the gate of the twenty-eighth NMOS transistor M28. The drain of the twenty-ninth NMOS transistor M29 and the drain of the thirtieth NMOS transistor M30 are respectively connected to the power supply voltage terminal vdda. The source of the twenty-ninth NMOS transistor M29 is configured to output the second bias current inject1.

[0094] In the startup circuit 11, the source of the 27th PMOS transistor M27 is connected to the power supply voltage terminal vdda. The gate of the 27th PMOS transistor M27 is connected to the drain of the 27th PMOS transistor M27, the drain of the 28th NMOS transistor M28, and the gate of the 28th NMOS transistor M28. The source of the 28th NMOS transistor M28 is connected to the first ground terminal vssa.

[0095] In this embodiment, the source of the twenty-ninth NMOS transistor M29 can be connected to the emitter of the second PNP transistor Q2. Those skilled in the art should understand that the connection between the source of the twenty-ninth NMOS transistor M29 and the bandgap reference core circuit 02 can be configured according to actual needs. During the power-on process of the entire bandgap reference circuit 100, when the reference current is at the zero equilibrium point, the twenty-ninth NMOS transistor M29 can provide current to the branch of the second PNP transistor Q2, causing the circuit to leave the zero-current state. As the source potential of the twenty-ninth NMOS transistor M29 rises, the circuit gradually enters the normal bias state, and eventually turns off the twenty-ninth NMOS transistor M29, completing the startup process. The startup circuit 11 no longer affects the bandgap reference core circuit 02.

[0096] In an optional embodiment, the bandgap reference circuit 100 further includes a MOS capacitor circuit coupled between the gate terminal of the current mirror in the bandgap reference circuit 100 and the power supply voltage terminal vdda or between the gate terminal and the first ground terminal vssa.

[0097] In this embodiment, the MOS capacitor circuit reduces the fluctuation of the gate potential of the current mirror, ensuring relative stability of the gate and improving stability. As a specific example, the MOS capacitor circuit includes at least one of the following: the thirty-fifth PMOS transistor M35, the thirty-sixth NMOS transistor M36, and the thirty-seventh PMOS transistor M37.

[0098] The source and drain of the 35th PMOS transistor M35 are connected to the power supply voltage terminal vdda, respectively. The gate of the 35th PMOS transistor M35 is connected to the gate terminal of the first common-source common-gate current mirror circuit in the bias voltage circuit 12. For example, the gate of the 35th PMOS transistor M35 is connected to the gate of the first PMOS transistor M1.

[0099] The source and drain of the thirty-sixth NMOS transistor M36 are connected to the first ground terminal vssa, respectively. The gate of the thirty-sixth NMOS transistor M36 is connected to the gate terminal of the current mirror in the second internal bias supply circuit of the bias voltage circuit 12. For example, the gate of the thirty-sixth NMOS transistor M36 is connected to the gate of the eighteenth NMOS transistor M18.

[0100] The source and drain of the thirty-seventh PMOS transistor M37 are connected to the power supply voltage terminal vdda, respectively. The gate of the thirty-seventh PMOS transistor M37 is connected to the gate terminal of the third common-source common-gate current mirror circuit in the reference voltage generation circuit 23 of the bandgap reference core circuit 02. For example, the gate of the thirty-seventh PMOS transistor M37 is connected to the gate of the twenty-first PMOS transistor M21.

[0101] In an optional embodiment, the bandgap reference circuit 100 further includes a start / stop control circuit;

[0102] The start / stop control circuit includes a first inverter U1 and a second inverter U2; the input terminal of the first inverter U1 is configured to input the start / stop control signal pd_bg, the output terminal of the first inverter U1 is connected to the input terminal of the second inverter U2 and is configured to output the first control signal pdb, and the output terminal of the second inverter U2 is configured to output the second control signal pd.

[0103] In an optional embodiment, the start-stop control circuit further includes at least one of the thirty-first NMOS transistor M31, the thirty-second NMOS transistor M32, the thirty-third PMOS transistor M33, and the thirty-fourth NMOS transistor M34;

[0104] The thirty-first NMOS transistor M31 is configured to turn on or off under the control of the second control signal pd to control the output of the startup circuit 11; the thirty-second NMOS transistor M32 is configured to turn on or off under the control of the second control signal pd to control the output of the bias circuit 01; the thirty-third PMOS transistor M33 is configured to turn on or off under the control of the first control signal pdb to control the output of the bias circuit; the thirty-fourth NMOS transistor M34 is configured to turn on or off under the control of the second control signal pd to control the output of the reference voltage Vbgr.

[0105] In this embodiment, the second control signal pd is provided by the internal circuit of the bandgap reference circuit 100 through a start-stop control circuit. The input port of the start-stop control signal pd_bg is the power-down port of the entire circuit structure. When the input port is set to a high potential (such as power supply voltage), the first control signal pdb is at a low potential (such as zero potential), the second control signal pd is at a high potential, and the entire bandgap reference circuit 100 is turned off; conversely, when the input port is at a low potential, the bandgap reference circuit 100 is turned on.

[0106] Those skilled in the art will understand that the coupling methods of the thirty-first NMOS transistor M31, the thirty-second NMOS transistor M32, the thirty-third PMOS transistor M33, and the thirty-fourth NMOS transistor M34 with each circuit can be configured according to actual needs. For example, the source of the thirty-first NMOS transistor M31 can be connected to the first ground terminal vssa, the drain of the thirty-first NMOS transistor M31 can be connected to the gate of the twenty-eighth NMOS transistor M28, and the gate of the thirty-first NMOS transistor M31 can be configured to input the second control signal pd. The source of the thirty-second NMOS transistor M32 can be connected to the first ground terminal vssa, the drain of the thirty-second NMOS transistor M32 can be connected to the gate of the fifth NMOS transistor M5, and the gate of the thirty-second NMOS transistor M32 can be configured to input the second control signal pd. The source of the thirty-third PMOS transistor M33 can be connected to the power supply voltage terminal vdda, and the drain of the thirty-third PMOS transistor M33 can be connected to the gate of the seventh PMOS transistor M7. The gate of the thirty-third PMOS transistor M33 can be configured to input the first control signal pdb. The source of the thirty-fourth NMOS transistor M34 can be connected to the first ground terminal vssa, and the drain of the thirty-fourth NMOS transistor M34 can be connected to the first terminal of the fourth resistor. The gate of the thirty-fourth NMOS transistor M34 can be configured to input the second control signal pd. In addition, the thirty-first NMOS transistor M31, the thirty-second NMOS transistor M32, the thirty-third PMOS transistor M33, and the thirty-fourth NMOS transistor M34 can all be other controllable semiconductor switching devices, which can be set according to actual needs. For example, they can include at least one of the following devices: BJT (transistor), SCR (silicon controlled rectifier), GTO (gate turn-off thyristor), MOSFET (metal-oxide-semiconductor field-effect transistor, abbreviated as MOS transistor), IGBT (insulated gate bipolar transistor), MCT (MOS controlled thyristor), and SIT (static induction transistor).

[0107] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A bias circuit, characterized in that, The bias circuit includes: A bias voltage circuit includes a first current path and a second current path parallel to the first current path; the second current path is configured to determine a second current based on a mirror current of a first current in the first current path, and to determine and output a bias voltage based on the mirror current of the second current; the first current is determined based on the PN junction voltage drop in the first current path; and The startup circuit is configured to provide a DC path to the bias voltage circuit when the bias circuit power supply is powered on, so that the bias voltage circuit is removed from the zero current balance state; after the bias circuit has completed startup and the bias voltage circuit outputs a bias voltage, the startup circuit stops working. The bias circuit is configured to be connected to a bandgap reference core circuit, which determines a bias current based on the second current and generates and outputs a reference voltage under the supply of the bias current and the bias voltage.

2. The bias circuit according to claim 1, characterized in that, The bias voltage circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a second resistor, a fifth NMOS transistor, a sixth NMOS transistor, a first PNP transistor, a first resistor, a seventeenth PMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, and a twentieth PMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the power supply voltage terminal, respectively. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The drain of the second PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor, and the gate of the sixth NMOS transistor, respectively. The drain of the fourth PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the second PMOS transistor, the gate of the seventeenth PMOS transistor, and the first terminal of the second resistor, respectively. The second terminal of the second resistor is connected to the gate of the third PMOS transistor, the gate of the fourth PMOS transistor, and the drain of the sixth NMOS transistor, respectively. The emitter of the first PNP transistor is connected to the source of the fifth NMOS transistor, and the base and collector of the first PNP transistor are connected to the first ground terminal respectively. The first end of the first resistor is connected to the source of the sixth NMOS transistor, and the second end of the first resistor is connected to the first ground terminal. The source of the seventeenth PMOS transistor and the source of the twentieth PMOS transistor are respectively connected to the power supply voltage terminal. The drain of the seventeenth PMOS transistor is respectively connected to the drain of the eighteenth NMOS transistor, the gate of the eighteenth NMOS transistor, and the gate of the nineteenth NMOS transistor. The drain of the nineteenth NMOS transistor is respectively connected to the drain of the twentieth PMOS transistor and the gate of the twentieth PMOS transistor and is configured to output the bias voltage. The source of the eighteenth NMOS transistor and the source of the nineteenth NMOS transistor are respectively connected to the first ground terminal.

3. The bias circuit according to claim 2, characterized in that, The startup circuit includes a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, and a thirtieth NMOS transistor; The source of the 27th PMOS transistor is connected to the power supply voltage terminal. The gate of the 27th PMOS transistor is connected to the drain of the 27th PMOS transistor, the drain of the 28th NMOS transistor, the gate of the 28th NMOS transistor, and the gate of the 30th NMOS transistor. The source of the 28th NMOS transistor is connected to the first ground terminal. The drain of the 30th NMOS transistor is connected to the power supply voltage terminal. The source of the 30th NMOS transistor is connected to the drain of the 5th NMOS transistor and is configured to output the first bias current.

4. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes a bandgap reference core circuit and a bias circuit as described in any one of claims 1-3; The bandgap reference core circuit is configured to determine a bias current based on a second current in the bias circuit, and to generate and output a reference voltage under the supply of the bias current and the bias voltage output by the bias circuit. The startup circuit in the bias circuit is also configured to provide a DC path to the bandgap reference core circuit when the bias circuit power supply is turned on, so that the bandgap reference core circuit can leave the zero current balance state; after the bias circuit completes startup and the bandgap reference core circuit outputs a reference voltage, the startup circuit stops working.

5. The bandgap reference circuit according to claim 4, characterized in that, The bandgap reference core circuit includes an operational amplifier circuit; the operational amplifier circuit includes a second common-source cascode current mirror circuit and a first operational amplifier. The second common-source cascode current mirror circuit includes a seventh PMOS transistor and an eighth PMOS transistor; The source of the seventh PMOS transistor is connected to the power supply voltage terminal, the drain of the seventh PMOS transistor is connected to the source of the eighth PMOS transistor, and the gates of the seventh PMOS transistor and the eighth PMOS transistor are respectively connected to the bias circuit to determine the bias current according to the second current in the bias circuit. The first operational amplifier includes a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor; The source of the ninth PMOS transistor and the source of the tenth PMOS transistor are respectively connected to the drain of the eighth PMOS transistor. The gate of the ninth PMOS transistor is configured as the first input terminal of the first operational amplifier, and the gate of the tenth PMOS transistor is configured as the second input terminal of the first operational amplifier. The drain of the ninth PMOS transistor is connected to the source of the eleventh PMOS transistor, and the drain of the tenth PMOS transistor is connected to the source of the twelfth PMOS transistor. The gates of the eleventh PMOS transistor and the twelfth PMOS transistor are respectively configured to input a second control signal. The drain of the eleventh PMOS transistor is connected to the drain of the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor, and the gate of the fourteenth NMOS transistor. The source of the thirteenth NMOS transistor and the source of the fourteenth NMOS transistor are respectively connected to the first ground terminal. The drain of the fourteenth NMOS transistor is connected to the drain of the twelfth PMOS transistor and is configured as the output terminal of the first operational amplifier.

6. The bandgap reference circuit according to claim 5, characterized in that, The bandgap reference core circuit also includes a first internal bias supply circuit; The first internal bias providing circuitry includes a fifteenth NMOS transistor and a sixteenth PMOS transistor; The gate of the fifteenth NMOS transistor is connected to the output of the first operational amplifier, the source of the fifteenth NMOS transistor is connected to the first ground terminal, the drain of the fifteenth NMOS transistor is connected to the drain of the sixteenth PMOS transistor and the gate of the sixteenth PMOS transistor respectively and is configured as the output of the first internal bias supply circuit, and the source of the sixteenth PMOS transistor is connected to the power supply voltage terminal.

7. The bandgap reference circuit according to claim 6, characterized in that, The core circuit of the bandgap reference also includes a reference voltage generation circuit. The reference voltage generating circuit includes a second PNP transistor, a third PNP transistor, a fourth PNP transistor, a third resistor, a fourth resistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a twenty-third PMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, and a twenty-sixth PMOS transistor. The gates of the 21st PMOS transistor, the 22nd PMOS transistor, and the 23rd PMOS transistor are respectively connected to the gate of the 16th PMOS transistor. The gates of the 24th PMOS transistor, the 25th PMOS transistor, and the 26th PMOS transistor are respectively configured as input bias voltages. The sources of the 21st PMOS transistor, the 22nd PMOS transistor, and the 23rd PMOS transistor are respectively connected to the power supply voltage terminal. The drain of the 21st PMOS transistor is connected to the source of the 24th PMOS transistor, the drain of the 22nd PMOS transistor is connected to the source of the 25th PMOS transistor, and the drain of the 23rd PMOS transistor is connected to the source of the 26th PMOS transistor. The drain of the 24th PMOS transistor is connected to the first input terminal of the first operational amplifier and the emitter of the second PNP transistor. The drain of the 25th PMOS transistor is connected to the second input terminal of the first operational amplifier and the first terminal of the third resistor. The second terminal of the third resistor is connected to the emitter of the third PNP transistor. The emitter of the fourth PNP transistor is connected to the second terminal of the fourth resistor. The first terminal of the fourth resistor is connected to the drain of the 26th PMOS transistor and is configured to output the reference voltage. The base, collector, base, collector, base, collector, base, and collector of the second PNP transistor are respectively connected to the second ground terminal.

8. The bandgap reference circuit according to claim 4, characterized in that, The startup circuit also includes a twenty-ninth NMOS transistor; The gate of the 29th NMOS transistor is connected to the gate of the 28th NMOS transistor, the drain of the 29th NMOS transistor is connected to the power supply voltage terminal, and the source of the 29th NMOS transistor is configured to output a second bias current. The source of the 27th PMOS transistor in the startup circuit is connected to the power supply voltage terminal, the gate of the 27th PMOS transistor is connected to the drain of the 27th PMOS transistor, the drain of the 28th NMOS transistor and the gate of the 28th NMOS transistor respectively, and the source of the 28th NMOS transistor is connected to the first ground terminal.

9. The bandgap reference circuit according to claim 4, characterized in that, The bandgap reference circuit also includes a MOS capacitor circuit, coupled between the gate terminal of the current mirror in the bandgap reference circuit and the power supply voltage terminal or between the gate terminal and the first ground terminal.

10. The bandgap reference circuit according to any one of claims 4-9, characterized in that, The bandgap reference circuit also includes a start / stop control circuit; The start-stop control circuit includes a first inverter and a second inverter; the input terminal of the first inverter is configured to input a start-stop control signal, the output terminal of the first inverter is connected to the input terminal of the second inverter and configured to output a first control signal, and the output terminal of the second inverter is configured to output a second control signal. The start-stop control circuit further includes at least one of the thirty-first NMOS transistor, the thirty-second NMOS transistor, the thirty-third PMOS transistor, and the thirty-fourth NMOS transistor; The 31st NMOS transistor is configured to be turned on or off under the control of the second control signal to control the output of the startup circuit; The thirty-second NMOS transistor is configured to turn on or off under the control of the second control signal to control the output of the bias circuit; the thirty-third PMOS transistor is configured to turn on or off under the control of the first control signal to control the output of the bias circuit. The 34th NMOS transistor is configured to be turned on or off under the control of the second control signal to control the output of the reference voltage.

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