A task processing method, apparatus, and multi-core processor in a multi-core processor

Abstract

This application discloses a task processing method, apparatus, and multi-core processor in a multi-core processor, relating to the field of integrated circuit technology, and invented to improve task execution efficiency. The method includes: receiving fault information sent by a currently faulty core among multiple cores; reading preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor based on the fault information; determining fifth state information based on the preset first state information and preset second state information, and updating the preset second state information using the fifth state information; determining sixth state information based on the identifier of the currently faulty core and the preset third state information, and updating the preset third state information using the sixth state information; and determining the currently available core based on the updated preset second state information, the updated preset third current state information, and preset fourth state information.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a task processing method, apparatus and multi-core processor in a multi-core processor. Background Technology

[0002] With the development of semiconductor technology, chip manufacturing processes are becoming increasingly complex, and the number of processor cores is increasing. Due to production defects and process deviations, the yield rate of chip manufacturing cannot reach 100%. In order to improve the yield and save costs, faulty processor cores are generally shielded before leaving the factory.

[0003] In existing technologies, when a faulty core occurs in a multi-core processor, such as a Network-on-Chip (NoC) architecture, the processing of the task involves drawing on computer network and parallel multiprocessor interconnection network technologies. Based on virtual topology, the algorithm is optimized by optimizing the row-wave column borrowing algorithm to process the faulty core, thereby further improving the reliability of multi-core processor task execution. However, in the process of processing the faulty core, the algorithm is complex and needs to take into account network distance and congestion, resulting in low task execution efficiency. Summary of the Invention

[0004] In view of this, embodiments of this application provide a task processing method, apparatus, and multi-core processor in a multi-core processor, which can improve task execution efficiency.

[0005] In a first aspect, embodiments of this application provide a task processing method in a multi-core processor, the multi-core processor including multiple cores; the method includes: receiving fault information sent by a currently faulty core among the multiple cores; the fault information including an identifier of the currently faulty core; and reading, according to the fault information, preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since leaving the factory; the third state information indicates whether the core has failed during use since leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, wherein being used includes being to be used and being used; and according to the preset first state information... Based on the information and the preset second state information, a fifth state information is determined, and the fifth state information is used to update the preset second state information so that the state of the target redundant core among the currently available redundant cores changes from unused to to be used; based on the identifier of the current faulty core and the preset third state information, a sixth state information is determined, and the sixth state information is used to update the preset third state information so that the state of the current faulty core changes from not faulty to faulty; based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information, the currently available cores are determined; the currently available cores include the target redundant core; the fourth state information indicates whether the core's state was disabled when the multi-core processor left the factory; the currently available cores execute tasks so that the target redundant core replaces the current faulty core in executing tasks.

[0006] Secondly, embodiments of this application provide a task processing device in a multi-core processor, the multi-core processor including multiple cores; the device includes: a receiving module, configured to receive fault information sent by a currently faulty core among the multiple cores; the fault information includes an identifier of the currently faulty core; a reading module, configured to read, according to the fault information, preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since leaving the factory; the third state information indicates whether the core has failed during use since leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, wherein being used includes being to be used and being used; a first updating module, configured to update, according to the preset first state information and the preset second state information, the current faulty core is identified by the fault information; the second state information includes whether the redundant core is not used and whether it is used, the third state information includes whether the core is to be used and whether it has been used; and a first updating module, configured to update, according to the preset first state information and the current faulty core is identified by the fault information. The system comprises: a second state information module, a third state information module, and an execution module. The second state information module determines a fifth state information and updates the second state information using the fifth state information, so that the state of the target redundant core among the currently available redundant cores changes from unused to to be used. The third state information module determines a sixth state information based on the identifier of the currently faulty core and the preset third state information, and updates the preset third state information using the sixth state information, so that the state of the currently faulty core changes from not faulty to faulty. The fourth state information module determines the currently available cores based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information; the currently available cores include the target redundant core; wherein the fourth state information indicates whether the core's state was disabled at the time the multi-core processor was manufactured. The execution module executes a task through the currently available cores, so that the target redundant core replaces the currently faulty core in performing the task.

[0007] Thirdly, embodiments of this application provide a multi-core processor, including: multiple cores; a fault repair module; the fault repair module includes a fault detection submodule, a computing submodule, and a first memory; wherein, the fault detection submodule is connected to the multiple cores and is used to receive fault information sent by the currently faulty core among the multiple cores; the fault information includes the identifier of the currently faulty core; the computing submodule is connected to the fault detection submodule and the first memory respectively, and is used to read preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor from the first memory according to the fault information; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since leaving the factory; the third state information indicates whether the core has failed during use since leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used. The computing submodule is further configured to determine fifth state information based on the preset first state information and the preset second state information, and update the preset second state information using the fifth state information, so that the state of the target redundant core in the currently available redundant cores changes from unused to to be used; and determine sixth state information based on the identifier of the currently faulty core and the third state information, and update the third state information using the sixth state information, so that the available core determination module obtains and determines the currently available core based on the updated preset second state information in the first memory, the updated preset third current state information, and the preset fourth state information in the second memory, so that the currently available core executes the task; the currently available core includes the target redundant core; the second memory is used to store the preset fourth state information; wherein, the fourth state information indicates whether the core state is masked when the multi-core processor leaves the factory.

[0008] The task processing method, apparatus, and multi-core processor in this embodiment read preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor based on the received fault information. Then, based on the preset first and second state information, a fifth state information is determined, and the fifth state information is used to update the preset second state information, changing the state of the target redundant core among the currently available redundant cores from unused to used. Based on the identifier of the currently faulty core and the preset third state information, a sixth state information is determined, and the sixth state information is used to update the preset third state information, changing the state of the currently faulty core from not having a fault. The process transforms a fault into a failure. Finally, based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information, the currently available core is determined. In this embodiment, after receiving the fault information, the state information is updated based on the preset first state information, the preset second state information, and the preset third state information corresponding to each core in the multi-core processor. Then, the updated preset second state information, the updated preset third current state information, and the preset fourth state information are used to determine the currently available core, and the currently available core executes the task, so that the target redundant core replaces the currently faulty core in executing the task. This improves task execution efficiency. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A flowchart illustrating a task processing method in a multi-core processor according to an embodiment of this application;

[0011] Figure 2 A flowchart illustrating a task processing device in a multi-core processor according to a specific embodiment of this application;

[0012] Figure 3 This is a schematic diagram of the structure of a multi-core processor provided in an embodiment of this application;

[0013] Figure 4 This is a schematic diagram of the structure of a multi-core processor provided in another embodiment of this application;

[0014] Figure 5 This is a schematic diagram of the structure of a multi-core processor provided in another embodiment of the present application;

[0015] Figure 6 This is a flowchart illustrating a task processing method in a multi-core processor according to a specific embodiment of this application. Detailed Implementation

[0016] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0017] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0018] Figure 1 This is a flowchart illustrating a task processing method in a multi-core processor according to an embodiment of this application, as shown below. Figure 1 As shown, this embodiment describes a task processing method in a multi-core processor, which includes multiple cores.

[0019] The method in this embodiment may include:

[0020] S101, Receive fault information sent by the currently faulty core among multiple cores.

[0021] In this embodiment, the fault information may include the identifier of the current fault core.

[0022] Fault information can identify reliability, availability, and maintainability. When an available core of a running task fails, the reliability, availability, and maintainability of that core are compromised. At this point, that core is the currently faulty core. After a failure occurs, the currently faulty core can send out the fault information.

[0023] The identifier of the currently faulty core can be information that distinguishes it from any other core. In some cases, multiple cores in a multi-core processor can be numbered from 0 to n (the number of cores is n+1), and the number can be used as an identifier.

[0024] S102. Based on the fault information, read the preset first state information, preset second state information and preset third state information corresponding to each core in the multi-core processor.

[0025] In this embodiment, the first state information indicates whether the core is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since the factory left the factory; and the third state information indicates whether the core has failed during use since the multi-core processor left the factory.

[0026] When a multi-core processor ships, it includes usable cores, which are used to run upcoming tasks. To improve the reliability of multi-core processors, redundant cores may also be included. Normally, while the usable cores are running a task, the redundant cores are not in operation. If a usable core fails, the redundant core can take over and run the task.

[0027] In this embodiment, regarding the second state information, for example, when a multi-core processor runs a task for the first time after leaving the factory, the available cores are used to run the task, while the redundant cores do not run the task. In this case, the redundant cores are in an unused state, meaning the second state information of the redundant cores indicates that the redundant cores are not used. It is understandable that during subsequent task execution, for example, if an available core fails, a redundant core needs to be used to replace the failed available core to run the task. The redundant core that has run the task can be marked as used; in this case, the second state information indicates that the redundant core is now in use.

[0028] In this embodiment, whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, where being used includes being to be used and already being used.

[0029] In this embodiment, for the third state information, before the multi-core processor leaves the factory and runs the task for the first time, the third state information of each processor core indicates that each core is in a fault-free state. After leaving the factory, when a normally functioning and usable core suddenly fails, the state of the core can be marked as a fault, and the third state information indicates that the core is in a fault state.

[0030] In this embodiment, the preset first state information, preset second state information, and preset third state information are state information that already exist before being read.

[0031] In some examples, the first state information can be configured at the factory, and this configuration remains unchanged throughout the task processing method in this embodiment. The first state information can be stored in a non-volatile storage device called a fuse, which is irreversible and difficult to change once set, preventing unauthorized alteration or unauthorized access. Fuses are set by the equipment manufacturer during the manufacturing process of multi-core processors (e.g., chips) and are typically not change by the end user. They provide a secure and reliable way to store and protect critical information at the multi-core processor level, ensuring the correct operation of the multi-core processor and the security of data.

[0032] The second and third state information can be stored in a storage unit that does not lose data when power is off, and the data in that storage unit can be modified.

[0033] S103. Based on the preset first state information and the preset second state information, determine the fifth state information, and use the fifth state information to update the preset second state information, so that the state of the target redundant core in the currently available redundant cores changes from unused to to to be used.

[0034] Since the preset first state information indicates whether the core is redundant when the multi-core processor leaves the factory, and the preset second state information indicates whether the redundant core has been used since the factory left the factory, the fifth state information can be determined based on the preset first state information and the preset second state information, and the preset second state information can be updated using the fifth state information to obtain the new second state information.

[0035] It is understood that in this embodiment, the preset second state information before the update indicates that the state of each redundant core is unused. The preset second state information after the update indicates that the state of one of the redundant cores, namely the target redundant core, changes from unused to to be used. Subsequently, this redundant core can replace the currently faulty core to perform tasks. In this step, the target redundant core has not yet started performing tasks; therefore, the updated preset second state information includes the state of the target redundant core being to be used.

[0036] In this embodiment, the state of the target redundant core to be used is transformed into the state of being used after the target redundant core replaces the currently faulty core to perform the task. This is so that when the available core performing the task fails after the method of this embodiment is completed, the updated second state information of this embodiment can be used to participate in the new round of calculation.

[0037] S104. Based on the identifier of the current faulty core and the preset third state information, determine the sixth state information, and use the sixth state information to update the preset third state information so that the current faulty core's state changes from no fault to fault.

[0038] Since the third state information indicates whether the core of the multi-core processor has failed during use from the time it was manufactured until now, the sixth state information can be determined based on the identifier of the currently failed core and the preset third state information. The preset third state information can then be updated using the sixth state information to obtain the new third state information.

[0039] The pre-updated third state information indicates that the current faulty core is in a state of no fault, while the updated pre-updated third state information indicates that the current faulty core is in a state of fault. In this embodiment, the state of the current faulty core identified in the pre-updated third state information is changed to "faulty".

[0040] S105. Determine the currently available cores based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information.

[0041] In this embodiment, the currently available cores include the target redundant cores.

[0042] In this embodiment, the fourth state information indicates whether the core state of the multi-core processor is masked when it leaves the factory.

[0043] Regarding the fourth state information, before the multi-core processor leaves the factory, due to process and other reasons, one or more cores may fail. In such cases, the faulty core can be masked, and the state of the core that failed at the time of leaving the factory is marked as faulty. In this embodiment, the state of the redundant core set at the time of leaving the factory can also be a masked state. In this embodiment, the fourth state information is used to indicate that the core is in a masked state.

[0044] S106. The currently available core performs the task so that the target redundant core replaces the currently faulty core in performing the task.

[0045] In this embodiment, the currently available cores are used to execute the task, and the target redundant core is included in the currently available redundant cores for executing the task. In this way, if the available core running the task fails, the redundant core can be used to replace it to run the task, thereby better meeting the user's requirements and saving costs.

[0046] In this embodiment, based on the received fault information, preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor are read. Then, based on the preset first state information and preset second state information, a fifth state information is determined, and the fifth state information is used to update the preset second state information, changing the state of the target redundant core among the currently available redundant cores from unused to to be used. Based on the identifier of the current faulty core and the preset third state information, a sixth state information is determined, and the sixth state information is used to update the preset third state information, changing the state of the current faulty core from not having a fault to having a fault. Finally, based on the updated preset second state information and the updated preset third state information, the fifth state information is determined, and the sixth state information is used to update the preset third state information, changing the state of the current faulty core from not having a fault to having a fault. The system uses a third current state information and a preset fourth state information to determine the currently available cores. In this embodiment, after receiving fault information, the system updates the state information based on the preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor. Then, the updated preset second state information, updated preset third current state information, and preset fourth state information are used to determine the currently available cores, and the currently available cores execute the tasks so that the target redundant core replaces the currently faulty core in executing the tasks. This improves task execution efficiency and avoids the problem of low task execution efficiency caused by the complexity of the algorithm due to the use of virtual topology-based methods in the prior art.

[0047] In some examples, the task processing method of this embodiment can be applied to multi-core processors with non-NoC architectures.

[0048] In a NoC architecture multi-core processor, each core needs to communicate with other cores during task execution. In a non-NoC architecture multi-core processor, each core does not need to communicate with other cores during task execution; that is, each core can independently complete the received task.

[0049] In one embodiment of this application, since the first state information and the fourth state information do not need to be updated, these two state information can be stored in the fuse memory; since the second state information and the third state information need to be updated, these two state information can be stored in the flash memory.

[0050] In some examples, the fifth state information is determined based on preset first state information and preset second state information, and may include:

[0051] S103a. Determine the seventh state information based on the preset first state information and the preset second state information.

[0052] In this embodiment, the seventh state information indicates whether the redundant core will be used. That is, based on the preset first state information and the preset second state information, it can be determined that one redundant core will be used, while the state of other redundant cores remains unused.

[0053] S103b. Determine the fifth state information based on the seventh state information and the preset second state information.

[0054] In this embodiment, the fifth status information indicates whether the redundant core has been used since the factory manufacturing process. The used redundant core includes the target redundant core. The fifth status information of the target redundant core indicates that it will be used. After the target redundant core is used to replace the current faulty core to run the task, the fifth status information of the target redundant core indicates that it has been used.

[0055] In some examples, the preset first state information is a preset first binary number, and the preset second state information is a preset second binary number. The preset first binary number maps each core to different bits in the binary number, and the value of each bit in the binary number is configured according to whether the state of each core is redundant when the multi-core processor leaves the factory. The preset second binary number maps each core to different bits in the binary number, and the value of each bit in the binary number is determined according to whether the redundant core has been used since the manufacturing process. The preset first state information and the preset second state information are represented by binary numbers, which facilitates the process of determining the currently available cores in a convenient and quick manner.

[0056] Correspondingly, in this embodiment, determining the seventh state information (S103a) based on the preset first state information and the preset second state information may include:

[0057] A1. Perform logical operations on the preset first binary number and the preset second binary number to obtain the third binary number.

[0058] In some cases, the third binary number can indicate whether a redundant core is available.

[0059] In a specific example, in the preset first binary number, 1 is used to indicate that the core is in a redundant state at the time of manufacture, and 0 indicates that the core is in a non-redundant state, such as the first binary number being 0001; in the preset second binary number, 1 is used to indicate that the redundant core has been used from the time of manufacture to the present, and 0 indicates the opposite state, such as the second binary number being 0000. The first binary number and the second binary number can be ORed to obtain the third binary number being 0001.

[0060] A2. Shift the third binary number to the right sequentially until it encounters a number that indicates the core is in use, and record the number of bits shifted to the right, n.

[0061] If 1 indicates that the core is in use, shift 0001 to the right sequentially until 1 is encountered. In this embodiment, the number of bits n shifted to the right is 0.

[0062] A3. Shift the number representing the core state as being used to the left by n bits to obtain the fourth binary number.

[0063] When n is 0, shifting 1 left by 0 bits results in the fourth binary number being 0001.

[0064] If the third binary number is 1010, then the fourth binary number is 0010.

[0065] In this embodiment, a third binary number is obtained by performing logical operations on a preset first binary number and a preset second binary number. The third binary number is then shifted to the right until it encounters a number that indicates the core state is in use, and the number of bits shifted to the right, n, is recorded. The number that indicates the core state is in use is then shifted to the left by n bits to obtain a fourth binary number. This method can determine the seventh state information more conveniently and quickly.

[0066] In some examples, determining the fifth state information (S103b) based on the seventh state information and the preset second state information may include:

[0067] B1. Perform logical operations on the fourth and second binary numbers to obtain the fifth binary number.

[0068] The fourth binary number and the second binary number can be ORed to obtain the fifth binary number.

[0069] In this embodiment, the fourth binary number and the second binary number are logically operated on to obtain the fifth binary number, which can conveniently and quickly determine the sixth state information.

[0070] Updating the preset second state information using the fifth state information (S103c) may include:

[0071] C1. Update the preset second binary number using the fifth binary number.

[0072] In some examples, the preset third status information is a preset sixth binary number; the preset sixth binary number is the process of mapping each core to different bits in the binary number, and determining the value of each bit in the binary number based on whether the core has malfunctioned since it was manufactured until now, and representing the preset third status information through the binary number, which facilitates the process of determining the currently available cores.

[0073] Correspondingly, in this embodiment, determining the sixth state information based on the identifier of the current fault core and the preset third state information, and updating the preset third state information using the sixth state information (S104) may include:

[0074] S104a. Based on the identifier of the current faulty core, determine that the current faulty core is located at the m-th bit in the preset sixth binary number.

[0075] It is understood that in this embodiment, the core identifier corresponds to the core's position in the binary number.

[0076] S104b: Shift the binary number representing the core state as faulty to the left by m bits, and perform a logical operation between the result and the preset sixth binary number to obtain the seventh binary number.

[0077] In this embodiment, the obtained result can be ORed with a preset sixth binary number.

[0078] If there are four cores, and 1 represents the state of a core failure, then 1 can be shifted left by m bits. If m is 2, then shifting 1 left by m bits will result in 0100. If the preset sixth binary number is 0001, then performing a bitwise OR operation between 0100 and 0001 will result in the seventh binary number 0101.

[0079] S104c, Update the preset sixth binary number using the seventh binary number.

[0080] In this embodiment, based on the identifier of the current faulty core, it is determined that the current faulty core is located at the m-th bit in the preset sixth binary number. The binary number representing the state of the core as having a fault is shifted left by m bits, and the result is logically operated with the preset sixth binary number to obtain the seventh binary number. The preset sixth binary number is then updated using the seventh binary number. In this way, the preset third state information can be updated more conveniently and quickly.

[0081] In some other examples, the preset fourth state information is a preset eighth binary number. The preset octal number is the process of mapping each core to different bits in the binary number, and determining the value of each bit in the binary number based on whether the core was disabled at the time of manufacture. The preset fourth state information is represented by the binary number, which facilitates the process of determining the currently available cores quickly and easily.

[0082] Correspondingly, in this embodiment, determining the currently available cores based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information (S105) may include:

[0083] S105a. Perform logical operations on the updated preset second binary number, the updated preset sixth binary number, and the preset eighth binary number to obtain the ninth binary number.

[0084] In this embodiment, the value of each bit in the ninth binary number indicates whether the core is currently available.

[0085] In some examples, performing logical operations on the updated preset second binary number, the updated preset sixth binary number, and the preset eighth binary number to obtain the ninth binary number (S105a) may include:

[0086] D1. Perform a logical OR operation on the updated preset second binary number and the updated preset sixth binary number to obtain the tenth binary number.

[0087] D2. Perform a logical XOR operation between the 12th binary number and the preset 8th binary number to obtain the 11th binary number.

[0088] D3. Perform a logical AND operation between the preset eighth binary number and the updated preset sixth binary number to obtain the twelfth binary number.

[0089] D4. Perform a logical OR operation on the eleventh and twelfth binary numbers to obtain the ninth binary number.

[0090] S105b: Determine the currently available cores based on the values ​​of each bit in the ninth binary number.

[0091] In some examples, after receiving fault information from the currently faulty core (S101) and before the currently available cores execute tasks (S106), the method may further include:

[0092] S107. End the tasks being executed by each core.

[0093] Before the currently faulty core issues a fault message, each core is executing a task. After the currently faulty core issues a fault message, in this embodiment, the tasks being executed by each core are killed.

[0094] In this embodiment, after determining the currently available cores and before the currently available cores execute tasks, the method may further include:

[0095] S108, Configure currently available cores.

[0096] The firmware or driver can be used to configure the currently available cores so that they have the conditions to perform tasks.

[0097] In this embodiment, the currently available cores can execute multiple tasks (S106), which may include:

[0098] S106a, Receive and parse the task to be executed.

[0099] The task to be executed may include the code to be executed, parameters, and task size information.

[0100] In this embodiment, after receiving the task to be executed, the task format is parsed to obtain the code to be executed, parameters, and task size information.

[0101] S106b: Distribute the task to the currently available cores so that the target redundant core can replace the currently faulty core to execute the task.

[0102] After parsing, tasks are distributed to each currently available core, and each currently available core executes the task. Among the currently available cores is the target redundant core. In this case, the target redundant core can replace the currently faulty core to execute the task.

[0103] For ease of management and calculation, in some cases, multiple cores belong to more than two core groups, and each core group has the same number of cores.

[0104] In this embodiment, reading the preset first state information, preset second state information, and preset third state information of each core in the multi-core processor based on the fault information (S102) may include:

[0105] S102b. Based on the identifier of the current faulty core, determine the target core group to which the current faulty core belongs.

[0106] Multiple cores can be pre-grouped based on their identifiers. The group containing the currently faulty core is the target core group.

[0107] S102c: Read the preset first state information, preset second state information and preset third state information corresponding to each core in the target core group.

[0108] In this embodiment, determining fifth state information based on preset first state information and preset second state information, and updating the preset second state information using the fifth state information (S103) may include:

[0109] S103d. Based on the preset first state information and preset second state information corresponding to the target core group, determine the fifth state information corresponding to the target core group, and update the preset second state information corresponding to the target core group using the fifth state information corresponding to the target core group.

[0110] In this embodiment, determining the sixth state information based on the identifier of the current fault core and the preset third state information, and updating the preset third state information using the sixth state information (S104) may include:

[0111] S104d. Based on the identifier of the current faulty core and the preset third state information corresponding to the target core group, determine the sixth state information corresponding to the target core group, and update the preset third state information corresponding to the target core group using the sixth state information corresponding to the target core group.

[0112] In this embodiment, determining the currently available cores based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information (S105) may include:

[0113] S105c: Based on the preset second state information corresponding to the updated target core group, the preset third current state information corresponding to the updated target core group, and the preset fourth state information corresponding to the target core group, determine the currently available cores in the target core group.

[0114] In this embodiment, the currently available cores may include the target redundant cores.

[0115] In this embodiment, the target core group to which the current faulty core belongs can be determined based on the identifier of the current faulty core. Based on the preset first state information and preset second state information corresponding to the target core group, the preset second state information corresponding to the target core group is updated. Based on the identifier of the current faulty core and the preset third state information corresponding to the target core group, the preset third state information corresponding to the target core group is updated. Finally, the currently available cores in the target core group are determined. The currently available cores in the target core group and the available cores in other core groups are used as the cores for the next task execution.

[0116] Figure 2 This is a schematic diagram of the structure of a processing device for a faulty core in a multi-core processor according to an embodiment of this application, as shown below. Figure 2As shown, this embodiment describes a processing device for a faulty core in a multi-core processor. The multi-core processor includes multiple cores. The device includes: a receiving module 11, used to receive fault information sent by the currently faulty core among the multiple cores; the fault information includes the identifier of the currently faulty core; a reading module 12, used to read preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor according to the fault information; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since leaving the factory; the third state information indicates whether the core has failed during use since leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, wherein being used includes being to be used and being used; and a first updating module 13, used to update the data according to the preset first state information and the preset third state information. The second update module 14 is used to determine the fifth state information based on the identifier of the current faulty core and the preset third state information, and to update the preset third state information using the sixth state information, so that the state of the target redundant core in the currently available redundant cores changes from unused to to be used; the second update module 15 is used to determine the currently available cores based on the updated preset second state information, the updated preset third current state information and the preset fourth state information; the currently available cores include the target redundant core; wherein, the fourth state information indicates whether the core state was masked when the multi-core processor was manufactured; the execution module 16 is used to execute tasks through the currently available cores, so that the target redundant core replaces the currently faulty core in executing tasks.

[0117] The apparatus of this embodiment can be used to perform Figure 1 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0118] The apparatus in this embodiment reads preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor based on the received fault information. Then, based on the preset first and second state information, it determines fifth state information and updates the preset second state information using the fifth state information, changing the state of the target redundant core among the currently available redundant cores from unused to to be used. Based on the identifier of the currently faulty core and the preset third state information, it determines sixth state information and updates the preset third state information using the sixth state information, changing the state of the currently faulty core from not having a fault to having a fault. Finally, based on the updated preset second state information and the updated... The currently available cores are determined by the preset third and fourth current status information. In this embodiment, after receiving the fault information, the status information is updated according to the preset first, second, and third status information corresponding to each core in the multi-core processor. Then, the currently available cores are determined by the updated preset second, third, and fourth status information, and the currently available cores execute the task so that the target redundant core replaces the currently faulty core in executing the task. This can improve the task execution efficiency and avoid the problem of low task execution efficiency caused by the complexity of the algorithm due to the use of virtual topology-based methods in the prior art.

[0119] As an optional implementation, the first update module includes: a first determining submodule, configured to determine a seventh state information based on the preset first state information and the preset second state information; the seventh state indicates whether the redundant core will be used; and a second determining submodule, configured to determine the fifth state information based on the seventh state information and the preset second state information.

[0120] As an optional implementation, the preset first state information is a preset first binary number, and the preset second state information is a preset second binary number; the preset first binary number maps each core to different bits in the binary number, and configures the value of each bit in the binary number according to whether the state of each core is redundant when the multi-core processor leaves the factory; the preset second binary number maps each core to different bits in the binary number, and determines the value of each bit in the binary number according to whether the redundant core has been used since the core left the factory; the first determining submodule is specifically used to: perform logical operations on the preset first binary number and the preset second binary number to obtain a third binary number; shift the third binary number to the right sequentially until it encounters a number indicating that the state of the core is used, and record the number of bits shifted to the right n; shift the number indicating that the state of the core is used to the left by n bits to obtain a fourth binary number.

[0121] As an optional implementation, the second determining submodule is specifically used to: perform logical operations on the fourth binary number and the second binary number to obtain a fifth binary number; wherein, the first updating module is specifically used to: update the preset second binary number using the fifth binary number.

[0122] As an optional implementation, the preset third state information is a preset sixth binary number; the preset sixth binary number is obtained by mapping each core to different bits in the binary number, and determining the value of each bit in the binary number based on whether the core has malfunctioned during use from the time it was manufactured until now; the first update module is specifically used to: determine the m-th bit of the currently faulty core in the preset sixth binary number based on the identifier of the currently faulty core; shift the binary number representing the state of the core as faulty m bits to the left, and perform a logical operation between the result and the preset sixth binary number to obtain a seventh binary number; update the preset sixth binary number using the seventh binary number.

[0123] As an optional implementation, the preset fourth state information is a preset eighth binary number; the preset eighth binary number is to map each core to different bits in the binary number, and to determine the value of each bit in the binary number based on whether the core is masked when it leaves the factory.

[0124] The determining module is specifically used to: perform logical operations on the updated preset second binary number, the updated preset sixth binary number, and the preset eighth binary number to obtain a ninth binary number; the value of each bit in the ninth binary number indicates whether the core is currently available; and determine the currently available core based on the value of each bit in the ninth binary number.

[0125] As an optional implementation, the apparatus is further configured to: terminate the tasks being executed by each core after the receiving module receives the fault information sent by the currently faulty core and before the execution module executes the task through the currently available core; wherein, the apparatus further includes: configuring the currently available core after the determining module determines the currently available core and before the execution module executes the task through the currently available core; wherein, the execution module is specifically configured to: receive and parse the task to be executed; distribute the task to the currently available core so that the target redundant core replaces the currently faulty core in executing the task.

[0126] As an optional implementation, the multiple cores belong to two or more core groups, with each core group having the same number of cores; wherein, the reading module is specifically used to: determine the target core group to which the currently faulty core belongs based on the identifier of the currently faulty core; and read preset first state information, preset second state information, and preset third state information corresponding to each core in the target core group; wherein, the first updating module is specifically used to: update the preset second state information corresponding to the target core group based on the preset first state information and preset second state information corresponding to the target core group; wherein, the second updating module is specifically used to: update the preset third state information corresponding to the target core group based on the identifier of the currently faulty core and the preset third state information corresponding to the target core group; wherein, the determining module is specifically used to: determine the currently available cores in the target core group based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information corresponding to the target core group; the currently available cores include the target redundant cores.

[0127] The apparatus described in the above embodiments can be used to execute the technical solutions of the above method embodiments. The implementation principle and technical effects are similar, and will not be repeated here.

[0128] refer to Figure 3 , Figure 4 and Figure 5This application also provides a multi-core processor, including: multiple cores 1 and a fault repair module 2; wherein, the fault repair module 2 includes a fault detection submodule 20, a computing submodule 21 and a first memory 22.

[0129] In this embodiment, the fault detection submodule 20 is connected to multiple cores 1 and computing submodule 21 respectively, and the computing submodule 21 is connected to the first memory 22.

[0130] In this embodiment, core 1 can be a computing core.

[0131] In this embodiment, the fault detection submodule 20 is used to receive fault information sent by the currently faulty core among multiple cores, and the calculation submodule 21 is used to read the preset first state information, preset second state information and preset third state information corresponding to each core in the multi-core processor from the first memory 22 according to the fault information.

[0132] In some embodiments, the first memory 22 may include three independent storage units: a non-volatile storage device fuse 22a, a faulty core mask memory 22b, and a used redundant core mask memory 22c. Fuse 22a stores first state information, faulty core mask memory 22b stores second state information, and the used redundant core mask memory 22c stores third state information. The faulty core mask memory 22b and the used redundant core mask memory 22c do not lose data in the event of a power outage, and the data in these storage units can be modified.

[0133] The first status information indicates whether the core is redundant when the multi-core processor leaves the factory; the second status information indicates whether the redundant core has been used since the factory left the factory; the third status information indicates whether the core has failed during use since the multi-core processor left the factory; whether the redundant core is used in the second status information includes whether the redundant core is not used and whether it is used, and whether it is used includes whether it will be used and whether it has been used.

[0134] In this embodiment, the calculation submodule 21 is further configured to determine a fifth state information based on a preset first state information and a preset second state information, and use the fifth state information to update the preset second state information so that the state of the target redundant core in the currently available redundant cores changes from unused to to be used; and determine a sixth state information based on the identifier of the current faulty core and the third state information, and use the sixth state information to update the third state information so that the state of the current faulty core changes from not having a fault to having a fault.

[0135] After updating the second and third state information, the available core determination module can obtain the first state information, the updated preset second state information, the updated preset third current state information, and the preset fourth state information from the first memory, and determine the currently available core based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information in the first memory, so that the currently available core can execute tasks.

[0136] The currently available cores in this embodiment include target redundant cores; the second memory is used to store preset fourth state information; wherein, the fourth state information indicates whether the core state is masked when the multi-core processor leaves the factory.

[0137] The second memory can also be a non-volatile memory device called fuse.

[0138] In some examples, the multi-core processor may include an available core determination module. Further, the available core determination module may include a microcontroller that is communicatively connected to a first memory and a second memory.

[0139] In other examples, the available core determination module is located outside the multi-core processor of this embodiment. In this way, the available core determination module can be connected to the multi-core processor through an interface and can obtain the status information stored in the first memory and the second memory of the multi-core processor.

[0140] Once the available core determination module identifies the currently available cores, the currently available cores can execute tasks. Since the currently available cores include the target redundant cores, the target redundant cores can replace the currently faulty cores in executing tasks.

[0141] After the fault detection submodule 20 receives the fault information sent by the currently faulty core among multiple cores, and before the currently available cores execute tasks, in this embodiment, the fault repair module 2 is specifically used to terminate the tasks being executed by each core. After the tasks being executed by each core are completed, the tasks can be re-executed using the currently available cores after the currently available cores are determined.

[0142] In the case where the multi-core processor includes an available core determination module, and the available core determination module includes a microcontroller, the microcontroller is connected to multiple cores; the microcontroller is specifically used to: configure the currently available cores after determining the currently available cores and before the currently available cores execute tasks.

[0143] After configuring the currently available cores, the conditions for executing tasks are met, providing a foundation for task execution.

[0144] After determining and configuring the currently available cores, the task can be re-executed. In this embodiment, the multi-core processor further includes: a task parsing module 3, used to receive and parse the task to be executed; and a task distribution module 4, which is connected to the task parsing module 3 and the multiple cores respectively, used to distribute the task to be executed to the currently available cores so that the target redundant core can replace the currently faulty core to execute the task.

[0145] Upon receiving a task, the task parsing module 3 parses the task and distributes the parsed task to the currently available cores through the task distribution module 4.

[0146] In this embodiment, after receiving fault information, the status information is updated according to the preset first status information, preset second status information, and preset third status information corresponding to each core in the multi-core processor. Then, the currently available core is determined using the updated preset second status information, updated preset third current status information, and preset fourth status information, and the currently available core executes the task so that the target redundant core replaces the currently faulty core in executing the task. This can improve task execution efficiency and avoid the problem of low task execution efficiency caused by the complexity of the algorithm due to the use of virtual topology-based methods in the prior art.

[0147] As an optional implementation, the computing submodule 21 includes: a first determining unit, configured to determine fifth state information based on preset first state information and preset second state information read from the first memory 22; the state of the fifth state information indicates whether the core is a target redundancy; a second determining unit, configured to determine sixth state information based on the fifth state information and the preset second state information; the sixth state information indicates whether the redundant core has been used since the factory was manufactured; and a first updating unit, configured to update the preset second state information using the sixth state information.

[0148] As an optional implementation, the preset first state information is a preset first binary number, and the preset second state information is a preset second binary number; the preset first binary number maps each core to different bits in the binary number, and configures the value of each bit in the binary number according to whether the state of each core is redundant when the multi-core processor leaves the factory; the preset second binary number maps each core to different bits in the binary number, and determines the value of each bit in the binary number according to whether the redundant core has been used since the core left the factory; the first determining unit is specifically used for: performing logical operations on the preset first binary number and the preset second binary number to obtain a third binary number; shifting the third binary number to the right sequentially until encountering a number indicating that the state of the core is redundant, and recording the number of bits shifted to the right n; shifting the number indicating that the state of the core is redundant to the left by n bits to obtain a fourth binary number.

[0149] As an optional implementation, the second determining unit is further configured to: a first logical operation subunit, configured to perform logical operations on the fourth binary number and the second binary number to obtain a fifth binary number; wherein, the first updating unit includes: an updating subunit, configured to update the preset second binary number using the fifth binary number.

[0150] As an optional implementation, the preset third state information is a preset sixth binary number; the preset sixth binary number is obtained by mapping each core to different bits in the binary number, and determining the value of each bit in the binary number based on whether the core has malfunctioned during use from the time it was manufactured until now; the calculation submodule 21 further includes: a third determining unit, used to determine the m-th bit of the currently faulty core in the preset sixth binary number based on the identifier of the currently faulty core; a logic operation unit, used to shift the binary number representing the state of a core as faulty m bits to the left, and perform a logic operation with the result and the preset sixth binary number to obtain a seventh binary number; and a second updating unit, used to update the preset sixth binary number using the seventh binary number.

[0151] As an optional implementation, the preset fourth state information is a preset eighth binary number; the preset eighth binary number is obtained by mapping each core to different bits in the binary number, and determining the value of each bit in the binary number based on whether the core was disabled at the time of manufacture; the microcontroller is specifically used to: perform logical operations on the updated preset second binary number, the updated preset sixth binary number, and the preset eighth binary number to obtain a ninth binary number; the value of each bit in the ninth binary number indicates whether the core is currently available; and determine the currently available core based on the value of each bit in the ninth binary number.

[0152] As an optional implementation, the multiple cores belong to two or more core groups, with each core group having the same number of cores; wherein, the calculation submodule 21 is specifically used for: determining the target core group to which the currently faulty core belongs based on the identifier of the currently faulty core; reading preset first state information, preset second state information, and preset third state information corresponding to each core in the target core group from the first memory 22; updating the preset second state information corresponding to the target core group based on the preset first state information and preset second state information corresponding to the target core group; and updating the preset third state information corresponding to the target core group based on the identifier of the currently faulty core and the preset third state information corresponding to the target core group, so that the state of the currently faulty core changes from no fault to faulty; wherein, the microcontroller is specifically used for: determining the currently available cores in the target core group based on the updated preset second state information corresponding to the target core group in the first memory 22, the updated preset third current state information corresponding to the target core group in the first memory 22, and the preset fourth state information corresponding to the target core group in the second memory.

[0153] The multi-core processors described in the above embodiments can be used to execute the technical solutions of the above method embodiments. Their implementation principles and technical effects are similar, and will not be repeated here.

[0154] The following detailed description of the solution in this application is based on a specific embodiment.

[0155] See Figure 3 and Figure 5 The task processing method in the multi-core processor of this embodiment may include:

[0156] 1. Start the task.

[0157] 2. Perform the task.

[0158] 3. Determine if there is a core RAS report.

[0159] 4. If present, the fault repair module 2 obtains the RAS information and ID of the fault core and terminates the task; otherwise, the task continues to be executed.

[0160] 5. Replace the faulty core with the target redundant core.

[0161] 6. Report the interruption to the firmware or driver and reconfigure the available computing cores.

[0162] 7. Report the application to re-execute the task.

[0163] The task processing method in the multi-core processor of this embodiment may include:

[0164] In this embodiment, the multi-core processor includes multiple cores, which are divided into 4 groups, each numbered Group0 to Group3. Each group has 16 cores, numbered Core0 to Core15. It is assumed that Core0 and Core3 in each group are disabled. Specifically, Core0 and Core3 in Group3 are faulty, while Core0 and Core3 in the other groups are redundant cores used to replace faulty cores in case of failure.

[0165] When the processor leaves the factory, it is configured with binary numbers to represent the core and its corresponding status information, including:

[0166] (1) indicates whether the core state is masked at the factory, denoted as chip_mask, and stored in the processor's non-volatile memory device fuse. Bit 0 indicates normal operation, and bit 1 indicates masking.

[0167] In this embodiment, chip_mask are as follows:

[0168] Group0: 0x0009 Group1: 0x0009 Group2: 0x0009 Group3: 0x0009

[0169] (2) indicates whether the core has failed during use. It is denoted as error_mask and stored in the fault core mask memory storage 22b. Bit 1 indicates a faulty core and 0 indicates a non-faulty core.

[0170] Since all cores are unused at the time of manufacture, in this embodiment, the error_masks are as follows:

[0171] Group0: 0x0000 Group1: 0x0000 Group2: 0x0000 Group3: 0x0000

[0172] (3) The binary number representing whether the core status of the multi-core processor is redundant when it leaves the factory is denoted as extra_mask and stored in fuse22a of the fault repair module. Here, bit 1 indicates a redundant available core and bit 0 indicates a non-redundant available core.

[0173] In this embodiment, extra_mask are as follows:

[0174] Group0: 0x0009 Group1: 0x0009 Group2: 0x0009 Group3: 0x0000

[0175] (4) The binary number representing whether the redundant core has been used since the factory was manufactured is denoted as used_mask and stored in the used redundant core mask memory 22c. Here, bit 1 indicates that the redundant core has been used and bit 0 indicates that the redundant core or non-redundant core has not been used.

[0176] Since the redundant cores are not used at the factory, the used_masks are as follows:

[0177] Group0: 0x0000 Group1: 0x0000 Group2: 0x0000 Group3: 0x0000 The method in this embodiment may include:

[0178] 1. Calculate the core of the task about to run.

[0179] See Figure 3 , Figure 4 and Figure 5 After the system starts, the firmware or driver is loaded. The firmware or driver obtains chip_mask, error_mask and used_mask from the second memory, the fault core mask memory 22b of the fault repair module and the redundant core mask memory 22c that has been used, and calculates the core of the task to be run by the following formula (1).

[0180] (chip_mask^(error_mask|used_mask))|(chip_mask&error_mask)(1)

[0181] Using the above formula, we obtain the values ​​shown in Table 1 below (bit 1 indicates that it is masked):

[0182] Group0: 0x0009 Group1: 0x0009 Group2: 0x0009 Group3: 0x0009

[0183] Table 1

[0184]

[0185] Table 1 is a calculation table of the calculation results obtained in each group based on the values ​​in the three corresponding memories and formula (1).

[0186] 2. Perform the task

[0187] Configure the core of the task that will be run soon.

[0188] The task includes the code to be executed, parameters, and task size information. This information is sent to the task parsing module 4 in a certain format. The task parsing module 4 parses the task format and obtains the code, parameters, and size information to be executed.

[0189] The task distribution module 5 distributes tasks to the cores that are about to run, based on the cores and the amount of tasks, so that the cores that receive the tasks can execute them.

[0190] Understandably, for a graphics processing unit (GPU), the calculation of the cores for the task to be run and the configuration of those cores can be performed by the central processing unit (CPU). For the CPU, the calculation of the cores for the task to be run and the configuration of those cores can be performed by the microcontroller within the CPU.

[0191] 3. Calculate the currently available cores

[0192] During task execution, if Core15 in Group 1 reports a faulty core, the fault detection submodule 20 of the fault repair module 2 obtains the ID of the faulty core. In the Group, the ID of Core15 is numbered m (m equals 15). Core number 15 is located in Group 1. Then:

[0193] (1) The calculation submodule 21 of the fault repair module 2 obtains the extra_mask of Group1, which is configured as 0x0009 at the factory.

[0194] (2) Obtain the used_mask of Group1. The factory configuration is 0x0000. Use extra_mask to XOR used_mask to get 0x0009, which indicates that the currently redundant and available cores are available.

[0195] (3) The currently available redundant core value 0x0009 is shifted right and the number of shifted bits n is recorded until 1 is encountered. Then 1 is shifted left by n bits or up to used_mask to obtain a new used_mask and update the value in the redundant core mask memory 22c that has been used, which is 0x1 here.

[0196] (4) Shift 1 left by m bits, then OR the resulting value with error_mask to get a new error_mask and update the value in fault core mask memory 22b, which is 0x8000 here, that is, core number 15 is the fault core.

[0197] (5) The interrupt is reported to the firmware or driver. The firmware or driver calculates the currently available cores based on the values ​​in the second memory fuse, the fault core mask memory 22b of the fault repair module 2, and the used redundant core mask memory 22c, so that the task can be re-executed. After calculating the currently available cores, the application is notified to re-execute the task.

[0198] In this embodiment, after receiving the RAS report from Core15 of Group1, the fault repair module 2 terminates the task on Core15.

[0199] Table 2

[0200]

[0201] Table 2 shows the new used_mask and new error_mask obtained through steps (1)-(4) in each group, as well as the currently available cores obtained by formula (1) based on chip_mask, new used_mask and new error_mask.

[0202] 4. Based on step 3, during the execution of the core task, if Core7 in Group 1 reports to RAS, the fault detection submodule 20 of the fault repair module 2 obtains the ID of the problematic core. In the Group, the ID of Core15 is numbered m (m equals 7, i.e., number m is the core ID). Core number 7 is in Group 1, then:

[0203] (1) Obtain the extra_mask of Group1, which is set to 0x0009 by default;

[0204] (2) Get the used_mask of Group1, which is currently 0x0001. Use extra_mask to XOR used_mask to get 0x0008, which indicates that the core is currently redundant and available.

[0205] (3) The currently available redundant core value 0x0008 is right-shifted and the number of shifted bits n is recorded until 1 is encountered. Then 1 is left-shifted n bits or used_mask to obtain a new used_mask and it is saved. Here it is 0x9.

[0206] (4) 1. Shift left by m bits, then OR the value with error_mask to get a new error_mask and save it. Here it is 0x8080, that is, the cores numbered 7 and 15 are the fault cores.

[0207] (5) The interrupt is reported to the firmware or driver. The firmware or driver recalculates the currently available cores based on the values ​​in the second memory fuse, the faulty core mask memory 22b, and the used redundant core mask memory 22c, configures the recalculated currently available cores, and informs the application to re-execute the task.

[0208] Table 3

[0209]

[0210] Table 3 shows the new used_mask and new error_mask obtained in each group through steps (1)-(4) based on the state in Table 2, and the currently available cores obtained by formula (1) based on chip_mask, new used_mask and new error_mask.

[0211] If no redundant cores are available within the group during the above process, a report is sent to the system, indicating a hardware malfunction.

[0212] In this embodiment, the task parsing module 4, the task distribution module 5, and the fault repair module 2 can be implemented in hardware.

[0213] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0214] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0215] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0216] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0217] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0218] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A task processing method in a multi-core processor, characterized by, The multi-core processor includes multiple cores; the method includes: Receive fault information sent by the currently faulty core among the plurality of cores; the fault information includes the identifier of the currently faulty core; Based on the fault information, preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor are read; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since leaving the factory; the third state information indicates whether the core has failed during use since leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, wherein being used includes being to be used and being used; Based on the preset first state information and the preset second state information, the fifth state information is determined, and the preset second state information is updated using the fifth state information, so that the state of the target redundant core in the currently available redundant cores changes from unused to to to be used; Based on the identifier of the current faulty core and the preset third state information, the sixth state information is determined, and the preset third state information is updated using the sixth state information, so that the state of the current faulty core changes from no fault to fault. Based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information, the currently available cores are determined; the currently available cores include the target redundant cores; wherein, the fourth state information indicates whether the cores were disabled when the multi-core processor left the factory. The currently available core performs the task so that the target redundant core replaces the currently faulty core in performing the task.

2. The method of claim 1, wherein, The step of determining the fifth state information based on the preset first state information and the preset second state information includes: Based on the preset first state information and the preset second state information, the seventh state information is determined; the seventh state indicates whether the redundant core will be used. The fifth state information is determined based on the seventh state information and the preset second state information.

3. The method of claim 2, wherein, The preset first state information is a preset first binary number, and the preset second state information is a preset second binary number; the preset first binary number maps each core to different bits in the binary number, and configures the value of each bit in the binary number according to whether the state of each core is redundant when the multi-core processor leaves the factory; the preset second binary number maps each core to different bits in the binary number, and determines the value of each bit in the binary number according to whether the redundant core has been used since the core left the factory. The step of determining the seventh state information based on the preset first state information and the preset second state information includes: Perform logical operations on the preset first binary number and the preset second binary number to obtain the third binary number; The third binary number is shifted to the right sequentially until a number representing the core state as being used is encountered, and the number of bits shifted to the right, n, is recorded. Shift the number representing the core state (the number being used) left by n bits to obtain the fourth binary number.

4. The method according to claim 3, characterized in that, Determining the fifth state information based on the seventh state information and the preset second state information includes: Perform logical operations on the fourth binary number and the second binary number to obtain the fifth binary number; The step of updating the preset second state information using the fifth state information includes: The preset second binary number is updated using the fifth binary number.

5. The method according to claim 4, characterized in that, The preset third state information is a preset sixth binary number; the preset sixth binary number is to map each core to different bits in the binary number, and to determine the value of each bit in the binary number based on whether the core has malfunctioned during use from the time it was manufactured until now. The step of determining sixth state information based on the identifier of the current fault core and the preset third state information, and updating the preset third state information using the sixth state information, includes: Based on the identifier of the current faulty core, it is determined that the current faulty core is located at the m-th bit in the preset sixth binary number; The binary number representing the core state as faulty is shifted left by m bits, and the result is logically operated with the preset sixth binary number to obtain the seventh binary number; The preset sixth binary number is updated using the seventh binary number.

6. The method according to claim 5, characterized in that, The preset fourth state information is a preset eighth binary number; the preset eighth binary number is to map each core to different bits in the binary number, and to determine the value of each bit in the binary number based on whether the core is masked when it leaves the factory. The step of determining the currently available cores based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information includes: The updated preset second binary number, the updated preset sixth binary number, and the preset eighth binary number are logically operated on to obtain the ninth binary number; the value of each bit in the ninth binary number indicates whether the core is currently available. The currently available cores are determined based on the values ​​of each bit in the ninth binary number.

7. The method according to claim 1, characterized in that, After receiving the fault information sent by the currently faulty core, and before the currently available cores execute tasks, the method further includes: End the tasks currently being performed by each core; The method further includes, after determining the currently available cores and before the currently available cores execute tasks: Configure the currently available cores; The currently available core execution tasks include: Receive and parse the task to be executed; The task is distributed to currently available cores so that the target redundant core replaces the currently faulty core in performing the task.

8. The method according to claim 1, characterized in that, The multiple cores belong to two or more core groups, and each core group has the same number of cores; The step of reading preset first state information, preset second state information, and preset third state information of each core in the multi-core processor based on the fault information includes: Based on the identifier of the currently faulty core, determine the target core group to which the currently faulty core belongs; Read the preset first state information, preset second state information and preset third state information corresponding to each core in the target core group; The step of determining fifth state information based on the preset first state information and the preset second state information, and updating the preset second state information using the fifth state information, includes: Based on the preset first state information and preset second state information corresponding to the target core group, determine the fifth state information corresponding to the target core group, and update the preset second state information corresponding to the target core group using the fifth state information corresponding to the target core group. The step of determining sixth state information based on the identifier of the current fault core and the preset third state information, and updating the preset third state information using the sixth state information, includes: Based on the identifier of the current faulty core and the preset third state information corresponding to the target core group, determine the sixth state information corresponding to the target core group, and update the preset third state information corresponding to the target core group using the sixth state information corresponding to the target core group. Specifically, the currently available cores are determined based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information, including: Based on the updated second state information corresponding to the target core group, the updated third current state information corresponding to the target core group, and the updated fourth state information corresponding to the target core group, the currently available cores in the target core group are determined.

9. A task processing device in a multi-core processor, characterized in that, The multi-core processor includes multiple cores; the device includes: A receiving module is used to receive fault information sent by the currently faulty core among the plurality of cores; the fault information includes the identifier of the currently faulty core; The reading module is used to read preset first state information, preset second state information, and preset third state information corresponding to each core in the multi-core processor according to the fault information; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since leaving the factory; the third state information indicates whether the core has failed during use since leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, wherein being used includes being to be used and being used; The first update module is used to determine the fifth state information based on the preset first state information and the preset second state information, and use the fifth state information to update the preset second state information so that the state of the target redundant core in the currently available redundant cores changes from unused to to to be used; The second update module is used to determine the sixth state information based on the identifier of the current fault core and the preset third state information, and use the sixth state information to update the preset third state information so that the state of the current fault core changes from no fault to fault. The determining module is used to determine the currently available cores based on the updated preset second state information, the updated preset third current state information, and the preset fourth state information; the currently available cores include the target redundant cores; wherein, the fourth state information indicates whether the cores were disabled when the multi-core processor was manufactured. An execution module is configured to perform tasks using the currently available cores, so that the target redundant core replaces the currently faulty core in performing the tasks.

10. The apparatus according to claim 9, characterized in that, The first update module is specifically used for: Based on the preset first state information and the preset second state information, the seventh state information is determined; the seventh state indicates whether the redundant core will be used. The fifth state information is determined based on the seventh state information and the preset second state information.

11. A multi-core processor, characterized in that, include: Multiple cores; Fault repair module; The fault repair module includes a fault detection submodule, a calculation submodule, and a first memory; wherein... The fault detection submodule is connected to the plurality of cores and is used to receive fault information sent by the currently faulty core among the plurality of cores; the fault information includes the identifier of the currently faulty core; The computing submodule is connected to the fault detection submodule and the first memory, respectively, and is used to read preset first state information, preset second state information and preset third state information corresponding to each core of the multi-core processor from the first memory according to the fault information; wherein, the first state information indicates whether the core state is redundant when the multi-core processor leaves the factory; the second state information indicates whether the redundant core has been used since the factory leaving the factory; the third state information indicates whether the core has failed during the use of the multi-core processor since the factory leaving the factory; whether the redundant core is used in the second state information includes whether the redundant core is not used and whether it is used, wherein being used includes being to be used and being used; The computing submodule is further configured to determine fifth state information based on the preset first state information and the preset second state information, and update the preset second state information using the fifth state information, so that the state of the target redundant core among the currently available redundant cores changes from unused to to to be used; and determine sixth state information based on the identifier of the currently faulty core and the third state information, and update the third state information using the sixth state information, so that the available core determination module obtains and determines the currently available core based on the updated preset second state information in the first memory, the updated preset third current state information, and the preset fourth state information in the second memory, so that the currently available core executes a task; the currently available core includes the target redundant core; the second memory is used to store the preset fourth state information; wherein, the fourth state information indicates whether the core state is disabled when the multi-core processor leaves the factory.

12. The multi-core processor according to claim 11, characterized in that, The computing submodule includes: The first determining unit is configured to determine fifth state information based on the preset first state information and the preset second state information read from the first memory; the state of the fifth state information indicates whether the core is a target redundancy. The second determining unit is used to determine the sixth state information based on the fifth state information and the preset second state information; the sixth state information indicates whether the redundant core has been used since the factory was manufactured. The first update unit is used to update the preset second state information using the sixth state information.

13. The multi-core processor according to claim 12, characterized in that, The preset first state information is a preset first binary number, and the preset second state information is a preset second binary number; the preset first binary number maps each core to different bits in the binary number, and configures the value of each bit in the binary number according to whether the state of each core is redundant when the multi-core processor leaves the factory; the preset second binary number maps each core to different bits in the binary number, and determines the value of each bit in the binary number according to whether the redundant core has been used since the core left the factory. The first determining unit is specifically used for: Perform logical operations on the preset first binary number and the preset second binary number to obtain the third binary number; The third binary number is shifted to the right sequentially until a number representing the core state is found to be redundant, and the number of bits shifted to the right, n, is recorded. Shift the redundant number representing the core state left by n bits to obtain the fourth binary number.

14. The multi-core processor according to claim 13, characterized in that, The second determining unit is further configured to: The first logical operation subunit is used to perform logical operations on the fourth binary number and the second binary number to obtain the fifth binary number; The first update unit includes: An update subunit is used to update the preset second binary number using the fifth binary number.

15. The multi-core processor according to claim 14, characterized in that, The preset third state information is a preset sixth binary number; the preset sixth binary number is to map each core to different bits in the binary number, and to determine the value of each bit in the binary number based on whether the core has malfunctioned during use from the time it was manufactured until now. The computing submodule further includes: The third determining unit is used to determine, based on the identifier of the current fault core, the m-th bit of the current fault core in a preset sixth binary number; The logic operation unit is used to shift the binary number representing a core state of fault to the left by m bits, and perform a logic operation with the preset sixth binary number to obtain the seventh binary number; The second update unit is used to update the preset sixth binary number using the seventh binary number.

16. The multi-core processor according to claim 15, characterized in that, The multi-core processor includes the available core determination module; the available core determination module includes a microcontroller; The microcontroller is communicatively connected to the first memory and the second memory, respectively.

17. The multi-core processor according to claim 16, characterized in that, The preset fourth state information is a preset eighth binary number; the preset eighth binary number is to map each core to different bits in the binary number, and to determine the value of each bit in the binary number based on whether the core is masked when it leaves the factory. The microcontroller is specifically used for: Perform logical operations on the updated preset second binary number, the updated preset sixth binary number, and the preset eighth binary number to obtain the ninth binary number; The value of each bit in the ninth binary number indicates whether the core is currently available. The currently available cores are determined based on the values ​​of each bit in the ninth binary number.

18. The multi-core processor according to claim 16, characterized in that, The fault repair module is also specifically used for: After the fault detection submodule receives the fault information sent by the currently faulty core among the multiple cores, and before the currently available cores execute their tasks, the tasks being executed by each core are terminated. The microcontroller is connected to the plurality of cores; the microcontroller is further configured to: After determining the currently available cores, configure the currently available cores before they execute tasks; Multi-core processors also include: The task parsing module is used to receive and parse tasks to be executed. The task distribution module is connected to the task parsing module and the plurality of cores respectively, and is used to distribute the task to be executed to the currently available cores, so that the target redundant core replaces the currently faulty core to execute the task.

19. The multi-core processor according to claim 16, characterized in that, The multiple cores belong to two or more core groups, and each core group has the same number of cores; Specifically, the calculation submodule is used for: Based on the identifier of the currently faulty core, determine the target core group to which the currently faulty core belongs; Read preset first state information, preset second state information, and preset third state information corresponding to each core in the target core group from the first memory; update the preset second state information corresponding to the target core group according to the preset first state information and preset second state information corresponding to the target core group; and update the preset third state information corresponding to the target core group according to the identifier of the current faulty core and the preset third state information corresponding to the target core group, so that the state of the current faulty core changes from no fault to faulty. Specifically, the microcontroller is used for: Based on the preset second state information corresponding to the target core group in the first memory, the preset third current state information corresponding to the target core group in the first memory, and the preset fourth state information corresponding to the target core group in the second memory, the currently available cores in the target core group are determined.

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