A pixel driving circuit, method, driving substrate and display panel

Abstract

The application relates to a pixel driving circuit, a method, a driving substrate and a display panel. The pixel driving circuit comprises a driving transistor, a reset compensation unit, a writing unit, a light-emitting control unit and a leakage isolation unit. The leakage isolation unit is arranged between a third transistor of the light-emitting control unit and a power supply. The leakage isolation unit is kept off when no light-emitting signal is received, so as to isolate the power supply from the driving transistor, and is turned on when the light-emitting signal is received. The pixel driving circuit provided by the application inhibits the leakage of the third transistor in the light-emitting control unit to the writing path, ensures the stability of the voltage written to the gate of the driving transistor in the writing stage, and makes the display of the picture more stable.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit, method, driving substrate and display panel. Background Technology

[0002] As consumers' demands increase, their requirements for the visual effects of screen displays are also rising. Traditional display panels have relatively simple pixel driving circuit designs, but these are insufficient to meet the demands for better visual effects. Therefore, the design of pixel driving circuits tends to be more complex. However, this increases the complexity of the circuits, making it easier to produce various visual defects while still meeting more visual effect requirements. These defects are often difficult to analyze and locate.

[0003] Therefore, optimizing the poor visual effects of pixel driving circuits is an urgent problem to be solved. Summary of the Invention

[0004] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide a pixel driving circuit, method, driving substrate and display panel, which aims to solve the problem of poor visual effect of pixel driving circuit.

[0005] A pixel driving circuit, comprising:

[0006] A driving transistor is disposed between a power supply and the anode of a light-emitting device, with a first end of the driving transistor close to the power supply and a second end of the driving transistor close to the anode of the light-emitting device.

[0007] A reset compensation unit is connected to the gate of the driving transistor. The reset compensation unit is configured to set the gate voltage of the driving transistor to an initial voltage when a reset signal is received, the initial voltage causing the driving transistor to turn on.

[0008] A write unit includes a first transistor and a second transistor. A first terminal of the first transistor receives a write voltage. A second terminal of the first transistor is connected to a first terminal of the driving transistor. A first terminal of the second transistor is connected to a second terminal of the driving transistor. A second terminal of the second transistor is connected to the gate of the driving transistor. The write unit is configured to configure the gate voltage of the driving transistor to the write voltage if a write signal is received when the gate voltage of the driving transistor is configured to the initial voltage.

[0009] The light-emitting control unit includes a third transistor disposed between the first terminal of the driving transistor and the power supply, and a fourth transistor disposed between the second terminal of the driving transistor and the anode of the light-emitting device; the light-emitting control unit is configured to turn on the power supply, the driving transistor and the light-emitting device when a light-emitting signal is received to drive the light-emitting device to work.

[0010] A leakage current isolation unit is disposed between the third transistor and the power supply. The leakage current isolation unit remains disconnected when it does not receive the light emission signal to isolate the power supply from the driving transistor, and turns on when it receives the light emission signal.

[0011] The aforementioned pixel driving circuit, by incorporating a leakage isolation unit, adds an extra layer of blocking between the power supply and the third transistor, thereby suppressing leakage from the third transistor into the write path. In some implementations, this ensures the stability of the voltage written to the gate of the driving transistor during the write phase, resulting in more stable image display. Furthermore, reducing leakage from the third transistor in some implementations also lowers overall power consumption to some extent.

[0012] Optionally, the leakage isolation unit includes a fifth transistor, the first terminal of which is connected to the power supply, the second terminal of which is connected to the first terminal of the third transistor, and the gate of the fifth transistor receives a light-emitting signal.

[0013] The fifth transistor isolates the fluctuations in the supply voltage to a certain extent, and in some implementation processes, it ensures the stability of the voltage at which the gate of the driving transistor is written during the writing phase.

[0014] Optionally, the leakage isolation unit further includes a sixth transistor, the first terminal of which is connected to a regulated voltage source, the second terminal of which is connected to the first terminal of the third transistor, the gate of which receives a write signal and is turned on when the write signal is received to stabilize the voltage at the first terminal of the third transistor using the regulated voltage source.

[0015] The sixth transistor is turned on during the write phase, allowing the voltage from the regulated voltage source to be applied to the first terminal of the third transistor. This regulated voltage source further stabilizes the voltage at the first terminal of the third transistor, preventing voltage fluctuations from affecting the write path. Therefore, in some implementations, while the fifth transistor isolates the third transistor from the power supply, the conduction of the sixth transistor applies a more stable voltage to the first terminal of the third transistor, bringing the voltage of the third transistor in the leakage circuit to a more stable state and ensuring greater stability when writing data to the gate of the sixth transistor.

[0016] Optionally, the transistors in the pixel driving circuit are all N-type transistors, and the voltage of the regulated voltage source is not less than a first voltage and less than 0V, wherein the first voltage is the lower limit of the write voltage increased by 0.5V.

[0017] The transistors in the pixel driving circuit are all P-type transistors. The voltage of the regulated voltage source is greater than 0V and not greater than the second voltage, which is the upper limit of the write voltage increased by 0.5V.

[0018] In some implementations, a voltage source that is closer to the write voltage can better ensure the stability of the write voltage.

[0019] Based on the same inventive concept, this application also provides a driving substrate, the driving substrate including a substrate body and a pixel driving circuit disposed on the substrate body, the pixel driving circuit including the pixel driving circuit described above.

[0020] The aforementioned driving substrate uses the aforementioned pixel driving circuit. In some embodiments, it provides more stable driving for the light-emitting devices, resulting in better driving performance and ensuring the final display visual effect.

[0021] Based on the same inventive concept, this application also provides a display panel, including a light-emitting device and the above-mentioned pixel driving circuit, wherein the light-emitting device is electrically connected to the second terminal of the driving transistor through the light-emitting control unit.

[0022] The aforementioned display panel uses the aforementioned pixel driving circuit, and in some embodiments, the display is more stable and the visual effect is better.

[0023] Based on the same inventive concept, this application also provides a pixel driving method applied to the above-mentioned display panel, the pixel driving method comprising:

[0024] During the reset phase, the reset signal is sent to the reset compensation unit so that the gate voltage of the driving transistor is configured to the initial voltage;

[0025] During the write phase, the write signal is sent to the write unit so that the gate voltage of the drive transistor is configured to the write voltage;

[0026] During the light-emitting phase, the light-emitting signal is sent to the light-emitting control unit and the leakage isolation unit to enable the light-emitting device to operate.

[0027] The reset phase, the write phase, and the light emission phase are executed sequentially.

[0028] The aforementioned pixel driving method drives the aforementioned display panel. During the writing phase, the power supply is isolated from the third transistor in the light-emitting control unit, reducing the possibility of leakage current from the third transistor to the writing path. In some implementations, this ensures the stability of data writing, making the gate data writing of the driving transistor more accurate and stable, so that the subsequent light-emitting phase can stably and accurately perform light-emitting display. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0030] Figure 2 A schematic diagram of the write path of a pixel driving circuit provided in an embodiment of this application;

[0031] Figure 3 This is a detailed structural schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0032] Figure 4 A schematic flowchart of a pixel driving method provided in another optional embodiment of this application;

[0033] Figure 5 A schematic diagram of the driving timing of a pixel driving method provided in another optional embodiment of this application;

[0034] Figure 6 A schematic diagram of a pixel driving circuit in the reset phase, provided in another optional embodiment of this application;

[0035] Figure 7 A schematic diagram of a pixel driving circuit during the writing stage, provided in another optional embodiment of this application;

[0036] Figure 8 A schematic diagram of a pixel driving circuit in the light-emitting stage, provided as another optional embodiment of this application;

[0037] Figure 9 A schematic diagram of another pixel driving circuit during the reset phase, provided as another optional embodiment of this application;

[0038] Figure 10 A schematic diagram of another pixel driving circuit during the writing stage, provided as another optional embodiment of this application;

[0039] Figure 11 A schematic diagram of another pixel driving circuit in the light-emitting stage, provided as another optional embodiment of this application;

[0040] Explanation of reference numerals in the attached figures:

[0041] 11-Reset compensation unit; 12-Write unit; 13-Light emission control unit; 14-Leakage isolation unit; T0-Drive transistor; T1-First transistor; T2-Second transistor; T3-Third transistor; T4-Fourth transistor; T5-Fifth transistor; T6-Sixth transistor; T7-Seventh transistor; T8-Eighth transistor; L-Light emission device; C-Parasitic capacitance; ELVDD-Power supply; Vref-Regulated voltage source; Vint-Negative potential source. Detailed Implementation

[0042] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0044] The design of pixel driving circuits in related technologies is prone to various visual defects.

[0045] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in subsequent embodiments.

[0046] Example:

[0047] This embodiment provides a pixel driving circuit, such as Figure 1 As shown, the pixel driving circuit includes a driving transistor T0, a reset compensation unit 11, a writing unit 12, a light emission control unit 13, and a leakage isolation unit 14.

[0048] In a pixel driving circuit, the driving transistor T0 is used to control the current magnitude, thereby controlling the brightness of the light-emitting device L. The driving transistor T0 is positioned between the power supply ELVDD and the anode of the light-emitting device L. It is understood that either the drain or source of the driving transistor T0 is electrically connected to the power supply ELVDD, and the other end of the drain or source is electrically connected to the anode of the light-emitting device L. In some applications, the connection positions of the drain and source can be interchanged to ensure normal function. It should be noted that, in this application, unless otherwise specified, the connections of transistors including, but not limited to, the driving transistor T0, are all based on the drain and source connecting the two ends of the circuit to be connected. The gate receives a corresponding control signal to control the conduction or disconnection between the drain and source. Furthermore, in this application, the first terminal of transistors including, but not limited to, the driving transistor T0, can be one of the source and drain terminals, while the second terminal can be the other. In some applications, the connection positions of the drain and source can be interchanged.

[0049] In this type of pixel driving circuit, the corresponding control phase can generally be divided into a reset phase, a write phase, and a light-emitting phase. The reset phase primarily ensures that the gate of the driving transistor T0 is pulled to a high potential, turning it on and preparing for the next phase, the write phase. For example, this ensures that when data is written to the driving transistor T0 during the write phase, the carriers within it are in a critical state, preventing the absorption of additional carriers and thus reducing the actual written voltage from being lower than the desired written voltage. The reset compensation unit 11 in this embodiment is used to perform the aforementioned compensation on the driving transistor T0. It is connected to the gate of the driving transistor T0 and configured to set the gate voltage of the driving transistor T0 to an initial voltage upon receiving a reset signal. In this embodiment, this initial voltage is the voltage that ensures the carriers in the driving transistor T0 are in a critical state, guaranteeing that no additional carriers are absorbed during data writing.

[0050] The write unit 12 includes a first transistor T1 and a second transistor T2. The first terminal of the first transistor T1 receives the write voltage, and the second terminal of the first transistor T1 is connected to the first terminal of the driving transistor T0. The first terminal of the second transistor T2 is connected to the second terminal of the driving transistor T0, and the second terminal of the second transistor T2 is connected to the gate of the driving transistor T0. The write unit 12 is configured to configure the gate voltage of the driving transistor T0 to the write voltage if a write signal is received when the gate voltage of the driving transistor T0 is configured to the initial voltage.

[0051] like Figure 2 , Figure 2The write path of the write unit 12 is illustrated by dashed lines. The first terminal of the first transistor T1 receives the write voltage Vdata. When the gate voltage of the driving transistor T0 is configured to the initial voltage, the driving transistor T0 is turned on. The write voltage Vdata is applied to the gate of the driving transistor T0 after passing through the first transistor T1, the driving transistor T0, and the second transistor T2. In practical applications, the specific value of the write voltage Vdata is determined based on the actual image to be displayed by the pixel. By writing different voltage data to the gate of the driving transistor T0, the conduction status of the driving transistor T0 during the light-emitting stage can be controlled, thereby controlling the light-emitting state of the light-emitting device L.

[0052] The light-emitting control unit 13 includes a third transistor T3 disposed between the first terminal of the driving transistor T0 and the power supply ELVDD, and a fourth transistor T4 disposed between the second terminal of the driving transistor T0 and the anode of the light-emitting device L. The light-emitting control unit 13 is configured to connect the power supply ELVDD, the driving transistor T0, and the light-emitting device L when a light-emitting signal is received, thereby driving the light-emitting device L to operate. Under normal conditions during the reset and write phases, when the light-emitting control unit 13 receives a light-emitting signal, the entire path of the power supply ELVDD, the driving transistor T0, and the light-emitting device L can be turned on, and the light-emitting device L starts to operate. At this time, the driving transistor T0 controls the current magnitude according to the voltage of its gate, so that the light-emitting device L presents the brightness required for the current pixel.

[0053] See also Figure 2 As can be seen, in the write path of the write unit 12 in this application, the second terminal of the first transistor T1 and the first terminal of the driving transistor T0 are connected to the third transistor T3, and the first terminal of the third transistor T3 is connected to the power supply ELVDD. The power supply ELVDD of the pixel driving circuit is usually a PMIC (Power Management IC). The output of the PMIC is affected by the input voltage and the load. The input voltage is different when the battery is fully charged and when it is low on power, so the output power supply voltage is not linear and stable, and there are small fluctuations within a certain range. In addition, when displaying particularly complex images, the power supply voltage of the power supply ELVDD is usually pulled away from the standard voltage. It is understandable that in practical applications, the transistors are not ideal devices. Therefore, the fluctuation or deviation of the power supply voltage of the power supply ELVDD will be applied to the write path of the write unit 12 to a certain extent through the third transistor T3. Therefore, when the writing unit 12 writes voltage data to the gate of the driving transistor T0, it will be affected, that is, the voltage written to the gate of the driving transistor T0 will be affected, resulting in a certain degree of visual defects, which usually manifests as uneven screen display.

[0054] To control the impact of leakage current in the third transistor T3, a leakage isolation unit 14 is disposed between the third transistor T3 and the power supply ELVDD. The leakage isolation unit 14 remains open when no light-emitting signal is received, isolating the power supply ELVDD from the driving transistor T0. When a light-emitting signal is received, the leakage isolation unit 14 is turned on, allowing the light-emitting device L to emit light normally. By setting the leakage isolation unit 14, an additional layer of blocking is added between the power supply ELVDD and the third transistor T3, thereby suppressing leakage current from the third transistor T3 into the write path. This ensures the stability of the voltage at which the gate of the driving transistor T0 is written during the write phase, resulting in a more stable display. Furthermore, reducing leakage current in the third transistor T3 also reduces overall power consumption to some extent.

[0055] like Figure 3 As shown, as a specific example, the pixel driving circuit of this embodiment can be designed as a 9T1C scheme, that is, it consists of nine transistors, including the driving transistor T0, and a capacitor. In some embodiments, the leakage isolation unit 14 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the power supply ELVDD, and the second terminal of the fifth transistor T5 is connected to the first terminal of the third transistor T3. The gate of the fifth transistor T5 receives the light emission signal. It can be understood that the fifth transistor T5 is also used to control the conduction and disconnection of the control path. Of course, in practical applications, the fifth transistor T5 is not an ideal device. However, in this embodiment, the voltage fluctuation received by the first terminal of the third transistor T3 is only the part that leaks through the fifth transistor T5. The power supply voltage fluctuation generated by the power supply ELVDD cannot be completely transmitted to the third transistor T3, and the voltage fluctuation is weakened by the third transistor T3 itself. Therefore, the voltage fluctuation generated by the second terminal of the third transistor T3 that can affect the write path is further weakened. It can be seen that the fifth transistor T5 isolates the power supply voltage fluctuation to a certain extent, ensuring the stability of the voltage at which the gate of the driving transistor T0 is written during the write stage.

[0056] It should be noted that in this embodiment, all transistors, including the driving transistor, are N-type transistors. In this embodiment, the N-type transistor is turned on when its gate is at a high potential. It should be understood that in practical applications, the pixel driving circuit of this embodiment can also use all P-type transistors, or even partially use N-type transistors and partially use P-type transistors. Those skilled in the art only need to make corresponding modifications based on the characteristics of N-type transistors and P-type transistors.

[0057] In some embodiments, the leakage isolation unit 14 further includes a sixth transistor T6. The first terminal of the sixth transistor T6 is connected to a regulated voltage source Vref, and the second terminal of the sixth transistor T6 is connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 receives a write signal and is turned on when the write signal is received to stabilize the voltage at the first terminal of the third transistor T3 using the regulated voltage source Vref. It should be noted that the regulated voltage source Vref connected to the sixth transistor T6 has good stability; its stability is at least better than the power supply ELVDD, and is generally more stable than the PMIC. In practical applications, the more stable the regulated voltage source Vref, the better. It can be a voltage output generated internally by the relevant drive control chip, and is less affected by external factors such as battery power and load.

[0058] During the write phase, the sixth transistor T6 is turned on, and the voltage output from the regulated voltage source Vref is applied to the first terminal of the third transistor T3. The regulated voltage source Vref further stabilizes the voltage at the first terminal of the third transistor T3, preventing voltage fluctuations from affecting the write path. While the fifth transistor T5 isolates the third transistor T3 from the power supply ELVDD, the conduction of the sixth transistor T6 applies a more stable voltage to the first terminal of the third transistor T3, pulling the voltage condition of the third transistor T3 in the leakage circuit to a more stable state, thus ensuring greater stability when writing data to the gate of the sixth transistor T6.

[0059] In the previous example, to further ensure the stability of the gate write voltage of the driving transistor T0, the voltage applied by the regulated voltage source Vref to the first terminal of the third transistor T3 is as close as possible to the write voltage. It is understood that the write voltage is a dynamically changing value, varying depending on the actual display screen. To ensure stability and reduce resource consumption, the regulated voltage source Vref is typically set to a fixed value. Furthermore, to achieve even better write voltage stability, when the transistors used in the pixel driving circuit are N-type transistors, the voltage of the regulated voltage source Vref can be configured to be no less than a first voltage and less than 0V, where the first voltage is the lower limit of the write voltage Vdata increased by 0.5V. When the transistors used in the pixel driving circuit are P-type transistors, the voltage of the regulated voltage source Vref can be configured to be greater than 0V and no greater than a second voltage, where the second voltage is the upper limit of the write voltage Vdata increased by 0.5V. In some examples, a voltage equal to the first voltage, the second voltage, or within 1V of the second voltage can provide better stability for the display. It's understandable that during pixel display, black and white display represent two extremes, and the write voltage Vdata for displaying black and white represent the upper and lower limits of the write voltage Vdata. If the transistor is an N-type transistor, the write voltage Vdata is a negative voltage, and the first voltage is Vdata plus +0.5V, meaning the absolute value of the first voltage is 0.5V less than the upper limit of the write voltage Vdata. If the transistor is a P-type transistor, the write voltage Vdata is a positive voltage, and the absolute value of the first voltage is 0.5V greater than the upper limit of the write voltage Vdata. As a more concrete example, assuming an N-type transistor, the write voltage Vdata for displaying black is -4.3V, and the write voltage for displaying white is -1.2V, then the lower limit of the write voltage Vdata is -4.3V. Therefore, the voltage of the regulated voltage source Vref can be configured from 0V to -3.8V (excluding 0V). For better performance, in practical applications, it can be selected between -2.8V and -3.8V (including the two endpoint values). As another specific example, assuming that the write voltage Vdata is 4.5V when displaying a black screen and 1.2V when displaying a white screen under a P-type transistor, the upper limit of the write voltage Vdata is 4.5V. Therefore, the voltage of the regulated voltage source Vref can be configured from 0V to 5V (excluding 0V). For better results, in practical applications, it can be selected between 4V and 5V (including the two terminal values).

[0060] The reset compensation unit 11 includes a parasitic capacitor C. The first terminal of the parasitic capacitor C is connected to the gate of the driving transistor T0. When the reset compensation unit 11 receives a reset signal, it configures the voltage at the first terminal of the parasitic capacitor C to the initial voltage. The reset compensation unit 11 also includes a seventh transistor T7 and an eighth transistor T8. The first terminal of the seventh transistor T7 is connected to the power supply ELVDD, and the second terminal of the seventh transistor T7 is connected to the gate of the driving transistor T0 and the first terminal of the parasitic capacitor C. The first terminal of the eighth transistor T8 is connected to the second terminal of the parasitic capacitor C and the anode of the light-emitting device L, and the second terminal of the eighth transistor T8 is connected to the negative potential source Vint. The gates of both the seventh transistor T7 and the eighth transistor T8 receive the reset signal Reset and are turned on when the reset signal Reset is received.

[0061] It should be noted that the connection relationships between each circuit unit and other parts in the pixel driving circuit of this embodiment are only used to indicate the connection logic of the circuit and its possible application methods. It does not limit the pixel driving circuit to include structures that can be externally connected or added in subsequent processes, such as power supplies and light-emitting devices. For example, the pixel driving circuit may include conductive lines for connecting to the power supply, or it may include areas for setting light-emitting devices (such as bonding pads or other structures or areas for bonding light-emitting devices). The corresponding structures on the pixel driving circuit have the aforementioned connection relationships with the bonding pads, conductive patterns, etc., used to set the light-emitting devices. Whether these externally connected or added structures are connected or added in subsequent processes does not affect the beneficial effects brought about by the structural improvements of the pixel driving circuit itself.

[0062] This embodiment also provides a driving substrate, which includes a substrate body and a pixel driving circuit disposed on the substrate body. The pixel driving circuit on the driving substrate may include the aforementioned pixel driving circuit. The substrate body may be any type of circuit substrate applicable to the display field, and may be a transparent substrate, such as a sapphire substrate or a glass substrate, or a non-transparent substrate.

[0063] This embodiment also provides a display panel, including a light-emitting device and the aforementioned pixel driving circuit, wherein the light-emitting device is electrically connected to the second terminal of the driving transistor through a light-emitting control unit.

[0064] Another optional embodiment of this application:

[0065] This embodiment provides a pixel driving method, which is applied to the display panel provided in the above embodiment. For example... Figure 4 As shown, the pixel driving method includes:

[0066] S101. During the reset phase, a reset signal is sent to the reset compensation unit so that the gate voltage of the driving transistor is configured to the initial voltage.

[0067] S102. During the writing phase, a write signal is sent to the write unit so that the gate voltage of the driving transistor is configured as the write voltage.

[0068] S103. During the light-emitting stage, a light-emitting signal is sent to the light-emitting control unit and the leakage isolation unit to make the light-emitting device work.

[0069] It should be noted that the reset stage, write stage and light emission stage are executed sequentially, meaning that the stages do not overlap, and the corresponding control signals of each stage are not output in an overlapping manner.

[0070] For example, see Figure 5 This document describes a control timing sequence for the pixel driving method of the display panel according to the present application. During the period t1-t2, the Reset signal is turned on and connected to the reset compensation unit, effectively sending the Reset signal. During the period t3-t4, the Gate signal is turned on and connected to the write unit and the leakage isolation unit, effectively sending the Gate signal. During the period t5-t6, the EM signal is turned on and connected to the light-emitting control unit, effectively sending the light-emitting signal EM to the light-emitting control unit. In this example, all signals are turned on at a high potential, which is equivalent to sending the signal at a high potential. In practical applications, depending on the type of transistor used and the specific circuit settings, the signals may also be configured to be turned on at a high potential.

[0071] This embodiment further elaborates on the pixel driving circuit and pixel driving method of the display panel based on the foregoing embodiments.

[0072] See Figure 6 During the reset phase, the reset signal Reset is activated, and the reset compensation unit 11 operates. The voltage at one end of the reset unit connected to the gate of the driving transistor T0 is configured as the initial voltage. This initial voltage is maintained and does not immediately disappear upon the end of the reset phase. This ensures that the charge carriers at the gate of the driving transistor T0 are in a critical state at the start of the next phase. For example, in some examples, this initial voltage is the input voltage of the power supply ELVDD, in which case the reset compensation unit 11 can be connected to the power supply ELVDD. During the reset phase, the transistors in the writing unit 12 and the light-emitting control unit 13 are both in the off state. Therefore, even if the voltage at the gate of the driving transistor T0 turns it on, the light-emitting device L will not emit light.

[0073] like Figure 7During the write phase, the write signal Gate is turned on, and the first transistor T1 and the second transistor T2 receive the write signal and turn on, connecting the write path formed by the first transistor T1, the driving transistor T0, and the second transistor T2. The write voltage Vdata is applied to the gate of the driving transistor T0 through this write path, completing the data writing. During the write phase, neither the light-emitting controller nor the reset compensation unit 11 operates, and no current flows through the light-emitting device L, so it does not emit light. In addition, during the write phase, the leakage isolation unit 14 isolates the power supply ELVDD from the third transistor T3 in the light-emitting control unit 13, reducing the possibility of leakage from the third transistor T3 to the write path.

[0074] During the light-emitting stage, the light-emitting signal EM is turned on, and the third transistor T3 and the fourth transistor T4 receive the light-emitting signal and are turned on. At the same time, the leakage isolation unit 14 also receives the light-emitting signal and no longer disconnects the power supply ELVDD from the third transistor T3. Figure 8 In the diagram, the current flow during the light-emitting stage is illustrated by a dashed line with an arrow. The current from the power supply ELVDD passes sequentially through the leakage isolation unit 14, the third transistor T3, the driving transistor T0, and the fourth transistor T4 before passing through the light-emitting device L. During this process, the light-emitting device L illuminates. Meanwhile, during the light-emitting stage, the writing unit 12 and the reset compensation unit 11 remain disconnected.

[0075] As can be seen, in this embodiment, the power supply ELVDD is separated from the third transistor T3 in the light-emitting control unit 13 during the writing stage, which reduces the possibility of leakage of the third transistor T3 to the writing path, ensures the stability of data writing, and makes the gate data writing of the driving transistor T0 more accurate and stable, so that the subsequent light-emitting stage can perform light-emitting display stably and accurately.

[0076] In some implementations, the leakage isolation unit 14 also includes a sixth transistor T6, to which a write signal is sent during the write phase to keep the first terminal voltage of the third transistor T3 stable.

[0077] For example, see Figure 9The pixel driving circuit includes a reset compensation unit 11 comprising a parasitic capacitor, a seventh transistor T7, and an eighth transistor T8. During the reset phase, the reset signal Reset is activated, and both the seventh transistor T7 and the eighth transistor T8 are in a conducting state. The first terminal of the parasitic capacitor is connected to the power supply ELVDD and the gate of the driving transistor T0. The input voltage of the power supply ELVDD is applied to the first terminal of the parasitic capacitor, charging it. This configures the voltage at the first terminal of the parasitic capacitor and the gate voltage of the driving transistor T0 to be the same as the input voltage of the power supply ELVDD. Furthermore, the second terminal of the parasitic capacitor is connected to the negative potential source Vint through the eighth transistor T8. Simultaneously, the anode of the light-emitting device L is also connected to the eighth transistor T8. This pulls the anode of the light-emitting device L to a negative potential during the reset phase, preventing the light-emitting device L from conducting due to the presence of the parasitic capacitor. During this phase, all other transistors are in a deactivated state.

[0078] See Figure 10 During the write phase, transistors T1, T2, and T6 are turned on, connecting the write path formed by T1, T0, and T2. The write voltage Vdata is applied to the gate of T0 via this write path, completing the data writing. The turn-on of T6 allows the output voltage of the regulated voltage source to be applied to the first terminal of T3. While T5 isolates T3 from the power supply ELVDD, the turn-on of T6 applies a more stable voltage to the first terminal of T3, bringing the voltage of T3 in the leakage circuit to a more stable state and ensuring greater stability during data writing to the gate of T6. During this phase, all other transistors are turned off.

[0079] See Figure 11 During the light-emitting stage, the third transistor T3 and the fourth transistor T4 receive the light-emitting signal and turn on. Simultaneously, the fifth transistor T5 in the leakage isolation unit 14 also receives the light-emitting signal and no longer disconnects the power supply ELVDD from the third transistor T3. It should be noted that the sixth transistor T6 in the leakage isolation unit 14 is in the off state to prevent the output voltage of the regulated voltage source from affecting the light emission. During this stage, all other transistors are also in the off state.

[0080] The pixel driving method of this embodiment can isolate the power supply from the writing path during the writing stage, reduce the voltage fluctuation of the power supply and the impact of leakage current of the third transistor connected to the writing path, and ensure the stability of the gate of the driving transistor when writing data, so as to make the display of the screen more stable.

[0081] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A pixel driving circuit, characterized in that, include: A driving transistor is disposed between a power supply and the anode of a light-emitting device, with a first end of the driving transistor close to the power supply and a second end of the driving transistor close to the anode of the light-emitting device. A reset compensation unit is connected to the gate of the driving transistor. The reset compensation unit is configured to set the gate voltage of the driving transistor to an initial voltage when a reset signal is received, the initial voltage causing the driving transistor to turn on. A write unit includes a first transistor and a second transistor. A first terminal of the first transistor receives a write voltage. A second terminal of the first transistor is connected to a first terminal of the driving transistor. A first terminal of the second transistor is connected to a second terminal of the driving transistor. A second terminal of the second transistor is connected to the gate of the driving transistor. The write unit is configured to configure the gate voltage of the driving transistor to the write voltage if a write signal is received when the gate voltage of the driving transistor is configured to the initial voltage. The light-emitting control unit includes a third transistor disposed between the first end of the driving transistor and the power supply, and a fourth transistor disposed between the second end of the driving transistor and the anode of the light-emitting device; The light-emitting control unit is configured to turn on the power supply, the driving transistor, and the light-emitting device when a light-emitting signal is received, so as to drive the light-emitting device to work. A leakage current isolation unit is disposed between the third transistor and the power supply. The leakage current isolation unit remains disconnected when it does not receive the light emission signal to isolate the power supply from the driving transistor, and turns on when it receives the light emission signal. The leakage isolation unit includes a fifth transistor, the first terminal of which is connected to the power supply, the second terminal of which is connected to the first terminal of the third transistor, and the gate of the fifth transistor receives a light-emitting signal. The leakage isolation unit further includes a sixth transistor, the first terminal of which is connected to a regulated voltage source, and the second terminal of which is connected to the first terminal of the third transistor. The gate of the sixth transistor receives a write signal and is turned on when the write signal is received to stabilize the voltage at the first terminal of the third transistor using the regulated voltage source.

2. The pixel driving circuit as described in claim 1, characterized in that, The transistors in the pixel driving circuit are all N-type transistors, and the voltage of the regulated voltage source is not less than a first voltage and less than 0V. The first voltage is the lower limit of the write voltage increased by 0.5V. Alternatively, the transistors in the pixel driving circuit are all P-type transistors, the voltage of the regulated voltage source is greater than 0V and not greater than the second voltage, the second voltage being the upper limit of the write voltage increased by 0.5V.

3. The pixel driving circuit as described in claim 1, characterized in that, The reset compensation unit includes a parasitic capacitor, the first end of which is connected to the gate of the driving transistor. When the reset compensation unit receives a reset signal, it configures the voltage at the first end of the parasitic capacitor to the initial voltage.

4. The pixel driving circuit as described in claim 3, characterized in that, The reset compensation unit also includes a seventh transistor and an eighth transistor; The first terminal of the seventh transistor is connected to the power supply, and the second terminal of the seventh transistor is connected to the gate of the driving transistor and the first terminal of the parasitic capacitance. The first terminal of the eighth transistor is connected to the second terminal of the parasitic capacitor and the anode of the light-emitting device, and the second terminal of the eighth transistor is connected to a negative potential source. The gates of both the seventh transistor and the eighth transistor receive the reset signal and are turned on when the reset signal is received.

5. A driving substrate, characterized in that, The driving substrate includes a substrate body and a pixel driving circuit disposed on the substrate body, wherein the pixel driving circuit includes the pixel driving circuit according to any one of claims 1-4.

6. A display panel, characterized in that, It includes a light-emitting device and a pixel driving circuit as described in any one of claims 1-4, wherein the light-emitting device is electrically connected to the second terminal of the driving transistor through the light-emitting control unit.

7. A pixel driving method, characterized in that, Applied to the display panel of claim 6, the pixel driving method includes: During the reset phase, the reset signal is sent to the reset compensation unit so that the gate voltage of the driving transistor is configured to the initial voltage; During the write phase, the write signal is sent to the write unit so that the gate voltage of the drive transistor is configured to the write voltage; During the light-emitting phase, the light-emitting signal is sent to the light-emitting control unit and the leakage isolation unit to enable the light-emitting device to operate. The reset phase, the write phase, and the light emission phase are executed sequentially.

8. The pixel driving method as described in claim 7, characterized in that, The display panel includes the pixel driving circuit of claim 3, and the pixel driving method further includes: During the write phase, a write signal is sent to the sixth transistor to keep the first terminal voltage of the third transistor stable.

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