Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a display area and a non-display area; the display area comprises a special-shaped edge and a first pixel circuit adjacent to the special-shaped edge, and the first pixel circuit comprises a first transistor; the non-display area comprises a second transistor, the second transistor is adjacent to the first transistor, and the second transistor is of the same type as the first transistor. According to the embodiment of the application, the consistency of the transistor characteristics of different pixel circuits is improved, and the display performance of the display product is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous advancement of display technology, users have increasingly higher performance requirements for display products.

[0003] Pixel circuits can be set in display products to drive light-emitting elements to emit light. Pixel circuits include transistors, and the characteristics of transistors affect the display performance of display products. Summary of the Invention

[0004] This application provides an array substrate, a display panel, and a display device, which helps to improve the consistency of transistor characteristics of different pixel circuits, thereby improving the display performance of the display product.

[0005] In a first aspect, embodiments of this application provide an array substrate, including: a display area and a non-display area; the display area includes an irregular edge and a first pixel circuit adjacent to the irregular edge, the first pixel circuit including a first transistor; the non-display area includes a second transistor, the second transistor being adjacent to the first transistor, and the second transistor being of the same type as the first transistor.

[0006] Based on the same inventive concept, in a second aspect, embodiments of this application provide a display panel including an array substrate as described in the first aspect embodiment.

[0007] Based on the same inventive concept, in a third aspect, embodiments of this application provide a display device, including a display panel as described in the second aspect embodiment.

[0008] According to the array substrate, display panel, and display device provided in the embodiments of this application, a second transistor is further provided in the non-display area. The second transistor is adjacent to the first transistor of the first pixel circuit, and the type of the second transistor is the same as that of the first transistor. In this way, the difference in the environment between at least some transistors of the first pixel circuit and transistors of the second pixel circuit can be reduced, thereby improving the consistency of characteristics between at least some transistors of the first pixel circuit and transistors of the second pixel circuit, which is beneficial to improving the display performance of the display product. Attached Figure Description

[0009] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0010] Figure 1This diagram shows a top view of an array substrate provided in one embodiment of the present application. Figure 2a Show Figure 1 An enlarged schematic diagram of the Q1 region; Figure 2b Show Figure 1 Another enlarged schematic diagram of the Q1 region; Figure 3a Show Figure 1 An enlarged schematic diagram of the Q2 region; Figure 3b Show Figure 1 Another enlarged schematic diagram of the Q2 region; Figure 4 This illustration shows a schematic diagram of a pixel circuit in an array substrate according to an embodiment of this application; Figure 5 This diagram shows a cross-sectional view of an array substrate provided in one embodiment of this application. Figure 6 This illustration shows a schematic diagram of a layout structure of a portion of an array substrate provided in one embodiment of this application; Figure 7 Show Figure 1 An enlarged schematic diagram of the Q3 region; Figure 8 This illustration shows another structural schematic diagram of the pixel circuit in an array substrate provided in one embodiment of this application; Figure 9 This diagram shows a top view of a display panel provided in one embodiment of the present application. Figure 10 This is a top view of a display device provided in one embodiment of the present application.

[0011] Explanation of reference numerals in the attached figures: 100. Array substrate; L1, irregular edge; L11, first irregular edge; L12, second irregular edge; L2, straight edge; 10. Pixel circuit; 11. First pixel circuit; 111. First transistor; 12. Second pixel circuit; 13. Third pixel circuit; 20. Second transistor; 30. Scan lines; 40. Virtual pixel circuit; 50. Light-emitting elements; 200. Display panel; 1000. Display device. Detailed Implementation

[0012] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0013] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0014] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0015] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0016] It should be noted that when a component is described as "connected" or "electrically connected" to another component, it can be directly connected to the other component, or there may be one or more intermediate components in between.

[0017] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0018] This application provides an array substrate, a display panel, and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the array substrate, the display panel, and the display device.

[0019] The array substrate provided in the embodiments of this application will be introduced first below.

[0020] Please refer to the reference. Figure 1 , Figure 2a , Figure 2b , Figure 3a as well as Figure 3b The array substrate 100 may include a display area AA and a non-display area NA.

[0021] When the array substrate 100 is used as a display panel, a light-emitting element may be provided corresponding to the display area AA of the array substrate 100, and no light-emitting element may be provided corresponding to the non-display area NA of the array substrate 100.

[0022] The display area AA may include an irregular edge L1, which may be a non-linear edge. The irregular edge L1 can be understood as at least a partial boundary between the display area AA and the non-display area NA, and the irregular edge L1 can also be considered as a partial edge of the non-display area NA.

[0023] For example, the display area AA may also include a straight edge L2.

[0024] The display area AA includes a plurality of pixel circuits 10 arranged in an array along a first direction X and a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X is the row direction and the second direction Y is the column direction.

[0025] When the array substrate is used to display products, the pixel circuit 10 within the display area AA can be connected to the light-emitting element, and the pixel circuit 10 can be used to drive the light-emitting element to emit light. The pixel circuit 10 can be referred to as a real pixel circuit. Pixel circuits not used to drive the light-emitting element can be referred to as virtual pixel circuits.

[0026] The first pixel circuit 11 is located adjacent to the irregular edge L1 within the display area AA. The first pixel circuit 11 includes a first transistor 111.

[0027] For example, the display area AA may further include a second pixel circuit 12, and a first pixel circuit 11 may be spaced between the second pixel circuit 12 and the irregular edge L1. That is, the first pixel circuit 11 is located between the second pixel circuit 12 and the irregular edge L1. The first pixel circuit 11 may be referred to as an edge pixel circuit, and the second pixel circuit 12 may be referred to as a non-edge pixel circuit.

[0028] The non-display area NA includes a second transistor 20, which is adjacent to the first transistor 111. It is understood that the second transistor 20 is located in the non-display area NA and near the irregular edge L1. The second transistor 20 is not used to drive the light-emitting element; the second transistor 20 can be referred to as a virtual transistor.

[0029] In addition, the second transistor 20 is of the same type as the first transistor 111.

[0030] For example, transistor types may include oxide transistors, polysilicon transistors, etc.

[0031] As an example, both the second transistor 20 and the first transistor 111 can be oxide transistors. For instance, the active layer material of both the second transistor 20 and the first transistor 111 can include indium gallium zinc oxide (IGZO).

[0032] As another example, both the second transistor 20 and the first transistor 111 may be polysilicon transistors. For example, the active layer material of both the second transistor 20 and the first transistor 111 may include low-temperature polysilicon (LTPS).

[0033] As explained in the background section, the characteristics of transistors affect the display performance of display products. Due to the difference in the location of the first pixel circuit 11 and the second pixel circuit 12, if the second transistor 20 is not provided, the environments of the transistors in the first pixel circuit 11 and the second pixel circuit 12 are significantly different. For example, the side of the first transistor 111 in the first pixel circuit 11 closest to the non-display area NA has no transistor, while the second pixel circuit 12 has the first transistor 111 between it and the non-display area NA. This difference in environment causes the transistors in the first pixel circuit 11 and the second pixel circuit 12 to have different states, resulting in different characteristics of the transistors in the first pixel circuit 11 and the second pixel circuit 12, thus affecting the display performance of the display product.

[0034] In this embodiment, a second transistor 20 is also provided in the non-display area NA. The second transistor 20 is adjacent to the first transistor 111 of the first pixel circuit 11, and the type of the second transistor 20 is the same as that of the first transistor 111. In this way, the difference in the environment between at least some transistors of the first pixel circuit 11 and the transistors of the second pixel circuit 12 can be reduced, thereby improving the consistency of characteristics between at least some transistors of the first pixel circuit 11 and the transistors of the second pixel circuit 12, which is beneficial to improving the display performance of the display product.

[0035] For example, the first pixel circuit 11 and the second pixel circuit 12 in the pixel circuit 10 have the same circuit structure, such as... Figure 4 As shown, both the first pixel circuit 11 and the second pixel circuit 12 can include multiple transistors. Some of the transistors in the first pixel circuit 11 are first transistors, and the other part of the transistors in the first pixel circuit 11 are transistors other than the first transistors. For example, some of the multiple transistors in the first pixel circuit 11 and the second pixel circuit 12 can be oxide transistors, and the other part can be polysilicon transistors.

[0036] The inventors discovered that, for example, hydrogen ions (H+) can easily cause a negative drift in the threshold voltage of oxide transistors. Therefore, oxide transistors are relatively sensitive to their environment; that is, different environments can easily cause differences in their characteristics. As described above, both the first transistor 111 and the second transistor 20 can be oxide transistors. This reduces the difference in the environments of the oxide transistors in the first pixel circuit 11 and the second pixel circuit 12, thereby improving the consistency of their characteristics.

[0037] Understandably, in this application, the second transistor 20 is only provided for the first oxide-type first transistor 111 in the first pixel circuit 11, and no other transistors are provided in the non-display area NA to correspond to the other transistors in the first pixel circuit 11. Compared with providing multiple transistors in the non-display area NA to correspond to each transistor in the first pixel circuit 11, the number of transistors that need to be provided in the non-display area NA is relatively small. In this way, the risk of insufficient space in the non-display area NA can be avoided. That is to say, the number of transistors provided in the non-display area NA is small, which is beneficial for narrow bezels.

[0038] To better understand the relatively small number of transistors in the non-display area NA, as shown in Figure 2 or Figure 3, dashed boxes P1 represent the area occupied by the first pixel circuit 11, P3 represents the area occupied by the second pixel circuit 12, and P4 represents the area occupied by the second transistor 20. Dashed boxes P1, P2, and P4 have the same shape, size, and area. Multiple transistors of the first pixel circuit 11 are located within dashed box P1, multiple transistors of the second pixel circuit 12 are located within dashed box P2, and the second transistor 20 is located within dashed box P4. The second transistor 20 corresponds only to the first transistor 111 of the first pixel circuit 11. Therefore, the number of transistors within dashed boxes P1 and P2 is greater than the number of transistors within dashed box P4.

[0039] In some embodiments, please refer to the reference Figure 1 As shown in Figure 2, the non-display area NA may include a first non-display area NA1, and the display area AA at least partially surrounds the first non-display area NA1. A second transistor 20 is provided in the first non-display area NA1 and near the display area AA.

[0040] And / or, the non-display area NA includes a second non-display area NA2, the second non-display area NA2 at least partially surrounds the display area AA, and a second transistor 20 is disposed in the second non-display area NA2 and near the display area AA.

[0041] For easy distinction, the irregular edge L1 of the display area AA may include a first irregular edge L11 and a second irregular edge L12. The first irregular edge L11 is adjacent to the first non-display area NA1, and the second irregular edge L12 is adjacent to the second non-display area NA2.

[0042] A second transistor 20 is disposed in the first non-display area NA1 and near the first irregular edge L11, or in the second non-display area NA2 and near the second irregular edge L12, or in both the first non-display area NA1 and near the first irregular edge L11 and the second non-display area NA2 and near the second irregular edge L12.

[0043] It is understandable that a first pixel circuit 11 is provided in the display area AA near the first irregular edge L11, and a first pixel circuit 11 is also provided in the display area AA near the second irregular edge L12.

[0044] The array substrate 100 may have an opening in the first non-display area NA1. In the display product, a camera or other photosensitive component, or other functional components, may be disposed at the position corresponding to the first non-display area NA1. The first non-display area NA1 can be referred to as the hole area of ​​the array substrate 100. Without a second transistor 20 disposed in the first non-display area NA1, bright spots are prone to appear around the first non-display area NA1. In this embodiment, a second transistor 20 is disposed in the first non-display area NA1 near the first irregular edge L11, which can reduce display abnormalities around the first non-display area NA1.

[0045] Figure 1 In the example shown, the first non-display area NA1 is circular. In other examples, the first non-display area NA1 may also be elliptical, racetrack-shaped, etc.

[0046] like Figure 1 As shown, the display area AA may include a rounded corner region, and the second irregular edge L12 is the edge of the rounded corner region. In this embodiment, a second transistor 20 is disposed in the second non-display area NA2 near the second irregular edge L12, which can reduce display abnormalities around the second non-display area NA2.

[0047] It should be noted that, Figure 2a , Figure 2b , Figure 3a as well as Figure 3b To clearly show the irregular edges, they are represented by thick solid lines.

[0048] In addition, such as Figure 2a or Figure 3a As shown, four second transistors 20 can be disposed within region P4, or, as... Figure 2b or Figure 3b As shown, two second transistors 20 can be installed in region P4.

[0049] In some embodiments, such as Figure 2a , Figure 2b , Figure 3a as well as Figure 3b As shown, the gate of the first transistor 111 and the gate of the second transistor 20 are connected to the same scan line 30. This reduces the number of scan lines required.

[0050] Scan line 30 can be used to transmit a scan signal to the transistor to control the state of the transistor. The scan signal can be high or low.

[0051] It should be noted that for N-type transistors, the on-level is high and the off-level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa; no distinction is made here. Additionally, the on-level and off-level in this embodiment are general terms; the on-level refers to any level that enables the transistor to conduct, and the off-level refers to any level that enables the transistor to turn off / become off.

[0052] When both the first transistor 111 and the second transistor 20 are oxide transistors, the first transistor 111 and the second transistor 20 can be N-type transistors.

[0053] For example, such as Figure 4 As shown, the first pixel circuit 11 and the second pixel circuit 12 may have the same structure. The pixel circuit may include a compensation transistor T4 and a reset transistor T5. The first pixel circuit 11 may also include a driving transistor T3, a first light-emitting control transistor T1, a second light-emitting control transistor T6, a data writing transistor T2, an initialization transistor T7, and a storage capacitor Cst1.

[0054] The first terminal of compensation transistor T4 is connected to the second terminal of driving transistor T3, the second terminal of compensation transistor T4 is connected to the gate of driving transistor T3, and the gate of compensation transistor T4 is connected to the first scan line SN1. The first terminal of reset transistor T5 is connected to the first reset signal line Vref1, the second terminal of reset transistor T5 is connected to the gate of driving transistor T3, and the gate of reset transistor T5 is connected to the second scan line SN2.

[0055] like Figure 2a , Figure 2b , Figure 3a as well as Figure 3b As shown, the second transistor 20 includes a first virtual transistor 21 and a second virtual transistor 22. The first virtual transistor 21 is adjacent to the compensation transistor T4, and the gates of the first virtual transistor 21 and the compensation transistor T4 are connected to the first scan line SN1. The second virtual transistor 22 is adjacent to the reset transistor T5, and the gates of the second virtual transistor 22 and the reset transistor T5 are connected to the second scan line SN2.

[0056] For example, compensation transistor T4 and reset transistor T5 are oxide transistors. The first virtual transistor 21 and the second virtual transistor 22 are also oxide transistors. Due to different environments, oxide transistors are more prone to exhibiting different characteristics. By providing a first virtual transistor 21 and a second virtual transistor 22 corresponding to compensation transistor T4 and reset transistor T5 respectively, the environmental differences between the oxide transistors in the first pixel circuit 11 and the second pixel circuit 12 can be reduced, thereby improving the consistency of characteristics between the oxide transistors in the first pixel circuit 11 and the second pixel circuit 12.

[0057] The active layers of the compensation transistor T4, the reset transistor T5, the first virtual transistor 21, and the second virtual transistor 22 are on the same film layer.

[0058] For example, such as Figure 5 As shown, the array substrate 100 may include a substrate 01 and multiple metal layers stacked on one side of the substrate 01. The multiple metal layers may include a first metal layer M1, a capacitor metal layer MC, a gate metal layer MG, a second metal layer M2, and a third metal layer M3. In the thickness direction of the array substrate 100, a first semiconductor layer b1 of the array substrate 100 is located between the first metal layer M1 and the substrate 01, and a second semiconductor layer b2 of the array substrate 100 is located between the capacitor metal layer MC and the gate metal layer MG. In addition, the array substrate 100 may also include a first gate insulating layer GI1, a capacitor insulating layer IMD, a first interlayer dielectric layer ILD1, a second gate insulating layer GI2, a third gate insulating layer GI3, a second interlayer dielectric layer ILD2, a first planarization layer PLN1, a second planarization layer PLN2, a pixel definition layer PDL, a support pillar PS, an anode layer RE, etc.

[0059] The active layers of the compensation transistor T4, the reset transistor T5, the first virtual transistor 21, and the second virtual transistor 22 can be located in the second semiconductor layer b2.

[0060] Both the capacitor metal layer MC and the gate metal layer MG can be provided with a first scan line SN1 and a second scan line SN2.

[0061] For example, the driving transistor T3, the first light-emitting control transistor T1, the second light-emitting control transistor T6, the data writing transistor T2, and the initialization transistor T7 are low-temperature polysilicon transistors. The active layer of the driving transistor T3, the first light-emitting control transistor T1, the second light-emitting control transistor T6, the data writing transistor T2, and the initialization transistor T7 may be located in the first semiconductor layer b1.

[0062] In some embodiments, the source and / or drain of the second transistor 20 are connected to a fixed-potential signal line. The fixed-potential signal line can be used to transmit a fixed signal. It should be noted that "fixed" can mean the signal remains essentially unchanged, but fluctuations due to factors such as coupling are not excluded. Transistors in a floating state are easily affected by other signals and become unstable. Therefore, when the source and / or drain of the second transistor 20 are connected to a fixed-potential signal line, the second transistor 20 can be in a floating state, which is more conducive to stabilizing the second transistor 20, and thus more conducive to ensuring the consistency of characteristics between at least some transistors in the first pixel circuit 11 and the transistors in the second pixel circuit 12.

[0063] For example, the source / drain of the first virtual transistor 21 and the source / drain of the second virtual transistor 22 can both be connected to a fixed potential signal line.

[0064] In some embodiments, the first pixel circuit 11 is connected to a reset signal line, and the fixed signal line includes the reset signal line. That is, the second transistor 20 and the first pixel circuit 11 are connected to the same reset signal line. This avoids the need to provide an additional signal line to connect the second transistor 20.

[0065] For example, such as Figure 4 As shown, the compensation transistor T4 of the first pixel circuit 11 is connected to the first reset signal line Vref1, and the initialization transistor T7 is connected to the second reset signal line Vref2. The second transistor 20 can be connected to either the first reset signal line Vref1 or the second reset signal line Vref2.

[0066] For example, the first terminal of the first virtual transistor 21 is connected to the first reset signal line Vref1, the second terminal of the first virtual transistor 21 is connected to the first terminal of the second virtual transistor 22, and the second terminal of the second virtual transistor 22 can also be connected to the first reset signal line Vref1.

[0067] In some embodiments, such as Figure 6 As shown, region P1, where the first pixel circuit 11 is located, includes multiple first vias h1. Region P4, where the second transistor 20 is located, includes multiple second vias h2.

[0068] During the fabrication of the array substrate, hydrogen ions H+ are generated. By setting the second via h2, it is beneficial to release hydrogen ions in region P4, which is more conducive to ensuring the stability of the second transistor 20, and thus ensuring the consistency of characteristics of at least some transistors of the first pixel circuit 11 and transistors of the second pixel circuit 12.

[0069] The number of first vias h1 in region P1 and the number of second vias h2 in region P4 can be the same. For each first via h1, one second via h2 can be set.

[0070] The first via h1 is used to connect different transistors in the first pixel circuit 11, or the first via h1 is used to connect the transistors in the first pixel circuit 11 with the signal lines.

[0071] The second via h2 is used to connect the second transistor 20 and the fixed potential signal line, or at least one second via h2 is in a floating state. Since the first pixel circuit 11 has a large number of transistors, and the second transistor 20 only corresponds to the first transistor 111 in the first pixel circuit 11, the first pixel circuit 11 requires a large number of first vias h1. In order to correspond to the first vias h1, the number of second vias h2 is also large. Therefore, when at least one second via h2 is in a floating state, it can avoid the second via h2 from having a connection relationship with structures that do not need to be connected.

[0072] The second via h2 can be called a virtual via.

[0073] In some embodiments, the distribution density of the first via h1 in region P1 where the first pixel circuit 11 is located is equal to the distribution density of the second via h2 in region P4 where the second transistor 20 is located. That is, the number of first via h1 and the number of second via h2 are the same in the same area. This further ensures that the environment in which the first pixel circuit 11 is located is the same as the environment in which the second pixel circuit 12 is located, thereby further improving the characteristic consistency of at least some transistors in the first pixel circuit 11 and transistors in the second pixel circuit 12, thus contributing to improved display performance of the display product.

[0074] In some embodiments, the distribution pattern of the first via h1 in region P1 where the first pixel circuit 11 is located is the same as the distribution pattern of the second via h2 in region P4 where the second transistor 20 is located.

[0075] For example, the plurality of first vias h1 in region P1 where the first pixel circuit 11 is located are mirror images of the plurality of second vias h2 in region P4 where the second transistor 20 is located.

[0076] In some embodiments, such as Figure 1 As shown, the display area AA may also include the straight edge L2. For example... Figure 7 As shown, the display area AA may also include a third pixel circuit 13 adjacent to the straight edge L2. The second pixel circuit 12 and the straight edge L2 may be spaced apart by the third pixel circuit 13; that is, the third pixel circuit 13 is located between the second pixel circuit 12 and the straight edge L2. The third pixel circuit 13 may be referred to as an edge pixel circuit.

[0077] The non-display area NA also includes a virtual pixel circuit 40, which is adjacent to the third pixel circuit 13. It is understood that the virtual pixel circuit 40 is located in the non-display area NA and near the straight edge L2. The virtual pixel circuit 40 is not used to drive the light-emitting element.

[0078] In addition, the number of transistors in the virtual pixel circuit 40 is the same as the number of transistors in the third pixel circuit 13.

[0079] The space around the non-display area of ​​the straight edge L2 is relatively ample compared to the space around the non-display area of ​​the irregular edge L1. A virtual pixel circuit 40 with a large number of transistors is set in the non-display area at the straight edge L2. In this way, the difference in environment between the transistors of the third pixel circuit 13 and the transistors of the second pixel circuit 12 can be reduced, thereby improving the consistency of characteristics between the transistors of the third pixel circuit 13 and the transistors of the second pixel circuit 12, which is more conducive to improving the display performance of the display product.

[0080] The circuit structure of the virtual pixel circuit 40 is the same as that of the third pixel circuit 13, except that the virtual pixel circuit 40 is not used to drive the light-emitting element.

[0081] The circuit structure of the third pixel circuit 13 can also be as follows: Figure 4 As shown.

[0082] In other examples, the circuit structures of the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 can be as follows: Figure 8 As shown, Figure 8 and Figure 4 The differences include: Figure 8 The structure shown also includes transistor T8. The first terminal of transistor T8 is connected to the bias adjustment signal line DVH, and the second terminal of transistor T8 is connected to the driving transistor T3. Transistor T8 can transmit the bias adjustment signal on the bias adjustment signal line DVH to the driving transistor T3 to adjust the bias state of the driving transistor T3.

[0083] in addition, Figure 4 and Figure 8 The middle data line (data) can be used to transmit data signals, the first power line (PVDD) can be used to transmit positive voltage signals, and the second power line (PVEE) can be used to transmit negative voltage signals.

[0084] When the array substrate 100 is used to display products, a light-emitting element 50 may be provided at a position corresponding to the display area AA.

[0085] Based on the same inventive concept, this application also provides a display panel. Figure 9 This diagram illustrates the structure of a display panel according to one embodiment of the present application. Figure 9As shown, the display panel 200 provided in this application embodiment may include the array substrate described in any of the above embodiments. Figure 9 The display panel shown can be an organic light-emitting diode (OLED) display panel.

[0086] Those skilled in the art should understand that in other implementations of this application, the display panel may also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0087] The display panel provided in this application embodiment has the beneficial effects of the array substrate provided in this application embodiment. For details, please refer to the specific description of the array substrate in the above embodiments. This embodiment will not repeat the description here.

[0088] Based on the same inventive concept, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 10 , Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 10 The provided display device 1000 includes the display panel 200 provided in any of the above embodiments of this application. Figure 10 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0089] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, include: Display area and non-display area; The display area includes an irregular edge and a first pixel circuit adjacent to the irregular edge, the first pixel circuit including a first transistor; The non-display area includes a second transistor, which is adjacent to the first transistor and is of the same type as the first transistor. The first transistor includes a compensation transistor and a reset transistor; The second transistor includes a first virtual transistor and a second virtual transistor; The first virtual transistor and the compensation transistor are adjacent to each other, and the gate of the first virtual transistor and the gate of the compensation transistor are connected to the first scan line; The second virtual transistor and the reset transistor are adjacent to each other, and the gate of the second virtual transistor and the gate of the reset transistor are connected to the second scan line; The source and / or drain of the first virtual transistor are connected to a fixed potential signal line, and / or the source and / or drain of the second virtual transistor are connected to a fixed potential signal line.

2. The array substrate according to claim 1, characterized in that, Both the first transistor and the second transistor are oxide transistors.

3. The array substrate according to claim 1, characterized in that, The source and / or drain of the second transistor are connected to a fixed potential signal line.

4. The array substrate according to claim 3, characterized in that, The first pixel circuit is connected to the reset signal line; the fixed potential signal line includes the reset signal line.

5. The array substrate according to claim 1, characterized in that, The area where the first pixel circuit is located includes multiple first vias; The region where the second transistor is located includes multiple second vias.

6. The array substrate according to claim 5, characterized in that, The distribution density of the first via in the area where the first pixel circuit is located is equal to the distribution density of the second via in the area where the second transistor is located.

7. The array substrate according to claim 5, characterized in that, The distribution pattern of the first via in the area where the first pixel circuit is located is the same as the distribution pattern of the second via in the area where the second transistor is located.

8. The array substrate according to claim 5, characterized in that, At least one of the second vias is in a suspended state.

9. The array substrate according to claim 1, characterized in that, The non-display area includes a first non-display area, the display area at least partially surrounds the first non-display area, and the second transistor is disposed in the first non-display area and near the display area; And / or, the non-display area includes a second non-display area, the second non-display area at least partially surrounding the display area, and the second transistor is disposed in the second non-display area and close to the display area.

10. The array substrate according to claim 1, characterized in that, The display area includes a straight edge and a third pixel circuit adjacent to the straight edge; The non-display area includes a virtual pixel circuit, which is adjacent to the third pixel circuit, and the number of transistors in the virtual pixel circuit is the same as the number of transistors in the third pixel circuit.

11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 10.

12. A display device, characterized in that, Includes the display panel according to claim 11.

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