Semiconductor structure and measurement method

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a measurement method. The semiconductor structure comprises a first wafer, a second wafer and at least one set of test structures, the test structures comprising two first test pads in the first wafer and two second test pads in the second wafer; wherein the first second test pad is offset relative to the first first test pad to a first offset direction, the second second test pad is offset relative to the second first test pad to a second offset direction, the first offset direction and the second offset direction are opposite directions parallel to a first direction, the area of the first first test pad opposite to the first second test pad is a first area, the area of the second first test pad opposite to the second second test pad is a second area, and the first area is equal to the second area. The embodiment of the present disclosure is at least beneficial to improve the alignment accuracy of wafer bonding.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a measurement method. Background Technology

[0002] Wafer bonding technology refers to the process of tightly bonding two polished homogeneous or heterogeneous wafers together through chemical and physical interactions. After wafer bonding, the atoms at the bonding interface react under the action of external forces to form covalent bonds and become one, so that the bonding interface reaches a specific bonding strength.

[0003] Wafer bonding requires controlling the accuracy of wafer alignment. Alignment marks are usually designed at the bonding interface of the two wafers. However, the process of aligning the two wafers using the current alignment marks cannot accurately determine the amount of displacement between the two wafers. This results in poor alignment accuracy between the two wafers, which in turn affects the performance of the bonded semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a measurement method, which at least helps to improve the alignment accuracy of wafer bonding.

[0005] This disclosure provides a semiconductor structure, including: a first wafer having a first bonding surface; a second wafer having a second bonding surface bonded to the first bonding surface; and at least one set of test structures, each test structure including: two first test pads spaced apart along a first direction within the first wafer, with the first bonding surface exposing the surface of the first test pads; and two second test pads spaced apart along the first direction within the second wafer, with the second bonding surface exposing the surface of the second test pads, each second test pad being bonded to a corresponding first test pad. The test pads are aligned; wherein, the first second test pad is offset in a first offset direction relative to the first first test pad, and the second second test pad is offset in a second offset direction relative to the second first test pad. The first offset direction and the second offset direction are opposite directions parallel to the first direction. The direction in which the second second test pad points to the first second test pad is the first offset direction. The area directly opposite the first first test pad and the first second test pad is the first area, and the area directly opposite the second first test pad and the second second test pad is the second area. The first area is equal to the second area.

[0006] In some embodiments, each of the first test pads exposed on the first bonding surface has the same shape.

[0007] In some embodiments, each of the second test pads exposed on the second bonding surface has the same shape.

[0008] In some embodiments, the shape of the first test pad exposed on the first bonding surface is a first square, and each first square has the same length in a first direction; the shape of the second test pad exposed on the second bonding surface is a second square, and each second square has the same length in a first direction.

[0009] In some embodiments, in a direction perpendicular to the first direction, the width of the first test pad exposed on the first bonding surface is smaller than the width of the second test pad exposed on the second bonding surface.

[0010] In some embodiments, the semiconductor structure further includes: a first power pad, with a first bonding surface exposing the first power pad; and a second power pad, with a second bonding surface exposing the second power pad, and the first power pad and the second power pad being directly opposite each other.

[0011] In some embodiments, along the first direction, the width of the first power pad exposed on the first bonding surface is the same as the width of the second power pad exposed on the second bonding surface.

[0012] In some embodiments, a first test pad is adjacent to a first power pad, a second test pad is adjacent to a second power pad, and a first test pad of a test structure is electrically connected to the adjacent first power pad, and a second test pad of a test structure is electrically connected to the adjacent second power pad.

[0013] In some embodiments, the first wafer has a first central region and a first edge region, and the second wafer has a second central region and a second edge region. The first central region and the second central region are directly opposite each other, and the first edge region and the second edge region are directly opposite each other. The first central region and the directly opposite second central region have corresponding test structures, and the first edge region and the directly opposite second edge region also have corresponding test structures.

[0014] In some embodiments, a first wafer includes a plurality of first chips, and a second wafer includes a plurality of second chips, each first chip being directly opposite a corresponding second chip; a portion of the first chips and the corresponding second chips have corresponding test structures.

[0015] In some embodiments, both the first chip and the second chip have a central chip region and a chip edge region, and the central chip region of the first chip and the central chip region of the second chip are directly opposite each other, and the chip edge region of the first chip and the chip edge region of the second chip are directly opposite each other, with the test structure located in the directly opposite central chip region and the directly opposite chip edge region.

[0016] In some embodiments, both the first chip and the second chip have a central chip region, the central chip region of the first chip and the central chip region of the opposite second chip are directly opposite each other, the first wafer also includes a first dicing channel located at the edge of the first chip, the second wafer also includes a second dicing channel located at the edge of the second chip and directly opposite the corresponding first dicing channel, the test structure is located in the central chip region directly opposite each other, and is located within the first dicing channel and the opposite second dicing channel.

[0017] In some embodiments, the semiconductor structure has at least two sets of test structures, wherein the first direction of at least one set of test structures is the X direction, and the first direction of at least another set of test structures is the Y direction.

[0018] In some embodiments, the material of the first test pad is the same as the material of the second test pad.

[0019] This disclosure also provides a measurement method, comprising: providing a first wafer and a second wafer in a semiconductor structure as described in any of the preceding claims; bonding a first bonding surface and a second bonding surface together for pre-bonding; after pre-bonding, obtaining a first area and a second area; if the first area is greater than the second area, determining that the second wafer has been displaced relative to the first wafer in a second offset direction; if the first area is less than the second area, determining that the second wafer has been displaced relative to the first wafer in a first offset direction; comparing the minimum value of the first area and the second area with a preset value to analyze and obtain the displacement amount.

[0020] In some embodiments, obtaining the first area and the second area includes: measuring the contact resistance between a first first test pad and a first second test pad to obtain the first area; and measuring the contact resistance between a second first test pad and a second second test pad to obtain the second area.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: the semiconductor structure includes a first wafer and a second wafer bonded together, and the first bonding surface of the first wafer and the second bonding surface of the second wafer are bonded together. The first wafer and the second wafer bonded together have a test structure for measuring the alignment deviation between the first wafer and the second wafer. The test structure includes two first test pads exposed on the first bonding surface and two second test pads exposed on the second bonding surface. The two first test pads and the two second test pads are arranged at intervals along a first direction for measuring the displacement of the second wafer relative to the first wafer in the first direction. Additionally, the first test pad corresponds to the first second test pad, and the second first test pad corresponds to the second second test pad. The first second test pad is offset relative to the first first test pad in a first offset direction parallel to the first direction, and the second second test pad is offset relative to the second first test pad in a second offset direction. If the first direction is the X direction, then the first offset direction can be the -X direction, and the second offset direction can be the +X direction. The first offset direction is also the direction from the second second test pad to the first second test pad. The area directly opposite the first first test pad and the first second test pad is the first area, and the area directly opposite the second first test pad and the second second test pad is the second area. The first area and the second area are the same. Thus, if the first area is greater than the second area, it is determined that the second wafer has been displaced relative to the first wafer in the second offset direction. If the first area is less than the second area, it is determined that the second wafer has been displaced relative to the first wafer in the first offset direction. The minimum value between the first area and the second area is compared with a preset value to obtain the amount of displacement of the second wafer relative to the first wafer. The preset value can be the area value when the first area equals the second area. In this way, by testing the structure, it is possible to determine whether the second wafer is aligned and bonded with the first wafer, and to obtain the displacement of the second wafer relative to the first wafer. Based on the displacement, the bonding between the first wafer and the second wafer in the next semiconductor structure can be calibrated, which can improve the alignment accuracy of the bonding between the first wafer and the second wafer in the semiconductor structure, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 3 A schematic diagram illustrating a portion of the second bonding surface of a first test pad is provided as an embodiment of this disclosure;

[0026] Figure 4 Another structural schematic diagram showing a portion of the second bonding surface of the first test pad provided in this embodiment of the present disclosure;

[0027] Figure 5 This is a schematic diagram of the structure of a first wafer provided in an embodiment of the present disclosure;

[0028] Figure 6 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, provided in an embodiment of this disclosure.

[0029] Figure 7 A schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, provided in an embodiment of this disclosure;

[0030] Figure 8 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, as provided in another embodiment of this disclosure. Detailed Implementation

[0031] As is known from the background art, the process of aligning two bonded wafers using current alignment marks cannot accurately determine the amount of displacement between the two bonded wafers, which in turn affects the performance of the semiconductor structure.

[0032] This disclosure provides a semiconductor structure and a measurement method. The semiconductor structure includes a first wafer and a second wafer bonded together, with a first bonding surface of the first wafer and a second bonding surface of the second wafer bonded together. The bonded first wafer and the second wafer have a test structure for measuring the alignment deviation between the first wafer and the second wafer. The test structure includes two first test pads exposed on the first bonding surface and two second test pads exposed on the second bonding surface. The two first test pads and the two second test pads are arranged at intervals along a first direction for measuring the displacement of the second wafer relative to the first wafer in the first direction. In addition, the first test pad corresponds to the first second test pad, and the second first test pad corresponds to the second second test pad. The first second test pad is offset relative to the first first test pad in a first offset direction parallel to the first direction, and the second second test pad is offset relative to the second first test pad in a second offset direction. If the first direction is the X direction, then the first offset direction can be the -X direction, and the second offset direction can be the +X direction. The first offset direction is also the direction in which the second second test pad points to the first second test pad. The area directly opposite the first first test pad and the first second test pad is the first area, and the area directly opposite the second first test pad and the second second test pad is the second area. The first area and the second area are the same. Thus, if the first area is greater than the second area, it is determined that the second wafer has been displaced relative to the first wafer in the second offset direction. If the first area is less than the second area, it is determined that the second wafer has been displaced relative to the first wafer in the first offset direction. By comparing the maximum value of the directly opposite area with the preset area, the displacement amount of the second wafer relative to the first wafer can be obtained. The preset area can be the area value when the first area equals the second area. In this way, by testing the structure, it is possible to determine whether the second wafer is aligned and bonded with the first wafer, and to obtain the displacement of the second wafer relative to the first wafer. Based on the displacement, the bonding between the first wafer and the second wafer in the next semiconductor structure can be calibrated, which can improve the alignment accuracy of the bonding between the first wafer and the second wafer in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0033] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0034] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A schematic diagram illustrating a portion of the second bonding surface of a first test pad is provided as an embodiment of this disclosure; Figure 4 Another structural schematic diagram showing a portion of the second bonding surface of the first test pad provided in this embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of a first wafer provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, provided in an embodiment of this disclosure. Figure 7 A schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram illustrating the positional relationship between a test structure on a first wafer and a first chip, as provided in another embodiment of this disclosure.

[0035] refer to Figure 1 The semiconductor structure includes: a first wafer 100 having a first bonding surface; a second wafer 110 having a second bonding surface bonded to the first bonding surface; and at least one set of test structures 120, each test structure 120 including: two first test pads 101 spaced apart within the first wafer 100 along a first direction, with the first bonding surface exposing the surface of the first test pads 101; and two second test pads 111 spaced apart within the second wafer 110 along the first direction, with the second bonding surface exposing the surface of the second test pads 111, each second test pad 111 being bonded to a corresponding first test pad 101. 01 is directly opposite; wherein, the first second test pad is offset in a first offset direction relative to the first first test pad 101, and the second second test pad is offset in a second offset direction relative to the second first test pad 101. The first offset direction and the second offset direction are opposite directions parallel to the first direction. The direction in which the second second test pad 111 points to the first second test pad 111 is the first offset direction. The area directly opposite the first first test pad 101 and the first second test pad 111 is the first area 200, and the area directly opposite the second first test pad 101 and the second second test pad 111 is the second area 201. The first area 200 is equal to the second area 201.

[0036] refer to Figure 1 and Figure 2The first test pad 101 and the second test pad 111, arranged at intervals along a first direction, are used to measure the displacement of the second wafer 110 relative to the first wafer 100 in the first direction. Furthermore, when the first wafer 100 and the second wafer 110 are aligned and bonded, the first area 200 and the second area 201 are the same. Therefore, if the second wafer 110 is displaced relative to the first wafer 100 in a second offset direction, the first second test pad 111 is displaced relative to the first first test pad 101 in the second offset direction, causing the first second test pad 111, which was displaced relative to the first first test pad 101 in the first offset direction, to move in the opposite second offset direction, and causing the second second test pad 111 to continue to be displaced relative to the second first test pad 101 in the second offset direction. This results in the facing area of ​​the second second test pad 111 and the second first test pad 101 decreasing, and the facing area of ​​the first second test pad 111 and the first first test pad 101 increasing. Clearly, the offset between the first wafer 100 and the second wafer 110 causes the first area 200 and the second area 201 to exhibit different trends.

[0037] Similarly, if the second wafer 110 is displaced relative to the first wafer 100 in the first offset direction, the first area 200 becomes smaller, while the second area 201 becomes larger. Thus, by comparing the size of the first area 200 and the size of the second area 201 in the test structure 120 with the size of the first area 200 or the second area 201 during alignment and bonding, it is possible to determine whether the second wafer 110 and the first wafer 100 are aligned and bonded, and to obtain the displacement of the second wafer 110 relative to the first wafer 100. This facilitates the calibration of the bonding between the first wafer 100 and the second wafer 110 in the next semiconductor structure based on the displacement, thereby ensuring better alignment accuracy between the first wafer 100 and the bonded second wafer 110 in the semiconductor structure.

[0038] The first wafer 100 and the second wafer 110 are wafers on which semiconductor devices or circuits are fabricated. In some embodiments, the wafers can be wafers on which semiconductor devices or circuits are fabricated with silicon as a substrate. In other embodiments, the substrate of the wafers can also be other semiconductor materials or other materials that can be used as substrates.

[0039] A first wafer 100 is bonded to a second wafer 110 to electrically connect semiconductor devices or circuits in the first wafer 100 to semiconductor devices or circuits in the second wafer 110. Specifically, a first bonding surface of the first wafer 100 and a second bonding surface of the second wafer 110 are disposed opposite to each other and bonded together. The first bonding surface can expose pads for leading out semiconductor devices or circuits in the first wafer 100, and the second bonding surface can expose pads for leading out semiconductor devices or circuits in the second wafer 110. By bonding the first wafer 100 and the second wafer 110, the first bonding surface and the second bonding surface are in contact, and the pads on the first bonding surface are in contact with the corresponding pads on the second bonding surface. The connection between the pads is used to achieve the connection between semiconductor devices or circuits in the first wafer 100 and semiconductor devices or circuits in the second wafer 110.

[0040] The interface state between the first and second bonding surfaces has a certain impact on the electrical properties and structural stability of the bonded semiconductor structure. Therefore, the structural stability of the first wafer 100 and the second wafer 110 can be improved by increasing the stress matching degree between the first and second bonding surfaces, or by avoiding impurities or bubbles at the bonding interface formed by the first and second bonding surfaces. Furthermore, the electrical properties of the semiconductor structure can be improved by increasing the alignment accuracy between the first wafer 100 and the second wafer 110.

[0041] The test structure 120 in the semiconductor structure provided in this embodiment is a structure for improving the alignment accuracy between the first wafer 100 and the second wafer 110. The test structure 120 includes two first test pads 101 and two second test pads 111 spaced apart along a first direction. The first direction can be any direction parallel to the surface of the first wafer 100 or the second wafer 110. If the first direction is the X direction, the two first test pads 101 and two second test pads 111 arranged in the first direction can measure the displacement of the second wafer 110 relative to the first wafer 100 in the X direction. Therefore, the first direction can be defined according to testing requirements to achieve the measurement of the displacement of the second wafer 110 relative to the first wafer 100 in any direction parallel to the surface of the first wafer 100 or the surface of the second wafer 110.

[0042] Taking the X direction as an example, the displacement of the second wafer 110 relative to the first wafer 100 in the X direction includes two cases: one is that the second wafer 110 is displaced in the +X direction relative to the first wafer 100, and the other is that the second wafer 110 is displaced in the -X direction relative to the first wafer 100. In the semiconductor structure provided in this embodiment, a set of test structures 120 is set in the X direction, which can measure the two displacement cases of the second wafer 110 relative to the first wafer 100 in the X direction. In this way, there is no need to reserve a large setting area for the test structures 120 in the first wafer 100 and the second wafer 110, which helps to reduce the manufacturing difficulty of the test structures 120.

[0043] In some embodiments, reference Figure 1 Both the first wafer 100 and the second wafer 110 include an insulating layer 130, which can be made of silicon oxide or silicon nitride. A first bonding surface exposes the insulating layer 130 of the first wafer 100, and a first test pad 101 is located within the insulating layer 130. The material of the first test pad 101 is a conductive material, such as copper, tungsten, or aluminum. A second bonding surface exposes the insulating layer 130 of the second wafer 110, and a second test pad 111 is located within the insulating layer 130 of the second wafer 110. The material of the second test pad 111 is also a conductive material, such as copper, tungsten, or aluminum.

[0044] In some embodiments, the material of the first test pad 101 is the same as the material of the second test pad 111. This is advantageous because it allows the first test pad 101 and the second test pad 111 to be formed using the same fabrication process and the same source material, thereby reducing the fabrication difficulty of the first test pad 101 and the second test pad 111.

[0045] refer to Figure 1In some embodiments, each first test pad 101 exposed on the first bonding surface has the same shape. Forming the first test pad 101 typically requires photolithography and etching processes. Photolithography defines the shape and dimensions of the first test pad 101. However, during photoresist exposure, the incident light used in the photolithography process can produce unwanted reflected or refracted light. This unwanted reflected or refracted light may expose unwanted photoresist, resulting in an error between the formed photoresist pattern and the pre-formed photoresist pattern after development. Furthermore, the intensity and direction of the reflected or refracted light are also related to the pre-formed photoresist pattern. If the pre-formed photoresist patterns are different, the errors in the photolithography process will also be different. Therefore, if each first test pad 101 has a different shape, the pre-formed photoresist pattern associated with the first test pad 101 will also be different. Different pre-formed photoresist patterns may lead to different photolithography errors in different first test pads 101, resulting in different setting errors between different first test pads 101, affecting the testing accuracy of the first test pads 101. Therefore, by setting each of the first test pads 101 exposed on the first bonding surface to have the same shape, the size error between first test pads 101 with different shapes due to different photolithography errors can be avoided. This helps to reduce the size error between different first test pads 101, and in turn, it helps to use the first test pads 101 with smaller size error to measure the alignment accuracy of wafer bonding more accurately.

[0046] In some embodiments, reference Figure 1 Each of the second test pads 111 exposed on the second bonding surface has the same shape. Similarly, if each second test pad 111 has a different shape, the preset photoresist pattern associated with the second test pad 111 will also be different. Different preset photoresist patterns may lead to different photolithographic errors in different second test pads 111, resulting in different setting errors between different second test pads 111, which affects the testing accuracy of the second test pads 111. Therefore, setting each of the second test pads 111 exposed on the second bonding surface to have the same shape can avoid different dimensional errors between second test pads 111 with different shapes due to different photolithographic errors. This helps to reduce the dimensional errors between different second test pads 111, and thus facilitates more accurate measurement of the alignment accuracy of wafer bonding using second test pads 111 with smaller dimensional errors.

[0047] In some embodiments, reference Figure 1 and Figure 3The first test pad 101 exposed on the first bonding surface is a first square, and each first square has the same length in the first direction; the second test pad 111 exposed on the second bonding surface is a second square, and each second square has the same length in the first direction. Taking the first direction as the X direction as an example, that is, in the test structure 120, the first first test pad 101 and the second first test pad 101 have the same shape, and both are first squares with the length direction parallel to the first direction and the width direction perpendicular to the first direction. The first and second test pads 111 have the same shape, and each test pad 111 is a second square with its length direction parallel to the first direction and its width direction perpendicular to the first direction. Thus, the shape of the overlapping part of the second test pad 111 and the corresponding first test pad 101 is square. If the second test pad 111 is displaced relative to the corresponding first test pad 101 in the first direction, the area of ​​the square of the overlapping part of the second test pad 111 and the corresponding first test pad 101 is linearly related to the amount of displacement of the second test pad 111 relative to the corresponding first test pad 101 in the first direction. In this way, it is easier to deduce the amount of displacement of the second wafer 110 relative to the first wafer 100 based on the area of ​​the square of the overlapping part of the second test pad 111 and the corresponding first test pad 101, which helps to reduce the difficulty of measuring the displacement.

[0048] In some embodiments, reference Figure 3 In the direction perpendicular to the first direction, the width of the first test pad 101 exposed on the first bonding surface is smaller than the width of the second test pad 111 exposed on the second bonding surface. Taking the first direction as the X direction as an example, the direction perpendicular to the first direction can be the Y direction. In the Y direction, if the width of the first test pad 101 is the same as the width of the second test pad 111, when the first test pad 101 is displaced relative to the second test pad 111 in the X direction, and the first test pad 101 is also displaced relative to the second test pad 111 in the Y direction, the facing area of ​​the first test pad 101 and the second test pad 111 can be larger than the facing area of ​​the first test pad 101 and the second test pad 111 during alignment bonding, or it can be smaller than the facing area of ​​the first test pad 101 and the second test pad 111 during alignment bonding. In this case, the positional relationship between the first wafer 100 and the second wafer 110 cannot be deduced from the facing area of ​​the first test pad 101 and the second test pad 111. Therefore, setting the width of the first test pad 101 to be smaller than the width of the second test pad 111 in the direction perpendicular to the first direction is beneficial to ensuring that the change in the area of ​​the first test pad 101 and the second test pad 111 facing each other has a clear pattern with the change in the position of the first wafer 100 relative to the second wafer 110, which in turn helps to ensure the test accuracy of the test structure 120.

[0049] In some embodiments, reference Figure 4 While ensuring that the change in the area of ​​the first test pad 101 and the second test pad 111 is consistent with the change in the position of the first wafer 100 relative to the second wafer 110, the width of the first test pad 101 exposed on the first bonding surface can also be greater than the width of the second test pad 111 exposed on the second bonding surface in the first direction. This is also beneficial to ensuring the test accuracy of the test structure 120.

[0050] In some embodiments, the shape of the first test pad 101 exposed on the first bonding surface or the shape of the second test pad 111 exposed on the second bonding surface may also be circular or other shapes.

[0051] In some embodiments, reference Figure 1 Taking the X-direction as an example, the width of the first test pad 101 along the first direction can be from 100nm to 10000nm, for example, 250nm, 450nm, 500nm, 5400nm, 8900nm, etc. The width of the second test pad 111 can also be from 100nm to 10000nm, for example, 100nm, 1500nm, 2500nm, 4500nm, 9500nm, etc. Specifically, the widths of the first test pad 101 and the second test pad 111 in the first direction can be reasonably set according to the dimensions of the first wafer 100 and the second wafer 110 in the first direction.

[0052] In some embodiments, reference Figure 1 Taking the X-direction as an example, the length of the first test pad 101 perpendicular to the first direction is 100nm to 1000nm, for example, it can be 250nm, 300nm, 450nm, 500nm, 800nm, etc. The length of the second test pad 111 is 100nm to 1000nm, for example, it can be 450nm, 360nm, 480nm, 550nm, 760nm, etc. Similarly, the widths of the first test pad 101 and the second test pad 111 in the first direction can be reasonably set according to the dimensions of the first wafer 100 and the second wafer 110 perpendicular to the first direction.

[0053] In some embodiments, the semiconductor structure further includes: a first power pad 102, with a first bonding surface exposing the first power pad 102; and a second power pad 112, with a second bonding surface exposing the second power pad 112, and the first power pad 102 and the second power pad 112 facing each other.

[0054] The first power pad 102 can be a pad for providing power to semiconductor devices or circuits in the first wafer 100, and the second power pad 112 can be a pad for providing power to semiconductor devices or circuits in the second wafer 110. The first power pad 102 and the second power pad 112 are connected to each other, so that the semiconductor devices or circuits in the first wafer 100 and the semiconductor devices or circuits in the second wafer 110 share a power lead, which helps to reduce the complexity of the lead layout in the semiconductor structure and helps to reduce the manufacturing difficulty of the semiconductor structure.

[0055] In some embodiments, reference Figure 1 Along the first direction, the width of the first power pad 102 exposed on the first bonding surface is the same as the width of the second power pad 112 exposed on the second bonding surface.

[0056] Taking the X direction as an example, the first power pad 102 and the second power pad 112, which are of the same width and directly opposite each other in the first direction, can be used as positioning marks in the process of setting the first test pad 101 and the second test pad 111. This is beneficial to accurately set the first test pad 101 in the first wafer 100 and accurately set the second test pad 111 in the second wafer 110 using the existing pads in the semiconductor structure. This avoids setting additional positioning marks and helps to reduce the manufacturing difficulty of the first test pad 101 and the second test pad 111.

[0057] In some embodiments, reference Figure 1The first test pad is adjacent to the first power pad 102, and the second test pad 111 is adjacent to the second power pad 112. The first test pad 101 of the test structure 120 is electrically connected to the adjacent first power pad 102, and the second test pad 111 of the test structure 120 is electrically connected to the adjacent second power pad 112. By positioning the test structure 120 adjacent to the first power pad 102 and the second power pad 112, and utilizing the first power pad 102 and the second power pad 112 to provide test current to the directly opposite first test pad 101 and second test pad 111, it is advantageous to avoid setting up additional conductive structures to provide test current to the test structure 120, thereby reducing the manufacturing difficulty of the semiconductor structure. Furthermore, if the first test pad 101 and the corresponding second test pad 111 are connected, the first test pad 101 and the corresponding second test pad 111 also provide more conduction paths for the current flowing through the first power pad 102 and the second power pad 112. The first test pad 101 and the second test pad 111 connected in parallel with the first power pad 102 and the second power pad 112 reduce the resistance of the power leads shared by the first wafer 100 and the second wafer 110, which is beneficial to improving the electrical performance of the semiconductor structure and to avoiding the problem of poor heat dissipation of the semiconductor structure caused by too many leads.

[0058] In some embodiments, reference Figure 1 The first power pad 102 can be disposed within the insulating layer 130 of the first wafer 100, and the second power pad 112 can be disposed within the insulating layer 130 of the second wafer 110. The first power pad 102 and the second power pad 112 are made of the same material, which may include copper, tungsten, or aluminum. Furthermore, the surface of the first wafer 100 opposite to the first bonding surface also exposes the first power pad 102, and the surface of the second wafer 110 opposite to the second bonding surface also exposes the second power pad 112. This facilitates the use of the exposed first power pad 102 to provide a power signal to the first power pad 102, and also facilitates the use of the exposed second power pad 112 to provide a power signal to the second power pad 112.

[0059] In some embodiments, reference Figure 1 , Figures 6 to 8The semiconductor structure has at least two sets of test structures 120, wherein the first direction in at least one set of test structures 120 is the X direction, and the first direction in at least another set of test structures 120 is the Y direction. It should be noted that the Y direction and the X direction are different directions. By setting at least two sets of test structures 120 within the semiconductor structure, with the first direction in one set of test structures 120 being the X direction and the first direction in the other set being the Y direction, the displacement of the second wafer 110 relative to the first wafer 100 in the X direction can be measured using the test structure 120 with the first direction in the X direction, and the displacement of the second wafer 110 relative to the first wafer 100 in the Y direction can be measured using the test structure 120 with the first direction in the Y direction. This allows for measurement of the displacement of the second wafer 110 relative to the first wafer 100 in multiple directions, thereby improving the alignment accuracy between the first wafer 100 and the second wafer 110 using the test structures 120 in multiple directions.

[0060] In some embodiments, the Y direction is perpendicular to the X direction. By combining the displacement measured by the two sets of test structures 120 set in the semiconductor structure, the displacement of the first wafer 100 and the second wafer 110 in all directions parallel to the surface of the first wafer 100 can be measured. This is beneficial to improve the alignment accuracy of the first wafer 100 and the second wafer 110 by using the test structure 120.

[0061] In some embodiments, reference Figure 1 and Figure 5 The first wafer 100 has a first central region 103 and a first edge region 104, and the second wafer 110 has a second central region and a second edge region. The first central region 103 and the second central region are directly opposite each other, and the first edge region 104 and the second edge region are directly opposite each other. The first central region 103 and the directly opposite second central region have corresponding test structures 120, and the first edge region 104 and the directly opposite second edge region also have corresponding test structures 120. Thus, by using the test structure 120 in the middle of the first wafer 100 and the second wafer 110, alignment measurement is performed between the center of the first wafer 100 and the center of the second wafer 110. Similarly, by using the test structures 120 at the edges of the first wafer 100 and the second wafer 110, alignment measurement is performed between the edges of the first wafer 100 and the edges of the second wafer 110. Aligning both the center and the edges allows for overall alignment measurement of the first wafer 100 and the second wafer 110. This facilitates precise measurement of the bonding between the first wafer 100 and the second wafer 110 using a limited number of test structures 120. It should be noted that the second middle region and the second edge region of the second wafer 110 are similar to those of the first wafer 100, but are not shown.

[0062] In some embodiments, a first central region 103 and an opposite second central region are provided with multiple sets of test structures 120, and a first edge region 104 and an opposite second edge region are also provided with multiple sets of test structures 120. A greater number of test structures 120 is beneficial for improving the alignment accuracy between the first wafer 100 and the second wafer 110.

[0063] In some embodiments, reference Figure 1 , Figures 6 to 8 The first wafer 100 includes a plurality of first chips 105, and the second wafer 110 includes a plurality of second chips, with each first chip 105 facing a corresponding second chip. Some of the first chips 105 and the facing second chips have corresponding test structures 120. Thus, not only can the displacement of the second wafer 110 relative to the first wafer 100 as a whole be measured using the test structures 120, but also the displacement of the second chips within the second wafer 110 relative to the corresponding first chips 105 within the first wafer 100 can be measured. This facilitates accurate acquisition of the displacement between the second chips and the first chips 105 using the test structures 120, thereby achieving accurate alignment and bonding between the second chips and the first chips 105. Higher alignment accuracy of the first chips 105 and second chips improves the performance of the semiconductor structure. It should be noted that the arrangement of the second chips in the second wafer 110 is similar to that of the first chips 105 in the first wafer 100; therefore, the structure of the second chips in the second wafer 110 is not shown.

[0064] In some embodiments, reference Figure 6 Both the first chip 105 and the second chip have a central chip region and a chip edge region. The central chip region of the first chip 105 is directly opposite the central chip region of the second chip, and the chip edge region of the first chip 105 is directly opposite the chip edge region of the second chip. The test structure 120 is located in the directly opposite central chip region and the directly opposite chip edge region.

[0065] The central region of the chip is the area near the center of the first chip 105 or the second chip, while the edge region is the area near the edge of the first chip 105 or the second chip. To improve the measurement of the alignment accuracy between the first chip 105 and the opposing second chip, at least two sets of corresponding test structures 120 can be provided within the first chip 105 and the opposing second chip. The two sets of test structures 120 can be located in the central region of the chip and the edge region of the chip, respectively. In this way, the alignment state between the center of the first chip 105 and the center of the second chip can be measured using the test structure 120 in the central region of the chip, and the alignment state between the edge of the first chip 105 and the edge of the second chip can be measured using the test structure 120 in the edge region of the chip. This facilitates accurate measurement of the bonding alignment between the first chip 105 and the opposing second chip using the test structure 120.

[0066] In some embodiments, reference Figure 7 or Figure 8 Both the first chip 105 and the second chip have a central region. The central regions of the first chip 105 and the corresponding central regions of the second chip are aligned. The first wafer 100 also includes a first dicing channel 106 located at the edge of the first chip 105, and the second wafer 110 also includes a second dicing channel located at the edge of the second chip and aligned with the corresponding first dicing channel 106. The test structure 120 is located in the opposing central regions of the chips, and also within the first dicing channel 106 and the opposing second dicing channel. Thus, the alignment status of the central regions of the first chip 105 and the second chip can be measured using the test structure 120 in the central region of the chips, and the alignment status of the edges of the first chip 105 and the edges of the second chip can be measured using the test structure 120 within the first and second dicing channels at the chip edges.

[0067] It is understood that, in the above embodiments, references Figure 6 and Figure 7 Taking the alignment measurement of the bonding between the middle of the first chip 105 and the opposite second chip as an example, at least two sets of test structures 120 can be provided at the middle of the first chip 105 and the middle of the opposite second chip. The first directions of the two sets of test structures 120 are different. In some embodiments, the first directions of the two sets of test structures 120 can be the X-direction and the Y-direction, which are perpendicular to each other. In this way, the displacement of the middle of the first chip 105 and the middle of the opposite second chip in various directions can be measured. Similarly, the test structures 120 for measuring the displacement of the edge of the first chip 105 and the edge of the opposite second chip in various directions are also similar. At least two sets of test structures 120 with different first directions can be provided at the edge of the first chip 105 and the edge of the opposite second chip. The first directions of the two sets of test structures 120 can be the X-direction and the Y-direction, which are perpendicular to each other.

[0068] In some embodiments, the spacing between the test structures 120 measuring in different directions can be small. In one example, a first chip 105 and an opposing second chip have multiple adjacent sets of test structures 120 measuring in different directions. In other embodiments, the spacing between the test structures 120 measuring in different directions can be larger. In one example, a first chip 105 and an opposing second chip have only one adjacent set of test structures 120 measuring in the X direction, while the test structures 120 measuring in the Y direction are located at a distance from the test structures 120 measuring in the X direction.

[0069] In the semiconductor structure provided in the above embodiments, the semiconductor structure includes a first wafer 100 and a second wafer 110 bonded together. The first wafer 100 has a first bonding surface, and the second wafer 110 has a second bonding surface for bonding with the first bonding surface. The semiconductor structure also includes a test structure 120 for measuring the alignment deviation between the first wafer 100 and the second wafer 110. The test structure 120 includes two first test pads 101 and two second test pads 111. The two first test pads 101 and the two second test pads 111 are arranged at intervals along a first direction for measuring the displacement of the second wafer 110 relative to the first wafer 100 in the first direction. Furthermore, the first first test pad 101 corresponds to the first second test pad 111, and the second first test pad 101 corresponds to the second second test pad 111. The first second test pad 111 is offset relative to the first first test pad 101 in a first offset direction parallel to a first direction, and the second second test pad 111 is offset relative to the second first test pad 101 in a second offset direction. The first offset direction is also the direction in which the second second test pad 111 points to the first second test pad 111. The area directly opposite the first first test pad 101 and the first second test pad 111 is a first area of ​​200. The area directly opposite the second first test pad 101 and the second second test pad 111 is a first area of ​​200. The area directly opposite the disk 111 is the second area 201. When the first wafer 100 and the second wafer 110 are aligned and bonded, the first area 200 and the second area 201 are the same. Thus, if the first area 200 is greater than the second area 201, it is determined that the second wafer 110 has been displaced relative to the first wafer 100 in the second offset direction. If the first area 200 is less than the second area 201, it is determined that the second wafer 110 has been displaced relative to the first wafer 100 in the first offset direction. By comparing the minimum value of the directly opposite area with a preset value, the displacement amount of the second wafer 110 relative to the first wafer 100 can be obtained. The preset value can be the area value when the first area 200 is equal to the second area 201. Thus, by using the test structure 120, it is possible to determine whether the second wafer 110 and the first wafer 100 are aligned and bonded, and to obtain the displacement of the second wafer 110 relative to the first wafer 100. Based on the displacement, the bonding between the first wafer 100 and the second wafer 110 in the next semiconductor structure is calibrated, which can improve the alignment accuracy of the bonding between the first wafer 100 and the second wafer 110 in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0070] Accordingly, this disclosure also provides a measurement method for measuring the semiconductor structure provided in the above embodiments. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be found in the detailed descriptions of the foregoing embodiments, and will not be repeated hereafter.

[0071] refer to Figure 1 The measurement method includes: providing a first wafer 100 and a second wafer 110 in the semiconductor structure described in the above embodiments; bonding a first bonding surface and a second bonding surface together for pre-bonding; after pre-bonding, obtaining a first area 200 and a second area 201; if the first area 200 is greater than the second area 201, it is determined that the second wafer 110 has been displaced relative to the first wafer 100 in a second offset direction; if the first area 200 is less than the second area 201, it is determined that the second wafer 110 has been displaced relative to the first wafer 100 in a first offset direction; comparing the minimum value of the first area 200 and the second area 201 with a preset value to analyze and obtain the displacement amount. The preset value can be the area value when the first wafer 100 and the second wafer 110 are aligned and bonded, i.e., when the first area 200 and the second area 201 are the same.

[0072] For details, please refer to Figure 1 and Figure 2 Taking the first direction as the X direction, the first offset direction as the -X direction, and the second offset direction as the +X direction as an example, if the first area 200 is less than the second area 201, that is, the area of ​​the second second test pad 111 facing the second first test pad 101 is greater than a preset value, and the area of ​​the first second test pad 111 facing the first first test pad 101 is less than a preset value, then the second second test pad 111 has been displaced in the -X direction relative to the second first test pad 101, and the first second test pad 111 has been displaced in the -X direction relative to the first first test pad 101. Therefore, it can be concluded that the second wafer 110 has been displaced in the -X direction relative to the first wafer 100.

[0073] Similarly, if the first area 200 is greater than the second area 201, then the second second test pad 111 is displaced in the +X direction relative to the second first test pad 101, and the first second test pad 111 is displaced in the +X direction relative to the first first test pad 101. Therefore, it can be concluded that the second wafer 110 is displaced in the +X direction relative to the first wafer 100.

[0074] Therefore, based on the size relationship between the first area 200 and the second area 201, the displacement of the second wafer 110 relative to the first wafer 100 can be accurately measured. Furthermore, by comparing the minimum value of the first area 200 and the second area 201 with a preset value, the displacement of the second wafer 110 relative to the first wafer 100 can be obtained. This facilitates the calibration of the bonding between the first wafer 100 and the bonded second wafer 110 based on the displacement, so that the first wafer 100 and the second wafer 110 have a small offset, which is beneficial to improving the performance of the semiconductor structure.

[0075] Additionally, refer to Figure 2 Taking the displacement of the second wafer 110 relative to the first wafer 100 in the -X direction as an example, the changing trend of the second area 201 is as follows: firstly, it gradually increases relative to a preset value; after reaching its maximum value, the second area 201 gradually decreases. Therefore, if the second area 201 is compared with the preset value, the direction of displacement may be incorrectly determined. Thus, in this embodiment, the displacement is analyzed based on the relatively small first area 200, which avoids incorrect determination of the direction of displacement, thereby improving the accuracy of the test structure 120 in measuring the relative position of the first wafer 100 and the second wafer 110.

[0076] In some embodiments, obtaining the first area 200 and the second area 201 includes: measuring the contact resistance between the first first test pad 101 and the first second test pad 111 to obtain the first area 200; and measuring the contact resistance between the second first test pad 101 and the second second test pad 111 to obtain the second area 201.

[0077] Specifically, leads can be set to bring out the first test pad 101 and the second test pad 111, and test current can be provided to the first test pad 101 and the second test pad 111 through the leads. When the first wafer 100 and the second wafer 110 are aligned and bonded, the contact resistance between the first test pad 101 and the first test pad 111 is defined as a preset resistance value. The contact resistance between the first test pad 101 and the first test pad 111 is measured, and the resistance value is compared with the preset resistance value to obtain a first area 200. The contact resistance between the second test pad 101 and the second test pad 111 is measured, and the resistance value is compared with the preset resistance value to obtain a second area 201. The larger the contact resistance between the first test pad 101 and the corresponding second test pad 111, the smaller the relative area between the first test pad 101 and the corresponding second test pad 111.

[0078] In some embodiments, the area of ​​the first test pad 101 and the corresponding second test pad 111 facing each other can also be measured by infrared measurement.

[0079] In the measurement method provided in the above embodiments, the first area 200 is determined by testing the facing area of ​​the first test pad 101 and the first second test pad 111, and the second area 201 is determined by testing the facing area of ​​the second test pad 101 and the second second test pad 111. The first area 200 and the second area 201 are compared to determine the displacement state of the second wafer 110 relative to the first wafer 100. The displacement amount of the second wafer 110 relative to the first wafer 100 can be obtained based on the minimum value of the first area 200 and the second area 201. The measured displacement amount is then used to calibrate the bonding between the next first wafer 100 and the bonded second wafer 110, so that the first wafer 100 and the second wafer 110 have a small offset, which is beneficial to improving the performance of the semiconductor structure.

[0080] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first wafer, the first wafer having a first bonding surface; The second wafer has a second bonding surface that is bonded to the first bonding surface; At least one set of test structures, the test structures including: Two first test pads are arranged at intervals along a first direction within the first wafer, and the first bonding surface exposes the surface of the first test pads. Two second test pads are arranged at intervals along the first direction within the second wafer, and the second bonding surface exposes the surface of the second test pads. Each second test pad is directly opposite the corresponding first test pad. Wherein, the first second test pad is offset in a first offset direction relative to the first first test pad, and the second second test pad is offset in a second offset direction relative to the second first test pad. The first offset direction and the second offset direction are opposite directions parallel to the first direction. The direction in which the second second test pad points to the first second test pad is the first offset direction. The area directly opposite the first first test pad and the first second test pad is the first area, and the area directly opposite the second first test pad and the second second test pad is the second area. The first area is equal to the second area.

2. The semiconductor structure as described in claim 1, characterized in that, Each of the first test pads exposed on the first bonding surface has the same shape.

3. The semiconductor structure as described in claim 2, characterized in that, Each of the second test pads exposed on the second bonding surface has the same shape.

4. The semiconductor structure as described in claim 3, characterized in that, The first test pad exposed on the first bonding surface is a first square, and each of the first squares has the same length in the first direction; the second test pad exposed on the second bonding surface is a second square, and each of the second squares has the same length in the first direction.

5. The semiconductor structure as described in claim 4, characterized in that, In a direction perpendicular to the first direction, the width of the first test pad exposed on the first bonding surface is smaller than the width of the second test pad exposed on the second bonding surface.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a first power pad, the first bonding surface of which exposes the first power pad; and a second power pad, the second bonding surface of which exposes the second power pad, and the first power pad and the second power pad are directly opposite each other.

7. The semiconductor structure as described in claim 6, characterized in that, Along the first direction, the width of the first power pad exposed on the first bonding surface is the same as the width of the second power pad exposed on the second bonding surface.

8. The semiconductor structure as described in claim 6, characterized in that, The first test pad is adjacent to the first power pad, the second test pad is adjacent to the second power pad, and the first test pad of the test structure is electrically connected to the adjacent first power pad, and the second test pad of the test structure is electrically connected to the adjacent second power pad.

9. The semiconductor structure as described in claim 1, characterized in that, The first wafer has a first central region and a first edge region, and the second wafer has a second central region and a second edge region. The first central region and the second central region are directly opposite each other, and the first edge region and the second edge region are directly opposite each other. The first central region and the directly opposite second central region have corresponding test structures, and the first edge region and the directly opposite second edge region also have corresponding test structures.

10. The semiconductor structure as described in claim 1, characterized in that, The first wafer includes a plurality of first chips, and the second wafer includes a plurality of second chips, each of the first chips being opposite to a corresponding second chip; a portion of the first chips and the opposite second chips have the corresponding test structure.

11. The semiconductor structure as described in claim 10, characterized in that, Both the first chip and the second chip have a central chip region and a chip edge region. The central chip region of the first chip and the central chip region of the second chip are directly opposite each other, and the chip edge regions of the first chip and the second chip are directly opposite each other. The test structure is located in the central chip region and the chip edge region of the opposite chip.

12. The semiconductor structure as described in claim 10, characterized in that, Both the first chip and the second chip have a central chip region, and the central chip region of the first chip and the central chip region of the opposite second chip are directly opposite each other. The first wafer also includes a first dicing channel located at the edge of the first chip, and the second wafer also includes a second dicing channel located at the edge of the second chip and directly opposite the corresponding first dicing channel. The test structure is located in the central chip region directly opposite each other, and is located within the first dicing channel and the opposite second dicing channel.

13. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure has at least two sets of test structures, wherein the first direction in at least one set of test structures is the X direction, and the first direction in at least another set of test structures is the Y direction.

14. The semiconductor structure as described in claim 1, characterized in that, The material of the first test pad is the same as that of the second test pad.

15. A measurement method, characterized in that, include: Provides the first wafer and the second wafer in any of the semiconductor structures described in claims 1-14; The first bonding surface and the second bonding surface are attached together for pre-bonding; After the pre-bonding is performed, the first area and the second area are obtained. If the first area is greater than the second area, it is determined that the second wafer has been displaced relative to the first wafer in the second offset direction; if the first area is less than the second area, it is determined that the second wafer has been displaced relative to the first wafer in the first offset direction. The displacement is obtained by comparing the minimum value of the first area and the second area with a preset value.

16. The measurement method as described in claim 15, characterized in that, The methods for obtaining the first area and the second area include: Measure the contact resistance between the first first test pad and the first second test pad to obtain the first area; The contact resistance between the second first test pad and the second second test pad is measured to obtain the second area.

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