A through-hole type vertical structure LED chip and a manufacturing method thereof

Abstract

The application provides a through-hole type vertical structure LED chip and a manufacturing method thereof. The through-hole type vertical structure LED chip is provided with a metal bonding layer, a diffusion prevention structure, a through-hole reflection structure, a metal reflection layer, a conduction layer, an insulation layer and an epitaxial layer on the side of a conductive substrate. The diffusion prevention structure is used to prevent the metal material of the metal bonding layer from diffusing to the through-hole reflection structure to form an alloy or penetrate into the surface of the through-hole reflection structure, thereby affecting the reflection effect of the through-hole reflection structure and the stability of the product. The diffusion prevention structure can be used to improve the light extraction efficiency of the chip and the reliability of the product, thereby improving the brightness and reliability of the through-hole type vertical structure LED chip. The process is simple, convenient and easy to produce.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to a through-hole type vertical structure LED chip and its fabrication method. Background Technology

[0002] Existing light-emitting diodes (LEDs) include horizontal and vertical types. Vertical LEDs are obtained by transferring a semiconductor barrier stack to a substrate with better conductivity and thermal conductivity, and removing the original epitaxial substrate. The semiconductor barrier stack includes at least a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked sequentially. Compared to horizontal LEDs, this effectively improves the technical problems of light absorption, current congestion, or poor heat dissipation caused by the epitaxial substrate. Substrate transfer generally employs bonding processes, primarily through metal-to-metal high-temperature, high-pressure bonding, especially through the formation of intermetallic compounds between high-melting-point and low-melting-point metals under suitable bonding conditions. This serves as an interconnection (the low-melting-point metal diffuses into the high-melting-point metal after melting and forms an intermetallic compound with a melting point and physicochemical properties between the two). In other words, a metal bonding layer is formed between one side of the semiconductor barrier stack and the substrate.

[0003] Existing through-hole vertical structure LED chips include through-holes that penetrate at least the second type semiconductor layer and the active region, exposing a portion of the first type semiconductor layer. A metal bonding layer is electrically connected to the first type semiconductor layer through the through-hole. The side of the first type semiconductor layer facing away from the active region is the light-emitting side, but light generated in the active region is absorbed at the through-hole. Currently, high-reflectivity metal is filled into the through-hole of the through-hole LED chip to ensure good reflection of light generated in the active region, thereby improving the chip's light extraction efficiency and thus increasing the brightness of the through-hole vertical structure LED chip. However, during the bonding process, the metal in the metal bonding layer easily migrates above its melting point. Under high temperature and pressure, it can overcome the barrier layer and diffuse into the through-hole, forming an alloy with the high-reflectivity metal within the through-hole or penetrating to the surface of the high-reflectivity metal, thus affecting the reflectivity of the high-reflectivity metal. This not only reduces the reflectivity of the LED chip's reflective layer, affecting the chip's light extraction efficiency, but the bonding metal may also diffuse to the periphery of the chip, affecting the LED's reliability and stability. Summary of the Invention

[0004] In view of this, the present invention provides a through-hole type vertical structure LED chip and its manufacturing method to solve the problems in the prior art where the through-hole of the through-hole type vertical structure LED chip is filled with high reflectivity metal, but the metal of the metal bonding layer is easy to migrate to the through-hole when it is above the melting point, forming an alloy with the high reflectivity metal in the through-hole or penetrating to the surface of the high reflectivity metal, thereby affecting the reflection effect of the high reflectivity metal.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A through-hole type vertical structure LED chip, characterized in that it comprises:

[0007] Conductive substrate;

[0008] A metal bonding layer, an anti-diffusion structure, a via-reflective structure, a metal reflective layer, a conductive layer, an insulating layer, and an epitaxial stack are disposed on one side of the conductive substrate; wherein, the anti-diffusion structure is used to prevent the metal material of the metal bonding layer from diffusing to the via-reflective structure; the epitaxial stack includes at least a second type semiconductor layer, an active region, and a first type semiconductor layer stacked sequentially along a first direction, and the surface of the epitaxial stack facing the conductive substrate has a groove extending toward the first type semiconductor layer, exposing a portion of the surface of the first type semiconductor layer; the first direction is perpendicular to the conductive substrate and extends from the conductive substrate toward the epitaxial stack;

[0009] The metal reflective layer is disposed on the side surface of the second type semiconductor layer opposite to the active region, and the conductive layer is disposed on the side surface of the metal reflective layer opposite to the second type semiconductor layer;

[0010] The insulating layer is disposed on the side of the epitaxial stack facing the conductive substrate and covers the exposed surfaces of the conductive layer, the metal reflective layer and the epitaxial stack. The insulating layer extends to the sidewall of the groove and exposes the bottom of the groove to form a first through hole. The insulating layer has an opening for external electrical connection by exposing a portion of the surface of the conductive layer.

[0011] The via-hole reflective structure is disposed on a portion of the surface of the insulating layer away from the epitaxial stack, and extends to form contact between the first via and the first type of semiconductor layer; the anti-diffusion structure is disposed on the side of the insulating layer away from the conductive layer, and covers the exposed surface of the via-hole reflective structure;

[0012] The metal bonding layer is stacked on the side surface of the anti-diffusion structure opposite to the epitaxial stack, and forms an electrical connection with the first type semiconductor layer through the anti-diffusion structure and the through-hole reflection structure. The conductive substrate is stacked on the side surface of the metal bonding layer opposite to the epitaxial stack.

[0013] Preferably, the anti-diffusion structure includes an anti-diffusion layer and a dielectric film layer. The anti-diffusion layer covers the exposed surfaces of the via reflective structure and the insulating layer. The dielectric film layer is disposed on a portion of the surface of the anti-diffusion layer facing away from the via reflective structure, and the vertical projection of the dielectric film layer on the plane of the conductive substrate covers the vertical projection of the via reflective structure on the plane of the conductive substrate. The metal bonding layer covers the exposed surface of the dielectric film layer and forms contact with the anti-diffusion layer.

[0014] Preferably, the anti-diffusion layer comprises a gold layer or a metal stack structure containing a gold layer.

[0015] Preferably, the interatomic spacing of the dielectric film material in the spatial structure is smaller than the atomic size of the metal material in the metal bonding layer, and the coefficient of thermal expansion of the dielectric film is in the range of 0.3*10. -6 / ℃ to 14*10 -6 / ℃, including endpoint values.

[0016] Preferably, the number of grooves is M, where M is a positive integer and M is greater than or equal to 1, the number of first through holes is N, and the number of through hole reflective structures is Q, then M = N = Q, and the grooves, first through holes, and through hole reflective structures correspond one-to-one.

[0017] Preferably, the vertical projection of the through-hole reflective structure on the plane of the conductive substrate covers the vertical projection of the groove on the plane of the conductive substrate, and the edge region of the vertical projection of the through-hole reflective structure and the metal reflective layer on the plane of the conductive substrate overlaps.

[0018] Preferably, the vertical projections of the through-hole reflective structure and the metal reflective layer onto the plane of the conductive substrate cover the vertical projection of the active region onto the plane of the conductive substrate.

[0019] Preferably, the through-hole reflective structure includes a first reflector and a first protective layer, wherein the first reflector forms contact with the first type of semiconductor layer through the first through-hole, and the first protective layer covers the exposed surface of the first reflector.

[0020] The present invention also provides a method for manufacturing a through-hole type vertical structure LED chip, characterized in that the method is used to manufacture the through-hole type vertical structure LED chip described in any of the above claims, and the manufacturing method includes the following steps:

[0021] S01, Provide a growth substrate;

[0022] S02, forming an epitaxial stack on one side surface of the growth substrate, the epitaxial stack comprising a first type semiconductor layer, an active region and a second type semiconductor layer stacked sequentially along the growth direction;

[0023] S03. A groove and a light-emitting platform are formed in the epitaxial stack, wherein the groove exposes a portion of the surface of the first type semiconductor layer;

[0024] S04. Deposit an insulating layer, the insulating layer covering the surface of the epitaxial stack, the sidewalls of the groove and its bottom, and pattern the insulating layer to expose a portion of the surface of the light-emitting platform;

[0025] S05. A metal reflective layer is formed on the exposed surface of the light-emitting platform;

[0026] S06. Fabricate a conductive layer that covers the surface of the metal reflective layer and extends to a portion of the surface of the insulating layer;

[0027] S07. Deposit an insulating layer again to cover the exposed surfaces of the conductive layer, the metal reflective layer, and the epitaxial stack, and pattern the insulating layer to expose the bottom of the groove to form a first through-hole;

[0028] S08. Fabricate a through-hole reflective structure, which is disposed on a portion of the surface of the insulating layer and extends to the first through-hole to form contact with the first type of semiconductor layer;

[0029] S09. Fabricate an anti-diffusion structure, wherein the anti-diffusion structure is disposed on the surface of the insulating layer and covers the exposed surface of the through-hole reflective structure;

[0030] S10, vapor-deposited metal bonding layer, wherein the metal bonding layer is stacked on the surface of the anti-diffusion structure;

[0031] S11. The chip structure formed in step S10 is fixed to a conductive substrate by a bonding process, and the conductive substrate is formed on the side surface of the metal bonding layer that is away from the epitaxial stack.

[0032] S12. Peel off the growth substrate to expose the first type of semiconductor layer;

[0033] S13. Etch a portion of the epitaxial stack to expose the insulating layer;

[0034] S14. Deposit a passivation layer, the passivation layer covering the exposed surface of the first type semiconductor layer and extending to the sidewalls of the epitaxial stack and the surface of the insulating layer;

[0035] S15. The passivation layer and the insulating layer are patterned by photolithography and etching to form an opening for external electrical connection by exposing a portion of the surface of the conductive layer.

[0036] The metal bonding forms an electrical connection with the first type of semiconductor layer through the anti-diffusion structure and the through-hole reflection structure;

[0037] The vertical projection of the through-hole reflective structure on the plane of the conductive substrate covers the vertical projection of the groove on the plane of the conductive substrate, and the edge region of the vertical projection of the through-hole reflective structure and the metal reflective layer on the plane of the conductive substrate overlaps.

[0038] The vertical projections of the through-hole reflective structure and the metal reflective layer onto the plane of the conductive substrate cover the vertical projection of the active region onto the plane of the conductive substrate.

[0039] The number of grooves is M, where M is a positive integer and M is greater than or equal to 1. The number of first through holes is N, and the number of through hole reflection structures is Q. Then M = N = Q, and the grooves, first through holes, and through hole reflection structures correspond one-to-one.

[0040] Preferably, the anti-diffusion structure includes an anti-diffusion layer and a dielectric film layer. The anti-diffusion layer covers the exposed surfaces of the via reflective structure and the insulating layer. The dielectric film layer is disposed on a portion of the surface of the anti-diffusion layer facing away from the via reflective structure, and the vertical projection of the dielectric film layer on the plane of the conductive substrate covers the vertical projection of the via reflective structure on the plane of the conductive substrate. The metal bonding layer covers the exposed surface of the dielectric film layer and forms contact with the anti-diffusion layer.

[0041] Preferably, the anti-diffusion layer comprises a gold layer or a metal stack structure containing a gold layer.

[0042] Preferably, the interatomic spacing of the dielectric film material in the spatial structure is smaller than the atomic size of the metal material in the metal bonding layer, and the coefficient of thermal expansion of the dielectric film is in the range of 0.3*10. -6 / ℃ to 14*10 -6 / ℃, including endpoint values.

[0043] Preferably, the through-hole reflective structure includes a first reflector and a first protective layer, wherein the first reflector forms contact with the first type of semiconductor layer through the first through-hole, and the first protective layer covers the exposed surface of the first reflector.

[0044] The above technical solution achieves the following results:

[0045] 1. The present invention provides a through-hole vertical structure LED chip, which comprises a metal bonding layer, an anti-diffusion structure, a through-hole reflective structure, a metal reflective layer, a conductive layer, an insulating layer, and an epitaxial stack on one side of a conductive substrate; wherein, the anti-diffusion structure is used to prevent the metal material of the metal bonding layer from diffusing to the through-hole reflective structure to form an alloy with the through-hole reflective structure or penetrating to the surface of the through-hole reflective structure, thereby affecting the reflection effect of the through-hole reflective structure and the stability of the product, and can be used to improve the light extraction efficiency of the chip and the reliability of the product, thereby improving the brightness and reliability of the through-hole vertical structure LED chip.

[0046] 2. Furthermore, by setting an anti-diffusion structure including an anti-diffusion layer and a dielectric film layer, the anti-diffusion layer covers the exposed surfaces of the via-hole reflective structure and the insulating layer, and the dielectric film layer is set on a portion of the surface of the anti-diffusion layer facing away from the via-hole reflective structure. The anti-diffusion layer prevents the metal material of the metal bonding layer from diffusing into the via-hole reflective structure and affecting the reflection effect, and also plays a role in expanding the current of the first type semiconductor layer. The vertical projection of the dielectric film layer on the plane of the conductive substrate covers the vertical projection of the via-hole reflective structure on the plane of the conductive substrate, which can further block the diffusion of metal material, improve the light extraction efficiency of the chip and the reliability of the product.

[0047] 3. Furthermore, by setting an anti-diffusion layer including a gold layer or a metal stack structure containing a gold layer, gold can react with the metal material diffused from the metal bonding layer to form an alloy, thereby achieving a blocking effect.

[0048] 4. Furthermore, by setting the atomic spacing of the dielectric film material in the spatial structure to be smaller than the atomic size of the metal material in the metal bonding layer, and the thermal expansion coefficient of the dielectric film layer being in the range of 0.3*10 -6 / ℃ to 14*10 -6 At / ℃, when the dielectric film material is heated during the bonding process, the spacing between atoms does not easily change, making it difficult for metal atoms to pass through. This acts as a barrier, further preventing the metal material of the metal bonding layer from diffusing into the through-hole reflection structure, thereby improving the light extraction efficiency of the chip and the reliability of the product.

[0049] 5. Further, by setting the number of grooves to M, where M is a positive integer and M is greater than or equal to 1, the number of first through holes to N, and the number of through hole reflection structures to Q, then M = N = Q. The number of grooves is not limited and can be set according to actual needs. A first through hole is set in each groove, and a through hole reflection structure is set in each first through hole, so that the grooves, first through holes, and through hole reflection structures correspond one-to-one.

[0050] 6. Furthermore, the vertical projection of the through-hole reflection structure onto the plane of the conductive substrate covers the vertical projection of the groove onto the plane of the conductive substrate, and the edge area of ​​the through-hole reflection structure and the vertical projection of the metal reflective layer onto the plane of the conductive substrate overlaps, ensuring that the light emitted from the active area can be reflected by the through-hole reflection structure at the through-hole and finally emitted from the light-emitting side, thereby further improving the light extraction efficiency of the chip.

[0051] 7. Furthermore, by setting the vertical projection of the via reflection structure and the metal reflection layer on the plane of the conductive substrate to cover the vertical projection of the active area on the plane of the conductive substrate, it is ensured that the light emitted by the active area can be reflected by the via reflection structure and the metal reflection layer, thereby further improving the light extraction efficiency of the chip.

[0052] 8. Furthermore, by setting a through-hole reflection structure including a first reflector and a first protective layer, the first reflector forms contact with the first type semiconductor layer through the first through-hole, and the first protective layer covers the exposed surface of the first reflector. The first protective layer can further prevent the metal material of the metal bonding layer from diffusing into the through-hole to form an alloy with the first reflector, or from penetrating into the surface of the first reflector, thus affecting the reflection effect of the through-hole reflection structure.

[0053] 9. The method for manufacturing a through-hole type vertical structure LED chip provided by the present invention achieves the beneficial effects of the above-mentioned LED chip while being simple, convenient and easy to mass-produce. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0055] Figure 1 SEM image of a through-hole vertical structure LED chip in the prior art after using silver as a high reflectivity metal and tin as a metal bonding layer;

[0056] Figure 2 FIB image of a through-hole vertical structure LED chip in the prior art after using silver as a high reflectivity metal and tin as a metal bonding layer;

[0057] Figures 3 to 4 This is a schematic diagram of a through-hole type vertical structure LED chip provided in an embodiment of the present invention;

[0058] Figure 5This is a SEM image of a through-hole type vertical structure LED chip provided in an embodiment of the present invention, after using silver as the first reflector and tin as the metal bonding layer;

[0059] Figures 6 to 7 This is a schematic diagram of another through-hole type vertical structure LED chip provided in an embodiment of the present invention;

[0060] Figures 8 to 22 This is a schematic diagram showing the structural steps of a method for fabricating a through-hole type vertical structure LED chip according to an embodiment of the present invention.

[0061] Explanation of symbols in the diagram:

[0062] 01. Growth substrate; A. First through-hole; B. Second through-hole;

[0063] 1. Conductive substrate; 2. Epitaxial stack; 21. Type I semiconductor layer; 22. Active region; 23. Type II semiconductor layer; 24. Groove; 25. Light-emitting mesa; 3. Insulating layer; 4. Metal reflective layer; 41. Second reflector; 42. Second protective layer; 5. Conductive layer; 6. Through-hole reflective structure; 61. First reflector; 62. First protective layer; 7. Anti-diffusion structure; 71. Anti-diffusion layer; 72. Dielectric film layer; 8. Metal bonding layer; 81. Adhesion layer; 82. Metal barrier layer; 9. Passivation layer. Detailed Implementation

[0064] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0065] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0066] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0067] As described in the background section, filling the vias of a through-hole vertical structure LED chip with a high-reflectivity metal allows light generated in the active region to be well reflected at the via, thereby improving the chip's light extraction efficiency and thus enhancing the brightness of the through-hole vertical structure LED chip. However, during the bonding process, the metal in the metal bonding layer is prone to migration above its melting point. Under high temperature and pressure, it can overcome the barrier layer and diffuse into the via, forming an alloy with the high-reflectivity metal inside the via or penetrating to the surface of the high-reflectivity metal (such as the interface between the high-reflectivity metal and the first-type semiconductor layer), thus affecting the reflection effect of the high-reflectivity metal inside the via.

[0068] The inventors discovered that when the high reflectivity metal of a through-hole vertical structure LED chip is gold, and the metal bonding layer includes tin, the tin diffuses into the through-hole and forms a gold-tin alloy with the gold, thereby reducing the reflectivity of the gold. When the high reflectivity metal is silver or aluminum, and the metal bonding layer includes indium, the indium diffuses into the through-hole and penetrates the surface of the silver or aluminum. Since the reflectivity of indium is relatively low, it also affects the reflectivity of the silver or aluminum.

[0069] For existing through-hole vertical structure LED chips, when using silver as the high-reflectivity metal and tin as the metal bonding layer, please refer to the following: Figure 1 The SEM (Scanning Electron Microscopy) images shown are as follows: Figure 2 The FIB (Focused Ion Beam) image shown is as follows: Figure 1 The SEM image shown was observed using a scanning electron microscope. When light from the microscope shines on the LED chip surface (i.e., the light-emitting surface), the bright and dark areas of the LED chip surface can be seen. The area outside the circle is the active light-emitting region, which is brighter; the circle represents the reflective area corresponding to the high-reflectivity metal inside the via, which is significantly darker. This is because tin diffuses into the via and forms a silver-tin alloy with silver, reducing the reflectivity of silver and causing the emitted light to be absorbed and not reflected. Figure 2 The FIB image shown, with the red box indicating the presence of tin metal at the interface between the highly reflective silver metal and the first-type semiconductor layer, demonstrates that tin has diffused to this interface. This not only reduces the reflectivity of the LED chip's reflective layer, affecting the chip's light extraction efficiency, but the bonding metal may also diffuse to the periphery of the chip, impacting the LED's reliability and stability.

[0070] In view of this, embodiments of this application provide a through-hole type vertical structure LED chip, such as... Figures 3 to 4 As shown, it includes:

[0071] Conductive substrate 1;

[0072] The conductive substrate 1 is provided with a metal bonding layer 8, an anti-diffusion structure 7, a via reflective structure 6, a metal reflective layer 4, a conductive layer 5, an insulating layer 3, and an epitaxial stack 2. The anti-diffusion structure 7 is used to prevent the metal material of the metal bonding layer 8 from diffusing to the via reflective structure 6. The epitaxial stack 2 includes at least a second type semiconductor layer 23, an active region 22, and a first type semiconductor layer 21 stacked sequentially along a first direction. The surface of the epitaxial stack 2 facing the conductive substrate 1 is provided with a groove 24 extending toward the first type semiconductor layer 21, exposing a portion of the surface of the first type semiconductor layer 21. The first direction is perpendicular to the conductive substrate 1 and points from the conductive substrate 1 toward the epitaxial stack 2.

[0073] The metal reflective layer 4 is disposed on the side surface of the second type semiconductor layer 23 away from the active region 22, and the conductive layer 5 is disposed on the side surface of the metal reflective layer 4 away from the second type semiconductor layer 23.

[0074] An insulating layer 3 is disposed on the side of the epitaxial stack 2 facing the conductive substrate 1, and covers the conductive layer 5, the metal reflective layer 4 and the exposed surface of the epitaxial stack 2. The insulating layer 3 extends to the sidewall of the groove 24 and exposes the bottom of the groove 24 to form a first through hole A. The insulating layer 3 has an opening for external electrical connection through a portion of the exposed surface of the conductive layer 5.

[0075] The through-hole reflection structure 6 is disposed on a portion of the surface of the insulating layer 3 away from the epitaxial stack 2, and extends to the first through-hole A to form contact with the first type semiconductor layer 21; the anti-diffusion structure 7 is disposed on the side of the insulating layer 3 away from the conductive layer 5, and covers the exposed surface of the through-hole reflection structure 6.

[0076] The metal bonding layer 8 is stacked on the side surface of the anti-diffusion structure 7 away from the epitaxial stack 2, and forms an electrical connection with the first type semiconductor layer 21 through the anti-diffusion structure 7 and the through-hole reflection structure 6. The conductive substrate 1 is stacked on the side surface of the metal bonding layer 8 away from the epitaxial stack 2.

[0077] It should be noted that in this embodiment, the through-hole reflective structure 6 is insulated from the conductive layer 5, the metal reflective layer 4, the second type semiconductor layer 23 and the active region 22 through the insulating layer 3, and the anti-diffusion structure 7 is insulated from the conductive layer 5 through the insulating layer 3; and in this embodiment, the conductive layer 5 can provide current expansion for the second type semiconductor layer 23.

[0078] It should also be noted that in this embodiment, the side of the first type semiconductor layer 21 facing away from the active region 22 is the light-emitting side, the metal reflective layer 4 is used to reflect the light emitted from the active region 22, and the through-hole reflective structure 6 ensures that the light emitted from the active region 22 can be reflected by the through-hole reflective structure 6 at the through-hole A. See the detailed reference below. Figure 3As shown in the figure, the dashed lines and arrows represent the light emitted from the active region 22 that illuminates the surface of the through-hole reflective structure 6 and is reflected by the through-hole reflective structure 6, and is finally emitted from the light-emitting side.

[0079] Optionally, in this embodiment, the anti-diffusion structure 7 includes an anti-diffusion layer 71 and a dielectric film layer 72. The anti-diffusion layer 71 covers the exposed surfaces of the through-hole reflective structure 6 and the insulating layer 3. The dielectric film layer 72 is disposed on a portion of the surface of the anti-diffusion layer 71 facing away from the through-hole reflective structure 6, and the vertical projection of the dielectric film layer 72 on the plane of the conductive substrate 1 covers the vertical projection of the through-hole reflective structure 6 on the plane of the conductive substrate 1. The metal bonding layer 8 covers the exposed surface of the dielectric film layer 72 and forms contact with the anti-diffusion layer 71.

[0080] Optionally, in this embodiment, the anti-diffusion layer 71 includes a gold layer or a metal stack structure containing a gold layer.

[0081] Optionally, in this embodiment, the anti-diffusion layer 71 includes a gold layer or a gold layer stacked with one or more of a nickel layer, a titanium layer, a platinum layer, and a chromium layer.

[0082] Optionally, in this embodiment, the total thickness of the gold layer in the anti-diffusion layer 71 ranges from 0A to 10000A, excluding endpoint values.

[0083] Optionally, in this embodiment, the interatomic spacing of the dielectric film layer 72 in the spatial structure is smaller than the atomic size of the metal material in the metal bonding layer 8, and the coefficient of thermal expansion of the dielectric film layer 72 is in the range of 0.3*10. -6 / ℃ to 14*10 -6 / ℃, including endpoint values.

[0084] It should be noted that, in this embodiment, the coefficient of thermal expansion refers to the magnitude of deformation of the material when it is heated. The smaller the coefficient, the less likely the material is to deform, and the larger the coefficient, the more likely the material is to deform.

[0085] Optionally, in this embodiment, the thickness of the dielectric film layer 72 ranges from 1000 Å to 5000 Å, excluding the endpoint values.

[0086] Optionally, in this embodiment, the dielectric film layer 72 includes, but is not limited to, one or more of silicon dioxide, silicon nitride, aluminum oxide, magnesium fluoride, and titanium dioxide, which are stacked alternately, and the number of alternating stacks is 1-5 groups.

[0087] Optionally, in this embodiment, the vertical projection of the through-hole reflective structure 6 on the plane of the conductive substrate 1 covers the vertical projection of the groove 24 on the plane of the conductive substrate 1, and the edge region of the vertical projection of the through-hole reflective structure 6 and the metal reflective layer 4 on the plane of the conductive substrate 1 overlaps.

[0088] Optionally, in this embodiment, the vertical projection of the through-hole reflective structure 6 and the metal reflective layer 4 onto the plane of the conductive substrate 1 covers the vertical projection of the active region 22 onto the plane of the conductive substrate 1.

[0089] Optionally, in this embodiment, the through-hole reflection structure 6 includes a first reflector 61 and a first protective layer 62. The first reflector 61 forms contact with the first type semiconductor layer 21 through the first through-hole A, and the first protective layer 62 covers the exposed surface of the first reflector 61.

[0090] Optionally, in this embodiment, the first reflector 61 is made of a highly reflective metal material, including but not limited to one or more of gold, silver, aluminum, and magnesium.

[0091] Optionally, in this embodiment, the first protective layer 62 includes, but is not limited to, one or more stacks of nickel, titanium, titanium-tungsten alloy, platinum, and chromium.

[0092] Optionally, in this embodiment, the metal bonding layer 8 includes, but is not limited to, one or more alloys of nickel, tin, gold, and indium.

[0093] Optionally, in one specific embodiment of this application, the first reflector 61 is silver, the metal bonding layer 8 is tin, the anti-diffusion layer 71 is a gold layer, and the dielectric film layer 72 is silicon dioxide. Specifically, as shown below... Figure 5 The SEM image shown was observed using a scanning electron microscope. Light emitted from the microscope hits the LED chip surface. The area outside the circle is the light-emitting region 22, and the area inside the circle is the reflection region corresponding to the through-hole reflection structure 6. Both areas show a bright effect, indicating that the tin is blocked by the anti-diffusion structure 7 during bonding and does not diffuse to the through-hole reflection structure 6, thus not affecting the reflection effect. During bonding, the tin diffuses when it reaches its melting point (tin melting point is 232℃, bonding temperature range is 230-300℃). When it diffuses to the dielectric film layer 72, the tin is blocked by silicon dioxide. The coefficient of thermal expansion of silicon dioxide is 0.5*10. -6 / ℃, when heated, the spacing between atoms of silicon dioxide does not easily change, and tin atoms do not easily pass through (the radius of tin atom is 1.41 Å, and the interatomic spacing of silicon dioxide is approximately 1.6-2.79 Å). When tin diffuses to the anti-diffusion layer 71, it will form a gold-tin alloy with the gold layer, so that the anti-diffusion structure 7 can block tin atoms from diffusing to the through-hole reflective structure 6.

[0094] Optionally, in this embodiment, the metal reflective layer 4 includes a second reflector 41 and a second protective layer 42. The second reflector 41 is disposed on the side surface of the second type semiconductor layer 23 facing away from the active region 22, and the second protective layer 42 covers the exposed surface of the second reflector 41.

[0095] Optionally, in this embodiment, the second reflector 41 is made of a highly reflective metal material, including but not limited to one or more of gold, silver, aluminum, and magnesium.

[0096] Optionally, in this embodiment, the second protective layer 42 includes, but is not limited to, one or more stacks of nickel, titanium, titanium-tungsten alloy, platinum, and chromium.

[0097] It should be noted that in this embodiment, the specific materials of the metal reflective layer 4 and the through-hole reflective structure 6 are not limited. The materials used to prepare the metal reflective layer 4 and the through-hole reflective structure 6 can be the same or different, and can be set according to actual needs.

[0098] Optionally, in this embodiment, the metal bonding layer 8 and the anti-diffusion structure 7 are further provided with a stacked adhesive layer 81 and a metal barrier layer 82, with the adhesive layer 81 in contact with the anti-diffusion structure 7 and the metal barrier layer 82 in contact with the metal bonding layer 8.

[0099] Optionally, in this embodiment, the adhesive layer 81 includes, but is not limited to, one or more of nickel, titanium, platinum, and chromium.

[0100] Optionally, in this embodiment, the metal barrier layer 82 includes a gold layer or a metal stack structure containing a gold layer.

[0101] Optionally, in this embodiment, the metal barrier layer 82 includes a gold layer or a gold layer stacked with one or more of a nickel layer, a titanium layer, a platinum layer, and a chromium layer.

[0102] It should be noted that in this embodiment, the specific materials of the metal barrier layer 82 and the anti-diffusion layer 71 are not limited. The materials used to prepare the metal barrier layer 82 and the anti-diffusion layer 71 can be the same or different, and can be set according to actual needs.

[0103] Optionally, in this embodiment, the insulating layer 3 is used for current blocking and insulation protection. The insulating layer 3 includes, but is not limited to, one or more of silicon dioxide, aluminum oxide, silicon nitride, magnesium fluoride, zirconium dioxide, titanium dioxide, gallium trioxide, and tin dioxide.

[0104] Optionally, this embodiment also includes a passivation layer 9, which covers the exposed surface of the first type semiconductor layer 21 and extends to the sidewall of the epitaxial stack 2.

[0105] It should be noted that in this embodiment, the specific doping type of the first type semiconductor layer 21 and the second type semiconductor layer 23 is not limited. The doping type of the first type semiconductor layer 21 is opposite to that of the second type semiconductor layer 23. The first type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0106] Optionally, in another embodiment of this application, the number of grooves 24 is M, where M is a positive integer and M is greater than or equal to 1, the number of first through holes A is N, and the number of through hole reflective structures 6 is Q. Then M = N = Q, and the grooves 24, the first through holes A, and the through hole reflective structures 6 correspond one-to-one.

[0107] Specifically, in one embodiment of this application, such as Figures 6 to 7 As shown, the epitaxial stack 2 has a plurality of grooves 24 extending toward the first type semiconductor layer 21 on the side surface facing the conductive substrate 1, and exposes a portion of the surface of the first type semiconductor layer 21; the insulating layer 3 is disposed on the side of the epitaxial stack 2 facing the conductive substrate 1, and covers the conductive layer 5, the metal reflective layer 4 and the exposed surface of the epitaxial stack 2, and the insulating layer 3 extends to the sidewall of each groove 24 to form a plurality of first through holes A; the through hole reflection structure 6 is disposed on a portion of the surface of the insulating layer 3 away from the epitaxial stack 2, and extends to each first through hole A to form contact with the first type semiconductor layer 21; the anti-diffusion structure 7 is disposed on the side of the insulating layer 3 away from the conductive layer 5, and covers the exposed surface of each through hole reflection structure 6.

[0108] Optionally, in this embodiment, the dielectric film layer 72 includes a second through hole B, the number of second through holes B is E, E is a positive integer, and E is greater than or equal to 2, and the metal bonding layer 8 forms contact with the anti-diffusion layer 71 through each of the second through holes B.

[0109] This invention also provides a method for fabricating a through-hole type vertical structure LED chip, used to fabricate any of the above-mentioned through-hole type vertical structure LED chips. The fabrication method includes the following steps:

[0110] S01, such as Figure 8 As shown, a growth substrate 01 is provided;

[0111] S02, such as Figure 9 As shown, an epitaxial stack 2 is formed on one side surface of the growth substrate 01. The epitaxial stack 2 includes a first type semiconductor layer 21, an active region 22 and a second type semiconductor layer 23 stacked sequentially along the growth direction.

[0112] S03, such as Figure 10 As shown, a groove 24 and a light-emitting mesa 25 are formed in the epitaxial stack 2, and the groove 24 exposes a portion of the surface of the first type semiconductor layer 21;

[0113] S04, such as Figure 11 As shown, an insulating layer 3 is deposited, which covers the surface of the epitaxial stack 2, the sidewalls of the groove 24 and its bottom, and the insulating layer 3 is patterned to expose part of the surface of the light-emitting platform 25.

[0114] S05, such as Figure 12 As shown, a metal reflective layer 4 is formed on the exposed surface of the light-emitting platform 25;

[0115] S06, such as Figure 13 As shown, a conductive layer 5 is fabricated, which covers the surface of the metal reflective layer 4 and extends to a portion of the surface of the insulating layer 3;

[0116] S07, such as Figure 14 As shown, an insulating layer 3 is deposited again to cover the exposed surfaces of the conductive layer 5, the metal reflective layer 4, and the epitaxial stack 2, and the insulating layer 3 is patterned to form a first through hole A at the bottom of the exposed groove 24;

[0117] S08, such as Figure 15 As shown, a through-hole reflective structure 6 is fabricated, which is disposed on a portion of the surface of the insulating layer 3 and extends to the first through-hole A to form contact with the first type semiconductor layer 21;

[0118] S09, such as Figure 16 As shown, an anti-diffusion structure 7 is fabricated. The anti-diffusion structure 7 is disposed on the surface of the insulating layer 3 and covers the exposed surface of the through-hole reflective structure 6.

[0119] S10, such as Figure 17 As shown, a vapor-deposited metal bonding layer 8 is stacked on the surface of the anti-diffusion structure 7.

[0120] S11, such as Figure 18 As shown, the chip structure formed in step S10 is fixed to the conductive substrate 1 by bonding process, and the conductive substrate 1 is formed on the side surface of the metal bonding layer 8 away from the epitaxial stack 2.

[0121] S12, such as Figure 19 As shown, the growth substrate 01 is peeled off to expose the first type semiconductor layer 21;

[0122] S13, such as Figure 20 As shown, the etched portion of the epitaxial stack 2 exposes the insulating layer 3.

[0123] S14, such as Figure 21 As shown, a passivation layer 9 is deposited, which covers the exposed surface of the first type semiconductor layer 21 and extends to the sidewalls of the epitaxial stack 2 and the surface of the insulating layer 3.

[0124] S15, such as Figure 22 As shown, the passivation layer 9 and the insulating layer 3 are patterned by photolithography and etching to form an opening for external electrical connection through a portion of the surface of the exposed conductive layer 5;

[0125] The anti-diffusion structure 7 is used to prevent the metal material of the metal bonding layer 8 from diffusing into the through-hole reflective structure 6;

[0126] The metal bonding layer 8 is electrically connected to the first type semiconductor layer 21 through the anti-diffusion structure 7 and the through-hole reflection structure 6.

[0127] It should be noted that in this embodiment, the through-hole reflective structure 6 is insulated from the conductive layer 5, the metal reflective layer 4, the second type semiconductor layer 23 and the active region 22 through the insulating layer 3, and the anti-diffusion structure 7 is insulated from the conductive layer 5 through the insulating layer 3; and in this embodiment, the conductive layer 5 can provide current expansion for the second type semiconductor layer 23.

[0128] It should also be noted that in this embodiment, the side of the first type semiconductor layer 21 facing away from the active region 22 is the light-emitting side, the metal reflective layer 4 is used to reflect the light emitted from the active region 22, and the through-hole reflective structure 6 ensures that the light emitted from the active region 22 can be reflected by the through-hole reflective structure 6 at the through-hole A. For details, please refer to... Figure 22 As shown in the figure, the dashed lines and arrows represent the light emitted from the active region 22 that illuminates the surface of the through-hole reflective structure 6 and is reflected by the through-hole reflective structure 6, and is finally emitted from the light-emitting side.

[0129] Optionally, in this embodiment, in step S03, forming the groove 24 specifically includes: copying the through hole on the photomask onto the photoresist through a spin coating, exposure, and development process, and then transferring the pattern onto the epitaxial stack 2 through dry etching.

[0130] Optionally, in this embodiment, in step S03, the groove 24 is formed by ICP, and the etching gas is CL2 and BCL3.

[0131] Optionally, in this embodiment, in step S05, forming the metal reflective layer 4 specifically includes:

[0132] First, the insulating layer 3 is patterned by uniform negative resist application, exposure and development processes, followed by wet etching or dry etching.

[0133] Alternatively, the insulating layer 3 can be patterned by first applying a uniform negative resist, followed by exposure and development processes, and then using BOE etching solution or ICP etching.

[0134] Without removing the resist from the epitaxial wafer, a metal reflective layer 4 is prepared by vapor deposition or sputtering.

[0135] Optionally, in this embodiment, in step S08, a through-hole reflective structure 6 is formed by photolithography and vapor deposition.

[0136] Optionally, in this embodiment, in step S10, the growth substrate 01 is peeled off by laser stripping or chemical etching.

[0137] Optionally, in this embodiment, the anti-diffusion structure 7 includes an anti-diffusion layer 71 and a dielectric film layer 72. The anti-diffusion layer 71 covers the exposed surfaces of the through-hole reflective structure 6 and the insulating layer 3. The dielectric film layer 72 is disposed on a portion of the surface of the anti-diffusion layer 71 facing away from the through-hole reflective structure 6, and the vertical projection of the dielectric film layer 72 on the plane of the conductive substrate 1 covers the vertical projection of the through-hole reflective structure 6 on the plane of the conductive substrate 1. The metal bonding layer 8 covers the exposed surface of the dielectric film layer 72 and forms contact with the anti-diffusion layer 71.

[0138] Optionally, in this embodiment, the anti-diffusion layer 71 includes a gold layer or a metal stack structure containing a gold layer.

[0139] Optionally, in this embodiment, the anti-diffusion layer 71 includes a gold layer or a gold layer stacked with one or more of a nickel layer, a titanium layer, a platinum layer, and a chromium layer.

[0140] Optionally, in this embodiment, the total thickness of the gold layer in the anti-diffusion layer 71 ranges from 0A to 10000A, excluding endpoint values.

[0141] Optionally, in this embodiment, the interatomic spacing of the dielectric film layer 72 in the spatial structure is smaller than the atomic size of the metal material in the metal bonding layer 8, and the coefficient of thermal expansion of the dielectric film layer 72 is in the range of 0.3*10. -6 / ℃ to 14*10 -6 / ℃, including endpoint values.

[0142] It should be noted that, in this embodiment, the coefficient of thermal expansion refers to the magnitude of deformation of the material when it is heated. The smaller the coefficient, the less likely the material is to deform, and the larger the coefficient, the more likely the material is to deform.

[0143] Optionally, in this embodiment, the thickness of the dielectric film layer 72 ranges from 1000 Å to 5000 Å, excluding the endpoint values.

[0144] Optionally, in this embodiment, the dielectric film layer 72 includes, but is not limited to, one or more of silicon dioxide, silicon nitride, aluminum oxide, magnesium fluoride, and titanium dioxide, which are stacked alternately, and the number of alternating stacks is 1-5 groups.

[0145] Optionally, in this embodiment, the vertical projection of the through-hole reflective structure 6 on the plane of the conductive substrate 1 covers the vertical projection of the groove 24 on the plane of the conductive substrate 1, and the edge region of the vertical projection of the through-hole reflective structure 6 and the metal reflective layer 4 on the plane of the conductive substrate 1 overlaps.

[0146] Optionally, in this embodiment, the vertical projection of the through-hole reflective structure 6 and the metal reflective layer 4 onto the plane of the conductive substrate 1 covers the vertical projection of the active region 22 onto the plane of the conductive substrate 1.

[0147] Optionally, in this embodiment, the through-hole reflection structure 6 includes a first reflector 61 and a first protective layer 62. The first reflector 61 forms contact with the first type semiconductor layer 21 through the first through-hole A, and the first protective layer 62 covers the exposed surface of the first reflector 61.

[0148] Optionally, in this embodiment, the first reflector 61 is made of a highly reflective metal material, including but not limited to one or more of gold, silver, aluminum, and magnesium.

[0149] Optionally, in this embodiment, the first protective layer 62 includes, but is not limited to, one or more stacks of nickel, titanium, titanium-tungsten alloy, platinum, and chromium.

[0150] Optionally, in this embodiment, the metal bonding layer 8 includes, but is not limited to, one or more alloys of nickel, tin, gold, and indium.

[0151] Optionally, in one specific embodiment of this application, the first reflector 61 is silver, the metal bonding layer 8 is tin, the anti-diffusion layer 71 is a gold layer, and the dielectric film layer 72 is silicon dioxide. Specifically, as shown below... Figure 5 The SEM image shown was observed using a scanning electron microscope. Light emitted from the microscope hits the LED chip surface. The area outside the circle is the light-emitting region 22, and the area inside the circle is the reflection region corresponding to the through-hole reflection structure 6. Both areas show a bright effect, indicating that the tin is blocked by the anti-diffusion structure 7 during bonding and does not diffuse to the through-hole reflection structure 6, thus not affecting the reflection effect. During bonding, the tin diffuses when it reaches its melting point (tin melting point is 232℃, bonding temperature range is 230-300℃). When it diffuses to the dielectric film layer 72, the tin is blocked by silicon dioxide. The coefficient of thermal expansion of silicon dioxide is 0.5*10. -6 / ℃, when heated, the spacing between atoms of silicon dioxide does not easily change, and tin atoms do not easily pass through (the radius of tin atom is 1.41 Å, and the interatomic spacing of silicon dioxide is approximately 1.6-2.79 Å). When tin diffuses to the anti-diffusion layer 71, it will form a gold-tin alloy with the gold layer, so that the anti-diffusion structure 7 can block tin atoms from diffusing to the through-hole reflective structure 6.

[0152] Optionally, in this embodiment, the metal reflective layer 4 includes a second reflector 41 and a second protective layer 42. The second reflector 41 is disposed on the side surface of the second type semiconductor layer 23 facing away from the active region 22, and the second protective layer 42 covers the exposed surface of the second reflector 41.

[0153] Optionally, in this embodiment, the second reflector 41 is made of a highly reflective metal material, including but not limited to one or more of gold, silver, aluminum, and magnesium.

[0154] Optionally, in this embodiment, the second protective layer 42 includes, but is not limited to, one or more stacks of nickel, titanium, titanium-tungsten alloy, platinum, and chromium.

[0155] It should be noted that in this embodiment, the specific materials of the metal reflective layer 4 and the through-hole reflective structure 6 are not limited. The materials used to prepare the metal reflective layer 4 and the through-hole reflective structure 6 can be the same or different, and can be set according to actual needs.

[0156] Optionally, in this embodiment, the metal bonding layer 8 and the anti-diffusion structure 7 are further provided with a stacked adhesive layer 81 and a metal barrier layer 82, with the adhesive layer 81 in contact with the anti-diffusion structure 7 and the metal barrier layer 82 in contact with the metal bonding layer 8.

[0157] Optionally, in this embodiment, the adhesive layer 81 includes, but is not limited to, one or more of nickel, titanium, platinum, and chromium.

[0158] Optionally, in this embodiment, the metal barrier layer 82 includes a gold layer or a metal stack structure containing a gold layer.

[0159] Optionally, in this embodiment, the metal barrier layer 82 includes a gold layer or a gold layer stacked with one or more of a nickel layer, a titanium layer, a platinum layer, and a chromium layer.

[0160] It should be noted that in this embodiment, the specific materials of the metal barrier layer 82 and the anti-diffusion layer 71 are not limited. The materials used to prepare the metal barrier layer 82 and the anti-diffusion layer 71 can be the same or different, and can be set according to actual needs.

[0161] Optionally, in this embodiment, the insulating layer 3 is used for current blocking and insulation protection. The insulating layer 3 includes, but is not limited to, one or more of silicon dioxide, aluminum oxide, silicon nitride, magnesium fluoride, zirconium dioxide, titanium dioxide, gallium trioxide, and tin dioxide.

[0162] It should be noted that in this embodiment, the specific doping type of the first type semiconductor layer 21 and the second type semiconductor layer 23 is not limited. The doping type of the first type semiconductor layer 21 is opposite to that of the second type semiconductor layer 23. The first type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer. The materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN.

[0163] Optionally, in another embodiment of this application, the number of grooves 24 is M, where M is a positive integer and M is greater than or equal to 1, the number of first through holes A is N, and the number of through hole reflective structures 6 is Q. Then M = N = Q, and the grooves 24, the first through holes A, and the through hole reflective structures 6 correspond one-to-one.

[0164] Specifically, in one embodiment of this application, reference is made to... Figures 6 to 7As shown, the epitaxial stack 2 has a plurality of grooves 24 extending toward the first type semiconductor layer 21 on the side surface facing the conductive substrate 1, and exposes a portion of the surface of the first type semiconductor layer 21; the insulating layer 3 is disposed on the side of the epitaxial stack 2 facing the conductive substrate 1, and covers the conductive layer 5, the metal reflective layer 4 and the exposed surface of the epitaxial stack 2, and the insulating layer 3 extends to the sidewall of each groove 24 to form a plurality of first through holes A; the through hole reflection structure 6 is disposed on a portion of the surface of the insulating layer 3 away from the epitaxial stack 2, and extends to each first through hole A to form contact with the first type semiconductor layer 21; the anti-diffusion structure 7 is disposed on the side of the insulating layer 3 away from the conductive layer 5, and covers the exposed surface of each through hole reflection structure 6.

[0165] Optionally, in this embodiment, the dielectric film layer 72 includes a second through hole B, the number of second through holes B is E, E is a positive integer, and E is greater than or equal to 2, and the metal bonding layer 8 forms contact with the anti-diffusion layer 71 through each of the second through holes B.

[0166] In summary, the above technical solution achieves the following results:

[0167] 1. The through-hole vertical structure LED chip provided in this embodiment comprises a metal bonding layer, an anti-diffusion structure, a through-hole reflective structure, a metal reflective layer, a conductive layer, an insulating layer, and an epitaxial stack on one side of a conductive substrate. The anti-diffusion structure is used to prevent the metal material of the metal bonding layer from diffusing to the through-hole reflective structure to form an alloy or to penetrate to the surface of the through-hole reflective structure, thereby affecting the reflection effect of the through-hole reflective structure and the stability of the product. This can be used to improve the light extraction efficiency of the chip and the reliability of the product, thereby improving the brightness and reliability of the through-hole vertical structure LED chip.

[0168] 2. Furthermore, by setting an anti-diffusion structure including an anti-diffusion layer and a dielectric film layer, the anti-diffusion layer covers the exposed surfaces of the via-hole reflective structure and the insulating layer, and the dielectric film layer is set on a portion of the surface of the anti-diffusion layer facing away from the via-hole reflective structure. The anti-diffusion layer prevents the metal material of the metal bonding layer from diffusing into the via-hole reflective structure and affecting the reflection effect, and also plays a role in expanding the current of the first type semiconductor layer. The vertical projection of the dielectric film layer on the plane of the conductive substrate covers the vertical projection of the via-hole reflective structure on the plane of the conductive substrate, which can further block the diffusion of metal material, improve the light extraction efficiency of the chip and the reliability of the product.

[0169] 3. Furthermore, by setting an anti-diffusion layer including a gold layer or a metal stack structure containing a gold layer, gold can react with the metal material diffused from the metal bonding layer to form an alloy, thereby achieving a blocking effect.

[0170] 4. Furthermore, by setting the atomic spacing of the dielectric film material in the spatial structure to be smaller than the atomic size of the metal material in the metal bonding layer, and the thermal expansion coefficient of the dielectric film layer being in the range of 0.3*10 -6 / ℃ to 14*10 -6 At / ℃, when the dielectric film material is heated during the bonding process, the spacing between atoms does not easily change, making it difficult for metal atoms to pass through. This acts as a barrier, further preventing the metal material of the metal bonding layer from diffusing into the through-hole reflection structure, thereby improving the light extraction efficiency of the chip and the reliability of the product.

[0171] 5. Further, by setting the number of grooves to M, where M is a positive integer and M is greater than or equal to 1, the number of first through holes to N, and the number of through hole reflection structures to Q, then M = N = Q. The number of grooves is not limited and can be set according to actual needs. A first through hole is set in each groove, and a through hole reflection structure is set in each first through hole, so that the grooves, first through holes, and through hole reflection structures correspond one-to-one.

[0172] 6. Further, by setting the dielectric film layer including second through holes, the number of second through holes is E, where E is a positive integer and E is greater than or equal to 2. The metal bonding layer forms contact with the anti-diffusion layer through each second through hole. The dielectric film layer can be provided with multiple second through holes. In addition to making the bonding surfaces equal in height when forming the metal bonding layer, avoiding bonding voids when the chip is bonded to the conductive substrate, which can lead to stress mismatch, heat accumulation and uneven current distribution, especially when there are multiple through hole reflection structures, the multiple second through holes of the dielectric film layer combined with the anti-diffusion layer form a dot matrix injection and current expansion to inject current into each through hole reflection structure and diffuse it to the light-emitting area, avoiding current congestion and allowing the current to be evenly distributed, thereby enabling the through hole type vertical structure LED chip to emit light evenly.

[0173] 7. Furthermore, the vertical projection of the through-hole reflection structure onto the plane of the conductive substrate covers the vertical projection of the groove onto the plane of the conductive substrate, and the edge area of ​​the through-hole reflection structure and the vertical projection of the metal reflective layer onto the plane of the conductive substrate overlaps, ensuring that the light emitted from the active area can be reflected by the through-hole reflection structure at the through-hole and finally emitted from the light-emitting side, thereby further improving the light extraction efficiency of the chip.

[0174] 8. Furthermore, by setting the vertical projection of the via reflection structure and the metal reflection layer on the plane of the conductive substrate to cover the vertical projection of the active area on the plane of the conductive substrate, it is ensured that the light emitted by the active area can be reflected by the via reflection structure and the metal reflection layer, thereby further improving the light extraction efficiency of the chip.

[0175] 9. Further, by setting a through-hole reflection structure including a first reflector and a first protective layer, the first reflector forms contact with the first type semiconductor layer through the first through-hole, and the first protective layer covers the exposed surface of the first reflector. The first protective layer can further prevent the metal material of the metal bonding layer from diffusing into the through-hole to form an alloy with the first reflector, or from penetrating into the surface of the first reflector, thus affecting the reflection effect of the through-hole reflection structure.

[0176] 10. Furthermore, by setting a metal reflective layer including a second reflector and a second protective layer, the second reflector is disposed on the side surface of the second type semiconductor layer away from the active region, and the second protective layer covers the exposed surface of the second reflector. The second protective layer can not only prevent the metal material of the metal bonding layer from diffusing to the second reflector and affecting the reflection effect of the metal reflective layer, but also prevent the metal material of the metal bonding layer from diffusing to the active region, thus avoiding the formation of non-radiative recombination centers in the active region, which would lead to a decrease in reliability.

[0177] 11. Furthermore, by setting a layered adhesive layer and a metal barrier layer between the metal bonding layer and the anti-diffusion structure, the metal barrier layer further prevents the metal material of the metal bonding layer from diffusing into the through hole, thus affecting the reflection effect of the through hole reflection structure.

[0178] 12. The method for manufacturing a through-hole type vertical structure LED chip provided in this embodiment achieves the beneficial effects of the above-mentioned LED chip while being simple, convenient, and easy to mass-produce.

[0179] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0180] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0181] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A through-hole type vertical structure LED chip, characterized in that, include: Conductive substrate; A metal bonding layer, an anti-diffusion structure, a via reflection structure, a metal reflection layer, a conductive layer, an insulating layer, and an epitaxial stack are disposed on one side of the conductive substrate; wherein, the epitaxial stack includes at least a second type semiconductor layer, an active region, and a first type semiconductor layer stacked sequentially along a first direction, and the surface of the epitaxial stack facing the conductive substrate has a groove extending toward the first type semiconductor layer, exposing a portion of the surface of the first type semiconductor layer; the first direction is perpendicular to the conductive substrate and extends from the conductive substrate toward the epitaxial stack; The metal reflective layer is disposed on the side surface of the second type semiconductor layer opposite to the active region, and the conductive layer is disposed on the side surface of the metal reflective layer opposite to the second type semiconductor layer; The insulating layer is disposed on the side of the epitaxial stack facing the conductive substrate and covers the exposed surfaces of the conductive layer, the metal reflective layer and the epitaxial stack. The insulating layer extends to the sidewall of the groove and exposes the bottom of the groove to form a first through hole. The insulating layer has an opening for external electrical connection by exposing a portion of the surface of the conductive layer. The via-hole reflective structure is disposed on a portion of the surface of the insulating layer away from the epitaxial stack, and extends to the point where the first via-hole forms contact with the first type of semiconductor layer; The anti-diffusion structure is disposed on the side of the insulating layer away from the conductive layer and covers the exposed surface of the through-hole reflective structure; The metal bonding layer is stacked on the side surface of the anti-diffusion structure opposite to the epitaxial stack, and forms an electrical connection with the first type semiconductor layer through the anti-diffusion structure and the through-hole reflection structure. The conductive substrate is stacked on the side surface of the metal bonding layer opposite to the epitaxial stack.

2. The through-hole type vertical structure LED chip according to claim 1, characterized in that: The anti-diffusion structure includes an anti-diffusion layer and a dielectric film layer. The anti-diffusion layer covers the exposed surfaces of the via-hole reflective structure and the insulating layer. The dielectric film layer is disposed on a portion of the surface of the anti-diffusion layer facing away from the via-hole reflective structure, and the vertical projection of the dielectric film layer on the plane of the conductive substrate covers the vertical projection of the via-hole reflective structure on the plane of the conductive substrate. The metal bonding layer covers the exposed surface of the dielectric film layer and forms contact with the anti-diffusion layer.

3. The through-hole type vertical structure LED chip according to claim 2, characterized in that: The anti-diffusion layer includes a gold layer or a metal stack structure containing a gold layer.

4. The through-hole type vertical structure LED chip according to claim 2, characterized in that: The interatomic spacing of the dielectric film material in the spatial structure is smaller than the atomic size of the metal material in the metal bonding layer, and the coefficient of thermal expansion of the dielectric film is in the range of 0.3*10. -6 / ℃ to 14*10 -6 / ℃, including endpoint values.

5. The through-hole type vertical structure LED chip according to claim 1, characterized in that: The number of grooves is M, where M is a positive integer and M is greater than or equal to 1. The number of first through holes is N, and the number of through hole reflection structures is Q. Then M = N = Q, and the grooves, first through holes, and through hole reflection structures correspond one-to-one.

6. The through-hole type vertical structure LED chip according to claim 1, characterized in that: The vertical projection of the through-hole reflective structure onto the plane of the conductive substrate covers the vertical projection of the groove onto the plane of the conductive substrate, and the edge region of the vertical projection of the through-hole reflective structure onto the plane of the conductive substrate overlaps with that of the metal reflective layer.

7. The through-hole type vertical structure LED chip according to claim 1, characterized in that: The vertical projections of the through-hole reflective structure and the metal reflective layer onto the plane of the conductive substrate cover the vertical projection of the active region onto the plane of the conductive substrate.

8. The through-hole type vertical structure LED chip according to claim 1, characterized in that: The through-hole reflective structure includes a first reflector and a first protective layer. The first reflector forms contact with the first type of semiconductor layer through the first through-hole, and the first protective layer covers the exposed surface of the first reflector.

9. A method for fabricating a through-hole type vertical structure LED chip, characterized in that, The method for fabricating a through-hole type vertical structure LED chip according to any one of claims 1 to 8 includes the following steps: S01, Provide a growth substrate; S02, forming an epitaxial stack on one side surface of the growth substrate, the epitaxial stack comprising a first type semiconductor layer, an active region and a second type semiconductor layer stacked sequentially along the growth direction; S03. A groove and a light-emitting platform are formed in the epitaxial stack, wherein the groove exposes a portion of the surface of the first type semiconductor layer; S04. Deposit an insulating layer, the insulating layer covering the surface of the epitaxial stack, the sidewalls of the groove and its bottom, and pattern the insulating layer to expose a portion of the surface of the light-emitting platform; S05. A metal reflective layer is formed on the exposed surface of the light-emitting platform; S06. Fabricate a conductive layer that covers the surface of the metal reflective layer and extends to a portion of the surface of the insulating layer; S07. Deposit an insulating layer again to cover the exposed surfaces of the conductive layer, the metal reflective layer, and the epitaxial stack, and pattern the insulating layer to expose the bottom of the groove to form a first through-hole; S08. Fabricate a through-hole reflective structure, which is disposed on a portion of the surface of the insulating layer and extends to the first through-hole to form contact with the first type of semiconductor layer; S09. Fabricate an anti-diffusion structure, wherein the anti-diffusion structure is disposed on the surface of the insulating layer and covers the exposed surface of the through-hole reflective structure; S10, vapor-deposited metal bonding layer, wherein the metal bonding layer is stacked on the surface of the anti-diffusion structure; S11. The chip structure formed in step S10 is fixed to a conductive substrate by a bonding process, and the conductive substrate is formed on the side surface of the metal bonding layer that is away from the epitaxial stack. S12. Peel off the growth substrate to expose the first type of semiconductor layer; S13. Etch a portion of the epitaxial stack to expose the insulating layer; S14. Deposit a passivation layer, the passivation layer covering the exposed surface of the first type semiconductor layer and extending to the sidewalls of the epitaxial stack and the surface of the insulating layer; S15. The passivation layer and the insulating layer are patterned by photolithography and etching to form an opening for external electrical connection by exposing a portion of the surface of the conductive layer. The metal bonding forms an electrical connection with the first type of semiconductor layer through the anti-diffusion structure and the through-hole reflection structure; The vertical projection of the through-hole reflective structure on the plane of the conductive substrate covers the vertical projection of the groove on the plane of the conductive substrate, and the edge region of the vertical projection of the through-hole reflective structure and the metal reflective layer on the plane of the conductive substrate overlaps. The vertical projections of the through-hole reflective structure and the metal reflective layer onto the plane of the conductive substrate cover the vertical projection of the active region onto the plane of the conductive substrate. The number of grooves is M, where M is a positive integer and M is greater than or equal to 1. The number of first through holes is N, and the number of through hole reflection structures is Q. Then M = N = Q, and the grooves, first through holes, and through hole reflection structures correspond one-to-one.

10. The method for manufacturing a through-hole type vertical structure LED chip according to claim 9, characterized in that: The anti-diffusion structure includes an anti-diffusion layer and a dielectric film layer. The anti-diffusion layer covers the exposed surfaces of the via-hole reflective structure and the insulating layer. The dielectric film layer is disposed on a portion of the surface of the anti-diffusion layer facing away from the via-hole reflective structure, and the vertical projection of the dielectric film layer on the plane of the conductive substrate covers the vertical projection of the via-hole reflective structure on the plane of the conductive substrate. The metal bonding layer covers the exposed surface of the dielectric film layer and forms contact with the anti-diffusion layer.

11. The method for manufacturing a through-hole type vertical structure LED chip according to claim 10, characterized in that: The anti-diffusion layer includes a gold layer or a metal stack structure containing a gold layer.

12. The method for manufacturing a through-hole type vertical structure LED chip according to claim 10, characterized in that: The interatomic spacing of the dielectric film material in the spatial structure is smaller than the atomic size of the metal material in the metal bonding layer, and the coefficient of thermal expansion of the dielectric film is in the range of 0.3*10. -6 / ℃ to 14*10 -6 / ℃, including endpoint values.

13. The method for manufacturing a through-hole type vertical structure LED chip according to claim 9, characterized in that: The through-hole reflective structure includes a first reflector and a first protective layer. The first reflector forms contact with the first type of semiconductor layer through the first through-hole, and the first protective layer covers the exposed surface of the first reflector.

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