A fast response, low ripple voltage, off-chip capacitor-free inductor voltage stabilizing circuit

Abstract

The application discloses a slice-out capacitor-free inductor voltage stabilizing circuit with fast response and low voltage ripple, comprising a cross-coupled charge pump, an error amplifier module, a digital logic control module and a low-dropout linear voltage regulator, wherein the cross-coupled charge pump is provided with a substrate dynamic biasing circuit for lifting an original power supply voltage and eliminating the influence of threshold voltage drop effect and body effect; the digital logic control module is used for generating different output voltages through a resistance feedback loop to realize the programmable function of the output voltage in the circuit; the error amplifier module is used for buffering and adjusting the node voltage in the resistance feedback loop in the digital logic control module; and the low-dropout linear voltage regulator is used for stabilizing the output voltage of the digital logic control module to improve the transient response speed and stability of the circuit. The application improves the problems of long transient response time and large ripple of the traditional voltage stabilizing circuit and the cost problem caused by the slice-out large capacitor.

Description

Technical Field

[0001] This invention belongs to the field of analog power management technology, specifically relating to a fast-response, low-ripple voltage regulator circuit without external capacitors or inductors, which can power various consumer electronic products. Background Technology

[0002] In today's era of rapid development of Internet technology, more and more mobile network terminal products are becoming popular, and portable mobile electronic products are being promoted and popularized, such as smartphones, Bluetooth headsets, tablets and other consumer electronics products. Most of these consumer electronics products require power supply, and their use is inseparable from power management technology.

[0003] With the rapid development of CMOS technology and the widespread adoption of System-on-Chip (SoC), power supply voltages are trending downwards. Traditional power management solutions are gradually revealing problems and can no longer meet the low-voltage requirements of SoCs. Some modules often need to be driven by voltages higher than the power supply voltage. Considering factors such as efficiency, noise, and cost, charge pumps, as traditional buck-boost power conversion circuits, have wide applications and significant advantages in various consumer electronics chips compared to traditional DC-DC converters. Generally, as an internal module power supply, the output voltage of a traditional regulated charge pump will fluctuate significantly when the load changes, and the recovery time is related to the operating clock frequency. Increasing the clock frequency will reduce the recovery time, but it will inevitably increase the system power consumption. On the other hand, similar to DC-DC switching power supplies, the noise of switching power supplies will reduce the signal-to-noise ratio (SNR) and other performance characteristics of the specific load generation circuit. Similarly, increasing the clock frequency will reduce ripple, but it will increase power consumption.

[0004] The traditional solution is to use external capacitors, which can effectively meet the requirements of fast recovery and low ripple during load transitions. However, while using a voltage regulator circuit with external load capacitors can also effectively meet the requirements of fast recovery and low ripple voltage during load transitions, the presence of external load capacitors increases the chip area and cost. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a fast-response, low-ripple voltage regulator circuit without external capacitors or inductors. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a fast-response, low-ripple voltage regulator circuit without external capacitors or inductors, comprising a cross-coupled charge pump, an error amplifier module, a digital logic control module, and a low-dropout linear regulator, wherein...

[0007] The cross-coupled charge pump has a substrate dynamic bias circuit to boost the original power supply voltage and eliminate the effects of threshold voltage drop and bulk effect.

[0008] The digital logic control module is used to generate different output voltages through a resistor feedback loop, thereby realizing the programmable function of the output voltage in the circuit; the error amplifier module is used to buffer and adjust the node voltage in the resistor feedback loop of the digital logic control module.

[0009] The low-dropout linear regulator is used to regulate the output voltage of the digital logic control module, thereby improving the transient response speed and stability of the circuit.

[0010] In one embodiment of the present invention, the cross-coupled charge pump includes NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6, PMOS transistors MP1, MP2, MP3, MP4, MP5, and MP6, capacitors C1, C2, and C3, wherein...

[0011] The drains of NMOS transistors MN1 and MN2 are both connected to the input terminal of the cross-coupled charge pump for inputting the original power supply voltage VIN. The gate of NMOS transistor MN1 is simultaneously connected to the gate of PMOS transistor MP1, the source of NMOS transistor MN2, the gate of NMOS transistor MN5, the drain of NMOS transistor MN6, the drain of PMOS transistor MP2, the drain of PMOS transistor MP5, and the gate of PMOS transistor MP6. The source of NMOS transistor MN1 is simultaneously connected to the drain of NMOS transistor MN4, the gate of NMOS transistor MN3, the gate of NMOS transistor MN2, the gate of PMOS transistor MP2, the drain of PMOS transistor MP3, the gate of PMOS transistor MP4, and the drain of PMOS transistor MP1.

[0012] The drain of NMOS transistor MN3 and the gate of NMOS transistor MN4 are connected to the drain of NMOS transistor MN1, and the source of NMOS transistor MN3 and the source of NMOS transistor MN4 are connected to the substrate of NMOS transistor MN1; the drain of NMOS transistor MN5 and the gate of NMOS transistor MN6 are connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN5 and the source of NMOS transistor MN6 are connected to the substrate of NMOS transistor MN2.

[0013] The source of PMOS transistor MP1 is simultaneously connected to the drain of PMOS transistor MP4, the gate of PMOS transistor MP3, the source of PMOS transistor MP2, the drain of PMOS transistor MP6, and the gate of PMOS transistor MP5. The source of PMOS transistor MP1 serves as the output terminal of the cross-coupled charge pump, used to input the processed voltage VDDA. The sources of PMOS transistors MP3 and MP4 are both connected to the substrate of PMOS transistor MP1. The sources of PMOS transistors MP5 and MP6 are both connected to the substrate of PMOS transistor MP2.

[0014] One end of capacitor C1 is connected to the source of NMOS transistor MN2, and the other end is connected to the first clock signal input terminal for inputting the first clock signal CLK. One end of capacitor C2 is connected to the source of NMOS transistor MN1, and the other end is connected to the second clock signal input terminal for inputting the second clock signal CLKN. One end of capacitor C3 is connected to the source of PMOS transistor MP1, and the other end is connected to the ground terminal GND.

[0015] In one embodiment of the present invention, the first clock signal CLK and the second clock signal CLKN are complementary clock signals with the same amplitude but opposite directions.

[0016] In one embodiment of the present invention, the error amplifier module includes PMOS transistors MP20, MP21, MP22, MP23, NMOS transistors MN27, MN28, MN29, MN30, and MN31, wherein...

[0017] The sources of PMOS transistors MP20, MP21, MP22, and MP23 are all connected to the output terminal of the cross-coupled charge pump. The gate of PMOS transistor MP20 is connected to the gate of PMOS transistor MP21, the drain of PMOS transistor MP21, and the drain of NMOS transistor MN28. The gate of PMOS transistor MP23 is connected to the gate of PMOS transistor MP22, the drain of PMOS transistor MP22, and the drain of NMOS transistor MN27.

[0018] The drain of the PMOS transistor MP20 is connected to the drain of the NMOS transistor MN30 and the output terminal V0 of the digital logic control module. The drain of the PMOS transistor MP23 is connected to the drain of the NMOS transistor MN29, the gate of the NMOS transistor MN29 and the gate of the NMOS transistor MN30.

[0019] The gate of NMOS transistor MN27 is connected to the reference voltage VREF. The gate of NMOS transistor MN28 is connected to the input terminal VB of the digital logic control module. The sources of NMOS transistors MN27 and MN28 are both connected to the drain of NMOS transistor MN31. The sources of NMOS transistors MN29, MN30, and MN31 are all connected to the ground terminal GND. The gate of NMOS transistor MN31 is connected to the low dropout linear regulator.

[0020] In one embodiment of the present invention, the digital logic control module includes a 3-to-8 decoder and a resistor feedback loop controlled by digital logic, wherein,

[0021] The 3-to-8 decoder is used to input a three-bit binary code and output eight control signals;

[0022] The digitally logic-controlled resistor feedback loop is used to generate different output voltages under the control of the eight control signals.

[0023] In one embodiment of the present invention, the digitally logic-controlled resistor feedback loop includes MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8, and resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13, wherein...

[0024] Resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 are connected in series between the output terminal V0 of the digital logic control module and the ground terminal GND. The gates of MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8 are respectively connected to the eight output terminals of the 3-8 decoder structure. The sources of MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8 are all connected at the node between resistors R11 and R12.

[0025] The drain of MOSFET M1 is connected to the output terminal V0 of the digital logic control module. The drain of MOSFET M2 is connected to the node between resistors R4 and R5. The drain of MOSFET M3 is connected to the node between resistors R5 and R6. The drain of MOSFET M4 is connected to the node between resistors R6 and R7. The drain of MOSFET M5 is connected to the node between resistors R7 and R8. The drain of MOSFET M6 is connected to the node between resistors R8 and R9. The drain of MOSFET M7 is connected to the node between resistors R9 and R10. The drain of MOSFET M8 is connected to the node between resistors R10 and R11. The input terminal VB of the digital logic control module is connected to the node between resistors R12 and R13.

[0026] In one embodiment of the present invention, the low-dropout linear regulator includes PMOS transistors MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, MP17, MP18, and MP19, and NMOS transistors MN7, MN8, MN9, and MN10. NMOS transistors MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19, MN20, MN21, MN22, MN23, MN24, MN25, and MN26; capacitors C4 and C5; and resistors R1, R2, and R3.

[0027] The sources of PMOS transistors MP7, MP8, MP9, MP10, MP11, MP18, and MP19 are all connected to the output terminal of the cross-coupled charge pump. The gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP8, the drain of PMOS transistor MP8, the drain of NMOS transistor MN22, and the gate of NMOS transistor MN22. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7, and the gate of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the source of PMOS transistor MP14, the source of PMOS transistor MP16, and the source of PMOS transistor MP17.

[0028] The gate of PMOS transistor MP10 is connected to the gate of PMOS transistor MP11, the gate of PMOS transistor MP18, the gate of PMOS transistor MP19, the drain of PMOS transistor MP18, and the drain of NMOS transistor MN23. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13, and the gate of NMOS transistor MN14. The drain of PMOS transistor MP11 is connected to the drain of NMOS transistor MN16, the gate of NMOS transistor MN16, and the gate of NMOS transistor MN15. The drain of PMOS transistor MP19 is connected to the drain of NMOS transistor MN24, the gate of NMOS transistor MN24, and the gate of NMOS transistor MN23.

[0029] The sources of PMOS transistors MP12, MP13, and MP15 are all connected to the output terminal V0 of the digital logic control module. The gate of PMOS transistor MP12 is connected to the gate of PMOS transistor MP13, the gate of PMOS transistor MP14, the drain of PMOS transistor MP14, and the drain of NMOS transistor MN14. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN8, the gate of NMOS transistor MN9, and the gate of NMOS transistor MN10.

[0030] The drain of PMOS transistor MP13 is connected to the drain of NMOS transistor MN17, the gate of NMOS transistor MN17, and the gate of NMOS transistor MN18. The gate of PMOS transistor MP15 is connected to the drain of PMOS transistor MP15, the drain of NMOS transistor MN15, the gate of PMOS transistor MP16, and the gate of PMOS transistor MP17. The drain of PMOS transistor MP16 is connected to the drain of NMOS transistor MN12, the gate of NMOS transistor MN12, and the gate of NMOS transistor MN11. The drain of PMOS transistor MP17 is connected to the drain of NMOS transistor MN19, the gate of NMOS transistor MN20, and the gate of NMOS transistor MN21.

[0031] The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN9, the gate of NMOS transistor MN8 is connected to the gate of NMOS transistor MN23, and the source of NMOS transistor MN8 is connected to the drain of both NMOS transistor MN10 and NMOS transistor MN11.

[0032] The sources of NMOS transistors MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN20, MN21, and MN26 are all connected to the ground terminal GND.

[0033] The drain of NMOS transistor MN18 is connected to the drain of NMOS transistor MN20 and the source of NMOS transistor MN19; the gate of NMOS transistor MN19 is connected to the gate of NMOS transistor MN23; and the drain of NMOS transistor MN21 is connected to the source of NMOS transistor MN22.

[0034] The source of NMOS transistor MN24 is connected to the drain of NMOS transistor MN26, the gate of NMOS transistor MN26, the gate of NMOS transistor MN25, and the gate of NMOS transistor MN31 in the error amplifier module; the drain of NMOS transistor MN25 is connected to the source of NMOS transistor MN23.

[0035] The resistor R1 and the capacitor C4 are connected in series between the gate and drain of the PMOS transistor MP9, the resistor R2 and the capacitor C5 are connected in parallel between the drain of the PMOS transistor MP9 and the ground terminal GND, the resistor R3 is connected between the source of the NMOS transistor MN25 and the ground terminal GND, and the drain of the PMOS transistor MP9 serves as the output terminal VOUT of the low dropout linear regulator.

[0036] In one embodiment of the present invention, the PMOS transistor MP10 and the PMOS transistor MP11 have the same width-to-length ratio.

[0037] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0038] 1. This invention provides a capacitor-free inductor voltage regulator circuit with fast transient response and low ripple voltage. This structure improves the problems of long transient response time and large ripple in traditional voltage regulator circuits, and also improves the cost problem caused by the use of large external capacitors in traditional voltage regulator circuits.

[0039] 2. This invention employs a cross-coupled charge pump with substrate dynamic bias circuit, an error amplifier module, a digital logic control circuit, and a low dropout voltage regulator circuit without external capacitors to jointly realize a capacitor-free inductor voltage regulator circuit with fast transient response and low ripple voltage. Compared with traditional power supply circuits, it has the characteristics of low ripple voltage, fast transient response characteristics, low power consumption, small area, and low production cost.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0041] Figure 1 This is an overall structural framework diagram of a fast-response, low-ripple voltage voltage regulator circuit without external capacitors and inductors provided in an embodiment of the present invention;

[0042] Figure 2 This is a circuit diagram of a traditional Dickson charge pump;

[0043] Figure 3 This is a circuit diagram of a cross-coupled charge pump provided in an embodiment of the present invention;

[0044] Figure 4 This is a circuit connection diagram of an error amplifier module, a digital logic control module, and a low-dropout linear regulator provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of the structure of a digital logic control module provided in an embodiment of the present invention. Detailed Implementation

[0046] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a fast-response, low-ripple voltage regulator circuit without external capacitors or inductors proposed according to the present invention.

[0047] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0048] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0049] This invention, based on existing technology, provides a capacitor-free, inductor-based voltage regulator circuit with fast transient response and low ripple voltage performance. This circuit improves upon the problems of long transient response time and large ripple in traditional voltage regulator circuits, and also addresses the cost issues caused by the use of large external capacitors in traditional voltage regulator circuits. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is an overall structural framework diagram of a fast-response, low-ripple voltage regulator circuit without external capacitors or inductors, provided by an embodiment of the present invention. The regulator circuit includes a cross-coupled charge pump 101, an error amplifier module 102, a digital logic control module 103, and a low-dropout linear regulator 104. The cross-coupled charge pump 101 has a substrate dynamic bias circuit to boost the original power supply voltage and eliminate the effects of threshold voltage drop and volume effect. The digital logic control module 103 generates different output voltages through a resistor feedback loop, realizing the programmable function of the output voltage in the circuit. The error amplifier module 102 buffers and adjusts the node voltage in the resistor feedback loop of the digital logic control module 103. The low-dropout linear regulator 104 regulates the output voltage of the digital logic control module 103, improving the transient response speed and stability of the circuit.

[0050] In other words, the capacitorless and inductorless voltage regulator circuit of the present invention boosts the low power supply voltage through a cross-coupled charge pump circuit (PUMP) with a substrate dynamic bias structure, then realizes the programmable output voltage through an error amplifier module (AMP) and a digital logic control module, and finally generates a fast-response and stable output voltage that can drive a large current through an off-chip low-dropout linear regulator (OCL-LDO). This structure ultimately realizes a voltage regulator circuit with programmable output voltage, fast transient response and low ripple voltage.

[0051] Please see Figure 2 , Figure 2This is a circuit diagram of a traditional Dickson charge pump. Traditional Dickson charge pump circuits are affected by threshold voltage drop and body effects, resulting in a reduced output voltage conversion factor and significant output voltage loss. Furthermore, the charge pump will not function properly when the supply voltage is close to the threshold voltage of the transfer transistor. Considering non-ideal factors, the actual output voltage of an N-stage Dickson charge pump circuit is given by the following formula:

[0052]

[0053]

[0054] Among them, V in Indicates the input voltage, V out This represents the actual output voltage of an N-stage Dickson charge pump circuit, where N is the number of charge pump stages and C... S Let's assume the parasitic capacitance of the MOSFET in the charge pump is... Figure 2 In this context, C1 = C2 = C3 = C4 = C, Ci (i = 1, 2, 3, 4) represents the charging and discharging capacitor at the i-th stage output terminal, and I... load V is the current flowing into the load. th ΔV is the threshold voltage of the MOSFET. thi To account for the volume effect, the threshold voltage correction term, V th0 V represents the threshold voltage of a MOSFET when there is no body effect. SB The source-substrate potential difference is represented by γ, and the volume effect coefficient is represented by γ. V T For thermal voltage, N sub n represents the substrate doping concentration. i This represents the intrinsic carrier concentration.

[0055] Please see Figure 3 , Figure 3 This is a circuit diagram of a cross-coupled charge pump provided in an embodiment of the present invention. The cross-coupled charge pump includes NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6, PMOS transistors MP1, MP2, MP3, MP4, MP5, and MP6, and capacitors C1, C2, and C3.

[0056] The drains of NMOS transistors MN1 and MN2 are both connected to the input of a cross-coupled charge pump, used to input the original power supply voltage VIN. The gate of NMOS transistor MN1 is simultaneously connected to the gate of PMOS transistor MP1, the source of NMOS transistor MN2, the gate of NMOS transistor MN5, the drain of NMOS transistor MN6, the drain of PMOS transistor MP2, the drain of PMOS transistor MP5, and the gate of PMOS transistor MP6. The source of NMOS transistor MN1 is simultaneously connected to the drain of NMOS transistor MN4, the gate of NMOS transistor MN3, the gate of NMOS transistor MN2, the gate of PMOS transistor MP2, the drain of PMOS transistor MP3, the gate of PMOS transistor MP4, and the drain of PMOS transistor MP1.

[0057] The drain of NMOS transistor MN3 and the gate of NMOS transistor MN4 are connected to the drain of NMOS transistor MN1, and the source of NMOS transistor MN3 and the source of NMOS transistor MN4 are connected to the substrate of NMOS transistor MN1; the drain of NMOS transistor MN5 and the gate of NMOS transistor MN6 are connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN5 and the source of NMOS transistor MN6 are connected to the substrate of NMOS transistor MN2.

[0058] The source of PMOS transistor MP1 is simultaneously connected to the drain of PMOS transistor MP4, the gate of PMOS transistor MP3, the source of PMOS transistor MP2, the drain of PMOS transistor MP6, and the gate of PMOS transistor MP5. The source of PMOS transistor MP1 serves as the output terminal of a cross-coupled charge pump, used to output the boosted voltage VDDA. The sources of PMOS transistors MP3 and MP4 are both connected to the substrate of PMOS transistor MP1. The sources of PMOS transistors MP5 and MP6 are both connected to the substrate of PMOS transistor MP2.

[0059] One end of capacitor C1 is connected to the source of NMOS transistor MN2, and the other end is connected to the first clock signal input terminal for inputting the first clock signal CLK. One end of capacitor C2 is connected to the source of NMOS transistor MN1, and the other end is connected to the second clock signal input terminal for inputting the second clock signal CLKN. One end of capacitor C3 is connected to the source of PMOS transistor MP1, and the other end is connected to the ground terminal GND.

[0060] In this embodiment, the first clock signal CLK and the second clock signal CLKN are complementary clock signals with the same amplitude but opposite directions.

[0061] The cross-coupled charge pump in this embodiment eliminates the threshold voltage and charge loss problems of traditional Dickson charge pump circuits, while the substrate dynamic bias circuit eliminates the influence of the bulk effect. Specifically, NMOS transistors MN1, MN2, MP1, and MP2 constitute a cross-coupled charge pump circuit. The circuit works by using complementary clock signals CLK and CLKN with the same amplitude but opposite direction to turn on the cross-coupled NMOS transistors MN1 and MN2, thereby charging capacitors C1 and C2 respectively, and then turning on PMOS transistors MP1 and MP2 respectively, so that the final voltage of the output terminal VDDA rises to 2VIN. When the first clock signal CLK is high, NMOS transistor MN1 is turned on to charge capacitor C2, and the voltage difference between the two plates of capacitor C2 is VIN. PMOS transistor MP2 is turned on to release the charge accumulated on capacitor C1 to the output terminal VDDA. Conversely, when the first clock signal CLK is low, NMOS transistor MN2 is turned on to charge capacitor C1, and PMOS transistor MP1 is turned on to release the charge accumulated on capacitor C2 to the output terminal VDDA. Through this alternating charging and discharging of the capacitor, the output voltage VDDA is eventually stabilized at 2VIN.

[0062] Figure 3 The structure within the dashed box is a substrate dynamic bias structure, which can eliminate the body effect. The body effect of NMOS transistor MN1 is eliminated by connecting NMOS transistors MN3 and MN4; the body effect of NMOS transistor MN2 is eliminated by connecting NMOS transistors MN5 and MN6; the body effect of PMOS transistor MP3 and MP4 is eliminated by connecting PMOS transistor MP1; and the body effect of PMOS transistor MP5 and MP6 is eliminated by connecting PMOS transistor MP2. A body effect occurs when the voltages at the source (S) and substrate (B) of a MOS transistor are different, thus affecting the threshold voltage V of the MOS transistor. th Therefore, as long as the source voltage and substrate voltage of the MOSFET are the same (i.e., V0), BS =0), thus eliminating the body effect. For NMOS transistors, the end with the lower potential between the source and drain terminals is the source; for PMOS transistors, the end with the higher potential between the source and drain terminals is the source; the substrate dynamic bias structure can automatically connect the substrate end and the source end of the MOS transistor. For example... Figure 3When the substrate bias circuit is working, taking NMOS transistor MN2 as an example: when the potential at terminal A is high and the potential at terminal B is low, NMOS transistor MN6 is turned on and NMOS transistor MN5 is turned off, making the substrate potential of NMOS transistor MN2 equal to the potential at terminal B (the low potential of NMOS is the source). Taking PMOS transistor MP2 as an example: when the potential at terminal C is high and the potential at terminal D is low, PMOS transistor MP5 is turned on and PMOS transistor MP6 is turned off, making the substrate potential of PMOS transistor MP2 equal to the potential at terminal C (the high potential of PMOS is the source). Therefore, it can be seen that the substrate potential of the MOS transistor in the cross-coupled charge pump is always connected to its source potential, thus eliminating the body effect.

[0063] Please see Figure 4 , Figure 4 This is a circuit connection diagram of an error amplifier module, a digital logic control module, and a low-dropout linear regulator provided in an embodiment of the present invention. The error amplifier module 102 is specifically composed of MN27-MN31 and MP20-MP23, employing a two-stage operational amplifier configuration to provide gain, primarily for buffering voltage regulation. Specifically, the error amplifier module 102 includes PMOS transistors MP20, MP21, MP22, and MP23, and NMOS transistors MN27, MN28, MN29, MN30, and MN31.

[0064] The sources of PMOS transistors MP20, MP21, MP22, and MP23 are all cross-coupled to the output of charge pump 101 for inputting the processed voltage VDDA. The gate of PMOS transistor MP20 is connected to the gate and drain of PMOS transistor MP21 and the drain of NMOS transistor MN28. The gate of PMOS transistor MP23 is connected to the gate and drain of PMOS transistor MP22 and the drain of NMOS transistor MN27. The drain of PMOS transistor MP20 is connected to the drain of NMOS transistor MN30 and the output V0 of the digital logic control module. The drain of PMOS transistor MP23 is connected to the drain and gate of NMOS transistor MN29 and the gate of NMOS transistor MN30.

[0065] The gate input reference voltage VREF of NMOS transistor MN27 is connected to the gate of NMOS transistor MN28, which is connected to the input terminal VB of digital logic control module 103. The sources of NMOS transistors MN27 and MN28 are both connected to the drain of NMOS transistor MN31. The sources of NMOS transistors MN29, MN30, and MN31 are all connected to ground terminal GND. The gate of NMOS transistor MN31 is connected to low dropout linear regulator 104.

[0066] Please see Figure 5 , Figure 5 This is a schematic diagram of a digital logic control module provided in an embodiment of the present invention. The digital logic control module 103 of this embodiment is used to implement a programmable output voltage function, including a 3-8 decoder structure and a resistor feedback loop controlled by digital logic. Specifically, the resistor feedback loop controlled by digital logic includes MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8, and resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13.

[0067] Resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 are connected in series between the output terminal V0 of the digital logic control module and the ground terminal GND. The gates of MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8 are connected to the eight output terminals of the 3-8 decoder structure. The sources of MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8 are all connected at the node between resistors R11 and R12.

[0068] The drain of MOSFET M1 is connected to the output terminal V0 of digital logic control module 103. The drain of MOSFET M2 is connected to the node between resistors R4 and R5. The drain of MOSFET M3 is connected to the node between resistors R5 and R6. The drain of MOSFET M4 is connected to the node between resistors R6 and R7. The drain of MOSFET M5 is connected to the node between resistors R7 and R8. The drain of MOSFET M6 is connected to the node between resistors R8 and R9. The drain of MOSFET M7 is connected to the node between resistors R9 and R10. The drain of MOSFET M8 is connected to the node between resistors R10 and R11. The input terminal VB of digital logic control module 103 is connected to the node between resistors R12 and R13.

[0069] In this embodiment, the 3-8 decoder is used to input three binary codes A0-A2 and output eight control signals X0-X7. The resistor feedback loop controlled by digital logic is used to generate different output voltages under the control of the eight control signals X0-X7. Specifically, the eight control signals X0-X7 control eight MOSFETs M1-M8. By controlling the on and off states of the eight MOSFETs, the resistance values ​​in the feedback loop are controlled, thereby generating different output voltages and realizing the programmable output voltage function.

[0070] Further, see also Figure 4 The low-dropout linear regulator in this embodiment includes PMOS transistors MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, and NMOS transistors MN7, MN8, MN9, MN10, and NM. OS transistor MN11, NMOS transistor MN12, NMOS transistor MN13, NMOS transistor MN14, NMOS transistor MN15, NMOS transistor MN16, NMOS transistor MN17, NMOS transistor MN18, NMOS transistor MN19, NMOS transistor MN20, NMOS transistor MN21, NMOS transistor MN22, NMOS transistor MN23, NMOS transistor MN24, NMOS transistor MN25, NMOS transistor MN26, capacitor C4, capacitor C5, resistor R1, resistor R2, and resistor R3.

[0071] The sources of PMOS transistors MP7, MP8, MP9, MP10, MP11, MP18, and MP19 are all connected to the output of the cross-coupled charge pump 101 for inputting the processed voltage VDDA. The gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP8, the drain of PMOS transistor MP8, the drain of NMOS transistor MN22, and the gate of NMOS transistor MN22. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7, and the gate of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the source of PMOS transistor MP14, the source of PMOS transistor MP16, and the source of PMOS transistor MP17.

[0072] The gate of PMOS transistor MP10 is connected to the gate of PMOS transistor MP11, the gate of PMOS transistor MP18, the gate of PMOS transistor MP19, the drain of PMOS transistor MP18, and the drain of NMOS transistor MN23. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13, and the gate of NMOS transistor MN14. The drain of PMOS transistor MP11 is connected to the drain of NMOS transistor MN16, the gate of NMOS transistor MN16, and the gate of NMOS transistor MN15. The drain of PMOS transistor MP19 is connected to the drain of NMOS transistor MN24, the gate of NMOS transistor MN24, and the gate of NMOS transistor MN23.

[0073] The sources of PMOS transistors MP12, MP13, and MP15 are all connected to the output terminal V0 of the digital logic control module. The gate of PMOS transistor MP12 is connected to the gate of PMOS transistor MP13, the gate of PMOS transistor MP14, the drain of PMOS transistor MP14, and the drain of NMOS transistor MN14. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN8, the gate of NMOS transistor MN9, and the gate of NMOS transistor MN10.

[0074] The drain of PMOS transistor MP13 is connected to the drain, gate, and gate of NMOS transistor MN17 and MN18. The gate of PMOS transistor MP15 is connected to the drain, gate, and gate of PMOS transistor MP16 and MP17. The drain of PMOS transistor MP16 is connected to the drain, gate, and gate of NMOS transistor MN12 and MN11. The drain of PMOS transistor MP17 is connected to the drain, gate, and gate of NMOS transistor MN20 and MN21. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN9. The gate of NMOS transistor MN8 is connected to the gate of NMOS transistor MN23. The source of NMOS transistor MN8 is connected to the drain of NMOS transistor MN10 and MN11.

[0075] The sources of NMOS transistors MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN20, MN21, and MN26 are all connected to ground (GND). The drain of NMOS transistor MN18 is connected to the drain of NMOS transistor MN20 and the source of NMOS transistor MN19. The gate of NMOS transistor MN19 is connected to the gate of NMOS transistor MN23. The drain of NMOS transistor MN21 is connected to the source of NMOS transistor MN22.

[0076] The source of NMOS transistor MN24 is connected to the drain of NMOS transistor MN26, the gate of NMOS transistor MN26, the gate of NMOS transistor MN25, and the gate of NMOS transistor MN31 in error amplifier module 102; the drain of NMOS transistor MN25 is connected to the source of NMOS transistor MN23; resistor R1 and capacitor C4 are connected in series between the gate and drain of PMOS transistor MP9; resistor R2 and capacitor C5 are connected in parallel between the drain of PMOS transistor MP9 and ground terminal GND; resistor R3 is connected between the source of NMOS transistor MN25 and ground terminal GND; and the drain of PMOS transistor MP9 serves as the output terminal VOUT of low dropout linear regulator 104.

[0077] Specifically, PMOS transistors MP18 and MP19, NMOS transistors MN23-MN26, and resistor R3 constitute a bias circuit to generate a bias voltage, providing gate voltage to NMOS transistors MN31, MN8, and MN19. PMOS transistors MP10, MP11, MP18, and MP19 constitute a current mirror circuit, mirroring the current generated in the bias circuit to provide a constant tail current to the transconductance unit composed of NMOS transistors MP12-MP17.

[0078] This embodiment of the OCL-LDO mainly consists of a high-speed error amplifier and a power transistor MP9. The high-speed error amplifier is formed by a transconductance unit and a current enhancement unit. I1 and I2 are constant tail current sources. In this embodiment, PMOS transistors MP10 and MP10 have the same width-to-length ratio, such that I1 = I2. V0 and VOUT are the input voltages of the transconductance unit. The output currents I3 and I4 are not limited by the tail current sources and have a quadratic relationship with (VOUT - V0). The expression for I4 is:

[0079]

[0080] Where, μ P C represents hole mobility. OX Indicates the gate oxide capacitance. This indicates the width-to-length ratio of the PMOS transistor MP17. This indicates the width-to-length ratio of the PMOS transistor MP15.

[0081] Furthermore, NMOS transistors MN8-MN12 and MN17-MN21 constitute a current enhancement circuit structure. This structure employs a nonlinear current mirror structure, which can maintain a low quiescent current and increase currents I5 and I6 as I3 and I4 increase. The nonlinear current mirror in this structure is implemented by adding NMOS transistors MN8 and MN19. By setting a bias voltage N2, it is ensured that NMOS transistors MN10 and MN20 operate near the linear region, i.e., the source-drain voltage V of MN10 and MN20 is... DS Slightly below the source-drain saturation voltage V DS,sat Since the bias voltage N2 is fixed, when I3 and I4 increase, the voltages at points A and B will decrease. Therefore, the drain-source voltage V of transistors MN10 and MN20 will also decrease. DS Below its source-drain saturation voltage V DS sat This drives them into the linear region. As long as NMOS transistors MN9 and MN21 operate in the saturation region, current boost can be achieved. Because the drain-source voltage of transistor MN20 is low, the drain-source voltage V of MN20... DS20 It can be approximated as:

[0082]

[0083] Among them, V THN V is the threshold voltage of NMOS transistor MN19. N2 V represents the gate voltage of NMOS transistor MN19. GS19 This represents the gate-source voltage of the NMOS transistor MN19, μ. n Indicates electron mobility. This indicates the aspect ratio of the NMOS transistor MN19. V DS20 As I4 increases, the current decreases, and the output current I6 can be expressed as:

[0084]

[0085] in, It is evident that the output current of the nonlinear current mirror structure is greater than that of the traditional current mirror. Through the combined action of the transconductance unit, current enhancement unit, and power transistor, the transient response speed and stability of the overall circuit are improved.

[0086] This invention provides a capacitor-free, inductor-free voltage regulator circuit with fast transient response and low ripple voltage. This structure improves upon the problems of long transient response time and large ripple in traditional voltage regulator circuits, and also addresses the cost issues caused by the use of large external capacitors in traditional voltage regulator circuits. This invention utilizes a cross-coupled charge pump with substrate dynamic bias circuitry, an error amplifier module, digital logic control circuitry, and a capacitor-free low-dropout voltage regulator circuit to achieve a capacitor-free, inductor-free voltage regulator circuit with fast transient response and low ripple voltage. Compared to traditional power supply circuits, it features low ripple voltage, faster transient response characteristics, low power consumption, small area, and low manufacturing cost.

[0087] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0088] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0089] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A fast-response, low-ripple voltage regulator circuit without external capacitors or inductors, characterized in that, It includes a cross-coupled charge pump (101), an error amplifier module (102), a digital logic control module (103), and a low-dropout linear regulator (104), wherein, The cross-coupled charge pump (101) has a substrate dynamic bias circuit for boosting the original power supply voltage and eliminating the effects of threshold voltage drop and bulk effect. The digital logic control module (103) is used to generate different output voltages through a resistor feedback loop to realize the programmable function of the output voltage in the circuit; the error amplifier module (102) is used to buffer and adjust the node voltage in the resistor feedback loop of the digital logic control module (103); The low-dropout linear regulator (104) is used to regulate the output voltage of the digital logic control module (103) to improve the transient response speed and stability of the circuit. The digital logic control module (103) includes a 3-8 decoder and a resistor feedback loop controlled by digital logic, wherein, The 3-to-8 decoder is used to input a three-bit binary code and output eight control signals; The digitally logic-controlled resistor feedback loop is used to generate different output voltages under the control of the eight control signals; The digitally logic-controlled resistor feedback loop includes MOSFETs M1, M2, M3, M4, M5, M6, M7, and M8, and resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13. The resistors R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 are connected in series between the output terminal V0 of the digital logic control module (103) and the ground terminal GND. The gates of the MOS transistors M1, M2, M3, M4, M5, M6, M7, and M8 are respectively connected to the eight output terminals of the 3-8 decoder structure. The sources of the MOS transistors M1, M2, M3, M4, M5, M6, M7, and M8 are all connected to the node between the resistors R11 and R12. The drain of MOS transistor M1 is connected to the output terminal V0 of the digital logic control module (103). The drain of MOS transistor M2 is connected to the node between resistors R4 and R5. The drain of MOS transistor M3 is connected to the node between resistors R5 and R6. The drain of MOS transistor M4 is connected to the node between resistors R6 and R7. The drain of MOS transistor M5 is connected to the node between resistors R7 and R8. The drain of MOS transistor M6 is connected to the node between resistors R8 and R9. The drain of MOS transistor M7 is connected to the node between resistors R9 and R10. The drain of MOS transistor M8 is connected to the node between resistors R10 and R11. The input terminal VB of the digital logic control module (103) is connected to the node between resistors R12 and R13.

2. The fast-response, low-ripple voltage regulator circuit without external capacitors or inductors according to claim 1, characterized in that, The cross-coupled charge pump (101) includes NMOS transistors MN1, MN2, MN3, MN4, MN5, and MN6, PMOS transistors MP1, MP2, MP3, MP4, MP5, and MP6, and capacitors C1, C2, and C3. The drains of NMOS transistors MN1 and MN2 are both connected to the input terminal of the cross-coupled charge pump for inputting the original power supply voltage VIN. The gate of NMOS transistor MN1 is simultaneously connected to the gate of PMOS transistor MP1, the source of NMOS transistor MN2, the gate of NMOS transistor MN5, the drain of NMOS transistor MN6, the drain of PMOS transistor MP2, the drain of PMOS transistor MP5, and the gate of PMOS transistor MP6. The source of NMOS transistor MN1 is simultaneously connected to the drain of NMOS transistor MN4, the gate of NMOS transistor MN3, the gate of NMOS transistor MN2, the gate of PMOS transistor MP2, the drain of PMOS transistor MP3, the gate of PMOS transistor MP4, and the drain of PMOS transistor MP1. The drain of NMOS transistor MN3 and the gate of NMOS transistor MN4 are connected to the drain of NMOS transistor MN1, and the source of NMOS transistor MN3 and the source of NMOS transistor MN4 are connected to the substrate of NMOS transistor MN1; the drain of NMOS transistor MN5 and the gate of NMOS transistor MN6 are connected to the drain of NMOS transistor MN2, and the source of NMOS transistor MN5 and the source of NMOS transistor MN6 are connected to the substrate of NMOS transistor MN2. The source of PMOS transistor MP1 is simultaneously connected to the drain of PMOS transistor MP4, the gate of PMOS transistor MP3, the source of PMOS transistor MP2, the drain of PMOS transistor MP6, and the gate of PMOS transistor MP5. The source of PMOS transistor MP1 serves as the output terminal of the cross-coupled charge pump (101) for inputting the processed voltage VDDA. The sources of PMOS transistor MP3 and PMOS transistor MP4 are both connected to the substrate of PMOS transistor MP1. The sources of PMOS transistor MP5 and PMOS transistor MP6 are both connected to the substrate of PMOS transistor MP2. One end of capacitor C1 is connected to the source of NMOS transistor MN2, and the other end is connected to the first clock signal input terminal for inputting the first clock signal CLK. One end of capacitor C2 is connected to the source of NMOS transistor MN1, and the other end is connected to the second clock signal input terminal for inputting the second clock signal CLKN. One end of capacitor C3 is connected to the source of PMOS transistor MP1, and the other end is connected to the ground terminal GND.

3. The fast-response, low-ripple voltage regulator circuit without external capacitors or inductors according to claim 2, characterized in that, The first clock signal CLK and the second clock signal CLKN are complementary clock signals with the same amplitude but opposite directions.

4. The fast-response, low-ripple voltage regulator circuit without external capacitors or inductors according to claim 2, characterized in that, The error amplifier module (102) includes PMOS transistors MP20, MP21, MP22, MP23, NMOS transistors MN27, MN28, MN29, MN30, and MN31, wherein... The sources of PMOS transistors MP20, MP21, MP22, and MP23 are all connected to the output terminal of the cross-coupled charge pump (101). The gate of PMOS transistor MP20 is connected to the gate of PMOS transistor MP21, the drain of PMOS transistor MP21, and the drain of NMOS transistor MN28. The gate of PMOS transistor MP23 is connected to the gate of PMOS transistor MP22, the drain of PMOS transistor MP22, and the drain of NMOS transistor MN27. The drain of the PMOS transistor MP20 is connected to the drain of the NMOS transistor MN30 and the output terminal V0 of the digital logic control module. The drain of the PMOS transistor MP23 is connected to the drain of the NMOS transistor MN29, the gate of the NMOS transistor MN29 and the gate of the NMOS transistor MN30. The gate of NMOS transistor MN27 is connected to the reference voltage VREF. The gate of NMOS transistor MN28 is connected to the input terminal VB of the digital logic control module (103). The source of NMOS transistor MN27 and the source of NMOS transistor MN28 are both connected to the drain of NMOS transistor MN31. The source of NMOS transistor MN29, the source of NMOS transistor MN30 and the source of NMOS transistor MN31 are all connected to the ground terminal GND. The gate of NMOS transistor MN31 is connected to the low dropout linear regulator (104).

5. The fast-response, low-ripple voltage regulator circuit without external capacitors or inductors according to claim 4, characterized in that, The low-dropout linear regulator (104) includes PMOS transistors MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, MP17, MP18, MP19, and NMOS transistors MN7, MN8, MN9, MN10, and NMOS. The following transistors are used: S-channel transistor MN11, NMOS transistors MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19, MN20, MN21, MN22, MN23, MN24, MN25, MN26; capacitors C4 and C5; and resistors R1, R2, and R3. The sources of PMOS transistors MP7, MP8, MP9, MP10, MP11, MP18, and MP19 are all connected to the output terminal of the cross-coupled charge pump (101). The gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP8, the drain of PMOS transistor MP8, the drain of NMOS transistor MN22, and the gate of NMOS transistor MN22. The drain of PMOS transistor MP7 is connected to the drain of NMOS transistor MN7, the gate of NMOS transistor MN7, and the gate of PMOS transistor MP9. The drain of PMOS transistor MP9 is connected to the source of PMOS transistor MP14, the source of PMOS transistor MP16, and the source of PMOS transistor MP17. The gate of PMOS transistor MP10 is connected to the gate of PMOS transistor MP11, the gate of PMOS transistor MP18, the gate of PMOS transistor MP19, the drain of PMOS transistor MP18, and the drain of NMOS transistor MN23. The drain of PMOS transistor MP10 is connected to the drain of NMOS transistor MN13, the gate of NMOS transistor MN13, and the gate of NMOS transistor MN14. The drain of PMOS transistor MP11 is connected to the drain of NMOS transistor MN16, the gate of NMOS transistor MN16, and the gate of NMOS transistor MN15. The drain of PMOS transistor MP19 is connected to the drain of NMOS transistor MN24, the gate of NMOS transistor MN24, and the gate of NMOS transistor MN23. The sources of PMOS transistors MP12, MP13, and MP15 are all connected to the output terminal V0 of the digital logic control module. The gate of PMOS transistor MP12 is connected to the gate of PMOS transistor MP13, the gate of PMOS transistor MP14, the drain of PMOS transistor MP14, and the drain of NMOS transistor MN14. The drain of PMOS transistor MP12 is connected to the drain of NMOS transistor MN8, the gate of NMOS transistor MN9, and the gate of NMOS transistor MN10. The drain of PMOS transistor MP13 is connected to the drain of NMOS transistor MN17, the gate of NMOS transistor MN17, and the gate of NMOS transistor MN18. The gate of PMOS transistor MP15 is connected to the drain of PMOS transistor MP15, the drain of NMOS transistor MN15, the gate of PMOS transistor MP16, and the gate of PMOS transistor MP17. The drain of PMOS transistor MP16 is connected to the drain of NMOS transistor MN12, the gate of NMOS transistor MN12, and the gate of NMOS transistor MN11. The drain of PMOS transistor MP17 is connected to the drain of NMOS transistor MN19, the gate of NMOS transistor MN20, and the gate of NMOS transistor MN21. The source of NMOS transistor MN7 is connected to the drain of NMOS transistor MN9, the gate of NMOS transistor MN8 is connected to the gate of NMOS transistor MN23, and the source of NMOS transistor MN8 is connected to the drain of both NMOS transistor MN10 and NMOS transistor MN11. The sources of NMOS transistors MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN20, MN21, and MN26 are all connected to the ground terminal GND. The drain of NMOS transistor MN18 is connected to the drain of NMOS transistor MN20 and the source of NMOS transistor MN19; the gate of NMOS transistor MN19 is connected to the gate of NMOS transistor MN23; and the drain of NMOS transistor MN21 is connected to the source of NMOS transistor MN22. The source of the NMOS transistor MN24 is connected to the drain of the NMOS transistor MN26, the gate of the NMOS transistor MN26, the gate of the NMOS transistor MN25, and the gate of the NMOS transistor MN31 in the error amplifier module (102); the drain of the NMOS transistor MN25 is connected to the source of the NMOS transistor MN23. The resistor R1 and the capacitor C4 are connected in series between the gate and drain of the PMOS transistor MP9, the resistor R2 and the capacitor C5 are connected in parallel between the drain of the PMOS transistor MP9 and the ground terminal GND, the resistor R3 is connected between the source of the NMOS transistor MN25 and the ground terminal GND, and the drain of the PMOS transistor MP9 serves as the output terminal VOUT of the low dropout linear regulator (104).

6. The fast-response, low-ripple voltage regulator circuit without external capacitors or inductors according to claim 5, characterized in that, The PMOS transistors MP10 and MP11 have the same width-to-length ratio.

Images