Signaling device, receiving device, transmission system, transmission method and chip

Abstract

The application discloses a signal sending device, a receiving device, a transmission system, a transmission method and a chip. The signal sending device is connected with a signal receiving end through a bus, and positive and reverse signal lines of the bus are respectively connected with two ends of a terminal resistance in the signal receiving end. The signal sending device comprises a driving module for sending a data signal through the bus, and a detection module connected with the bus and used for obtaining a feedback signal of the signal receiving end according to a sending end voltage difference of the positive and reverse signal lines. When the sending end voltage difference is greater than / equal to a set threshold value, the feedback signal represents that the terminal resistance is disconnected with the positive and / or reverse signal line in the signal receiving end. Therefore, the feedback signal of the signal receiving end can be obtained by the signal sending end without other transmission channels, and channel resources are saved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a signal transmitting device, a receiving device, a transmission system, a transmission method, and a chip. Background Technology

[0002] LVDS (Low-Voltage Differential Signaling) has advantages such as low power consumption, low bit error rate, low crosstalk and strong integration capability, making it very suitable for high-frequency and high-speed transmission environments, and it has been widely used in fields such as display and image sampling, aviation and aerospace.

[0003] A traditional LVDS transmission system consists of three parts: a transmitter, a receiver, and a terminating resistor. The transmitter converts the input electrical signal into a differential current signal. This current passes through a terminating resistor, for example, a 100Ω resistor, creating a voltage difference across the resistor. The receiver then converts this differential voltage signal into a logic level to achieve data transmission.

[0004] However, in traditional LVDS signal transmission, data can only be transmitted in one direction (i.e., from the sender to the receiver). If a data transmission error occurs or there is a signal that needs to be fed back, it cannot be transmitted back through the same channel. Instead, it is necessary to use SPI / I2C to access the data status in the integrated circuit or to use GPIO to transmit specific signals, thereby enabling communication between the host and the integrated circuit.

[0005] Therefore, there is an urgent need for a new signal transmitting device, receiving device, transmission system, transmission method, and chip. Summary of the Invention

[0006] In view of the above problems, the purpose of this application is to provide a signal transmitting device, receiving device, transmission system, transmission method and chip that do not require other transmission channels, and the signal transmitting end can obtain the feedback signal from the signal receiving end, thus saving channel resources.

[0007] According to one aspect of this application, a signal transmitting device is provided, which is connected to a signal receiving end via a bus. A forward signal line and a reverse signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving end. The signal transmitting device includes: a driving module for transmitting data signals via the bus; and a detection module connected to the bus for obtaining a feedback signal from the signal receiving end based on the voltage difference between the transmitting ends of the forward signal line and the reverse signal line. When the voltage difference at the transmitting end is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the forward signal line and / or the reverse signal line at the signal receiving end.

[0008] Optionally, the driving module is further configured to send a verification signal via the bus, the verification signal being used to verify whether the data signal is transmitted abnormally.

[0009] Optionally, the signal transmitting device further includes a frequency modulation module, which is used to modulate the transmission frequency of the data signal in at least one transmission stage, so that the transmission frequency of the data signal in each of the transmission stages respectively characterizes each check code of the check signal, and different transmission frequencies correspond to different values ​​of the check codes.

[0010] Optionally, the transmission stages can be divided according to the transmission duration or according to the length of the transmitted data signal.

[0011] Optionally, the verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

[0012] According to another aspect of this application, a signal receiving device is provided, which is connected to a signal transmitting end via a bus. The forward signal line and the reverse signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving device end. The signal receiving device includes: a receiving module for receiving data signals and verification signals via the bus; and a control module connected to the two ends of the terminating resistor for determining whether the data signal is abnormally transmitted based on the verification signal, and disconnecting the connection between the terminating resistor and the forward signal line and / or the reverse signal line when a transmission abnormality occurs, so that the bus provides a corresponding feedback signal at the signal transmitting end.

[0013] Optionally, the transmission frequency of the data signal during at least a partial transmission phase represents each check code of the verification signal, and different transmission frequencies correspond to different values ​​of the check codes. The signal receiving device further includes a frequency detection module for detecting the transmission frequency of the data signal to receive the verification signal.

[0014] Optionally, the transmission stages can be divided according to the transmission duration or according to the length of the transmitted data signal.

[0015] Optionally, the verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

[0016] According to a third aspect of this application, a signal transmission system is provided, including a signal transmitting device and a signal receiving device connected via a bus. A forward signal line and a reverse signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving end. The signal transmitting device includes: a driving module for transmitting data signals via the bus; and a detection module connected to the bus for obtaining a feedback signal at the signal receiving end based on the voltage difference between the transmitting ends of the forward and reverse signal lines. When the voltage difference at the transmitting ends is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the forward and / or reverse signal lines at the signal receiving end. The signal receiving device includes: a receiving module for receiving data signals and a verification signal via the bus; and a control module connected to the two ends of the terminating resistor for determining whether the data signal transmission is abnormal based on the verification signal, and disconnecting the terminating resistor from the forward and / or reverse signal lines when transmission is abnormal, so that the bus provides a corresponding feedback signal at the signal transmitting end.

[0017] Optionally, the signal transmitting device further includes a frequency modulation module, which is used to modulate the transmission frequency of the data signal in at least one transmission stage, so that the transmission frequency of the data signal in each transmission stage respectively represents each check code of the verification signal, and different transmission frequencies correspond to different values ​​of the check codes; the signal receiving device further includes a frequency detection module, which is used to detect the transmission frequency of the data signal to receive the verification signal.

[0018] Optionally, the transmission stages can be divided according to the transmission duration or according to the length of the transmitted data signal.

[0019] Optionally, the verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

[0020] According to a fourth aspect of this application, a chip is provided, including a signal transmitting device as described in any of the preceding claims or a signal receiving device as described in any of the preceding claims.

[0021] According to a fifth aspect of this application, a signal transmission method is provided, comprising: transmitting a data signal and a verification signal from a signal transmitting end to a signal receiving end via a bus, wherein a forward signal line and a reverse signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving end; determining at the signal receiving end whether the data signal transmission is abnormal through the verification signal, and disconnecting the terminating resistor from the forward signal line and / or the reverse signal line at the signal receiving end when the data signal transmission is abnormal; and obtaining a feedback signal at the signal receiving end based on the voltage difference between the transmitting ends of the forward signal line and the reverse signal line, wherein when the voltage difference between the transmitting ends is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the forward signal line and / or the reverse signal line at the signal receiving end.

[0022] Optionally, the signal transmission method further includes: modulating the transmission frequency of the data signal in at least one transmission stage at the signal transmitting end, such that the transmission frequency of the data signal in each transmission stage characterizes a check code of the check signal, and different transmission frequencies correspond to different values ​​of the check code; and detecting the transmission frequency of the data signal at the signal receiving end to obtain the check signal.

[0023] Optionally, the transmission stages can be divided according to the transmission duration or according to the length of the transmitted data signal.

[0024] Optionally, the check signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy check algorithm, and parity check algorithm.

[0025] According to the signal transmitting device, receiving device, transmission system, transmission method, and chip provided in this application, when a data signal transmission is abnormal, the terminating resistor at the signal end is disconnected, causing the detection module to detect an increase in the voltage difference between the transmitting ends of the forward and reverse signal lines, and using this voltage difference change as a feedback signal at the signal receiving end. Therefore, no other transmission channel is needed; the signal transmitting end can obtain the feedback signal from the signal receiving end, saving channel resources.

[0026] Furthermore, in this application, the transmission frequency of the data signal is modulated according to the verification signal, so that the verification signal is transmitted along with the data signal without needing to occupy a separate data length, which can further reduce the consumption of transmission time and bandwidth and improve transmission efficiency.

[0027] Furthermore, in this application, by including error correction codes generated by ECC encoding in the verification signal, the data signal can self-check and correct errors in transmission, thereby improving the reliability of data transmission and reducing transmission time and bandwidth consumption. Attached Figure Description

[0028] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a schematic structural block diagram of the signal transmission system according to the first embodiment of this application;

[0030] Figure 2A A schematic circuit diagram of the signal transmission system according to an embodiment of this application is shown during the transmission phase.

[0031] Figure 2B A schematic circuit diagram of the signal transmission system in the feedback phase according to an embodiment of this application is shown;

[0032] Figure 3A The equivalent circuit diagram of the transmission stage of a current-driven signal transmission system is shown.

[0033] Figure 3B The equivalent circuit diagram of the feedback stage of a current-driven signal transmission system is shown.

[0034] Figure 4A The equivalent circuit diagram of the transmission stage of a voltage-driven signal transmission system is shown.

[0035] Figure 4B The equivalent circuit diagram of the feedback stage of a voltage-driven signal transmission system is shown.

[0036] Figure 5 This diagram illustrates a schematic structural block diagram of a signal transmission system according to a second embodiment of this application.

[0037] Figure 6 This diagram illustrates the correspondence between signal transmission frequency and check signal encoding.

[0038] Figure 7 A flowchart illustrating the signal transmission method is shown.

[0039] Figure 8 A flowchart illustrating the signal receiving method is shown.

[0040] Figure 9 This is a schematic flowchart illustrating a signal transmission method according to an embodiment of this application. Detailed Implementation

[0041] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0042] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0043] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0044] Figure 1 A schematic structural block diagram of the signal transmission system according to the first embodiment of this application is shown. Figure 1 As shown, the signal transmission system 100 includes a signal transmitting device 110 and a signal receiving device 120. Multiple buses 130 are connected between the signal transmitting device 110 and the signal receiving device 120, and the positive and negative signal lines of the buses are respectively connected to the two ends of a terminating resistor at the signal receiving device 120.

[0045] Furthermore, such as Figure 1 As shown, the signal transmitting device 110 includes a driving module 111 and a detection module 112, both connected to a bus. The driving module 111 transmits data signals and verification signals via the bus, and the detection module 112 detects the voltage difference between the transmitting ends of the forward and reverse signal lines. The signal receiving device 120 includes a receiving module 121 and a control module 122. The receiving module 121 receives data signals and verification signals via the bus, and the control module 122 is connected to both ends of a terminating resistor. It determines whether the data signal transmission is abnormal based on the verification signal and disconnects the terminating resistor from the forward and / or reverse signal lines when transmission is abnormal.

[0046] Figure 2A and Figure 2BSchematic circuit diagrams of the signal transmission system according to an embodiment of this application are shown in the transmission and feedback phases, respectively. Taking a single bus as an example, as follows... Figure 2A As shown, the forward signal line is connected between the non-inverting terminals Dout+ and Rin+ of the driving module 111 and the receiving module 121; the reverse signal line is connected between the reverse terminals Dout- and Rin- of the driving module 111 and the receiving module 121, and the forward and reverse signal lines are respectively connected to the two ends of the terminating resistor Rt at the signal receiving device 120. The driving module 111 converts the single-ended signal Din into a differential signal and sends it out. Specifically, in this embodiment, the signal sent by the driving module 111 includes a data signal and a verification signal used to verify whether the data signal is transmitted abnormally. The receiving module 121 receives the differential signal from the driving module 111 and parses it, thereby converting the differential signal into a signal Rout in a usable format (e.g., parallel data or serial data). The control module 122 verifies the data signal according to the parsed verification signal, thereby determining whether the data signal is transmitted abnormally. In the case of transmission abnormality, such as Figure 2B As shown, the control module 122 disconnects the terminating resistor Rt from the forward signal line and / or the reverse signal line, causing a larger voltage difference between the transmitting end of the forward and reverse signal lines. Therefore, when the detection module 112 detects that the voltage difference at the transmitting end is greater than or equal to a set threshold, it indicates that the terminating resistor Rt is disconnected from the forward signal line and / or the reverse signal line, i.e., the data signal transmission is abnormal. Therefore, feedback signals from the receiving device can be obtained without using other transmission channels, saving channel resources.

[0047] Signal transmission systems typically employ two driving methods: current-driven and voltage-driven. Current-driven transmission transmits data by controlling the current output from the transmitting end. The driving module adjusts the output current based on changes in the logic level of the input signal. The receiving end determines the logic level of the input signal based on the received current magnitude. Voltage-driven transmission transmits data by controlling the voltage output from the transmitting end. The driving module adjusts the output voltage based on changes in the logic level of the input signal. The receiving end determines the logic level of the input signal based on the received voltage magnitude.

[0048] Figure 3A and Figure 3B The equivalent circuit diagrams of the transmitting and receiving ends of a current-driven signal transmission system are shown respectively during the transmission and feedback phases. For example... Figure 3A and 3B As shown, in a current-driven signal transmission system, the resistance relationship between the signal transmitting device 110 and the signal receiving device 120 can be equivalent to resistors R1 and R2 connected in parallel, where resistor R1 is the transmitting end resistance, resistor R2 is the terminating resistance, and current source I supplies power to resistors R1 and R2. During the transmission phase, see... Figure 3A Resistors R1 and R2 are connected in parallel and in series with current source I. At this time, the voltage across resistor R1 (i.e., the voltage difference between the forward and reverse signal lines detected by detection module 112) is V1. During the feedback phase, see... Figure 3B With resistor R2 disconnected and resistor R1 connected in series with current source I, the voltage across resistor R1 (i.e., the voltage difference between the forward and reverse signal lines detected by detection module 112) is V1'. Based on the relationship between parallel resistors, it can be determined that when resistor R2 is disconnected, V1' > V1. In some embodiments, for example, if both resistors R1 and R2 are 100Ω, then V1'...

[0049] =2V1.

[0050] Figure 4A and Figure 4B The equivalent circuit diagrams of the transmitting and receiving ends of a voltage-driven signal transmission system are shown respectively during the transmission and feedback phases. Figure 4A and 4B As shown, in a voltage-driven signal transmission system, the resistance relationship between the signal transmitting device 110 and the signal receiving device 120 can be equivalent to resistors R3, R4, and R5 connected in series, where resistors R3 and R4 are the transmitting end resistances, and resistor R5 is the terminating resistance. During the transmission phase, see... Figure 4A During the transmission phase, resistors R3, R4, and R5 are connected in series and powered by the supply voltage (e.g., 0.4V). At this time, the voltage between the forward and reverse signal lines (i.e., the voltage difference between the forward and reverse signal lines detected by the detection module 112) is V2. During the feedback phase, see... Figure 4B When resistor R5 is disconnected, the voltage between the forward and reverse signal lines (i.e., the voltage difference between the forward and reverse signal lines detected by detection module 112) is V2', which is the supply voltage. Based on the voltage division relationship of the series resistors, it can be determined that when resistor R5 is disconnected, V2' > V2.

[0051] In summary, disconnecting the terminating resistor when a data signal transmission anomaly is detected will cause the voltage difference between the forward and reverse signal lines to increase (e.g., double the voltage during transmission). Therefore, when the voltage difference between the forward and reverse signal lines at the transmitting end detected by the detection module 112 is greater than or equal to a set threshold, the terminating resistor is determined to be open, indicating a data signal transmission anomaly. This eliminates the need for additional transmission channels to report the anomaly to the transmitting end, saving channel resources and reducing system complexity and cost.

[0052] However, it should be understood that in some embodiments, when the terminating resistor is connected to the forward signal line and the reverse signal line respectively, the voltage difference between the forward and reverse signal lines detected by the detection module is used as the aforementioned set threshold. In some other embodiments, the size of this set threshold can be determined according to actual needs. For example, to reduce the influence of bus noise on the voltage difference between the forward and reverse signal lines, the set threshold can be slightly larger than the voltage difference between the forward and reverse signal lines detected by the detection module when the terminating resistor is connected to the forward and reverse signal lines respectively.

[0053] Figure 5 A schematic structural block diagram of a signal transmission system according to a second embodiment of this application is shown. Figure 5 As shown, the signal transmission system 200 includes a signal transmitting device 210 and a signal receiving device 220. Multiple buses 230 are connected between the signal transmitting device 210 and the signal receiving device 220, and the positive and negative signal lines of the buses are respectively connected to the two ends of a terminating resistor at the signal receiving device 220.

[0054] The signal transmission system 200 of the second embodiment of this application differs from the signal transmission system 100 of the first embodiment of this application in that the signal transmitting device 210 further includes a frequency modulation module 213 connected to the driving module, and the signal receiving device 220 further includes a frequency detection module 223 connected to the receiving module 221 and the control module 222 respectively.

[0055] The frequency modulation module 213 modulates the transmission frequency of the data signal in at least one transmission stage, so that the transmission frequency of the data signal in each transmission stage represents a different check code of the check signal, with different transmission frequencies corresponding to different check codes. For example, if the check signal includes multiple binary bits, then the check signal includes two check codes: "0" and "1". See also... Figure 6 In some embodiments, a first transmission frequency of the data signal represents the value "0" and a second transmission frequency represents the value "1". The change in the transmission frequency of the data signal represents the check codes of the check signal. The check signal does not need to occupy the data length, which can further reduce the consumption of transmission time and bandwidth and improve transmission efficiency.

[0056] Correspondingly, in the signal receiving device 220, the frequency detection module 223 detects the transmission frequency of the data signal, records the change state of the transmission frequency, and looks up the value corresponding to the periodic change of the transmission frequency through a lookup table, thereby obtaining the corresponding verification signal.

[0057] In some embodiments, the transmission stages are divided according to the transmission duration. For example, the transmission frequency of the data signal in the first transmission duration corresponds to the first checksum of the check signal, the transmission frequency of the data signal in the second transmission duration corresponds to the second checksum of the check signal, and so on. However, it should be understood that the correspondence between the transmission frequency of the data signal and the check signal should not be limited thereto. For example, in some other embodiments, the transmission stages are divided according to the length of the transmitted data signal. For example, the transmission frequency of the first m bits of the data signal corresponds to the first checksum of the check signal, the transmission frequency of the next n bits of the data signal corresponds to the second checksum of the check signal, and so on (n and m are integers and n may be the same as or different from m).

[0058] In the various embodiments of this application, the encoding algorithm for obtaining the check signal is not limited. For example, in some embodiments, the check signal can be obtained by encoding with algorithms such as CRC (Cyclic Redundancy Check) or parity check. In a preferred embodiment, the check signal is obtained by encoding with the ECC (Error Correction Code) algorithm. In the event of abnormal data signal transmission, the control module can also correct the abnormal data signal based on the check signal. Therefore, even if the data signal is interfered with or damaged during transmission, it can self-check and correct these errors, improving the reliability of data transmission, reducing the number of retransmissions, and thus reducing transmission time and bandwidth consumption. Furthermore, in some other embodiments, especially in the case of long-distance transmission, the check signal may also include a check code obtained by multiple encoding algorithms to improve overall transmission efficiency and performance.

[0059] Figure 7 This diagram illustrates a flow chart of a signal transmission method using a signal transmission device according to an embodiment of this application. Figure 7 As shown, the signal transmission method includes the following steps:

[0060] Step S110: Send data signal and verification signal:

[0061] In this step, the signal transmitting device sends data signals and verification signals to the signal receiving end via a bus. The positive and negative signal lines of the bus are connected to the two ends of a terminating resistor at the signal receiving end, respectively. Specifically, in this embodiment, the driving module converts the single-ended signal into an LVDS (differential signal) and transmits it through multiple buses. In some embodiments, the transmission frequency of the data signal is modulated in at least one transmission stage so that the transmission frequency of the data signal in each transmission stage represents a different checksum of the verification signal. This eliminates the need for the verification signal to occupy a separate data length, further reducing transmission time and bandwidth consumption and improving transmission efficiency.

[0062] In the embodiments of this application, the method of dividing the transmission stage is not limited. For example, in some embodiments, the transmission stages are divided according to the transmission duration, and in other embodiments, the transmission stages are divided according to the length of the transmitted data signal.

[0063] The encoding algorithm for obtaining the check signal is not limited in the various embodiments of this application. For example, in some embodiments, the check signal can be obtained by encoding with algorithms such as CRC (Cyclic Redundancy Check) or parity check. In a preferred embodiment, the check signal is obtained by encoding with ECC (Error Correction Code) algorithm. In the event of abnormal data signal transmission, the control module can also correct the abnormal data signal based on the check signal. Therefore, even if the data signal is interfered with or damaged during transmission, it can self-check and correct these errors, improving the reliability of data transmission, reducing the number of retransmissions, and thus reducing transmission time and bandwidth consumption. Furthermore, in some other embodiments, especially in the case of long-distance transmission, the check signal may also include a check code obtained by multiple encoding algorithms to further save bandwidth consumption.

[0064] Step S120: Detect the voltage difference between the transmitting ends of the forward signal line and the reverse signal line.

[0065] In this step, the feedback signal at the receiving end is obtained by detecting the voltage difference between the transmitting end of the forward signal line and the reverse signal line. When the voltage difference at the transmitting end is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the forward signal line and / or the reverse signal line at the signal receiving end.

[0066] However, it should be understood that in some embodiments, when the terminating resistor is connected to the forward signal line and the reverse signal line respectively, the voltage difference between the forward and reverse signal lines detected by the detection module is used as the aforementioned set threshold. In some other embodiments, the size of this set threshold can be determined according to actual needs. For example, to reduce the influence of bus noise on the voltage difference between the forward and reverse signal lines, the set threshold can be slightly larger than the voltage difference between the forward and reverse signal lines detected by the detection module when the terminating resistor is connected to the forward and reverse signal lines respectively.

[0067] Figure 8 This diagram illustrates a flow chart of a signal receiving method using a signal receiving device according to an embodiment of this application. Figure 8 As shown, the signal receiving method includes the following steps:

[0068] Step S210: Receive data signal and verification signal:

[0069] In this step, the signal receiving device receives the data signal and check signal transmitted by the signal transmitting end via a bus. The positive and negative signal lines of the bus are connected to the two ends of a terminating resistor at the signal receiving end, respectively. Specifically, in this embodiment, the receiving module converts the received LVDS signal into a usable format data signal and check signal. In some embodiments, if the check codes of the check signal are characterized by the transmission frequency of the data signal, the transmission frequency of the data signal is detected simultaneously with the data signal, and the change state of the transmission frequency is recorded. A lookup table is then used to find the value corresponding to the periodic change of the transmission frequency, thereby parsing the corresponding check signal according to the different codes corresponding to the transmission frequency. This eliminates the need for the check signal to occupy a separate data length, further reducing transmission time and bandwidth consumption, and improving transmission efficiency.

[0070] Step S220: Verify whether the data signal transmission is abnormal based on the verification signal.

[0071] In this step, the control module of the signal receiving device verifies the data signal based on the verification signal to determine whether the data signal transmission is abnormal. If an abnormality occurs, the connection between the forward and / or reverse signal lines and the terminating resistor is disconnected, allowing the bus to provide a corresponding feedback signal at the signal transmitting end.

[0072] Figure 9 A schematic flowchart of the signal transmission method provided in this application is shown. Figure 9 As shown, the transmission method provided in this application includes the following steps:

[0073] Step S10: Send data signal and verification signal:

[0074] In this step, the signal transmitting end sends a data signal and a verification signal to the signal receiving end via the bus. The verification signal is used to verify whether the data signal transmission is abnormal. The positive and negative signal lines of the bus are connected to the two ends of the terminating resistor at the signal receiving end, respectively. Specifically, in this embodiment, the driving module 111 converts the single-ended signal into an LVDS signal (differential signal) and sends it through multiple buses.

[0075] In some embodiments, the transmission frequency of the data signal is modulated within at least one transmission stage, so that the transmission frequency of the data signal in each transmission stage represents a check code of the check signal, thereby eliminating the need for the check signal to occupy a separate data length, further reducing transmission time and bandwidth consumption, and improving transmission efficiency. For example, if the check signal includes multiple binary bits, then the check signal includes two check codes, namely "0" and "1". In some embodiments, a first transmission frequency of the data signal represents the code "0"; a second transmission frequency represents the code "1". By characterizing the check signal through changes in the data signal transmission frequency, transmission time and bandwidth consumption can be further reduced, improving transmission efficiency. In the embodiments of this application, the method of dividing the transmission stages is not limited. For example, in some embodiments, the transmission stages are divided according to the transmission duration, while in other embodiments, the transmission stages are divided according to the length of the transmitted data signal.

[0076] The encoding algorithm for obtaining the check signal is not limited in the various embodiments of this application. For example, in some embodiments, the check signal can be obtained by encoding with algorithms such as CRC (Cyclic Redundancy Check) or parity check. In a preferred embodiment, the check signal is obtained by encoding with ECC (Error Correction Code) algorithm. In the event of abnormal data signal transmission, the control module can also correct the abnormal data signal based on the check signal. Therefore, even if the data signal is interfered with or damaged during transmission, it can self-check and correct these errors, improving the reliability of data transmission, reducing the number of retransmissions, and thus reducing transmission time and bandwidth consumption. Furthermore, in some other embodiments, especially in the case of long-distance transmission, the check signal may also include a check code obtained by multiple encoding algorithms to further save bandwidth consumption.

[0077] Step S20: Receive data signal and verification signal:

[0078] In this step, the signal receiving end receives the data signal and the verification signal sent by the signal transmitting end via the bus. Specifically, in the embodiments of this application, the receiving module of the signal receiving device receives the LVDS signal and parses it into a usable format.

[0079] In some embodiments, if the data signal transmission frequency represents each check code of the check signal, the data signal transmission frequency is detected while the data signal is received, and the change state of the transmission frequency is recorded. The value corresponding to the periodic change of the transmission frequency is found by looking up a lookup table, and the corresponding check signal is obtained by parsing the different codes corresponding to the transmission frequency.

[0080] Step S30: Determine whether the data signal transmission is abnormal based on the verification signal:

[0081] In this step, the control module determines whether the data signal is transmitted normally based on the verification signal. If the transmission is normal, the reception is completed; if the transmission is abnormal, the connection between the terminating resistor and the positive signal line and / or the reverse signal line of the signal receiving end is disconnected.

[0082] Step S40: Voltage detection:

[0083] In this step, the detection module detects the voltage difference between the transmitting ends of the forward and reverse signal lines. If a transmission anomaly occurs, the terminating resistor is disconnected, increasing the voltage difference between the forward and reverse signal lines. When this voltage difference is greater than or equal to a set threshold, the terminating resistor is determined to be disconnected, indicating a data signal transmission anomaly. Therefore, the receiving end does not require additional transmission channels to report the anomaly to the transmitting end, conserving signal resources.

[0084] This application also provides a chip, which includes the signal transmitting device or signal receiving device as described above, and therefore also has the beneficial effects described above, which will not be repeated here.

[0085] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A signal transmitting device, connected to a signal receiving end via a bus, wherein the positive signal line and the negative signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving end, wherein, The signal transmitting device includes: The driver module is used to transmit data signals via the bus, and the driver module is also used to transmit a verification signal via the bus, the verification signal being used to verify whether the data signal is transmitted abnormally; and A detection module, connected to the bus, is used to obtain the feedback signal from the signal receiving end based on the voltage difference between the transmitting ends of the positive signal line and the negative signal line. When the voltage difference at the transmitting end is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the positive signal line and / or the reverse signal line at the signal receiving end.

2. The signal transmitting device according to claim 1, wherein, The signal transmitting device further includes a frequency modulation module, which is used to modulate the transmission frequency of the data signal in at least one transmission stage, so that the transmission frequency of the data signal in each transmission stage respectively represents each check code of the check signal, and different transmission frequencies correspond to different values ​​of the check codes.

3. The signal transmitting device according to claim 2, wherein, The transmission stages are divided according to the transmission duration or according to the length of the transmitted data signal.

4. The signal transmitting device according to claim 1, wherein, The verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

5. A signal receiving device, connected to a signal transmitting end via a bus, wherein the positive signal line and the negative signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving end, wherein, The signal receiving device includes: A receiving module is used to receive data signals and verification signals via the bus; and The control module is connected to both ends of the terminating resistor and is used to determine whether the data signal is transmitted abnormally based on the verification signal. If the transmission is abnormal, the connection between the terminating resistor and the positive signal line and / or the reverse signal line is disconnected, so that the bus provides a corresponding feedback signal at the signal transmitting end.

6. The signal receiving device according to claim 5, wherein, The transmission frequencies of the data signal during at least a partial transmission phase respectively characterize each check code of the check signal, with different transmission frequencies corresponding to different values ​​of the check codes. The signal receiving device further includes: A frequency detection module is used to detect the transmission frequency of the data signal in order to receive the verification signal.

7. The signal receiving device according to claim 6, wherein, The transmission stages are divided according to the transmission duration or according to the length of the transmitted data signal.

8. The signal receiving device according to claim 6, wherein, The verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

9. A signal transmission system, comprising a signal transmitting device and a signal receiving device connected via a bus, wherein the forward signal line and the reverse signal line of the bus are respectively connected to the two ends of a terminating resistor at the signal receiving end, wherein, The signal transmitting device includes: The driver module is used to transmit data signals via the bus, and the driver module is also used to transmit a verification signal via the bus, the verification signal being used to verify whether the data signal is transmitted abnormally; and A detection module, connected to the bus, is used to obtain the feedback signal from the signal receiving end based on the voltage difference between the transmitting ends of the positive signal line and the negative signal line. When the voltage difference at the transmitting end is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the positive signal line and / or the reverse signal line at the signal receiving end. The signal receiving device includes: A receiving module is used to receive data signals and verification signals via the bus; and The control module, connected to both ends of the terminating resistor, is used to determine whether the data signal is transmitted abnormally based on the verification signal, and disconnect the terminating resistor from the positive signal line and / or the reverse signal line when the transmission is abnormal, so that the bus provides a corresponding feedback signal at the signal transmitting end.

10. The signal transmission system according to claim 9, wherein, The signal transmitting device further includes a frequency modulation module, which is used to modulate the transmission frequency of the data signal in at least one transmission stage, so that the transmission frequency of the data signal in each transmission stage respectively characterizes each check code of the check signal, and different transmission frequencies correspond to different values ​​of the check codes. The signal receiving device further includes a frequency detection module for detecting the transmission frequency of the data signal in order to receive the verification signal.

11. The signal transmission system according to claim 10, wherein, The transmission stages are divided according to the transmission duration or according to the length of the transmitted data signal.

12. The signal transmission system according to claim 10, wherein, The verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

13. A chip comprising a signal transmitting device as described in any one of claims 1 to 4 or a signal receiving device as described in any one of claims 5 to 8.

14. A signal transmission method, comprising: Data signals and verification signals are sent from the signal transmitting end to the signal receiving end via the bus. The positive signal line and the negative signal line of the bus are respectively connected to the two ends of the terminating resistor at the signal receiving end. At the signal receiving end, a verification signal is used to determine whether the data signal is abnormally transmitted, and if the data signal is abnormally transmitted, the connection between the terminating resistor and the positive signal line and / or the reverse signal line is disconnected at the signal receiving end. as well as The signal receiving end obtains a feedback signal based on the voltage difference between the transmitting end of the forward signal line and the reverse signal line. When the voltage difference at the transmitting end is greater than or equal to a set threshold, the feedback signal indicates that the terminating resistor is disconnected from the forward signal line and / or the reverse signal line at the signal receiving end.

15. The signal transmission method according to claim 14, wherein, The signal transmission method further includes: The transmission frequency of the data signal is modulated during at least one transmission stage at the signal transmitting end, such that the transmission frequency of the data signal in each transmission stage characterizes a checksum of the check signal, with different transmission frequencies corresponding to different values ​​of the checksum; and The transmission frequency of the data signal is detected at the signal receiving end to obtain the verification signal.

16. The signal transmission method according to claim 15, wherein, The transmission stages are divided according to the transmission duration or according to the length of the transmitted data signal.

17. The signal transmission method according to claim 14, wherein, The verification signal is obtained by encoding using at least one of the following algorithms: error checking and correction algorithm, cyclic redundancy algorithm, and parity check algorithm.

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