Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure preparation method and a semiconductor structure, the method comprising: providing a substrate, forming an initial stack structure on the substrate, the initial stack structure comprising first dielectric layers and target semiconductor layers alternately stacked in sequence along a first direction, the first dielectric layers being adjacent to the substrate; forming a target gate trench in the initial stack structure, the target gate trench contacting an upper surface of the substrate, a portion of the target semiconductor layers being exposed and suspended in the target gate trench, a sidewall of the target gate trench extending along a second direction comprising a first sub-sidewall and a second sub-sidewall stacked in sequence from inside to outside; and forming two gate structures surrounding the target semiconductor layers and spaced along the second direction in the target gate trench. The present disclosure can at least increase the thickness, width of the gate structure and the distance between adjacent word line structures in a single memory cell structure while ensuring that the number of memory cells per unit volume does not decrease.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design and manufacturing technology, and in particular to methods for preparing semiconductor structures and semiconductor structures. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, the market has placed higher demands on the storage capacity and performance of semiconductor memory products. Improving the storage capacity of semiconductor memory products while ensuring their performance has become a constant goal for researchers, leading to the development of three-dimensional stacked memory structures.

[0003] In a three-dimensional stacked memory structure, the thickness and width of the gate structure and word line structure directly affect the overall performance of the three-dimensional stacked memory structure. However, in the traditional fabrication methods of three-dimensional stacked memory structures, it is difficult to change or control the thickness and width of the gate structure and word line structure in a single memory cell structure. Furthermore, as the number of memory cells per unit volume in a three-dimensional stacked memory structure continues to increase, the space occupied by the word line structure per unit volume and the spacing between adjacent word line structures continue to decrease, which increases the complexity of the fabrication process and reduces the performance and reliability of the fabricated product. Summary of the Invention

[0004] Based on this, the present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, which can at least increase the thickness and width of the gate structure and word line structure and the spacing of adjacent word line structures in a single memory cell structure while ensuring that the number of memory cells per unit volume is not reduced, thereby reducing the complexity of the fabrication process and increasing the performance and reliability of the fabricated product.

[0005] According to various embodiments of this disclosure, one aspect provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an initial stacked structure on the substrate, the initial stacked structure including a first dielectric layer and a target semiconductor layer alternately stacked along a first direction, the first dielectric layer being adjacent to the substrate; forming a first trench isolation structure, a second trench isolation structure, and a third trench isolation structure spaced apart along a second direction and extending along a third direction within the initial stacked structure, defining two gate trench regions extending along the second direction and spaced apart along the third direction; forming a target gate trench with its bottom surface contacting the upper surface of the substrate within the gate trench regions, the target semiconductor layer partially exposed and suspended within the target gate trench, the sidewalls of the target gate trench extending along the second direction including a first sub-sidewall and a second sub-sidewall stacked sequentially from the inside to the outside; forming two gate structures spaced apart along the second direction surrounding the target semiconductor layer within the target gate trench, the adjacent gate structures along the second direction and the third direction being mutually insulated; the first direction, the second direction, and the third direction being perpendicular to each other.

[0006] In the semiconductor structure fabrication method described in the above embodiments, taking the first direction as the thickness direction, the second direction as the length direction, and the third direction as the width direction as an example, since the thickness of the first dielectric layer can be set to be greater than the thickness of the target semiconductor layer, it is easier to remove the first dielectric layer located on both sides of the target gate trench along the second direction using a lateral etching process to form an isolation structure between adjacent word line structures along the thickness direction, thereby increasing the spacing between adjacent word line structures along the thickness direction; since the length of the gate trench region along the third direction is used to limit the length of the gate structure along the third direction, by increasing the length of the gate trench region along the third direction, the width or length of the subsequently fabricated word line structure can be increased, thereby reducing the connection impedance between the word line structure and the gate structure; since the first trench isolation structure and the second trench isolation structure can be controlled or changed, the spacing between adjacent word line structures along the thickness direction can be increased. The length and width of the isolation structure and the third trench isolation structure can be controlled or changed to increase the size of the gate structure subsequently formed in the target gate trench and the spacing between adjacent gate structures along the second direction. Since the first trench isolation structure and the third trench isolation structure can be used to form a bridge word line portion connected to the gate structure, and then multiple layers of horizontally spaced word lines are stacked in the thickness direction, so that the horizontal word lines are connected to the corresponding gate structure via the bridge word lines, compared with forming a multi-layer word line structure stacked in the thickness direction directly on the outside of the gate structure, this embodiment can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, thereby reducing the complexity of the manufacturing process and increasing the performance and reliability of the manufactured product.

[0007] According to some embodiments of this disclosure, the target gate trench is filled with a first low dielectric constant material layer surrounding the gate structure; the first dielectric layer and the target semiconductor layer have a first preset etch selectivity ratio; the method for fabricating the semiconductor structure further includes: using the first low dielectric constant material layer as an etch stop layer, using a lateral etching process to remove the first dielectric layer between adjacent target semiconductor layers to obtain a first gap; and filling the first gap with a first isolation material layer.

[0008] According to some embodiments of this disclosure, the target semiconductor layer and the first isolation material layer have a second preset etching selectivity ratio; the method for fabricating the semiconductor structure further includes: using the first low dielectric constant material layer as an etching stop layer, using a lateral etching process to remove the portion of the target semiconductor layer located on opposite sides of the target gate trench along the second direction to obtain a second gap; and forming a word line structure within the second gap.

[0009] According to some embodiments of this disclosure, the character line structure includes a first character line portion extending along a third direction and a second character line portion extending along a second direction; wherein the first character line portion and the second character line portion are integrally formed structures.

[0010] According to some embodiments of this disclosure, two target gate trenches are symmetrical to each other along a third direction; the method for fabricating the semiconductor structure further includes: removing a first sub-sidewall to form a first sidewall trench, wherein a portion of the target semiconductor layer located within the first sidewall trench is exposed and suspended; doping the target semiconductor layer within the first sidewall trench to form a source structure on the target semiconductor layer in the first sidewall trench between adjacent gate structures along a third direction, and forming a drain structure on the target semiconductor layer in the first sidewall trench on the side of the gate structure away from the source structure along a third direction; forming an insulating dielectric layer in the first sidewall trench with its top surface flush with the upper surface of the initial stacked structure; removing a second sub-sidewall to obtain a second sidewall trench, wherein a portion of the target semiconductor layer located within the second sidewall trench is exposed and suspended; and silicide treatment of the target semiconductor layer in the second sidewall trench.

[0011] According to some embodiments of the present disclosure, the method for fabricating a semiconductor structure further includes: forming a bulk isolation structure extending along a second direction and having its bottom surface in contact with the substrate; forming a bit line structure on a target semiconductor layer on the side of the drain structure away from the bulk isolation structure; and forming a capacitor structure on a target semiconductor layer between the source structure and the bulk isolation structure.

[0012] According to some embodiments of this disclosure, the upper surfaces of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure are flush with the upper surface of the initial stacked structure; the step of forming the target gate trench includes: etching portions of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure located on opposite sides of the gate trench region along a third direction to obtain a first sidewall trench extending along a second direction, wherein a portion of the target semiconductor layer located within the first sidewall trench is exposed and suspended; forming a first sub-sidewall in the first sidewall trench with its top surface flush with the upper surface of the initial stacked structure; etching portions of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure located on opposite sides of the gate trench region along a third direction to obtain a second sidewall trench located on the side of the first sub-sidewall facing away from the gate trench region, adjacent to the first sub-sidewall, and extending along a second direction, wherein a portion of the target semiconductor layer located within the second sidewall trench is exposed and suspended; forming a second sub-sidewall in the second sidewall trench with its top surface flush with the upper surface of the initial stacked structure.

[0013] According to some embodiments of this disclosure, the step of forming a gate structure surrounding a target semiconductor layer within a target gate trench includes: forming a gate oxide layer on the outer surface of the target semiconductor layer within the target gate trench, the gate oxide layer surrounding the target semiconductor layer; forming a first sub-metal layer on the outer surface of the gate oxide layer using a deposition process, the first sub-metal layer surrounding the gate oxide layer; forming a second sub-metal layer on the outer surface of the first sub-metal layer within the target gate trench using a deposition process, the second sub-metal layer surrounding the first sub-metal layer; the first sub-metal layer and the second sub-metal layer constitute a gate metal layer; wherein the material of the second sub-metal layer is the same as the material of the word line structure.

[0014] According to some embodiments of this disclosure, after forming the second sub-metal layer, the method further includes: depositing a first low-dielectric-constant material layer, the first low-dielectric-constant material layer filling the gap between adjacent gate structures in the target gate trench; the first low-dielectric-constant material layer is made of the same material as the second sub-sidewall.

[0015] According to some embodiments of this disclosure, before the step of forming a gate oxide layer on the outer surface of the target semiconductor layer in the target gate trench, the method further includes: trimming the target semiconductor layer located in the target gate trench along the inner diameter direction of the target semiconductor layer.

[0016] According to some embodiments of this disclosure, the thickness of the first dielectric layer is greater than the thickness of the target semiconductor layer.

[0017] According to some embodiments of this disclosure, the step of trimming the portion of the target semiconductor layer located within the target gate trench includes: processing the portion of the target semiconductor layer located within the target gate trench using an in-situ oxidation process to obtain an in-situ oxide layer; and removing the in-situ oxide layer using a wet etching process; wherein the cross-section of the trimmed target semiconductor layer perpendicular to a third direction is circular or elliptical.

[0018] According to some embodiments of this disclosure, the first preset etching selectivity ratio is 5:1-20:1.

[0019] According to some embodiments of this disclosure, the second preset etching selectivity ratio is 5:1-30:1.

[0020] According to some embodiments, this disclosure also provides a semiconductor structure prepared using the semiconductor structure preparation method in any embodiment of this disclosure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0023] Figures 2-5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11 and Figure 13a This is a three-dimensional cross-sectional schematic diagram of different steps in the preparation method of the semiconductor structure provided in some embodiments of this disclosure;

[0024] Figure 5b for Figure 5a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0025] Figure 5c for Figure 5a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0026] Figure 6b for Figure 6a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the CC' direction;

[0027] Figure 6c for Figure 6a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0028] Figure 7b for Figure 7a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the CC' direction;

[0029] Figure 7c for Figure 7a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0030] Figure 8b for Figure 8a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the CC' direction;

[0031] Figure 8c for Figure 8a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0032] Figure 9b for Figure 9a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the CC' direction;

[0033] Figure 9c for Figure 9a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0034] Figure 10b for Figure 10a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the CC' direction;

[0035] Figure 10c for Figure 10a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the BB' direction;

[0036] Figure 12 This is a top view schematic diagram of a storage cell structure provided in one embodiment of the present disclosure;

[0037] Figure 13b for Figure 13a A top view of the three-dimensional structure shown;

[0038] Figure 14 This is a top view schematic diagram of a storage cell structure provided in another embodiment of this disclosure;

[0039] Among them, the oz direction can be the first direction, the ox direction can be the second direction, the oy direction can be the third direction, and the oz direction can be the height / thickness direction.

[0040] Explanation of reference numerals in the attached figures:

[0041] 100. Substrate; 11. First dielectric layer; 12. Target semiconductor layer; 1311. First trench; 1321. Second trench; 1331. Third trench; 131. First trench isolation structure; 132. Second trench isolation structure; 133. Third trench isolation structure; 134. Gate trench region; 14. Target gate trench; 141. First sub-sidewall; 142. Second sub-sidewall; 21. Gate oxide layer; 22. Gate metal layer; 2 21. First sub-metal layer; 222. Second sub-metal layer; 20. Gate structure; 144. First low dielectric constant material layer; 15. First isolation material layer; 16. Insulating dielectric layer; 30. Word line structure; 31. First word line section; 32. Second word line section; 18. Body isolation structure; 191. Source structure; 192. Drain structure; 40. Capacitor structure; 50. Bit line structure; 200. Memory cell structure; 300. Body structure. Detailed Implementation

[0042] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components relevant to this disclosure and are not drawn according to the actual number, shape, and size of components in implementation, the type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout may also be more complex. Please note that mutual insulation between two entities in the embodiments of this disclosure includes, but is not limited to, the presence of one or more of insulating materials, insulating fumes, or gaps between the two entities.

[0048] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as Gate All Around (GAA) transistors. In GAA transistors, the gate surrounds the channel area from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects. GAA transistors include Lateral Gate All Around (LGAA) transistors and Vertical Gate All Around (VGAA) transistors. In LGAA transistors, the channel and gate structures extend parallel to the substrate surface, making it difficult to control the dimensions of the gate structure and the word lines connected to it. Furthermore, increasing the number of memory cells per unit volume by directly forming word lines extending parallel to the substrate surface outside the gate structure inevitably reduces the volume of the word lines and the spacing between adjacent word lines, increasing the complexity of the fabrication process and reducing the performance and reliability of the fabricated product.

[0049] This disclosure aims to provide a method for fabricating a semiconductor structure and a semiconductor structure that can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures while ensuring that the number of memory cells per unit volume is not reduced. It can also control the size of the transistor gate structure connected to the word line structure, thereby reducing the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0050] Please refer to Figure 1 In some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0051] Step S110: Provide a substrate and form an initial stacked structure on the substrate. The initial stacked structure includes a first dielectric layer and a target semiconductor layer that are alternately stacked along a first direction. The first dielectric layer is adjacent to the substrate.

[0052] Step S120: A first trench isolation structure, a second trench isolation structure, and a third trench isolation structure are formed in the initial stacked structure, which are spaced apart along the second direction and extend along the third direction, and two gate trench regions that extend along the second direction and are spaced apart along the third direction are defined.

[0053] Step S130: A target gate trench is formed in the gate trench region, with the bottom surface contacting the upper surface of the substrate. The target semiconductor layer is partially exposed and suspended in the target gate trench. The sidewalls of the target gate trench extending along the second direction include a first sub-sidewall and a second sub-sidewall stacked sequentially from the inside to the outside.

[0054] Step S140: Two gate structures spaced apart along the second direction are formed in the target gate trench surrounding the target semiconductor layer. The adjacent gate structures along the second direction and the third direction are insulated from each other. The first direction, the second direction and the third direction are perpendicular to each other.

[0055] For details, please continue to refer to Figure 1Taking the first direction as the thickness direction, the second direction as the length direction, and the third direction as the width direction as an example, since the thickness of the first dielectric layer can be set to be greater than the thickness of the target semiconductor layer, it is easier to remove the first dielectric layer located on both sides of the target gate trench along the second direction using a lateral etching process to form an isolation structure between adjacent word line structures along the thickness direction, thereby increasing the spacing between adjacent word line structures along the thickness direction; since the length of the gate trench region along the third direction is used to limit the length of the gate structure along the third direction, by increasing the length of the gate trench region along the third direction, the width or length of the subsequently fabricated word line structure can be increased, thereby reducing the connection impedance between the word line structure and the gate structure; since the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure can be controlled or changed... The length and width of the isolation structure can be controlled or changed, thereby increasing the size of the gate structure subsequently formed in the target gate trench and the spacing between adjacent gate structures along the second direction. Since the first trench isolation structure and the third trench isolation structure can be used to form a bridge word line portion connected to the gate structure, and then multiple layers of horizontally spaced word lines are stacked in the thickness direction, so that the horizontal word lines are connected to the corresponding gate structure via the bridge word lines, compared with forming a multi-layer word line structure stacked in the thickness direction directly on the outside of the gate structure, this embodiment can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, reducing the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0056] For example, please refer to Figures 1-2 Step S110 may include the following steps:

[0057] Step S111: Provide substrate 100;

[0058] Step S112: An initial stacked structure is formed on the substrate 100. The initial stacked structure includes a first dielectric layer 11 and a target semiconductor layer 12 that are alternately stacked along a first direction (e.g., the oz direction). The first dielectric layer 11 is adjacent to the substrate 100.

[0059] For example, a first-type doped well region (not shown) is formed within the substrate 100. The substrate can be constructed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 100 should not limit the scope of this disclosure. P-type ions can be implanted into the substrate 100 using an ion implantation process to form a first type of doped well region (not shown). The P-type ions can be any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. The material of the first dielectric layer 11 can be, but is not limited to, silicon-germanium (SiGe), and the material of the target semiconductor layer 12 can be, but is not limited to, silicon (Si). The silicon-germanium first dielectric layer 11 can completely transfer the silicon lattice of the substrate 100 to the stacked silicon channel layers, ensuring that each silicon channel layer has the same silicon lattice as the substrate 100.

[0060] For example, please refer to Figures 3-4In step S120, an etching process can be used to form a first trench 1311, a second trench 1321, and a third trench 1331 within the initial stacked structure. These trenches are spaced apart along a second direction (e.g., the ox direction) and extend along a third direction (e.g., the oy direction). The first trench 1311, the second trench 1321, and the third trench 1331 expose the upper surface of the substrate 100. The first direction (e.g., the oz direction), the second direction (e.g., the ox direction), and the third direction (e.g., the oy direction) are perpendicular to each other. The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high-concentration plasma etching (HDP). Then, using a deposition process, isolation materials are deposited in the first trench 1311, the second trench 1321, and the third trench 1331 to obtain the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133. The bottom surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 contact the upper surface of the substrate 100. After forming the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133, a chemical mechanical polishing process can be used. CMP (Chemical Motion Polishing) flushes the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 with the upper surface of the initial stacked structure. This facilitates the formation of a smooth first mask layer on the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133. The initial stacked structure is then etched based on the patterned first mask layer to obtain the target gate trench, improving the controllability of the target gate trench morphology and its consistency with the expected structure. The isolation material within the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 may include one or more of polysilicon, silicon nitride, silicon oxide, and silicon oxynitride. The deposition process may include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0061] As an example, please continue to refer to Figures 3-4The initial stacked structure can be set to be symmetrical about the axis of symmetry of the second trench isolation structure 132 extending along a third direction (e.g., the oy direction) to improve the symmetry of the semiconductor structure, reduce the process complexity, and facilitate the monitoring of the structural and electrical parameters of the fabricated product.

[0062] As an example, please continue to refer to Figures 2-4 The thickness of the first dielectric layer 11 can be [60nm, 100nm], for example, the thickness of the first dielectric layer 11 can be 60nm, 70nm, 80nm, 90nm, or 100nm, etc. The thickness of the target semiconductor layer 12 can be [5nm, 20nm], for example, the thickness of the target semiconductor layer 12 can be 5nm, 10nm, 15nm, or 20nm, etc. The first dielectric layer 11 itself provides tensile stress. Each layer cannot be too thick, otherwise it is easy to cause problems such as body tilting. It also cannot be too thin, to avoid increasing the parasitic capacitance and leakage probability between the subsequent word line structures.

[0063] For example, please refer to Figures 4-6c The upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 are flush with the upper surface of the initial stacked structure; the step of forming the target gate trench 14 in step S130 may include the following steps:

[0064] Step S131: Etch portions of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 located on opposite sides of the gate trench region 134 along a third direction (e.g., the oy direction) to obtain a first sidewall trench (not shown) extending along a second direction (e.g., the ox direction), with the portion of the target semiconductor layer 12 located within the first sidewall trench exposed and suspended.

[0065] Step S132: A first sub-sidewall 141 with its top surface flush with the upper surface of the initial stacked structure is formed in the first sidewall trench; portions of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 located on opposite sides of the gate trench region 134 along a third direction (e.g., the oy direction) are etched to obtain a second sidewall trench (not shown) located on the side of the first sub-sidewall away from the gate trench region 134, adjacent to the first sub-sidewall 141, and extending along a second direction (e.g., the ox direction); the portion of the target semiconductor layer 12 located in the second sidewall trench is exposed and suspended.

[0066] Step S133: A second sub-sidewall 142 is formed in the second sidewall groove, with its top surface flush with the upper surface of the initial stacked structure.

[0067] As an example, please continue to refer to Figures 4-5cIn step S131, a second patterned mask layer (not shown) can be formed on the upper surface of the initial stacked structure. The second patterned mask layer has an opening pattern that defines the position and shape of the first sidewall trench. Based on the second patterned mask layer, an etching process is used to etch the portions of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 located on opposite sides of the gate trench region 134 along a third direction (e.g., the oy direction). The first dielectric layer 11 between adjacent target semiconductor layers 12 is removed, resulting in a first sidewall trench (not shown) extending along a second direction (e.g., the ox direction). The portion of the target semiconductor layer 12 located within the first sidewall trench is exposed and suspended. The etching process may include, but is not limited to, dry etching and / or wet etching processes. The dry etching process may include, but is not limited to, one or more of RIE, ICP, and HDP.

[0068] As an example, please continue to refer to Figures 4-5c In step S132, a deposition process can be used to form a first sub-sidewall 141 within the first sidewall trench, with its top surface flush with the upper surface of the initial stacked structure. Then, a third patterned mask layer (not shown) is formed on the upper surface of the initial stacked structure. This third patterned mask layer has an opening pattern that defines the position and shape of the second sidewall trench. Based on the third patterned mask layer, an etching process is used to etch portions of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 located on opposite sides of the gate trench region 134 along a third direction (e.g., the oy direction). The first dielectric layer 11 between adjacent target semiconductor layers 12 is removed, resulting in a second sidewall trench (not shown) located on the side of the first sub-sidewall 141 away from the gate trench region 134, adjacent to the first sub-sidewall 141, and extending along a second direction (e.g., the ox direction). The portion of the target semiconductor layer 12 located within the second sidewall trench is exposed and suspended. The etching process can include, but is not limited to, dry etching and / or wet etching processes. Dry etching processes can include, but are not limited to, one or more of RIE, ICP, and HDP.

[0069] As an example, please continue to refer to Figures 4-5c In step S133, a deposition process can be used to form a second sub-sidewall 142 within the second sidewall trench, with its top surface flush with the upper surface of the initial stacked structure. The deposition process can include, but is not limited to, one or more of the following processes: CVD, ALD, HDP, and SOD.

[0070] As an example, please continue to refer to Figures 6a-6c After forming the second sub-sidewall 142 in step S130, whose top surface is flush with the upper surface of the initial stacked structure, the following steps may also be included:

[0071] Step S134: The first dielectric layer 11 in the gate trench region 134 is removed by etching process to obtain the target gate trench 14 on the upper surface of the bottom surface contacting the substrate 100. The target semiconductor layer 12 is partially exposed and suspended in the target gate trench 14. The sidewalls of the target gate trench 14 extending along the second direction (e.g., the ox direction) include a first sub-sidewall 141 and a second sub-sidewall 142 stacked sequentially from the inside to the outside.

[0072] For example, the etching process may include, but is not limited to, dry etching and / or wet etching. Dry etching processes may include, but are not limited to, one or more of RIE, ICP, and HDP.

[0073] For example, please refer to Figures 7a-7c The step of forming two gate structures 20 spaced apart along a second direction (e.g., the ox direction) surrounding the target semiconductor layer 12 in step S140 may include the following steps:

[0074] Step S141: A gate oxide layer 21 is formed on the outer surface of the target semiconductor layer 12 within the target gate trench 14, and the gate oxide layer 21 surrounds the target semiconductor layer 12;

[0075] Step S142: A first sub-metal layer 221 is formed on the outer surface of the gate oxide layer 21 using a deposition process. The first sub-metal layer 221 surrounds the gate oxide layer 21.

[0076] Step S143: A second sub-metal layer 222 is formed on the outer surface of the first sub-metal layer 221 in the target gate trench 14 using a deposition process. The second sub-metal layer 222 surrounds the first sub-metal layer 221. The first sub-metal layer 221 and the second sub-metal layer 222 constitute the gate metal layer 22. The material of the second sub-metal layer 222 is the same as the material of the word line structure.

[0077] As an example, please continue to refer to Figures 7a-7cIn step S141, one or more of the following processes can be used to form a gate oxide layer 21 on the outer surface of the target semiconductor layer 12 within the target gate trench 14: in-situ steam generation (ISSG), atomic layer deposition (ALD), plasma vapor deposition (PVD), and rapid thermal oxidation (RTO). The gate oxide layer 21 can be formed using a high-k dielectric material. For example, the material of the gate oxide layer 21 can include, but is not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), and strontium titanium oxide (SrTiO3). The gate metal layer 22 includes a first sub-metal layer 221 and a second sub-metal layer 222 stacked sequentially from the inside out; the deposition process can include, but is not limited to, one or more of the following processes: CVD, ALD, HDP, and SOD. The first sub-metal layer 221 or the second sub-metal layer 222 may be any one or more of titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W). The material of the second sub-metal layer 222 is the same as that of the word line structure, which facilitates increasing the contact area between the word line structure and the gate structure 20 and reducing the connection impedance between them.

[0078] As an example, please continue to refer to Figures 7a-7c Before forming the gate oxide layer 21 on the outer surface of the target semiconductor layer 12 within the target gate trench 14 in step S141, the following steps may also be included:

[0079] Step S135: Trim the target semiconductor layer 12 located within the target gate trench 14 along the inner diameter direction of the target semiconductor layer 12.

[0080] As an example, please continue to refer to Figures 7a-7c The portion of the target semiconductor layer 12 located within the target gate trench 14 can be treated using an in-situ oxidation process to obtain an in-situ oxide layer (not shown). This in-situ oxide layer is then removed using a wet etching process. The cross-section of the trimmed target semiconductor layer 12 perpendicular to a third direction (e.g., the oy direction) is circular or elliptical to avoid tip discharge. By trimming along the inner diameter of the target semiconductor layer 12 and changing the exposed and suspended portion of the target semiconductor layer 12 within the target gate trench 14, the size of the subsequently formed gate structure 20 can be relatively increased, thereby improving the electrical performance and reliability of the fabricated semiconductor product.

[0081] As an example, please continue to refer to Figures 7a-7cAfter forming two gate structures 20 spaced apart along a second direction (e.g., the ox direction) surrounding the target semiconductor layer 12 in the target gate trench 14 in step S140, the following steps may also be included:

[0082] Step S144: Deposit a first low dielectric constant material layer 144, the first low dielectric constant material layer 144 filling the gap between adjacent gate structures 20 in the target gate trench 14; the first low dielectric constant material layer 144 is made of the same material as the second sub-sidewall 142.

[0083] For example, a deposition process can be used to fill the target gate trench 14 with a first low dielectric constant material layer 144, followed by a planarization process, a push-to-plan process, an etching process, and a chemical mechanical polishing process to planarize the upper surface of the first low dielectric constant material layer 144. This allows for setting the etching selectivity ratio between the first low dielectric constant material layer 144 and the first dielectric layer 11, effectively preventing damage to the target semiconductor layer 12 during etching of the first dielectric layer 11 located on opposite sides of the target gate trench 14 along a second direction (e.g., the ox direction).

[0084] For example, the first low dielectric constant material layer 144 includes, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), a hydrogenated silicon oxide carbon layer (SiCOH), or other types of silicon-based low-k dielectric layers (e.g., dielectric layers with k less than 4.0).

[0085] For example, please refer to Figures 8a-8c The first dielectric layer 11 and the target semiconductor layer 12 can be configured to have a first preset etching selectivity; after forming the first low dielectric constant material layer 144 in step S144, the following steps may also be included:

[0086] Step S151: Using the first low dielectric constant material layer 144 in the target gate trench 14 as the etching stop layer, the first dielectric layer 11 between adjacent target semiconductor layers 12 is removed by a lateral etching process to obtain the first gap (not shown).

[0087] Step S152: Fill the first gap with the first insulating material layer 15.

[0088] As an example, please continue to refer to Figures 8a-8cFor example, the first isolation material layer 15 may include one or more of polysilicon, silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 11 and the target semiconductor layer 12 may be configured with a first preset etch selectivity ratio, which is 5:1 to 20:1. For example, the first preset etch selectivity ratio can be 5:1, 8:1, 10:1, 12:1, 15:1, 17:1, or 20:1, etc., so that when the first low-dielectric-constant material layer 144 within the target gate trench 14 is used as the etch stop layer, the target semiconductor layer 12 can be well protected during the removal of the first dielectric layer 11 between adjacent target semiconductor layers 12 using a lateral etching process. This results in a first gap with a morphological structure that meets expectations, ensuring the isolation performance of the first isolation material layer 15 filled within the first gap.

[0089] As an example, please continue to refer to Figures 8a-8c The thickness of the first dielectric layer 11 can be set to be greater than the thickness of the target semiconductor layer 12, so as to increase the spacing between adjacent word line structures along the thickness direction, reduce the parasitic capacitance between adjacent word line structures, and effectively avoid short circuits between adjacent word line structures.

[0090] For example, please refer to Figures 9a-9c After filling the first gap with the first insulating material layer 15 in step S152, the following steps may also be included:

[0091] Step S161: Using the first low dielectric constant material layer 144 in the target gate trench 14 as the etching stop layer, a lateral etching process is used to remove the portion of the target semiconductor layer 12 located on opposite sides of the target gate trench 14 along the second direction (e.g., the ox direction) to obtain the second gap (not shown).

[0092] Step S162: Form the character line structure 30 within the second gap.

[0093] As an example, please continue to refer to Figures 9a-9cThe materials used for the character line structure can include, but are not limited to, any one or more of rubidium, cobalt, nickel, titanium, tungsten, tantalum, tantalum titanide, tungsten nitride, copper, and aluminum. The target semiconductor layer 12 and the first isolation material layer 15 can be set to have a second preset etching selection ratio, which is 5:1-30:1. For example, the second preset etching selection ratio can be 5:1, 15:1, 20:1, 25:1 or 30:1, etc. This allows the target semiconductor layer 12 to be removed from the target gate trench 14 along the second direction (e.g., the ox direction) by using a lateral etching process with the first low dielectric constant material layer 144 in the target gate trench 14 as the etching stop layer. This results in a second gap with a morphological structure that meets the expected requirements, ensuring the electrical performance and reliability of the word line structure formed in the second gap. The word line structure 30 includes a first word line portion 31 extending along a third direction (e.g., the oy direction) and a second word line portion 32 extending along a second direction (e.g., the ox direction); wherein the first word line portion 31 and the second word line portion 32 are integrally formed structures. Compared to forming a multi-layer word line structure stacked in the thickness direction directly on the outside of the gate structure, this embodiment can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0094] For example, please refer to Figures 10a-10c Two target gate trenches 14 can be configured to be symmetrical to each other along a third direction (e.g., the oy direction); after forming the word line structure in the second gap in step S162, the following steps may also be included:

[0095] Step S171: Remove the first sub-sidewall 141 to form a first sidewall trench (not shown), and the portion of the target semiconductor layer 12 located in the first sidewall trench is exposed and suspended;

[0096] Step S172: The target semiconductor layer 12 in the first sidewall trench is doped to form a source structure on the target semiconductor layer 12 in the first sidewall trench between adjacent gate structures 20 along a third direction (e.g., the oy direction). Figures 10a-10c (not shown in the diagram), and a drain structure is formed on the target semiconductor layer 12 within the first sidewall trench of the gate structure 20 on the side away from the source structure along a third direction (e.g., the oy direction). Figures 10a-10c (not shown in the image);

[0097] Step S173: An insulating dielectric layer 16 with its top surface flush with the upper surface of the initial stacked structure is formed in the first sidewall groove;

[0098] Step S174: Remove the second sub-sidewall 142 to obtain a second sidewall trench (not shown), and the target semiconductor layer 12 is partially exposed and suspended within the second sidewall trench;

[0099] Step S175: Perform siliconization on the target semiconductor layer 12 within the second sidewall trench.

[0100] As an example, please continue to refer to Figures 10a-10c In step S171, an etching process can be used to remove the first sub-sidewall 141 to obtain a first sidewall trench (not shown). The target semiconductor layer 12 located within the first sidewall trench is exposed and suspended. The target semiconductor layer 12 within the first sidewall trench is then doped, for example, by vapor phase doping, to form a source structure on the target semiconductor layer 12 within the first sidewall trench between adjacent gate structures 20 along a third direction (e.g., the oy direction). Figures 10a-10c (not shown in the diagram), and a drain structure is formed on the target semiconductor layer within the first sidewall trench of the gate structure 20 along a third direction (e.g., the oy direction) away from the source structure. Figures 10a-10c (Not shown in the diagram); then, an insulating material layer, such as silicon oxide, is filled into the first sidewall trench, followed by planarization to obtain an insulating dielectric layer 15 with its top surface flush with the upper surface of the initial stacked structure. Next, an etching process is used to remove the second sub-sidewall 142, resulting in a second sidewall trench (not shown). The target semiconductor layer 12 is partially exposed and suspended within the second sidewall trench. The target semiconductor layer 12 within the second sidewall trench is then silicided to reduce the contact resistance between the source structure and the capacitor structure, and between the drain structure and the bit line structure. Finally, an insulating dielectric layer 16, such as silicon oxide, is formed within the second sidewall trench with its top surface flush with the upper surface of the initial stacked structure. Because the insulating dielectric layer 16 and the second sub-sidewall 142 have a high etch selectivity, during the etching and removal of the second sub-sidewall 142, the first dielectric layer 11 within the second sidewall trench can be removed while avoiding damage to the target semiconductor layer 12 within the second sidewall trench.

[0101] For example, please refer to Figures 11-12 After forming the source and drain structures in step S180, the following steps may also be included:

[0102] Step S1911: Form a body isolation structure 18 that extends along a second direction (e.g., the ox direction) and whose bottom surface contacts the upper surface of the substrate 100;

[0103] Step S1912: A bit line structure 50 is formed on the target semiconductor layer 12 on the side of the drain structure 192 away from the body isolation structure 18; and a capacitor structure 40 is formed on the target semiconductor layer 12 between the source structure 191 and the body isolation structure 18.

[0104] As an example, please continue to refer to Figures 11-12 In step S1911, an etching process can be used to etch the initial stacked structure to obtain a bulk isolation trench (not shown). The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, any one or more of RIE, ICP, and HDP. Then, an isolation material is deposited in the bulk isolation trench to obtain the bulk isolation structure 18. The deposition process can include, but is not limited to, any one or more of CVD, ALD, HDP, and SOD. The isolation material can include, but is not limited to, any one or more of silicon nitride, silicon oxide, silicon oxynitride, and polysilicon.

[0105] As an example, please continue to refer to Figures 11-12 The position of the body isolation structure 18 can be set so that the semiconductor structure is symmetrical about the axis of symmetry m1 extending along the ox direction of the body isolation structure 18, or the gate structure 20 adjacent along the ox direction can be symmetrical about the axis of symmetry m2 extending along the oy direction.

[0106] As an example, please continue to refer to Figure 12In step S1912, a bit line structure 50 can be formed on the target semiconductor layer 12 on the side of the drain structure 192 away from the body isolation structure 18; and a capacitor structure 40 can be formed on the target semiconductor layer 12 between the source structure 191 and the body isolation structure 18, resulting in a memory cell structure 200. Adjacent source structures 191 along the oy direction are symmetrical about the axis of symmetry m1, and adjacent drain structures 192 along the oy direction are symmetrical about the axis of symmetry m1. In this embodiment, multiple body structures 300 are spaced apart along the oz direction, and each body structure 300 includes four centrally symmetrical memory cell structures 200. Since the thickness of the first dielectric layer can be set to be greater than the thickness of the target semiconductor layer, it is easier to remove the first dielectric layer located on both sides of the target gate trench along the second direction using a lateral etching process to form an isolation structure between adjacent word line structures along the thickness direction, thereby increasing the spacing between adjacent word line structures along the thickness direction. Since the length of the gate trench region along the third direction is used to define the length of the gate structure along the third direction, increasing the length of the gate trench region along the third direction can increase the width or length of the subsequently fabricated word line structure, thereby reducing the connection impedance between the word line structure and the gate structure. Since the length and width of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure can be controlled or changed, it is possible to control or change the spacing between the word line structure and the gate structure. By changing the length and width of the target gate trench, the size of the gate structure subsequently formed in the target gate trench and the spacing between adjacent gate structures along the second direction can be increased. Since the first trench isolation structure and the third trench isolation structure can be used to form bridge word lines connected to the gate structure, and then multiple layers of horizontally spaced word lines are stacked in the thickness direction, the horizontal word lines are connected to the corresponding gate structure via the bridge word lines. Compared with forming multiple layers of word lines stacked in the thickness direction directly on the outside of the gate structure, this embodiment can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0107] As an example, please continue to refer to Figure 12In the memory cell structure 200, the target semiconductor layer extends along the oy direction and can employ first-type doping, such as light P-type doping. The channel conductive layer (not shown) is located between the source structure 191 and the drain structure 192 and can employ first-type doping, such as heavy P-type doping, to form the channel region of the transistor. The drain structure 192 can employ second-type doping, such as heavy N-type doping, to form the drain region of the transistor. The source structure 191 can employ second-type doping, such as heavy N-type doping, to form the source region of the transistor. P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions; N-type impurity ions can include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0108] For example, please refer to Figures 1-14 After forming the source and drain structures in step S180, the following steps may also be included:

[0109] Step S1921: Form a body isolation structure 18 that extends along a second direction (e.g., the ox direction) and whose bottom surface contacts the upper surface of the substrate 100;

[0110] Step S1922: Remove the first sub-sidewall 141 to form a first sidewall trench (not shown), and the portion of the target semiconductor layer 12 located in the first sidewall trench is exposed and suspended;

[0111] Step S1923: The target semiconductor layer 12 in the first sidewall trench is doped to form a drain structure 192 on the target semiconductor layer 12 located on the side of the gate structure 20 away from the body isolation structure 18 along a third direction (e.g., the ox direction), and a source structure 191 is formed on the target semiconductor layer 12 in the first sidewall trench between the gate structure 20 and the body isolation structure 18.

[0112] Step S1924: An insulating dielectric layer 16 with its top surface flush with the upper surface of the initial stacked structure is formed in the first sidewall trench; the second sub-sidewall 142 is removed to obtain a second sidewall trench (not shown), and the target semiconductor layer 12 is partially exposed and suspended in the second sidewall trench.

[0113] Step S1925: Perform siliconization on the target semiconductor layer 12 within the second sidewall trench.

[0114] As an example, please continue to refer to Figures 9a-11 , Figures 13a-14Because of the high etching selectivity between the insulating dielectric layer 16 and the second sub-sidewall 142, during the etching and removal of the second sub-sidewall 142, the first dielectric layer 11 within the second sidewall trench can be removed while avoiding damage to the target semiconductor layer 12 within the second sidewall trench. Siliconization of the target semiconductor layer 12 within the second sidewall trench reduces the contact resistance between the source structure 191 and the capacitor structure 40, and between the drain structure 192 and the bit line structure 50.

[0115] As an example, please continue to refer to Figures 13a-14 The semiconductor structure fabrication method described in this embodiment yields a plurality of body structures 300 spaced apart along the oz direction. Each body structure 300 includes a memory cell structure 200 symmetrical about a symmetry axis m2 extending along the oy direction. The target semiconductor layer in the memory cell structure 200 extends along the oy direction and can employ a first type of doping, such as light P-type doping. A channel conductive layer (not shown) is located between the source structure 191 and the drain structure 192 and can employ a first type of doping, such as heavy P-type doping, to form the channel region of the transistor. The drain structure 192 can employ a second type of doping, such as heavy N-type doping, to form the drain region of the transistor. The source structure 191 can employ a second type of doping, such as heavy N-type doping, to form the source region of the transistor. P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions; N-type impurity ions can include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0116] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0117] Please refer to Figures 7a-7cThe semiconductor structure provided in this embodiment includes a substrate 100 and an initial stacked structure on the substrate 100. The initial stacked structure includes a first dielectric layer 11 and a target semiconductor layer 12 alternately stacked along a first direction (e.g., the oz direction). The first dielectric layer 11 is adjacent to the substrate 100. A first trench isolation structure 131, a second trench isolation structure 132, and a third trench isolation structure 133 are formed within the initial stacked structure, spaced apart along a second direction (e.g., the ox direction) and extending along a third direction (e.g., the oy direction). The bottom surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 contact the upper surface of the substrate 100, and the interior... A target gate trench is formed on the upper surface of the substrate with two bottom surfaces. The target gate trench extends along a second direction (e.g., the ox direction) and is spaced apart along a third direction (e.g., the oy direction). A gate structure is disposed around the outer surface of the portion of the target semiconductor layer 12 located within the target gate trench. The sidewalls of the target gate trench extending along the second direction (e.g., the ox direction) include a first sub-sidewall 141 and a second sub-sidewall 142 stacked sequentially from the inside to the outside. The gate structures 20 adjacent along the second direction (e.g., the ox direction) and the third direction (e.g., the oy direction) are mutually insulated. The first direction (e.g., the oz direction), the second direction (e.g., the ox direction), and the third direction (e.g., the oy direction) are perpendicular to each other. Since the thickness of the first dielectric layer can be set to be greater than the thickness of the target semiconductor layer, it is easier to remove the first dielectric layer located on both sides of the target gate trench along the second direction using a lateral etching process to form an isolation structure between adjacent word line structures along the thickness direction, thereby increasing the spacing between adjacent word line structures along the thickness direction. Since the length of the gate trench region along the third direction is used to define the length of the gate structure along the third direction, increasing the length of the gate trench region along the third direction can increase the width or length of the subsequently fabricated word line structure, thereby reducing the connection impedance between the word line structure and the gate structure. Since the length and width of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure can be controlled or changed, it is possible to control or change the spacing between the word line structure and the gate structure. By changing the length and width of the target gate trench, the size of the gate structure subsequently formed in the target gate trench and the spacing between adjacent gate structures along the second direction can be increased. Since the first trench isolation structure and the third trench isolation structure can be used to form bridge word lines connected to the gate structure, and then multiple layers of horizontally spaced word lines are stacked in the thickness direction, the horizontal word lines are connected to the corresponding gate structure via the bridge word lines. Compared with forming multiple layers of word lines stacked in the thickness direction directly on the outside of the gate structure, this embodiment can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0118] Please note that the above embodiments are for illustrative purposes only and are not intended to limit this disclosure.

[0119] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0121] The above embodiments merely illustrate several implementation methods of this disclosure, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and an initial stacked structure is formed on the substrate. The initial stacked structure includes a first dielectric layer and a target semiconductor layer that are alternately stacked sequentially along a first direction. The first dielectric layer is adjacent to the substrate. A first trench isolation structure, a second trench isolation structure, and a third trench isolation structure are formed within the initial stacked structure, spaced apart along the second direction and extending along the third direction, and two gate trench regions extending along the second direction and spaced apart along the third direction are defined. A target gate trench is formed in the gate trench region, with its bottom surface contacting the upper surface of the substrate. The target semiconductor layer is partially exposed and suspended within the target gate trench. The sidewalls of the target gate trench extending along the second direction include a first sub-sidewall and a second sub-sidewall stacked sequentially from the inside to the outside. Two gate structures spaced apart along the second direction are formed within the target gate trench, surrounding the target semiconductor layer. The gate structures adjacent along the second direction and the third direction are insulated from each other. The first direction, the second direction, and the third direction are perpendicular to each other.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The target gate trench is filled with a first low dielectric constant material layer surrounding the gate structure; The first dielectric layer and the target semiconductor layer have a first preset etching selectivity ratio; the method further includes: Using the first low dielectric constant material layer as the etching stop layer, a lateral etching process is used to remove the first dielectric layer between adjacent target semiconductor layers to obtain a first gap; A first insulating material layer is filled into the first gap.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The target semiconductor layer and the first isolation material layer have a second preset etching selectivity ratio; the method further includes: Using the first low dielectric constant material layer as the etching stop layer, a lateral etching process is used to remove the portion of the target semiconductor layer located on opposite sides of the target gate trench along the second direction, to obtain the second gap; A character line structure is formed within the second gap.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The character line structure includes a first character line portion extending along the third direction and a second character line portion extending along the second direction; The first and second character lines are integrally formed.

5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The two target gate trenches are symmetrical to each other along the third direction; the method further includes: The first sub-sidewall is removed to form a first sidewall trench, in which the portion of the target semiconductor layer located within the first sidewall trench is exposed and suspended. The target semiconductor layer in the first sidewall trench is doped to form a source structure on the target semiconductor layer in the first sidewall trench between adjacent gate structures along the third direction, and a drain structure is formed on the target semiconductor layer in the first sidewall trench away from the source structure along the third direction of the gate structure. An insulating dielectric layer is formed in the first sidewall groove, with its top surface flush with the upper surface of the initial stacked structure; The second sub-sidewall is removed to obtain a second sidewall trench, in which the portion of the target semiconductor layer located within the second sidewall trench is exposed and suspended; The target semiconductor layer within the second sidewall trench is subjected to siliconization treatment.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The method further includes: A body isolation structure is formed that extends along the second direction and whose bottom surface contacts the upper surface of the substrate; A bit line structure is formed on the target semiconductor layer on the side of the drain structure away from the body isolation structure; and A capacitor structure is formed on the target semiconductor layer between the source structure and the body isolation structure.

7. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The upper surfaces of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure are flush with the upper surface of the initial stacked structure; The steps of forming the target gate trench include: Etching portions of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure located on opposite sides of the gate trench region along the third direction yields a first sidewall trench extending along the second direction, wherein the portion of the target semiconductor layer located within the first sidewall trench is exposed and suspended. A first sub-sidewall is formed in the first sidewall groove, with its top surface flush with the upper surface of the initial stacked structure; Etching portions of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure located on opposite sides of the gate trench region along the third direction yields a second sidewall trench located on the side of the first sub-sidewall facing away from the gate trench region, adjacent to the first sub-sidewall, and extending along the second direction. The portion of the target semiconductor layer located within the second sidewall trench is exposed and suspended. A second sub-sidewall is formed within the groove of the second sidewall, with its top surface flush with the upper surface of the initial stacked structure.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of forming a gate structure surrounding the target semiconductor layer within the target gate trench includes: A gate oxide layer is formed on the outer surface of the target semiconductor layer within the target gate trench, and the gate oxide layer surrounds the target semiconductor layer. A first sub-metal layer is formed on the outer surface of the gate oxide layer using a deposition process; the first sub-metal layer surrounds the gate oxide layer. A second sub-metal layer is formed on the outer surface of the first sub-metal layer within the target gate trench using a deposition process; the second sub-metal layer surrounds the first sub-metal layer; the first sub-metal layer and the second sub-metal layer constitute a gate metal layer; wherein the material of the second sub-metal layer is the same as the material of the word line structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After forming the second sub-metal layer, the process also includes: A first low-dielectric-constant material layer is deposited, which fills the gap between adjacent gate structures within the target gate trench; the first low-dielectric-constant material layer is made of the same material as the second sub-sidewall.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, Prior to the step of forming a gate oxide layer on the outer surface of the target semiconductor layer within the target gate trench, the method further includes: Trim the portion of the target semiconductor layer located within the target gate trench along the inner diameter direction of the target semiconductor layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The step of trimming the portion of the target semiconductor layer located within the target gate trench includes: The portion of the target semiconductor layer located within the target gate trench is treated using an in-situ oxidation process to obtain an in-situ oxide layer. The in-situ oxide layer is removed using a wet etching process; wherein, the cross-section of the target semiconductor layer perpendicular to the third direction after trimming is circular or elliptical.

12. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The thickness of the first dielectric layer is greater than the thickness of the target semiconductor layer.

13. The method for preparing a semiconductor structure according to any one of claims 2-4, characterized in that: The first preset etching selection ratio is 5:1-20:

1.

14. The method for preparing a semiconductor structure according to claim 3 or 4, characterized in that: The second preset etching selection ratio is 5:1-30:

1.

15. A semiconductor structure, characterized in that, It is prepared by the method described in any one of claims 1-14.

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