Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure preparation method and a semiconductor structure, comprising: providing a substrate, forming an initial stack structure on the substrate, the initial stack structure comprising first dielectric layers and target semiconductor layers alternately stacked in sequence along a first direction, the first dielectric layers being adjacent to the substrate; forming first, second and third trench isolation structures in the initial stack structure, the first, second and third trench isolation structures being spaced apart along a second direction and extending along a third direction; forming two spaced-apart gate trenches contacting a bottom surface of the substrate, a portion of the target semiconductor layers in the gate trenches being exposed and suspended; and forming gate structures surrounding the target semiconductor layers in the gate trenches. The embodiments of the present disclosure can at least increase the space volume occupied by the word line structure and the distance between adjacent word line structures while ensuring that the number of storage units per unit volume does not decrease, and can control the size of the word line structure connected to the transistor gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design and manufacturing technology, and in particular to semiconductor structure preparation methods and semiconductor structures. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, the market has placed higher demands on the storage capacity and performance of semiconductor memory products. Improving the storage capacity of semiconductor memory products while ensuring their performance has become a constant goal for researchers, leading to the development of three-dimensional stacked memory structures.

[0003] In a three-dimensional stacked memory structure, the performance of the transistors connected by the word line structure directly affects the overall performance of the three-dimensional stacked memory structure. In the traditional fabrication method of three-dimensional stacked memory structure, it is difficult to change the gate size of the transistor. Furthermore, as the number of memory cells per unit volume in the three-dimensional stacked memory structure continues to increase, the space occupied by the word line structure per unit volume and the spacing between adjacent word line structures continue to decrease. This increases the complexity of the fabrication process and reduces the performance and reliability of the fabricated product. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure fabrication method and a semiconductor structure, which can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures while ensuring that the number of memory cells per unit volume is not reduced, and can control the size of the transistor gate structure connected to the word line structure, thereby reducing the complexity of the fabrication process and increasing the performance and reliability of the fabricated product.

[0005] According to various embodiments of this disclosure, one aspect provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming an initial stacked structure on the substrate, the initial stacked structure including a first dielectric layer and a target semiconductor layer alternately stacked along a first direction, the first dielectric layer being adjacent to the substrate; forming a first trench isolation structure, a second trench isolation structure, and a third trench isolation structure spaced apart along a second direction and extending along a third direction within the initial stacked structure; forming two spaced gate trenches with their bottom surfaces contacting the upper surface of the substrate, the portion of the target semiconductor layer located within the gate trenches being exposed and suspended; forming a gate structure surrounding the target semiconductor layer within the gate trenches, the adjacent gate structures along the first and second directions being mutually insulated from each other; the first, second, and third directions being perpendicular to each other.

[0006] In the semiconductor structure fabrication method described in the above embodiments, since the exposed and suspended portion of the target semiconductor layer located in the gate trench can be trimmed and modified before forming the gate structure, the size of the subsequently formed gate structure can be controlled. Since the first trench isolation structure and the third trench isolation structure can be used to form a bridge word line portion connected to the gate structure, and then multiple layers of horizontally spaced word lines are stacked in a direction perpendicular to the substrate surface, so that the horizontal word lines are connected to the corresponding gate structure via the bridge word lines, compared with forming a multilayer word line structure stacked in a direction perpendicular to the substrate surface directly on the outside of the gate structure, this embodiment can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, thereby reducing the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0007] According to some embodiments, the upper surfaces of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure are flush with the upper surface of the initial stacked structure; forming two spaced gate trenches with their bottom surfaces contacting the upper surface of the substrate includes: forming a first mask layer covering the upper surfaces of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure; patterning the first mask layer and etching the initial stacked structure based on the patterned first mask layer as a mask to obtain the gate trenches, wherein the remaining portions of the first trench isolation structure and the remaining portions of the third trench isolation structure located on opposite sides of the gate trenches along a second direction constitute the first sidewalls of the gate trenches.

[0008] According to some embodiments, forming a gate structure surrounding a target semiconductor layer in a gate trench includes: trimming the portion of the target semiconductor layer located in the gate trench along the inner diameter direction of the target semiconductor layer to obtain a gate support pillar; forming a gate oxide layer on the outer surface of the gate support pillar; depositing a metal material layer, wherein the portion of the metal material layer surrounding the gate oxide layer constitutes a gate metal layer, and the gate oxide layer and the gate metal layer constitute the gate structure.

[0009] According to some embodiments, the portion of the metal material layer located on the first sidewall constitutes the second sidewall; after forming a gate structure surrounding the target semiconductor layer in the gate trench, the method includes: filling the gate trench with a first low-dielectric material layer, the upper surface of the first low-dielectric material layer being flush with the upper surface of the initial stacked structure; removing the first sidewall, the second sidewall, and a portion of the initial stacked structure to obtain a word line auxiliary trench extending in a third direction and with its bottom surface contacting the upper surface of the substrate; filling the word line auxiliary trench with a second low-dielectric material layer, the upper surface of the second low-dielectric material layer being flush with the upper surface of the initial stacked structure.

[0010] According to some embodiments, after forming a gate structure surrounding the target semiconductor layer in the gate trench, the method further includes: removing portions of the target semiconductor layer located on opposite sides of the gate trench along a second direction, and removing portions of the second low-dielectric material layer located between adjacent first dielectric layers along a first direction, to obtain a first word line trench; using the gate metal layer as an etch stop layer, etching the first low-dielectric material layer along the second direction to obtain a second word line trench; forming a first word line portion in the first word line trench, and forming a second word line portion in the second word line trench, wherein the first word line portion and the second word line portion constitute a word line structure.

[0011] According to some embodiments, after forming the word line structure, the process includes: removing a portion of the first dielectric layer located on opposite sides of the gate trench along a second direction to obtain a word line isolation trench; and forming a third low-dielectric material layer within the word line isolation trench.

[0012] According to some embodiments, the two gate trenches are symmetrical to each other along a third direction; after forming a third low-dielectric material layer in the word line isolation trench, the method includes: forming a body isolation structure between the two gate trenches with its bottom surface contacting the upper surface of the substrate; forming a source structure between the body isolation structure and an adjacent gate structure; and forming a drain structure on the side of the gate structure away from the body isolation structure along a third direction.

[0013] According to some embodiments, after forming a third low-dielectric material layer in the word line isolation trench, the method further includes: forming a body isolation structure with its bottom surface contacting the upper surface of the substrate between the two gate trenches; and forming a source structure and a drain structure on the target semiconductor layer located on opposite sides of the gate structure along a third direction, with the source structure located between the gate structure and the body isolation structure.

[0014] According to some embodiments, after forming a third low-dielectric material layer in the word line isolation trench, the method further includes: forming a capacitor structure on a target semiconductor layer between the body isolation structure and the source structure, and forming a bit line structure on a target semiconductor layer on the side of the drain structure away from the capacitor structure along a third direction.

[0015] According to some embodiments, the adjacent source structure along the third direction is symmetrical along the third direction; and / or the adjacent drain structure along the third direction is symmetrical along the third direction.

[0016] According to some embodiments, the first character line portion and the second character line portion are prepared in the same process step.

[0017] According to some embodiments, the length of the second word line portion along the third direction is equal to the length of the gate structure along the third direction.

[0018] According to some embodiments, the initial stacked structure is symmetrical about a second direction with respect to the axis of symmetry of the second trench isolation structure extending along a third direction.

[0019] According to some embodiments, at least two of the first low-dielectric material layer, the second low-dielectric material layer, and the third low-dielectric material layer are made of the same material.

[0020] According to some embodiments, this disclosure also provides a semiconductor structure prepared using the semiconductor structure preparation method in any embodiment of this disclosure. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a semiconductor structure fabrication method provided in one embodiment of the present disclosure;

[0023] Figures 2-5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12 and Figure 14 This is a three-dimensional cross-sectional schematic diagram of different steps in the semiconductor structure fabrication method provided in some embodiments of this disclosure;

[0024] Figure 5b for Figure 5a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0025] Figure 5c In one embodiment of this disclosure Figure 5a A schematic diagram of the cross-sectional structure obtained along the AA' direction after the gate structure is formed in the three-dimensional structure shown;

[0026] Figure 6b for Figure 6a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0027] Figure 7b for Figure 7a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0028] Figure 8b for Figure 8a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0029] Figure 9b for Figure 9aA schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0030] Figure 10b for Figure 10a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0031] Figure 11b for Figure 11a A schematic diagram of the cross-sectional structure of the three-dimensional structure shown along the AA' direction;

[0032] Figure 13 This is a top view schematic diagram of a storage cell structure provided in one embodiment of the present disclosure;

[0033] Figure 15 This is a top view schematic diagram of a storage cell structure provided in another embodiment of this disclosure;

[0034] Among them, the oz direction can be the first direction, the oy direction can be the second direction, the ox direction can be the third direction, and the oz direction can be the height / thickness direction.

[0035] Explanation of reference numerals in the attached figures:

[0036] 100. Substrate; 11. First dielectric layer; 12. Target semiconductor layer; 1311. First trench; 1321. Second trench; 1331. Third trench; 131. First trench isolation structure; 132. Second trench isolation structure; 133. Third trench isolation structure; 134. First mask layer; 14. Gate trench; 141. First sidewall; 142. Second sidewall; 143. Gate support pillar; 21. Gate oxide layer; 22. Gate metal layer ; 20. Gate structure; 144. First low-dielectric material layer; 15. Word line auxiliary trench; 16. Second low-dielectric material layer; 41. First word line trench; 31. First word line; 32. Second word line; 30. Word electrode structure; 17. Third low-dielectric material layer; 18. Body isolation structure; 191. Source structure; 192. Drain structure; 40. Capacitor structure; 50. Bit line structure; 200. Memory cell structure; 300. Body structure. Detailed Implementation

[0037] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of this disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0043] Please note that the mutual insulation between the two in the embodiments of this disclosure includes, but is not limited to, the presence of one or more of the following: insulating material, insulating fumes, or gaps.

[0044] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor processes are gradually transitioning from planar transistors to more efficient three-dimensional transistors, such as Gate All Around (GAA) transistors. In GAA transistors, the gate surrounds the channel area from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects. GAA transistors include Lateral Gate All Around (LGAA) transistors and Vertical Gate All Around (VGAA) transistors. In LGAA transistors, the channel and gate structures extend parallel to the substrate surface, making it difficult to control the dimensions of the gate structure and the word lines connected to it. Furthermore, increasing the number of memory cells per unit volume by directly forming word lines extending parallel to the substrate surface outside the gate structure inevitably reduces the volume of the word lines and the spacing between adjacent word lines, increasing the complexity of the fabrication process and reducing the performance and reliability of the fabricated products.

[0045] This disclosure aims to provide a semiconductor structure fabrication method and semiconductor structure, which can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures while ensuring that the number of memory cells per unit volume is not reduced, and can control the size of the transistor gate structure connected to the word line structure, thereby reducing the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0046] Please refer to Figure 1 In some embodiments of this disclosure, a method for fabricating a semiconductor structure is provided, comprising the following steps:

[0047] Step S110: Provide a substrate and form an initial stacked structure on the substrate. The initial stacked structure includes a first dielectric layer and a target semiconductor layer that are alternately stacked along a first direction. The first dielectric layer is adjacent to the substrate.

[0048] Step S120: Form a first trench isolation structure, a second trench isolation structure and a third trench isolation structure that are spaced apart along the second direction and extend along the third direction within the initial stacked structure;

[0049] Step S130: Form two spaced gate trenches with the bottom surface contacting the upper surface of the substrate, with the portion of the target semiconductor layer located within the gate trenches exposed and suspended;

[0050] Step S140: A gate structure surrounding the target semiconductor layer is formed in the gate trench, and adjacent gate structures along the first direction and the second direction are mutually insulated; the first direction, the second direction and the third direction are perpendicular to each other.

[0051] Specifically, after forming a first trench isolation structure, a second trench isolation structure, and a third trench isolation structure spaced apart along the second direction and extending along the third direction within the initial stacked structure, two spaced gate trenches with their bottom surfaces contacting the upper surface of the substrate are formed, exposing and suspending a portion of the target semiconductor layer within the gate trenches, thereby forming a gate structure surrounding the target semiconductor layer within the gate trenches. Since the exposed and suspended portion of the target semiconductor layer within the gate trenches can be trimmed and modified before forming the gate structure, the size of the subsequently formed gate structure can be controlled. Since the first trench isolation structure and the third trench isolation structure can be used to form bridge word lines connected to the gate structure, and then multiple layers of spaced horizontal word lines are stacked in a direction perpendicular to the substrate surface, allowing the horizontal word lines to connect to the corresponding gate structure via the bridge word lines, compared to directly forming multiple word line structures stacked in a direction perpendicular to the substrate surface on the outside of the gate structure, this embodiment can at least increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume, reducing the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0052] For example, please refer to Figures 1-2 Step S110 may include the following steps:

[0053] Step S111: Provide substrate 100;

[0054] Step S112: An initial stacked structure is formed on the substrate 100. The initial stacked structure includes a first dielectric layer 11 and a target semiconductor layer 12 that are alternately stacked along a first direction (e.g., the oz direction). The first dielectric layer 11 is adjacent to the substrate 100.

[0055] For example, a first-type doped well region (not shown) is formed within the substrate 100. The substrate can be constructed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 100 should not limit the scope of this disclosure. P-type ions can be implanted into the substrate 100 using an ion implantation process to form a first type of doped well region (not shown). The P-type ions can be any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. The material of the first dielectric layer 11 can be, but is not limited to, silicon-germanium (SiGe), and the material of the target semiconductor layer 12 can be, but is not limited to, silicon (Si). The silicon-germanium first dielectric layer 11 can completely transfer the silicon lattice of the substrate 100 to the stacked silicon channel layers, ensuring that each silicon channel layer has the same silicon lattice as the substrate 100.

[0056] For example, please refer to Figures 1-4In step S120, an etching process can be used to form a first trench 1311, a second trench 1321, and a third trench 1331 within the initial stacked structure. These trenches are spaced apart along a second direction (e.g., the oy direction) and extend along a third direction (e.g., the ox direction). The first trench 1311, the second trench 1321, and the third trench 1331 expose the upper surface of the substrate 100. The first direction (e.g., the oz direction), the second direction (e.g., the oy direction), and the third direction (e.g., the ox direction) are perpendicular to each other. The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high-concentration plasma etching (HDP). Then, using a deposition process, isolation materials are deposited in the first trench 1311, the second trench 1321, and the third trench 1331 to obtain the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133. The bottom surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 contact the upper surface of the substrate 100. After forming the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133, a chemical mechanical polishing process can be used. CMP (Chemical Motion Polishing) flushes the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 with the upper surface of the initial stacked structure. This facilitates the formation of a smooth first mask layer on the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133, and the etching of the initial stacked structure based on the patterned first mask layer to obtain the gate trench, thereby improving the controllability of the morphology after gate trench etching. The isolation material within the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 may include one or more of polysilicon, silicon nitride, silicon oxide, and silicon oxynitride. The deposition process may include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0057] As an example, please continue to refer to Figure 4The initial stacked structure is symmetrical about the axis of symmetry of the second trench isolation structure 132 extending along a third direction (e.g., the ox direction) to improve the symmetry of the semiconductor structure, reduce the process complexity, and facilitate the monitoring of the structural and electrical parameters of the fabricated product.

[0058] As an example, please continue to refer to Figure 4 The thickness of the target semiconductor layer 12 can be [60nm, 100nm], for example, the thickness of the target semiconductor layer 12 can be 60nm, 70nm, 80nm, 90nm or 100nm, etc. The thickness of the first dielectric layer 11 can be [5nm, 20nm], for example, the thickness of the first dielectric layer 11 can be 5nm, 10nm, 15nm or 20nm, etc. The first dielectric layer 11 itself provides tensile stress, and each layer cannot be too thick, otherwise it is easy to cause problems such as body tilting; defects are inevitable in the fabrication process of the target semiconductor layer 12, and increasing its thickness means increasing the probability and / or number of defect locations; if the thickness of the silicon-germanium first dielectric layer 11 is too thick and there are many defects, it is easy to cause more severe mismatch of the top target semiconductor layer 12.

[0059] For example, please refer to Figure 1 , Figures 4-5b The step of forming two spaced gate trenches 14 with their bottom surfaces contacting the upper surface of the substrate in step S130 may include the following steps:

[0060] Step S131: Form a first mask layer 134, which covers the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132 and the third trench isolation structure 133;

[0061] Step S132: Pattern the first mask layer 134, and etch the initial stacked structure based on the patterned first mask layer 134 as a mask to obtain the gate trench 14. The remaining portions of the first trench isolation structure 131 and the remaining portions of the third trench isolation structure 133 located on opposite sides of the gate trench 14 along the second direction (e.g., the oy direction) constitute the first sidewall 141 of the gate trench 14.

[0062] As an example, please continue to refer to Figure 4In step S131, a deposition process can be used to form a first mask layer 134 covering the upper surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133. The first mask layer 134 can include a single-layer structure or a multi-layer structure. The first mask layer 134 includes, but is not limited to, hard mask layers. Hard mask layers are, for example, spin-on hard masks (SOH). The SOH layer can be an insulating layer of a hydrocarbon (CxHy) system, which may include silicon hard mask materials, carbon hard mask materials, and organic hard mask materials, etc. SOH is an auxiliary material for forming semiconductor micro-patterns, and it has the characteristics of filling gaps, increasing flatness, and enhancing corrosion resistance. Using this material to form a hard mask layer can improve the subsequent etching effect. The deposition process can include, but is not limited to, one or more of CVD, ALD, HDP, and SOD processes.

[0063] As an example, please continue to refer to Figures 5a-5b In step S132, the initial stacked structure can be etched using a patterned first mask layer 134 as a mask and dry etching and wet etching processes to obtain a gate trench 14. The portion of the target semiconductor layer 12 located within the gate trench is exposed and suspended. The remaining portions of the first trench isolation structure 131 and the remaining portions of the third trench isolation structure 133 located on opposite sides of the gate trench 14 along a second direction (e.g., the oy direction) constitute the first sidewall 141 of the gate trench 14 to protect the sidewalls of the gate trench 14. Before forming the gate structure, the exposed and suspended portion of the target semiconductor layer 12 within the gate trench 14 can be trimmed and modified, thereby controlling the dimensions of the subsequently formed gate structure.

[0064] For example, please refer to Figure 1 and Figure 5c The formation of the gate structure 20 surrounding the target semiconductor layer 12 within the gate trench 14 in step S140 may include the following steps:

[0065] Step S141: Trim the portion of the target semiconductor layer 12 located inside the gate trench 14 along the inner diameter direction of the target semiconductor layer 12 to obtain the gate support pillar 143;

[0066] Step S142: Form a gate oxide layer 21 on the outer surface of the gate support pillar 143;

[0067] Step S143: Deposit a metal material layer. The portion of the metal material layer surrounding the gate oxide layer 21 constitutes the gate metal layer 22. The gate oxide layer 21 and the gate metal layer 22 constitute the gate structure 20.

[0068] As an example, please continue to refer to Figure 5cIn step S141, an etching process can be used to trim the portion of the target semiconductor layer 12 located within the gate trench 14 along the inner diameter direction of the target semiconductor layer 12. By controlling the etching rate and etching time, the thickness of the target semiconductor layer 12 removed can be controlled, thereby controlling the thickness and length along the oy direction of the gate support pillar 143. This allows control over the thickness and length along the oy direction of the gate oxide layer 21 or gate metal layer 22 subsequently formed on the outer surface of the gate support pillar 143. The etching process can include, but is not limited to, dry etching and / or wet etching. Dry etching processes can include, but are not limited to, any one or more of RIE, ICP, and HDP.

[0069] As an example, please continue to refer to Figure 5c In step S142, one or more of the following processes can be used to form a gate oxide layer 21 on the outer surface of the gate support pillar 143 within the gate trench 14: in-situ steam generation (ISSG), atomic layer deposition (ALD), plasma vapor deposition (PVD), and rapid thermal oxidation (RTO). The gate oxide layer 21 can be formed using a material with a high k dielectric constant. For example, the material of the gate oxide layer 21 can include, but is not limited to, one or more of the following: aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), and strontium titanium oxide (SrTiO3).

[0070] As an example, please continue to refer to Figure 5cIn step S143, a metal material layer can be formed using a deposition process. The portion of the metal material layer located on the first sidewall 141 constitutes the second sidewall 142; the portion of the metal material layer surrounding the gate oxide layer 21 constitutes the gate metal layer 22. The gate oxide layer 21 and the gate metal layer 22 constitute the gate structure 20. The deposition process can be any one or more of the following, including but not limited to chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD). The metal material layer can be any one or more of the following, including but not limited to titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W). Since the thickness of the target semiconductor layer 12 removed during the trimming of the target semiconductor layer 12 can be controlled, the thickness of the gate support pillar 143 and its length along the oy direction can be controlled. This allows control over the thickness and length along the oy direction of the gate oxide layer 21 or gate metal layer 22 subsequently formed on the outer surface of the gate support pillar 143, thereby enabling control over the dimensions of the fabricated gate structure 20.

[0071] For example, please refer to Figure 1 , Figures 6a-8b After forming the gate structure 20 surrounding the target semiconductor layer 12 in the gate trench 14 in step S140, the following steps may also be included:

[0072] Step S151: Fill the gate trench 14 with a first low-dielectric material layer 144, the upper surface of the first low-dielectric material layer 144 being flush with the upper surface of the initial stacked structure.

[0073] Step S152: Remove the first sidewall 141, the second sidewall 142 and part of the initial stacked structure to obtain a word line auxiliary trench 15 that extends along the third direction and whose bottom surface contacts the upper surface of the substrate 100.

[0074] Step S153: Fill the word line auxiliary trench 15 with a second low dielectric material layer 16, the upper surface of the second low dielectric material layer 16 being flush with the upper surface of the initial stacked structure.

[0075] As an example, please continue to refer to Figures 6a-6bIn step S151, one or more of the following processes can be used to fill the gate trench 14 with a first low-dielectric material layer 144: In-situ Steam Generation (ISSG), atomic layer deposition, plasma vapor deposition, and rapid thermal oxidation (RTO). Afterward, one or more of the following processes can be used: wet etching, dry etching, chemical mechanical polishing, and planar etching to planarize the upper surface of the first low-dielectric material layer 144 along the thickness direction (e.g., the oz direction), so that the upper surface of the first low-dielectric material layer 144 is flush with the upper surface of the initial stacked structure, so as to protect the gate structure 20 during the subsequent etching and formation of word line trenches.

[0076] As an example, please continue to refer to Figures 7a-7b In step S152, an etching process can be used to remove the first sidewall 141, the second sidewall 142, and part of the initial stacked structure, resulting in a word line auxiliary trench 15 extending along a third direction (e.g., the ox direction) and with its bottom surface contacting the upper surface of the substrate 100. This facilitates the subsequent formation of bridge word lines that connect to the gate structure via the word line auxiliary trench 15. Subsequently, multiple layers of horizontally spaced word lines are stacked in a direction perpendicular to the upper surface of the substrate 100, allowing the horizontal word lines to connect to the corresponding gate structure via the bridge word lines. Compared to directly forming a multi-layer word line structure stacked in a direction perpendicular to the upper surface of the substrate 100 on the outside of the gate structure, this embodiment can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product. The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, any one or more of RIE, ICP, and HDP.

[0077] As an example, please continue to refer to Figures 8a-8b In step S153, a second low-dielectric material layer 16 can be filled into the word line auxiliary trench 15 using a deposition process. Then, one or more of the following processes can be used: wet etching, dry etching, chemical mechanical polishing, and planar etching, to planarize the upper surface of the second low-dielectric material layer 16 along the thickness direction (e.g., the oz direction), making the upper surface of the second low-dielectric material layer 16 flush with the upper surface of the initial stacked structure. This facilitates the protection of the gate structure 20 during the subsequent etching and formation of the word line trench. The deposition process can include, but is not limited to, one or more of the following processes: CVD, ALD, HDP, and SOD.

[0078] For example, please refer to Figure 1 , Figures 9a-10b After forming the gate structure 20 surrounding the target semiconductor layer 12 in the gate trench 14 in step S140, the following steps may also be included:

[0079] Step S161: Remove the portion of the target semiconductor layer 12 located on opposite sides of the gate trench 14 along the second direction, and remove the portion of the second low dielectric material layer 16 located between adjacent first dielectric layers 11 along the first direction to obtain the first word line trench 41;

[0080] Step S162: Using the gate metal layer 22 as the etching stop layer, etch the first low dielectric material layer 144 along the second direction to obtain the second word line trench (not shown);

[0081] Step S163: A first character line portion 31 is formed in the first character line portion groove 41, and a second character line portion 32 is formed in the second character line portion groove (not shown). The first character line portion 31 and the second character line portion 32 constitute the character line structure 30.

[0082] As an example, please continue to refer to Figures 9a-9b In step S161, an etching process can be used to remove the portion of the target semiconductor layer 12 located on opposite sides of the gate trench 14 along the second direction (e.g., the oy direction), and to remove the portion of the second low-dielectric material layer 16 located between adjacent first dielectric layers 11 along the first direction (e.g., the oz direction), thereby obtaining the first word line trench 41. The etching process can include, but is not limited to, dry etching and / or wet etching processes. The dry etching process can include, but is not limited to, any one or more of RIE, ICP, and HDP.

[0083] As an example, please continue to refer to Figure 9a The length of the second word line portion 32 along a third direction (e.g., the ox direction) is equal to the length of the gate structure 20 along a third direction (e.g., the ox direction) to reduce the connection impedance between the word line structure 30 and the gate structure 20.

[0084] As an example, please continue to refer to Figures 9a-10bIn step S162, the gate metal layer 22 can be used as the etching stop layer, and the first low-dielectric material layer 144 can be etched along the second direction using an etching process to obtain the second word line trench. The etching process can include, but is not limited to, dry etching and / or wet etching processes. The dry etching process can include, but is not limited to, any one or more of RIE, ICP, and HDP. In step S163, a deposition process can be used to form the first word line 31 in the first word line trench 41 and the second word line 32 in the second word line trench (not shown). The first word line 31 and the second word line 32 constitute the word line structure 30. The first word line 31 and the second word line 32 can be formed in the same process step or in different process steps. The deposition process can include, but is not limited to, any one or more of CVD, ALD, HDP, and SOD processes. The material of the character line structure 30 may be one or more of the following, including but not limited to rubidium, cobalt, nickel, titanium, tungsten, tantalum, tantalum titanide, tungsten nitride, copper and aluminum.

[0085] For example, please refer to Figures 11a-11b After forming the word line structure 30 in step S163, the following steps are also included:

[0086] Step S171: Remove the portion of the first dielectric layer 11 located on both sides of the gate trench 14 along the second direction (e.g., the oy direction) to obtain a word line isolation trench (not shown);

[0087] Step S172: Form a third low-dielectric material layer 17 within the word line isolation trench.

[0088] As an example, please continue to refer to Figures 11a-11bIn step S171, an etching process can be used to remove portions of the first dielectric layer 11 located on opposite sides of the gate trench 14 along the second direction, resulting in a word line isolation trench (not shown). The etching process can include, but is not limited to, dry etching and / or wet etching. Dry etching can include, but is not limited to, any one or more of RIE, ICP, and HDP. In step S172, a deposition process can be used to form a third low-dielectric material layer 17 within the word line isolation trench, ensuring that adjacent word line structures 30 are mutually insulated along the oz direction. The deposition process can include, but is not limited to, any one or more of CVD, ALD, HDP, and SOD processes. At least two of the first low-dielectric material layer 144, the second low-dielectric material layer 16, and the third low-dielectric material layer 17 are made of the same material. The low-dielectric material layer can include, but is not limited to, silicon oxide, SiLK, MSQ, porous SiLK, and porous MSQ, any one or more of these materials. Compared to multilayer word line structures that are directly formed on the outside of the gate structure and stacked in a direction perpendicular to the substrate surface, this embodiment can increase the space volume occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0089] For example, please refer to Figures 12-13 Two gate trenches 14 can be configured to be symmetrical to each other along a third direction (e.g., the ox direction); after forming the third low-dielectric material layer 17 in the word line isolation trench in step S172, the following steps may also be included:

[0090] Step S181: Form a body isolation structure 18 between the two gate trenches 14, with the bottom surface contacting the upper surface of the substrate 100;

[0091] Step S182: A source structure 191 is formed between the body isolation structure 18 and the adjacent gate structure 20, and a drain structure 192 is formed on the side of the gate structure 20 away from the body isolation structure 18 along a third direction (e.g., the ox direction).

[0092] As an example, please continue to refer to Figure 12 In step S181, an etching process can be used to etch the initial stacked structure to obtain a bulk isolation trench (not shown). The etching process can include, but is not limited to, dry etching and / or wet etching. The dry etching process can include, but is not limited to, any one or more of RIE, ICP, and HDP. Then, an isolation material is deposited in the bulk isolation trench to obtain the bulk isolation structure 18. The deposition process can include, but is not limited to, any one or more of CVD, ALD, HDP, and SOD. The isolation material can include, but is not limited to, any one or more of silicon nitride, silicon oxide, silicon oxynitride, and polysilicon.

[0093] As an example, please continue to refer to Figure 13 The position of the body isolation structure 18 can be set so that the semiconductor structure is symmetrical about the axis of symmetry m1 extending along the oy direction of the body isolation structure 18, or the gate structure 20 adjacent along the oy direction can be symmetrical about the axis of symmetry m2.

[0094] As an example, please continue to refer to Figure 13 In step S182, a source structure 191 can be formed on the target semiconductor layer between the body isolation structure 18 and the adjacent gate structure 20, and a drain structure 192 can be formed on the target semiconductor layer on the side of the gate structure 20 away from the body isolation structure 18 along a third direction (e.g., the ox direction), resulting in a memory cell structure 200. Adjacent source structures 191 along the ox direction are symmetrical about the axis of symmetry m1, and adjacent drain structures 192 along the ox direction are also symmetrical about the axis of symmetry m1. In this embodiment, a plurality of body structures 300 are spaced apart along the oz direction, and each body structure 300 includes four centrally symmetrical memory cell structures 200. Because the exposed and suspended portions of the target semiconductor layer within the gate trench can be trimmed and altered before the gate structure is formed, the dimensions of the subsequently formed gate structure can be controlled. Furthermore, because the first and third trench isolation structures can be used to form bridge word lines connected to the gate structure, and multiple layers of horizontally spaced word lines can be stacked in a direction perpendicular to the substrate surface, allowing the horizontal word lines to connect to the corresponding gate structure via the bridge word lines, this embodiment, compared to directly forming multiple word line structures stacked in a direction perpendicular to the substrate surface on the outside of the gate structure, can increase the space occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0095] As an example, please continue to refer to Figure 13 In the memory cell structure 200, the target semiconductor layer extends along the ox direction and can employ first-type doping, such as light P-type doping. The channel conductive layer (not shown) is located between the source structure 191 and the drain structure 192 and can employ first-type doping, such as heavy P-type doping, to form the channel region of the transistor. The drain structure 192 can employ second-type doping, such as heavy N-type doping, to form the drain region of the transistor. The source structure 191 can employ second-type doping, such as heavy N-type doping, to form the source region of the transistor. P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions; N-type impurity ions can include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0096] For example, please refer to Figures 14-15 After forming the third low-dielectric material layer 17 in the word line isolation trench in step S172, the following steps may also be included:

[0097] Step S181: Form a body isolation structure 18 between the two gate trenches 14, with the bottom surface contacting the upper surface of the substrate 100;

[0098] Step S183: A source structure 191 and a drain structure 192 are formed on the target semiconductor layer located on opposite sides of the gate structure 20 along a third direction (e.g., the ox direction). The source structure 191 is located between the gate structure 20 and the body isolation structure 18.

[0099] As an example, please continue to refer to Figure 15 The semiconductor structure fabrication method described in this embodiment yields a plurality of body structures 300 spaced apart along the oz direction. Each body structure 300 includes a memory cell structure 200 symmetrical about the symmetry axis m2. The target semiconductor layer in the memory cell structure 200 extends along the ox direction and can employ a first type of doping, such as light P-type doping. A channel conductive layer (not shown) is located between the source structure 191 and the drain structure 192 and can employ a first type of doping, such as heavy P-type doping, to form the channel region of the transistor. The drain structure 192 can employ a second type of doping, such as heavy N-type doping, to form the drain region of the transistor. The source structure 191 can employ a second type of doping, such as heavy N-type doping, to form the source region of the transistor. P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions; N-type impurity ions can include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions.

[0100] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0101] Please refer to Figures 5a-5cThe semiconductor structure provided in this embodiment includes a substrate 100 and an initial stacked structure on the substrate 100. The initial stacked structure includes a first dielectric layer 11 and a target semiconductor layer 12 alternately stacked along a first direction (e.g., the oz direction). The first dielectric layer 11 is adjacent to the substrate 100. A first trench isolation structure 131, a second trench isolation structure 132, and a third trench isolation structure 133 are formed within the initial stacked structure, arranged at intervals along a second direction (e.g., the oy direction) and extending along a third direction (e.g., the ox direction). The bottom surfaces of the first trench isolation structure 131, the second trench isolation structure 132, and the third trench isolation structure 133 are in contact with the upper surface of the substrate 100; two spaced gate trenches 14 are formed in the initial stacked structure, with the target semiconductor layer 12 partially exposed and suspended inside the gate trenches 14; a gate structure 20 is disposed around the outside of the target semiconductor layer 12 inside the gate trenches 14, and adjacent gate structures 20 along the first direction (e.g., the oz direction) and the second direction (e.g., the oy direction) are mutually insulated; the first direction, the second direction, and the third direction are perpendicular to each other. Because the exposed and suspended portions of the target semiconductor layer within the gate trench can be trimmed and altered before the gate structure is formed, the dimensions of the subsequently formed gate structure can be controlled. Furthermore, because the first and third trench isolation structures can be used to form bridge word lines connected to the gate structure, and multiple layers of horizontally spaced word lines can be stacked in a direction perpendicular to the substrate surface, allowing the horizontal word lines to connect to the corresponding gate structure via the bridge word lines, this embodiment, compared to directly forming multiple word line structures stacked in a direction perpendicular to the substrate surface on the outside of the gate structure, can increase the space occupied by the word line structure and the spacing between adjacent word line structures without reducing the number of memory cells per unit volume. This reduces the complexity of the fabrication process while increasing the performance and reliability of the fabricated product.

[0102] Please note that the above embodiments are for illustrative purposes only and do not imply limitation of this disclosure. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually.

[0103] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of this disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the disclosed patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and an initial stacked structure is formed on the substrate. The initial stacked structure includes a first dielectric layer and a target semiconductor layer that are alternately stacked sequentially along a first direction. The first dielectric layer is adjacent to the substrate. A first trench isolation structure, a second trench isolation structure, and a third trench isolation structure are formed within the initial stacked structure, which are spaced apart along the second direction and extend along the third direction. Two spaced gate trenches are formed with their bottom surfaces contacting the upper surface of the substrate, and the portion of the target semiconductor layer located within the gate trenches is exposed and suspended. A gate structure is formed within the gate trench surrounding the target semiconductor layer, and adjacent gate structures along the first direction and the second direction are mutually insulated; the first direction, the second direction, and the third direction are perpendicular to each other; The upper surfaces of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure are flush with the upper surface of the initial stacked structure; The formation of two spaced gate trenches with their bottom surfaces contacting the upper surface of the substrate includes: A first mask layer is formed, which covers the upper surfaces of the first trench isolation structure, the second trench isolation structure, and the third trench isolation structure; The first mask layer is patterned, and the initial stacked structure is etched based on the patterned first mask layer as a mask to obtain the gate trench. The remaining portions of the first trench isolation structure and the remaining portions of the third trench isolation structure located on opposite sides of the gate trench along the second direction constitute the first sidewall of the gate trench.

2. The semiconductor structure fabrication method according to claim 1, characterized in that, The formation of a gate structure surrounding the target semiconductor layer within the gate trench includes: Trim the portion of the target semiconductor layer located within the gate trench along the inner diameter direction of the target semiconductor layer to obtain a gate support pillar; A gate oxide layer is formed on the outer surface of the gate support pillar; A metal material layer is deposited, the portion of which surrounds the gate oxide layer constitutes a gate metal layer, and the gate oxide layer and the gate metal layer constitute the gate structure.

3. The semiconductor structure fabrication method according to claim 2, characterized in that, The portion of the metal material layer located on the first sidewall constitutes the second sidewall; after forming the gate structure surrounding the target semiconductor layer within the gate trench, the process includes: A first low-dielectric material layer is filled in the gate trench, and the upper surface of the first low-dielectric material layer is flush with the upper surface of the initial stacked structure. Remove the first sidewall, the second sidewall, and part of the initial stacked structure to obtain a word line auxiliary trench that extends along the third direction and whose bottom surface contacts the upper surface of the substrate. A second low-dielectric material layer is filled in the word line auxiliary trench, and the upper surface of the second low-dielectric material layer is flush with the upper surface of the initial stacked structure.

4. The semiconductor structure fabrication method according to claim 3, characterized in that, After forming the gate structure surrounding the target semiconductor layer within the gate trench, the method further includes: Remove the portion of the target semiconductor layer located on opposite sides of the gate trench along the second direction, and remove the portion of the second low-dielectric material layer located between the adjacent first dielectric layers along the first direction to obtain the first word line trench; Using the gate metal layer as the etching stop layer, the first low-dielectric material layer is etched along the second direction to obtain the second word line trench; A first character line portion is formed in the groove of the first character line portion, and a second character line portion is formed in the groove of the second character line portion, wherein the first character line portion and the second character line portion constitute a character line structure.

5. The semiconductor structure fabrication method according to claim 4, characterized in that, After forming the word line structure, the process includes: Remove the portion of the first dielectric layer located on both sides of the gate trench along the second direction to obtain a word line isolation trench; A third low-dielectric material layer is formed within the word line isolation trench.

6. The semiconductor structure fabrication method according to claim 5, characterized in that, The two gate trenches are symmetrical to each other along the third direction; After forming a third low-dielectric material layer within the word line isolation trench, the process includes: A body isolation structure is formed between the two gate trenches, with its bottom surface contacting the upper surface of the substrate; A source structure is formed between the body isolation structure and the adjacent gate structure, and a drain structure is formed on the side of the gate structure away from the body isolation structure along the third direction.

7. The semiconductor structure fabrication method according to claim 5, characterized in that, After forming a third low-dielectric material layer within the word line isolation trench, the method further includes: A body isolation structure is formed between the two gate trenches, with its bottom surface contacting the upper surface of the substrate; A source structure and a drain structure are formed on a target semiconductor layer located on opposite sides of the gate structure along the third direction, wherein the source structure is located between the gate structure and the body isolation structure.

8. The method for fabricating a semiconductor structure according to claim 6 or 7, characterized in that, After forming a third low-dielectric material layer within the word line isolation trench, the method further includes: A capacitor structure is formed on a target semiconductor layer between the body isolation structure and the source structure, and a bit line structure is formed on a target semiconductor layer on the side of the drain structure away from the capacitor structure along the third direction.

9. The semiconductor structure fabrication method according to claim 6, characterized in that: The source structures adjacent to the third direction are symmetrical along the third direction; and / or The adjacent drain structures along the third direction are symmetrical along the third direction.

10. The method for fabricating a semiconductor structure according to any one of claims 4-7, characterized in that, The first and second letter lines are prepared in the same process step.

11. The method for fabricating a semiconductor structure according to any one of claims 4-7, characterized in that, The length of the second word line portion along the third direction is equal to the length of the gate structure along the third direction.

12. The method for fabricating a semiconductor structure according to any one of claims 1-7, characterized in that, The initial stacked structure is symmetrical about the second direction with respect to the axis of symmetry of the second trench isolation structure extending along the third direction.

13. The method for fabricating a semiconductor structure according to any one of claims 5-7, characterized in that, At least two of the first low-dielectric material layer, the second low-dielectric material layer, and the third low-dielectric material layer are made of the same material.

14. A semiconductor structure, characterized in that, It is prepared by the semiconductor structure preparation method according to any one of claims 1-13.

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