Photoelectric conversion apparatus, camera module, endoscope, endoscope system, and device

Abstract

An optical-electric conversion apparatus includes: a pixel array in which a plurality of pixels are arranged so as to form a plurality of rows and a plurality of columns; a drive controller configured to drive the pixel array; a horizontal transfer unit configured to sequentially output analog signals respectively output from the plurality of columns of the pixel array; an AD converter configured to convert the analog signals output from the horizontal transfer unit into digital signals; a first clock generator configured to generate a clock signal for controlling an operation of the drive controller; and a second clock generator configured to generate a clock signal for controlling the horizontal transfer unit and the AD converter, and a clock tree in which clock signals are distributed from the first clock generator and a clock tree in which clock signals are distributed from the second clock generator form different clock trees from each other.

Description

Technical Field

[0001] This invention relates to photoelectric conversion devices, camera modules, endoscopes, endoscope systems, and apparatus. Background Technology

[0002] In recent years, ultra-miniature photoelectric conversion devices have been developed for applications such as endoscopes. In the endoscope system described in PTL 1, analog image signals are output via signal cables, and AD conversion is performed externally to the photoelectric conversion device, thereby reducing the circuit size of the photoelectric conversion device. However, in the configuration described in PTL 1, the output image is susceptible to noise due to the use of a long transmission path for outputting analog signals. On the other hand, NPL 1 describes an ultra-miniature digital image sensor that includes a successive approximation AD converter in the photoelectric conversion device and outputs a digital signal.

[0003] Citation List

[0004] Patent documents

[0005] PTL 1: Japanese Patent Application Publication No. 2020-192328

[0006] Non-patent literature

[0007] NPL 1: M. Waeny et al., "Ultra small digital image sensor for endoscopic applications", briefing at the 2009 International Image Sensor Workshop, (Norway), March 26, 2009. Summary of the Invention

[0008] Technical issues

[0009] In the configuration described in NTPL 1, the readout controller controls the image capture and horizontal transfer operations using a clock output from a ring oscillator, and the AD conversion controller controls the AD converter. Since the AD conversion needs to operate synchronously with the horizontal transfer operation, the number of clock buffers arranged in the circuit for timing control increases to maintain synchronization between the control of the readout controller and the control of the AD conversion controller, and the circuit size becomes larger. The increased number of clock buffers also leads to increased power consumption.

[0010] The purpose of this invention is to provide a technique that is advantageous in suppressing the increase in circuit size and power consumption caused by clock control, and in miniaturizing photoelectric conversion devices.

[0011] Solution to the problem

[0012] In view of the above problems, the photoelectric conversion device according to an embodiment of the present invention is a photoelectric conversion device comprising: a pixel array, wherein a plurality of pixels are arranged in the pixel array to form a plurality of rows and a plurality of columns; a drive controller configured to drive the pixel array; a horizontal transmission unit configured to sequentially output analog signals respectively output from the plurality of columns of the pixel array; an AD converter configured to convert the analog signals output from the horizontal transmission unit into digital signals; a first clock generator configured to generate a clock signal for controlling the operation of the drive controller; and a second clock generator configured to generate a clock signal for controlling the horizontal transmission unit and the AD converter, characterized in that the clock tree from which the clock signal is distributed from the first clock generator and the clock tree from which the clock signal is distributed from the second clock generator form different clock trees from each other.

[0013] Advantages of the invention

[0014] According to the present invention, there is a technique that is advantageous in suppressing the increase in circuit size and power consumption caused by clock control, and in miniaturizing photoelectric conversion devices.

[0015] Other features and advantages of the invention will become clear from the following description taken in conjunction with the accompanying drawings. It should be noted that the same reference numerals denote the same or similar components throughout all the drawings. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0017] Figure 1 This is a diagram illustrating an example of the arrangement of a photoelectric conversion device according to an embodiment;

[0018] Figure 2 It is shown Figure 1 An illustration of an example arrangement of pixels in a photoelectric conversion device;

[0019] Figure 3 It is shown Figure 1 A diagram illustrating an example arrangement of the horizontal transmission units of the photoelectric conversion device shown;

[0020] Figure 4 It is shown Figure 1 A diagram illustrating an example of output data during a horizontal transmission period of the photoelectric conversion device shown;

[0021] Figure 5 yes Figure 1 Timing diagram of horizontal transmission in the photoelectric conversion device shown;

[0022] Figure 6 It is shown Figure 1 A diagram illustrating an example arrangement of the AFE in the photoelectric conversion device shown;

[0023] Figure 7 It is shown Figure 1 A diagram illustrating an example arrangement of the AD converters in the photoelectric conversion device shown;

[0024] Figure 8 yes Figure 1 Timing diagram of the AFE in the photoelectric conversion device shown;

[0025] Figure 9 It is shown Figure 1 An example diagram illustrating the layout of the photoelectric conversion device shown;

[0026] Figure 10 It is shown Figure 2 An illustration of the pixel modifications shown;

[0027] Figure 11 It is shown Figure 3 A modified diagram of the horizontal transmission unit shown;

[0028] Figure 12A It is shown Figure 1 A modified illustration of the photoelectric conversion device shown;

[0029] Figure 12B It is shown Figure 12A An example diagram illustrating the layout of the photoelectric conversion device shown;

[0030] Figure 13 It shows including Figure 1 The diagram illustrates an example arrangement of the camera module of the photoelectric conversion device, the endoscope using the camera module, and the endoscope system; and

[0031] Figure 14 It shows including Figure 1 An example diagram illustrating the arrangement of the photoelectric conversion device. Detailed Implementation

[0032] In the following, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but the invention is not limited to requiring all such features, and multiple such features can be suitably combined. Furthermore, in the drawings, the same reference numerals are given to the same or similar configurations, and redundant descriptions thereof are omitted.

[0033] refer to Figures 1 to 14 The present disclosure will describe a photoelectric conversion device according to embodiments thereof. Figure 1 This is a block diagram illustrating a schematic arrangement of the photoelectric conversion device 100 according to this embodiment. Figure 1 As shown, the photoelectric conversion device 100 includes a pixel array 101, a drive controller 102, a horizontal transmission unit 104, an analog front end (AFE) 105, a digital signal processor (DSP) 107, and an output unit 108.

[0034] In pixel array 101, multiple pixels 201 are arranged to form multiple rows and multiple columns. Drive controller 102 drives pixel array 101. Horizontal transmission unit 104 sequentially outputs analog signals from multiple columns of pixel array 101 to vertical signal lines 202 to AFE 105. AFE 105 includes an analog amplifier and an AD converter, and converts the analog signals output from the horizontal transmission unit into digital signals. DSP 107 performs digital signal processing on the digital signals output from AFE 105. Output unit 108 is an interface for outputting digital data from DSP 107 to the outside of photoelectric conversion device 100.

[0035] The photoelectric conversion device 100 also includes a first clock generator 103 that generates clock signals for controlling the operation of the drive controller 102, and a second clock generator 106 that generates clock signals for controlling the horizontal transmission unit 104 and the AFE 105. The first clock generator 103 uses the first clock signal to control the drive controller 102. The second clock generator 106 uses a second clock signal and a third clock signal to control the horizontal transmission unit 104 and the AFE 105. The first clock generator 103, the second clock generator 106, and the corresponding clock signals will be described later.

[0036] Figure 2 An example of the arrangement of pixels 201 in pixel array 101 is shown. The output node of pixel 201 is connected to vertical signal line 202. Vertical signal line 202 is connected to a constant current source (not shown) and horizontal transmission unit 104.

[0037] Pixel 201 includes a photoelectric conversion element 311, a charge transfer switch 312, a floating diffuser (FD), a reset switch 313, a signal amplification switch 314, and a row selection switch 315. The photoelectric conversion element 311 may be, for example, a device such as a photodiode (PD) that generates a charge corresponding to the amount of light entering the photoelectric conversion element 311.

[0038] A charge transfer switch 312 is disposed between the photoelectric conversion element 311 and the floating diffuser FD. The charge transfer switch 312 may be a transfer transistor used to read the charge stored in the photoelectric conversion element 311. The charge transfer switch 312 is controlled between an ON state and an OFF state by a control signal PTX.

[0039] A reset switch 313 is positioned between the power supply voltage VDD and the floating diffuser FD. The reset switch 313 may be a reset transistor used to supply the power supply voltage VDD to the floating diffuser FD to reset the circuit. The reset switch 313 is controlled by a control signal PRES to switch between an ON and OFF state.

[0040] The signal amplification switch 314 can be a source follower transistor that converts the charge stored in the floating diffuser FD into a voltage, amplifies it, and outputs it as a voltage signal to the vertical signal line 202. The control terminal of the signal amplification switch 314 is connected to the floating diffuser FD. The two main terminals of the signal amplification switch 314 are connected to the power supply voltage VDD and the row selection switch 315, respectively.

[0041] A row selection switch 315 is positioned between the output of the signal amplification switch 314 and the vertical signal line 202. The row selection switch 315 can be a transistor used to select the row from which the pixel signal is to be output. The row selection switch 315 is controlled between an ON and OFF state by a control signal PSEL.

[0042] In each pixel 201, for example, a noise signal (N signal) is read out, and then a signal signal (S signal) is read out. The change in the floating diffusion FD after the reset of the floating diffusion FD is released is read out as the N signal via signal amplification switch 314. Then, the charge of the photoelectric conversion element 311 is transferred to the floating diffusion FD via charge transfer switch 312, and the charge transferred from the photoelectric conversion element 311 to the floating diffusion is read out as the S signal via signal amplification switch 314. AFE 105 performs correlated double sampling processing on the S signal and N signal output from pixel 201 to remove reset noise from the floating diffusion FD.

[0043] The drive controller 102 controls the photoelectric conversion device 100 under the control of an external control device (not shown). The drive controller 102 controls its internal state machine according to serial communication with the external control device and transitions from a stopped state to an image capture state. In the image capture state, the drive controller 102 generates control signals PTX, PRES, and PSEL for the pixel array 101 based on, for example, the values ​​of horizontal and vertical counters arranged in the drive controller 102, thereby controlling the exposure control and readout operation of the pixels 201. The control signals PTX, PRES, and PSEL are generated for each row of the pixel array 101. The slit rolling operation can be performed by controlling the reset row scan and readout row scan for the pixels 201 in parallel.

[0044] The drive controller 102 also generates horizontal transfer control signals and readout control signals for the horizontal transfer unit 104, and image capture control signals for the AFE 105 and the second clock generator 106, based on a horizontal counter, a vertical counter, and a state machine. The horizontal transfer control signals are valid when image capture is completed and readout is ready in the top row of the pixel array 101, and invalid when readout is completed in the last row. Essentially, the horizontal transfer control signals indicate the time period for outputting analog signals from each pixel 201 in the pixel array 101. The readout control signals are used to control the output of N and S signals from the pixel 201 via the vertical signal line 202. The image capture control signals indicate the image capture time period for performing image capture in the pixel array 101. The image capture control signals are valid when the state machine of the drive controller 102 is in the image capture state. The image capture control signals are used to control the operation of the AFE 105 and the second clock generator 106.

[0045] The horizontal and vertical counters of the drive controller 102 can be controlled, for example, by an external synchronization method based on a synchronization signal externally input to the photoelectric conversion device 100, or by an internal synchronization method based on a synchronization signal generated internally by the horizontal and vertical counters. The internal synchronization method can reduce the number of input terminals when considering miniaturization of the photoelectric conversion device 100 for applications such as endoscopes. In this embodiment, pixels are driven by a slit-rolling operation. However, if the pixel structure supports a global shutter, then shutter scanning can be performed simultaneously on all pixels.

[0046] The horizontal transmission unit 104 has the function of outputting an analog signal of pixel 201 output from pixel array 101 to AFE 105 in synchronization with a horizontal transmission control signal transmitted from drive controller 102 and a second clock signal supplied from second clock generator 106. The horizontal transmission unit 104 also has the function of generating a horizontal synchronization signal indicating a horizontal time period and outputting it to AFE 105.

[0047] Figure 3 This is a block diagram illustrating an example arrangement of the horizontal transmission unit 104. The horizontal transmission unit 104 includes an edge detection circuit 1041, a horizontal transmission controller 1042, two sets of vertical signal line selectors 1043, and an output controller 1044.

[0048] Edge detection circuit 1041 detects the edge of the horizontal transmission control signal output to horizontal transmission unit 104 when drive controller 102 causes each pixel 201 in pixel array 101 to output an analog signal. When the edge of the horizontal transmission control signal is detected, edge detection circuit 1041 outputs a clock-width pulse to horizontal transmission controller 1042.

[0049] The horizontal transfer controller 1042 includes a shift register for each clock transfer pulse. The shift register may have a ring circuit arrangement in which multiple registers FF are connected serially and the output of the last stage register of the multiple registers FF is connected to the input of the first stage register of the multiple registers FF. The OR signal of the output pulse of the edge detection circuit 1041 and the signal of the last stage register in the shift register is input to the first stage register in the shift register.

[0050] The shift register of the horizontal transfer controller 1042 is configured such that the pulse cycles from the first-level register to the last-level register during a horizontal transfer period used to transfer a signal corresponding to a row of the pixel array 101. For example, consider the following case: Figure 4As shown, a horizontal transmission period includes a horizontal synchronization period Hblk, which comprises two periods and includes a period for outputting a horizontal synchronization signal, a horizontal blanking period, etc. In one period, a signal is output from one pixel 201, and signals are output from m pixels 201. The horizontal synchronization period Hblk is a period in which no signal is output from pixel 201. In this case, the shift register of the horizontal transmission controller 1042 can be formed by a shift register that cycles through m periods + the horizontal synchronization period Hblk (which includes two periods in this embodiment). That is, it can be said that the number of multiple registers FF included in the shift register of the horizontal transmission controller 1042 is defined by the number of pixels 201 that transmit signals in one horizontal transmission period and the horizontal synchronization period. The horizontal transmission controller 1042 is connected to the switch SWT of the vertical signal line selector 1043 to control the readout operation of the vertical signal line selector 1043 according to the pulse position of the shift register.

[0051] The vertical signal line selector 1043 has a memory function that holds the S-signal and N-signal of the pixel 201 input via the vertical signal line 202. For example, the wiring capacitance between switches SWT and SWS, and the wiring capacitance between switches SWT and SWN, can be used as memory. The vertical signal line selector 1043 has the function of outputting the S-signal and N-signal of each column of the pixel array 101 to the AFE 105 during a horizontal transmission period according to the control signal input from the horizontal transmission controller 1042.

[0052] The vertical signal line selector 1043 transmits analog signals output from pixels 201 arranged in a row of pixel array 101 to AFE 105 by using, for example, two horizontal transmission periods. Figure 5A timing diagram for horizontal transmission is shown. First, during the first horizontal transmission period, control signals P_TN1 and P_TS1 are read from the N signal input from the drive controller 102, and the N and S signals of the first row are sequentially output from pixel 201 to vertical signal line 202. Vertical signal line selector 1043 holds the N and S signals. Here, the N and S signals are respectively held in memory N and memory S of vertical signal line selector 1043. Then, during the second horizontal transmission period, the held N and S signals are sequentially output to AFE 105 according to the control signal output from the shift register of horizontal transmission controller 1042. Since the pulses cycle once in the shift register of horizontal transmission controller 1042 during one horizontal transmission period, the signal output from pixel 201 of one row is output to AFE 105 during one horizontal transmission period. During the horizontal synchronization period Hblk, when there is no pixel signal output during the horizontal transmission period, the vertical signal line selector 1043 does not select the vertical signal line 202 but selects a predetermined fixed potential, and this fixed potential is output to the AFE 105. Additionally, the output of the first-stage register of the horizontal transmission controller 1042 is output to the AFE 105 as the horizontal synchronization signal HS.

[0053] In this manner, the output of signals from pixels 201 arranged in a row of pixel array 101 and their horizontal transmission to AFE 105 are performed using two horizontal transmission periods. To transmit the analog signal output from pixel 201 to AFE 105 in each horizontal transmission period, horizontal transmission unit 104 may include at least two sets of vertical signal line selectors 1043. The two sets of vertical signal line selectors 1043 are controlled by output controller 1044 to alternately perform one of reading the signal from pixel 201 and its horizontal transmission for each horizontal transmission period. Figure 5 The horizontal transfer operation for the first row and the horizontal transfer operation for the second row are shown.

[0054] The horizontal transfer unit 104 repeats the above operation until the readout scan of the entire area of ​​the pixel array 101 is completed and the horizontal transfer control signal input from the drive controller 102 is invalid. Thus, an image signal of one frame is transferred from the pixel array 101 to the AFE 105. The horizontal transfer unit 104 can be reset until the horizontal transfer control signal is valid and the transfer of the next frame begins.

[0055] AFE 105 performs gain adjustment processing, correlation double sampling processing, and AD conversion processing to convert the analog signal into a digital signal on the S and N signals of the analog signal output from the horizontal transmission unit 104. Figure 6An example arrangement of AFE 105 in this embodiment is shown. AFE 105 includes AMP unit 1051, AD converter 1052, and horizontal synchronization signal delay circuit 1053.

[0056] The AMP unit 1051 performs correlated double sampling and gain adjustment processing on the S and N signals transmitted from the horizontal transmission unit 104. The gain adjustment processing can be performed using a programmable gain amplifier (PGA), which can adjust for each setting value from a register (not shown). When an image capture control signal is received from the drive controller 102, instructing for an image capture period to be performed in the pixel array 101, the AMP unit 1051 outputs the processing result of the analog signal input from the horizontal transmission unit 104 to the AD converter 1052, synchronized with the second clock signal supplied from the second clock generator 106.

[0057] The AD converter 1052 performs an AD conversion, converting the analog signal transmitted from the AMP unit 1051 into a digital signal. In this embodiment, it is assumed that the AD converter 1052 is a successive approximation AD converter, and arrangement examples and operation examples will be described. Figure 7 As shown, the AD converter 1052 includes an AD conversion controller 10521, a sample-and-hold unit 10522, a successive approximation register 10524, a DAC 10525, and a comparator 10523. The AD conversion controller 10521 controls the AD conversion operation in the AD converter 1052. The sample-and-hold unit 10522 holds the voltage of the analog signal transmitted from the AMP unit 1051. The DAC 10525 performs DA conversion based on the output value of the successive approximation register 10524 and a reference voltage. The comparator 10523 compares the output voltage of the DAC 10525 with the voltage of the sample-and-hold unit 10522.

[0058] Figure 8 This is a timing diagram illustrating an example of the operation of the AD converter 1052. Based on the image capture control signal transmitted from the drive controller 102, the AD converter 1052 begins the operation of converting the analog signal into a digital signal. More specifically, upon receiving the image capture control signal, the AD conversion controller 10521 generates control signals for the sample-and-hold unit 10522, the comparator 10523, and the successive approximation register 10524 in synchronization with a third clock signal supplied from the second clock generator 106. Thus, the AD conversion process begins. The operation of AD conversion of the analog signal output from a pixel 201 will be described below.

[0059] Based on the sampling signal from the AD conversion controller 10521, the sample-and-hold unit 10522 receives the voltage during the stable period of the analog signal V_IN input from the AMP unit 1051. As described above, the horizontal transmission unit 104 (and the AMP unit 1051) outputs an analog signal synchronously with the second clock signal supplied from the second clock generator 106. Here, the time from the edge of the clock signal that triggered the output of the analog signal in the horizontal transmission unit 104 to the stabilization of the analog signal V_IN output after the analog signal has been processed by the AMP unit 1051 is indicated by time T_STBL. In this case, the sample-and-hold unit 10522 needs to receive the analog signal V_IN after a period equal to or longer than time T_STBL has elapsed since the rise of the second clock signal. That is, the AD converter 1052 needs to sample the analog signal that has been output from the horizontal transmission unit 104 synchronously with the second clock signal supplied from the second clock generator 106 after a predetermined time has elapsed since the edge of the clock signal that triggered the analog signal. Therefore, the AD conversion controller 10521 makes the sampled signal valid after a time T_STBL or more has elapsed since the rise of the second clock. For example, the aforementioned external control device may be able to set the validity timing of the sampled signal. After the sampling of the analog signal V_IN is completed, the sample-and-hold unit 10522 outputs a voltage V_SMPL to the comparator 10523.

[0060] The successive approximation register 10524 has the function of controlling the voltage output from the DAC 10525 to the comparator 10523 according to the SAR control signal supplied from the AD conversion controller 10521, and the function of outputting the AD conversion result. The successive approximation register 10524 may have a control number equal to or greater than the control number of bits corresponding to the output accuracy of the AD converter 1052. Here, it will be described assuming that the output bit number of the AD converter 1052 is 10 bits and the bit number of the successive approximation register 10524 is also 10 bits.

[0061] At time T_SAR1, as the initial value for the AD conversion of the analog signal output from each pixel 201, the successive approximation register 10524 outputs a value to the DAC 10525 that is 1 in the MSB and 0 in the remaining bits, i.e., the intermediate value of the maximum output value. Based on the output value of the successive approximation register 10524, the DAC 10525 outputs the voltage V_DAC1 of the intermediate value to the comparator 10523. At time T_COMP1, based on the comparator control signal output by the AD conversion controller 10521, the comparator 10523 compares the voltage V_SMPL output by the sample-and-hold unit 10522 with the voltage V_DAC1 output by the DAC 10525. As a result of the comparison, if the voltage V_SMPL is higher than the voltage V_DAC1, then the comparator 10523 outputs 1, and the successive approximation register 10524 determines that the MSB is 1. If the voltage V_SMPL is lower than the voltage V_DAC1, then comparator 10523 outputs 0, and successive approximation register 10524 determines that MSB is 0.

[0062] In the next loop, at time T_SAR2, the successive approximation register 10524 sets the MSB to the value determined above, the bits after the MSB to 1, and the remaining bits to 0, thereby causing DAC 10525 to generate voltage V_DAC2. Comparator 10523 compares the sampled voltage V_SMPL with the voltage V_DAC2.

[0063] By repeating the above operations until the bit precision (LSB) of the AD conversion is reached, the value of each bit is determined, and the AD conversion is completed. The digital signal (digital data) output from the AD converter 1052 can be serial data synchronized with a third clock signal or parallel data synchronized with a second clock signal. Here, it will be described as if the digital signal output from the AD converter 1052 is serial data synchronized with a third clock signal. In this case, the comparison result output by the comparator 10523 is output from the successive approximation register 10524. In addition, the clock signal synchronized with the output digital signal (the third clock signal in this embodiment) is output from the AFE 105 to the DSP 107. Furthermore, the horizontal synchronization signal delay circuit 1053 of the AFE 105 delays the horizontal synchronization signal transmitted from the horizontal transmission unit 104 by the internal delay of the AFE 105 and supplies it to the DSP 107.

[0064] In this embodiment, an example of performing AD conversion in an AD converter 1052 has been described. However, the invention is not limited thereto. To increase the accuracy of AD conversion, for example, AD conversion can be divided into high-order and low-order bits, and an amplifier that increases the gain of the input voltage during the low-order AD conversion can be provided to increase the accuracy of the low-order AD conversion. Various AD conversion methods can be used, such as flash AD conversion, pipelined AD conversion, and ΔΣ AD conversion, in which multiple reference voltages are set and the comparison of the output signals of AMP unit 1051 is performed in parallel using a parallel comparator. To miniaturize the photoelectric conversion device 100, a method for reducing the circuit size of AD converter 1052 can be selected as needed. During the horizontal synchronization period Hblk during which no signal is output from pixel 201, a digital signal corresponding to a predetermined fixed potential can be output as described above. Alternatively, for example, appropriate additional information can be output during this period.

[0065] DSP 107 performs various digital processing operations on the digital signal output from AFE 105's AD converter 1052, such as digital gain processing and shadow correction processing. DSP 107 is supplied with a third clock signal from the second clock generator 106 via AFE 105, which includes AD converter 1052, and performs digital processing on the digital signal synchronously with the third clock signal. DSP 107 outputs the processed digital signal to output unit 108.

[0066] Output unit 108 is an interface for outputting digital signals to the outside of photoelectric conversion device 100. Output unit 108 can use, for example, a differential output such as LVDS. When output unit 108 uses a clock embedding protocol that requires a small number of pins, the circuit size of photoelectric conversion device 100 can be reduced. However, the invention is not limited thereto. For example, protocols such as MIPI or... The communication standard can be used for output unit 108. In this embodiment, the horizontal transmission period has the same cycle in each line. Figure 4 As shown, after outputting the signal during a horizontal synchronization period that includes two time periods, a digital signal of m pixels is output.

[0067] Next, the first clock generator 103, the second clock generator 106, the clock tree that distributes clock signals from the first clock generator 103, and the clock tree that distributes clock signals from the second clock generator 106 will be described.

[0068] The first clock generator 103 generates a first clock signal for controlling the operation of the drive controller 102. The resolution of the horizontal transmission control signal and readout control signal transmitted from the drive controller 102 to the horizontal transmission unit 104 is lower than the resolution of the drive pulses used by the drive controller 102 to drive the pixel array 101. Similarly, the resolution of the image capture control signal transmitted from the drive controller 102 to the second clock generator 106 and AFE 105 is lower than the resolution of the drive pulses used by the drive controller 102 to drive the pixel array 101. Therefore, the frequency of the first clock signal is determined by the resolution of the drive pulses used to drive the pixel array 101, with respect to the operating frequency of the drive controller 102. In this embodiment, it is assumed that the frequency of the first clock signal supplied by the first clock generator 103 to the drive controller 102 to drive each pixel 201 arranged in the pixel array 101 is 5 MHz.

[0069] The second clock generator 106 generates a second clock signal and a third clock signal for controlling the operation of the horizontal transmission unit 104 and the AFE 105. More specifically, as described above, the second clock generator 106 generates the second clock signal and supplies it to the horizontal transmission unit 104 and the AFE 105. The second clock generator 106 also generates the third clock signal and supplies it to the AFE 105. Figure 8 As shown, the AD converter 1052, which operates synchronously with the third clock signal, needs to operate faster than the AMP unit 1051, which operates synchronously with the second clock signal. That is, the frequency of the third clock signal supplied to the AD converter 1052 from the second clock generator 106 is higher than the frequency of the second clock signal supplied from the second clock generator 106 to the horizontal transmission unit 104 and the AMP unit 1051. For example, the frequency of the second clock signal can be 10MHz, and the frequency of the third clock signal can be 120MHz.

[0070] In this manner, the second clock generator 106 supplies clock signals of different frequencies to the horizontal transmission unit 104 and the AD converter 1052 respectively based on the reference clock signal in the second clock generator 106. For example, the second clock generator can supply a 120MHz reference clock signal as a third clock signal to the AD converter 1052, and supply a clock signal obtained by dividing the reference clock signal into 12 signals as a second clock signal to the horizontal transmission unit 104 and the AMP unit 1051. Alternatively, for example, a 10MHz reference clock signal can be supplied as a second clock signal to the horizontal transmission unit 104 and the AMP unit 1051, and a clock signal obtained by multiplying the reference clock signal by 12 can be supplied as a third clock to the AD converter 1052. Alternatively, the reference clock signal in the second clock generator 106 can have a frequency higher than the frequencies of the second and third clock signals, and can be divided into each desired frequency.

[0071] The reference clock signal in each of the first clock generator 103 and the second clock generator 106 can be externally input. Alternatively, for example, each of the first clock generator 103 and the second clock generator 106 may include an oscillator for generating a reference clock signal for supplying the first to third clock signals.

[0072] In this embodiment, as described above, the frequency of the third clock signal is higher than the frequencies of the first and second clock signals. That is, the frequency of the third clock signal supplied to the AD converter 1052 by the second clock generator 106 is higher than the frequency of the clock signal supplied to the drive controller 102 by the first clock generator 103. Additionally, the frequency of the second clock signal is higher than the frequency of the first clock signal. That is, the frequency of the second clock signal supplied to the horizontal transmission unit 104 and the AMP unit 1051 by the second clock generator 106 is higher than the frequency of the clock signal supplied to the drive controller 102 by the first clock generator 103. However, the invention is not limited thereto. For example, the frequency of the first clock signal may be equal to the frequency of the second clock signal or the frequency of the third clock signal.

[0073] As described above, the AD converter 1052 needs to be matched to the timing of sampling performed in the sample-and-hold unit 10522 for the analog signal output from the AMP unit 1051. Therefore, each of the AD converter 1052 and the second clock generator 106 begins operation according to the image capture control signal transmitted from the drive controller 102. Furthermore, the AD converter 1052 and the second clock generator 106 operate such that the phase relationship between the second clock signal, the third clock signal, the sampling signal, the comparator control signal, and the SAR control signal is... Figure 8 The relationship shown is consistent.

[0074] In this way, each of the horizontal transmission unit 104 and AFE 105 (AMP unit 1051 and AD converter 1052) operates without being supplied with a first clock signal directly from the first clock generator 103 or via the drive controller 102. That is, in this embodiment, the clock tree from which the clock signal is distributed from the first clock generator 103 and the clock tree from which the clock signal is distributed from the second clock generator 106 form clock trees that are different from each other.

[0075] Figure 9 The block layout of the photoelectric conversion device 100 and the clock signals to be supplied are shown. In this embodiment, the driving of the pixel array 101 is controlled by a first clock signal supplied from the first clock generator 103, and the driving of the horizontal transmission unit 104 and AFE 105 is controlled by a second clock signal and a third clock signal supplied from the second clock generator 106. Additionally, the operation of the horizontal transmission unit 104 and AFE 105 is initiated by horizontal transmission control signals, readout control signals, and image capture control signals (each of which has low resolution) transmitted from the drive controller 102. Therefore, it is unnecessary to arrange numerous clock buffers for timing control between the clock tree that distributes clock signals from the first clock generator 103 and the clock tree that distributes clock signals from the second clock generator 106. Furthermore, as... Figure 9 As shown, the horizontal transmission unit 104 and AFE 105, which operate on a clock tree supplied with clock signals from the second clock generator 106, can be arranged relatively close to each other. Therefore, the number of clock buffers can be reduced. As a result, the increase in circuit size and power consumption of the photoelectric conversion device 100 due to clock control can be suppressed, and miniaturization of the photoelectric conversion device 100 can be achieved.

[0076] Next, use Figure 10 and Figure 11 This will be described as a case in which two or more adjacent pixels (photoelectric conversion elements 311) in the pixel array 101 share a floating diffusion FD for further miniaturization of the photoelectric conversion device 100. Figure 10 An example of an arrangement of a pixel group 901 in which two or more adjacent pixels (photoelectric conversion elements 311) share a floating diffusion FD is shown, and Figure 11 An example of the arrangement of the horizontal transmission unit 1004 corresponding to the pixel array 101 including pixel group 901 is shown.

[0077] In this embodiment, the pixel array 101 includes pixels (photoelectric conversion elements 311) arranged in an n-row × m-column matrix. In this case, as... Figure 10As shown, a pixel group 901 is formed, in which K photoelectric conversion elements 311 arranged along the vertical signal line 202 and L photoelectric conversion elements 311 arranged in the row direction share a floating diffusion FD. In other words, the output nodes of the K×L photoelectric conversion elements 311 are connected to a vertical signal line 202. Here, as... Figure 10 As shown, the description will be given by assuming K=4, L=2, and a total of eight photoelectric conversion elements 311a to 311h share a floating diffuser FD and are connected to a vertical signal line 202.

[0078] In the above embodiment, pixels 201 arranged in a row of pixel array 101 can output analog signals during a horizontal transmission period. On the other hand, if pixel array 101 has such Figure 10 The two photoelectric conversion elements 311 arranged in the row direction shown share the floating diffusion FD arrangement. Therefore, the signals of the pixels (photoelectric conversion elements 311) arranged in the odd-numbered rows and the signals of the pixels (photoelectric conversion elements 311) arranged in the even-numbered rows need to be output in different horizontal transmission periods.

[0079] Therefore, with including Figure 10 The horizontal transmission unit 1004 corresponding to the pixel array 101 of the pixel group 901 shown is configured to be connected to m / L vertical signal lines 202, as shown. Figure 11 As shown in the diagram. As described above, a horizontal transmission period includes a horizontal synchronization period Hblk and a period for outputting signals from pixels. Therefore, the shift register of the horizontal transmission controller 1042 of the horizontal transmission unit 1004 is configured such that pulses cycle from the first-level register to the last-level register in m / L periods + horizontal synchronization period Hblk (e.g., the two periods as described above). In this case, the number of the multiple registers FF of the shift register can be m / L+2. In this way, it can be said that the number of the multiple registers FF of the shift register of the horizontal transmission controller 1042 is defined by the number of pixels 201 that transmit signals in a horizontal transmission period, the horizontal synchronization period, and the number of photoelectric conversion elements 311 arranged in the row direction among the photoelectric conversion elements 311a to 311h sharing the floating diffusion FD.

[0080] During a horizontal transmission period, the drive controller 102 reads a signal from a photoelectric conversion element 311 in the pixel group 901. The drive controller 102 controls the pixel group 901 and the transmission control signal to the horizontal transmission unit 1004 so that signals are read sequentially from, for example, photoelectric conversion elements 311a, 311b, ..., 311h over eight horizontal transmission periods. When signals are output from photoelectric conversion elements 311a, 311c, 311e, and 311g, the drive controller 102 transmits the signal to the vertical signal line selector 1043 while setting the N-signal readout control signal 1 and the S-signal readout control signal 1 to the connected state, and outputs the signal to the AFE 105 in the next horizontal transmission period. When signals are output from photoelectric conversion elements 311b, 311d, 311f and 311h, the drive controller 102 transmits the signals to the vertical signal line selector 1043 while setting the N signal readout control signal 2 and the S signal readout control signal 2 to the connected state, and outputs the signals to the AFE 105 in the next horizontal transmission period.

[0081] In this way, when two or more pixels (photoelectric conversion elements 311) arranged in the row direction share the floating diffusion FD, the number of stages in the shift register FF is configured such that the pulse cycles through m / L time periods + horizontal synchronization time period Hblk. Thus, a horizontal transmission unit 1004 operating similarly to the horizontal transmission unit 104 described above can be configured. By using... Figure 10 and Figure 11 The arrangement described herein can reduce the circuit size of the pixel array 101 and further miniaturize the photoelectric conversion device 100.

[0082] exist Figure 1 In the arrangement shown, an example has been described where the first clock generator 103 and the second clock generator 106 generate the first to third clock signals separately. However, the generation of clock signals is not limited to... Figure 1 The arrangement shown is illustrated. The photoelectric conversion device 100 may include an oscillator 109, and each of the first clock generator 103 and the second clock generator 106 may generate a clock signal based on the output of the oscillator 109.

[0083] Figure 12A An example of the arrangement of a photoelectric conversion device 100 including an oscillator 109 is shown, and Figure 12B The block layout of the photoelectric conversion device 100 and the clock signal to be supplied are shown. For example... Figure 12AAs shown, each of the first clock generator 103 and the second clock generator 106 receives a clock signal output by the oscillator 109. The first clock generator 103 generates a first clock signal, and the second clock generator 106 generates a second clock signal and a third clock signal. Since the clock tree that distributes the first clock signal is different from the clock tree that distributes the second and third clock signals, the phase of the clock signal supplied from the oscillator 109 does not need to be aligned in the first clock generator 103 and the second clock generator 106. The frequency of the oscillator 109 can be configured to be adjusted, for example, by a voltage supplied from an external power supply (not shown). Alternatively, the frequency of the oscillator 109 can be configured to be adjusted via communication from the aforementioned external control device.

[0084] Here, we will assume that oscillator 109 generates a 120MHz clock signal for the description. In this case, the first clock generator 103 can divide the 120MHz clock signal supplied from oscillator 109 into 12 clock signals and output a 10MHz clock signal as the first clock signal. The second clock generator 106 can divide the 120MHz clock signal into 12 clock signals and output a 10MHz clock signal as the second clock signal. Alternatively, the second clock generator 106 can output the entire 120MHz clock signal supplied from oscillator 109 as a 120MHz third clock signal.

[0085] like Figure 12A and Figure 12B As shown, with the oscillator 109 arranged in the photoelectric conversion device 100, the first clock signal, the second clock signal, and the third clock signal for controlling the various components in the photoelectric conversion device 100 are generated based on the clock signal output from an oscillator 109. Therefore, shifts due to clock skew are unlikely to occur. Similarly, in Figure 12A and Figure 12B In the arrangement shown, it is not necessary to arrange numerous clock buffers for timing control between the clock tree that receives clock signals from the first clock generator 103 and the clock tree that receives clock signals from the second clock generator 106. Furthermore, as... Figure 12A As shown, the horizontal transmission unit 104 and AFE 105, which operate on a clock tree supplied with clock signals from the second clock generator 106, can be arranged relatively close to each other. Therefore, the number of clock buffers can be reduced. As a result, the increase in circuit size and power consumption of the photoelectric conversion device 100 due to clock control can be suppressed, and miniaturization of the photoelectric conversion device 100 can be achieved.

[0086] Next, as an application example of the photoelectric conversion device 100 described above, a camera module including the photoelectric conversion device 100, an endoscope using the camera module including the photoelectric conversion device 100, and an endoscope system will be described. Figure 13 This is a block diagram illustrating an example configuration of an endoscope system 1300, which includes an endoscope 1320 that uses a camera module 1310 including the aforementioned photoelectric conversion device 100. The endoscope system 1300 includes the endoscope 1320, which includes the camera module 1310 and a cable 1321. The camera module 1310 includes the photoelectric conversion device 100, and the cable 1321 is used to transmit signals output from the camera module 1310. The endoscope system 1300 also includes a control device 1330 connected to the cable 1321 and including a signal processor 1331 for processing the signals output from the camera module 1310. The endoscope system 1300 also includes a display device 1340 for displaying an image corresponding to the signals output from the camera module 1310, and a light source device 1350 for supplying light during image capture performed by the camera module 1310.

[0087] In the endoscope system 1300, at least a portion of the endoscope 1320, including a camera module 1310 and a cable 1321, is inserted into a body cavity and used to observe a target. The camera module 1310 is disposed in the endpiece 1324 of the endoscope 1320 for insertion into the body cavity. The camera module 1310 includes the aforementioned photoelectric conversion device 100 and an optical system 1311 that allows light to enter the photoelectric conversion device 100. The optical system 1311 is formed by including one or more lenses.

[0088] An illumination optical system 1352 for illuminating an observation target with light emitted from a light source device 1350 is disposed in the end portion 1324 of an endoscope 1320, where a camera module 1310 is located. The illumination optical system 1352 is formed by including one or more lenses. Light emitted from the light source device 1350 is supplied to the illumination optical system 1352 via an optical path 1351, such as a flexible optical fiber, and illuminates the observation target.

[0089] The cable 1321 of the endoscope 1320 can be flexible. By operating the manipulator 1322 of the endoscope 1320, the cable 1321 can be deformed in any direction and angle. Therefore, the camera module 1310 can be pointed in a desired direction corresponding to the observation target. A signal transmission line 1323 is arranged in the cable 1321 and transmits the signal output from the camera module 1310 to the signal processor 1331 of the control device 1330. The aforementioned optical path 1351 can also pass through the cable 1321.

[0090] Furthermore, forceps and wires for collecting biological tissue from the target area, insertion holes for inserting injection needles, etc., can be arranged in the endoscope 1320's endpiece 1324 and cable 1321, as well as storage holes for storing electric scalpels, etc., used for similarly collecting biological tissue. Fluid channels for supplying air or water to the target area or for aspirating fluid from the target area can also be arranged in the endoscope 1320's endpiece 1324 and cable 1321.

[0091] Control device 1330 includes a controller 1335 for controlling various components of endoscope system 1300. Controller 1335 may be circuitry including a processor (e.g., CPU, MPU, ASIC, etc.) that executes software (programs) to perform processing. The program is stored, for example, in memory 1332 of control device 1330. When a user operates user interface 1333 of control device 1330, the program can be read and executed by controller 1335. The program may be supplied to controller 1335 via a network or various storage media such as external memory. User interface 1333 may be, for example, a personal computer attached to endoscope system 1300, or it may be a touch panel. Alternatively, display device 1340 may be used as part of user interface 1333.

[0092] According to user operation, controller 1335 transmits image capture condition setting data, such as exposure conditions, from photoelectric conversion device 100 to photoelectric conversion device 100 via signal transmission line 1323. Controller 1335 can also function as signal processor 1331, which processes the image signal obtained by photoelectric conversion device 100, thereby converting it into data that can, for example, be displayed as an image on display device 1340. Figure 13 In the configuration shown, the signal output from the camera module 1310 is processed in a portion of the controller 1335, but the controller 1335 and the signal processor 1331 can be arranged independently. The image display data processed by the signal processor 1331 can be stored in the memory 1332 of the control device 1330.

[0093] Display device 1340 may be, for example, a liquid crystal display (LCD). Control device 1330 and display device 1340 can be connected via wires or wirelessly. Display device 1340 can be used to display an image of the observed target based on signals obtained from photoelectric conversion device 100. When observing a subject using endoscope system 1300, display device 1340 can also display setting information for each component included in endoscope system 1300, such as image capture conditions of photoelectric conversion device 100.

[0094] The light source device 1350 can be, for example, a light source that emits white light. Alternatively, the light source device 1350 can be a light source that emits red or blue light other than white light. The light emitted by the light source device 1350 is not limited to visible light, as long as the photoelectric conversion element 311 of the photoelectric conversion device 100 is sensitive to the color of light. The light source device 1350 is configured to emit light of an appropriate wavelength according to the observed target. The light source device 1350 emits light of a set color under the control of the controller 1335 of the control device 1330. At the same time, the photoelectric conversion device 100 performs image capture under the control of the controller 1335 of the control device 1330. Thus, an image of the observed target can be acquired.

[0095] When the circuit size of the photoelectric conversion device 100 is suppressed as described above and the photoelectric conversion device 100 is miniaturized, the camera module 1310 can be miniaturized. Therefore, the end portion 1324 of the endoscope 1320 to be inserted into the body cavity is miniaturized, reducing the burden on the patient. When the size of the end portion 1324 of the endoscope 1320 does not need to be changed, miniaturization of the camera module 1310 creates leeway in the space that can be used for the aforementioned insertion port, storage port, fluid channel, etc., enabling the endoscope 1320 to achieve versatility.

[0096] Application examples of photoelectric conversion device 100 are not limited to Figure 13 The camera module 1310, endoscope 1320, and endoscope system 1300 are shown. Figure 14 This is a schematic diagram illustrating an apparatus 1400 including a photoelectric conversion device 100 according to this embodiment. The photoelectric conversion device 100 can be housed in a package 1420 and mounted on the apparatus 1400. The package 1420 may include a base to which the photoelectric conversion device 100 is fixed, and a cover made of glass or the like facing the pixel array 101 of the photoelectric conversion device 100. The package 1420 may also include engagement members such as bonding wires and protrusions for connecting the terminals of the base to the output terminals of the output unit 108 of the photoelectric conversion device 100.

[0097] Device 1400 may include at least any one of optical device 1440, control device 1450, processing device 1460, display device 1470, storage device 1480, and mechanical device 1490. Optical device 1440 is implemented using, for example, lenses, shutters, and mirrors. Control device 1450 controls photoelectric conversion device 100. Control device 1450 is, for example, a semiconductor device such as an ASIC.

[0098] Processing device 1460 is a signal processor used to process signals output from photoelectric conversion device 100. Processing device 1460 is a semiconductor device such as a CPU or ASIC used to form an analog front-end (AFE) or digital front-end (DFE). Display device 1470 is an EL display device or liquid crystal display device that displays information (images) obtained by photoelectric conversion device 100. Storage device 1480 is a magnetic or semiconductor device that stores information (images) obtained by photoelectric conversion device 100. Storage device 1480 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or hard disk drive.

[0099] Mechanical device 1490 includes a moving or propulsive unit such as a motor or engine. Device 1400 displays signals output from photoelectric conversion device 100 on display device 1470 and performs external transmissions via a communication device (not shown) of device 1400. For this purpose, in addition to the memory circuitry and arithmetic circuitry of photoelectric conversion device 100, device 1400 may also include a storage device 1480 and a processing device 1460. Mechanical device 1490 can be controlled based on signals output from photoelectric conversion device 100.

[0100] Device 1400 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones or wearable devices) or cameras (e.g., interchangeable-lens cameras, compact cameras, camcorders, or surveillance cameras). Mechanical devices 1490 in the camera can drive components of the optical device 1440 to perform zoom, focus, and shutter operations. Alternatively, mechanical devices 1490 in the camera can move the photoelectric conversion device 100 to perform anti-vibration operations.

[0101] Device 1400 can also be a transport device such as a vehicle, ship, or aircraft. The mechanical device 1490 within the transport device can function as a mobile device. Device 1400 as a transport device is suitable for transporting the photoelectric conversion device 100, or for assisting and / or automating driving (manipulation) via imaging functions. Processing equipment 1460 for assisting and / or automating driving (manipulation) can perform processing for operating the mechanical device 1490 as a mobile device based on information obtained from the photoelectric conversion device 100. Alternatively, device 1400 can be a medical device (such as an endoscope as described above), a measuring device (such as a distance measuring sensor), an analytical device (such as an electron microscope), an office device (such as a photocopier), or an industrial device (such as a robot).

[0102] According to the above embodiments, a photoelectric conversion device 100 with reduced circuit size and suppressed power consumption is realized. Therefore, the value of the apparatus 1400 including the photoelectric conversion device 100 can be increased. This aforementioned "increased value" corresponds to at least one of the following: added functionality, improved performance, improved characteristics, improved reliability, increased production output, reduced environmental impact, reduced cost, reduced size, and reduced weight.

[0103] Therefore, using the photoelectric conversion device 100 according to this embodiment in the device 1400 will increase the value of the device. For example, by incorporating the photoelectric conversion device 100 into the transport device, the transport device will be able to have excellent performance when performing external imaging of the transport device or when measuring the external environment. Therefore, in the production and sale of transport devices, it is determined that incorporating the semiconductor device according to this embodiment into the transport device will be advantageous in increasing the performance of the transport device itself. In particular, the photoelectric conversion device 100 is suitable for transport devices that use information obtained by the photoelectric conversion device 100 to perform driving support and / or automatic driving of the transport device.

[0104] The disclosure in this specification also includes the complement of the concepts described herein. That is, for example, if the description "A is B" (A = B) exists in this specification, then even if the description "A is not B" (A ≠ B) is omitted, this specification will still disclose or imply "A is not B". This is because if the description "A is B" is provided, then the case of "A is not B" is taken into consideration.

[0105] This invention is not limited to the embodiments described above, and various changes and modifications can be made within the spirit and scope of this invention. Therefore, the appended claims are presented to inform the public of the scope of this invention.

[0106] This application claims priority to Japanese Patent Application No. 2021-103548, filed on June 22, 2021, which is hereby incorporated herein by reference.

Claims

1. A photoelectric conversion device, comprising: A pixel array in which multiple pixels are arranged to form multiple rows and multiple columns; A drive controller configured to drive the pixel array; A horizontal transmission unit configured to sequentially output analog signals from multiple columns of the pixel array; An AD converter, configured to convert an analog signal output from the horizontal transmission unit into a digital signal; A first clock generator is configured to generate a clock signal for controlling the operation of the drive controller. as well as A second clock generator, configured to generate clock signals for controlling the horizontal transmission unit and the AD converter, is characterized in that... The clock tree that distributes clock signals from the first clock generator and the clock tree that distributes clock signals from the second clock generator form clock trees that are different from each other.

2. The photoelectric conversion device according to claim 1, characterized in that, The drive controller causes the pixel array to output an analog signal and transmits a horizontal transmission control signal to the horizontal transmission unit, indicating the time period for outputting the analog signal from the pixel array. The horizontal transmission unit starts outputting the analog signal from the pixel array to the AD converter in accordance with the horizontal transmission control signal and in synchronization with the clock signal supplied from the second clock generator.

3. The photoelectric conversion device according to claim 1, characterized in that, The drive controller transmits an image capture control signal to the second clock generator, indicating the image capture period for performing image capture in the pixel array, and Based on the image capture control signal, the second clock generator begins to generate a clock signal for controlling the AD converter.

4. The photoelectric conversion device according to claim 3, characterized in that, Based on the image capture control signal, the AD converter begins the operation of converting the analog signal into a digital signal.

5. The photoelectric conversion device according to claim 1, characterized in that, The AD converter samples the analog signal output from the horizontal transmission unit, which is synchronized with the clock signal supplied from the second clock generator, after a predetermined time has elapsed from the edge of the clock signal output from the triggered analog signal.

6. The photoelectric conversion device according to claim 1, characterized in that, The horizontal transfer unit includes a shift register in which multiple registers are connected serially, and the output of the last-stage register among the multiple registers is connected to the input of the first-stage register among the multiple registers. In the shift register, the pulse cycles from the first-level register to the last-level register during a horizontal transmission period for transmitting a signal corresponding to a row of the pixel array.

7. The photoelectric conversion device according to claim 6, characterized in that, The number of the plurality of registers is defined by the number of pixels among the plurality of pixels that transmit signals during the horizontal transmission period and the horizontal synchronization period.

8. The photoelectric conversion device according to claim 1, characterized in that, Each of the plurality of pixels includes a photoelectric conversion element, and No fewer than two photoelectric conversion elements share a floating diffusion.

9. The photoelectric conversion device according to claim 6, characterized in that, Each of the plurality of pixels includes a photoelectric conversion element. At least two photoelectric conversion elements share a floating diffusion, and The number of the plurality of registers is defined by the number of pixels that transmit signals during the horizontal transmission period, the horizontal synchronization period, and the number of photoelectric conversion elements arranged in the row direction among the not less than two photoelectric conversion elements sharing floating diffusion.

10. The photoelectric conversion device according to claim 1, characterized in that, It also includes oscillators, Each of the first clock generator and the second clock generator generates a clock signal based on the output of the oscillator.

11. The photoelectric conversion device according to claim 1, characterized in that, Each of the first clock generator and the second clock generator includes an oscillator configured to generate a clock signal.

12. The photoelectric conversion device according to claim 1, characterized in that, The second clock generator supplies clock signals of different frequencies to the horizontal transmission unit and the AD converter respectively based on the reference clock signal in the second clock generator.

13. The photoelectric conversion device according to claim 12, characterized in that, The frequency of the clock signal supplied from the second clock generator to the AD converter is higher than the frequency of the clock signal supplied from the second clock generator to the horizontal transmission unit.

14. The photoelectric conversion device according to claim 12, characterized in that, The second clock generator supplies the reference clock signal to the AD converter and supplies the clock signal obtained by dividing the reference clock signal to the horizontal transmission unit.

15. The photoelectric conversion device according to claim 1, characterized in that, The frequency of the clock signal supplied to the AD converter by the second clock generator is higher than the frequency of the clock signal supplied to the drive controller by the first clock generator.

16. The photoelectric conversion device according to claim 1, characterized in that, The frequency of the clock signal supplied to the horizontal transmission unit by the second clock generator is higher than the frequency of the clock signal supplied to the drive controller by the first clock generator.

17. The photoelectric conversion device according to claim 1, characterized in that, The AD converter is a successive approximation AD converter.

18. The photoelectric conversion device according to claim 1, characterized in that, It also includes a digital signal processor configured to perform digital signal processing on the digital signal output from the AD converter. The digital signal processor is supplied with a clock signal from the second clock generator via the AD converter.

19. A camera module, comprising: The photoelectric conversion device according to any one of claims 1 to 18; as well as An optical system configured to allow light to enter the photoelectric conversion device.

20. An endoscope comprising: The camera module according to claim 19; as well as A cable configured to transmit signals output from the camera module.

21. An endoscope system, comprising: The endoscope according to claim 20; as well as A signal processor, connected to a cable, is configured to process signals output from a camera module.

22. An electronic device, characterized in that, include: The photoelectric conversion device according to any one of claims 1 to 18; as well as A signal processor configured to process signals output from the photoelectric conversion device.

Images