A multi-core chip and a debugging method of a multi-core chip

Abstract

The application discloses a multi-core chip, a debugging method, computer equipment and a storage medium, wherein the multi-core chip of one embodiment comprises at least one partition, the partition comprises a control unit and a plurality of kernel units, wherein the kernel unit comprises a collection circuit, the collection circuit is used for determining the voltage drop generated by starting the kernel unit; the control unit is connected with the collection circuit of each kernel unit, and is used for determining the starting interval period of the plurality of kernel units according to the voltage drop determined by the collection circuit, and the plurality of kernel units are started according to the starting interval period. The embodiment provided by the application can reduce the IR voltage drop, improve the stability of the chip and reduce the power consumption of the chip by adjusting the starting interval period of each kernel unit and starting each kernel unit according to the starting interval period while keeping the chip power supply voltage unchanged.

Description

Technical Field

[0001] This invention relates to the field of computer control technology, and in particular to a multi-core chip and a debugging method for the multi-core chip. Background Technology

[0002] In related technologies, high-load operation of multi-core chips can easily cause IR drop, resulting in a momentary voltage decrease that affects chip performance and functionality. To solve this problem, it is usually necessary to dynamically adjust the supply voltage according to the load conditions to compensate for IR drop. However, dynamically adjusting the supply voltage leads to an increase in chip power consumption. Summary of the Invention

[0003] To address at least one of the aforementioned problems, a first embodiment of the present invention provides a multi-core chip.

[0004] It includes at least one partition, said partition comprising a control unit and multiple kernel units, wherein,

[0005] The kernel unit includes a data acquisition circuit, which is used to determine the voltage drop generated during the startup of the kernel unit.

[0006] The control unit, connected to the acquisition circuit of each core unit, is used to determine the startup interval period of the plurality of core units based on the voltage drop determined by the acquisition circuit. The plurality of core units then start up according to the startup interval period. This embodiment determines the voltage drop generated during startup of each core unit through the acquisition circuit located in each core unit, and determines the startup interval period of each core unit based on the voltage drop through the control unit, then starts up according to the startup interval period. This reduces the IR voltage drop while maintaining a constant chip supply voltage. In other words, this embodiment staggers the startup times of core units within the same partition by setting the startup interval period for each core unit, thereby avoiding the IR voltage drop problem caused by large loads and large currents due to simultaneous startup of core units in related technologies, effectively reducing the chip's IR voltage drop and improving chip stability.

[0007] Furthermore, the acquisition circuit is also used to acquire the oscillation frequency of the core unit;

[0008] The control unit is further configured to determine a target voltage value based on a voltage-frequency lookup table and the oscillation frequency of the plurality of core units, and to determine the startup interval period based on the target voltage value, wherein the voltage-frequency lookup table is stored in the control unit.

[0009] In this embodiment, the target voltage value of each core unit is characterized as an oscillation frequency by the acquisition circuit set in each core unit, and then the oscillation frequency is converted into the target voltage value by the voltage-frequency lookup table stored in the control unit, thereby determining the start-up interval period based on the target voltage value.

[0010] Furthermore, the control unit is also configured to form a startup cycle table based on the startup interval period, and configure the registers of the kernel unit according to the startup cycle table.

[0011] This embodiment improves the flexibility of multi-core chip startup interval adjustment by forming a startup interval table and setting it in the registers of each core unit, which facilitates the adjustment and modification of the startup interval of each core unit.

[0012] Furthermore, the control unit is also used to obtain the oscillation frequency of the multiple kernel units in the idle state during the startup process of the multiple kernel units in each partition according to the preset multiple voltage detection values, and generate and store the voltage-frequency lookup table.

[0013] In this embodiment, during the startup process of multiple core units in an idle state, the acquisition circuit is used to obtain the oscillation frequency of the core units under multiple voltage detection values, so as to form a voltage-frequency comparison table as the basis for adjusting the startup interval period of each core unit, which can accurately measure the target voltage value of each core unit.

[0014] Furthermore, the acquisition circuit includes NAND gates, an even number of NOT gates, a buffered NOT gate, and a sampling unit, wherein...

[0015] The NAND gate includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the NAND gate is connected to an enable signal. The second input terminal and the output terminal of the NAND gate are connected end-to-end with the even number of NOT gates to form a ring oscillator.

[0016] The buffered NOT gate includes an input terminal and an output terminal, and the input terminal of the buffered NOT gate is connected to the oscillation signal output by the ring oscillator;

[0017] The sampling unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sampling unit is connected to the output terminal of the buffer NOT gate, the second input terminal of the sampling unit is connected to a preset clock signal, and the output terminal of the sampling unit is connected to the control unit.

[0018] Furthermore, the sampling unit includes a counter.

[0019] The sampling unit forms a sampling period based on the incoming clock signal, collects the number of oscillation signals through the counter during the sampling period, and determines the oscillation frequency based on the sampling period and the number of oscillation signals.

[0020] In this embodiment, the acquisition circuit connects the operating voltage of the corresponding core unit through a NAND gate, and uses the inherent propagation delay time of the gate circuit to connect the NAND gate and an even number of NOT gates end to end to form a ring oscillator. When the operating voltage of the core unit is connected, the circuit outputs an oscillation signal. The oscillation signal is then acquired using a buffered NOT gate and a sampling unit, and the number of oscillation signals in the acquisition period is converted into an oscillation frequency by a counter and output to the control unit. In other words, the operating voltage of each core unit is represented as the oscillation frequency, so that the control unit can easily and effectively obtain the operating voltage of each core unit according to the oscillation frequency and the voltage-frequency lookup table.

[0021] Furthermore, the frequency of the oscillation signal output by the ring oscillator is at least twice the frequency of the preset clock signal.

[0022] This embodiment ensures that the oscillation signal can be effectively acquired by the counter during the sampling period to characterize the operating voltage of each core unit by limiting the multiple relationship between the frequency of the oscillation signal and the frequency of the clock signal.

[0023] A second embodiment of the present invention provides a debugging method for a multi-core chip, comprising:

[0024] In response to the voltage drop generated by the startup of multiple kernel units, the oscillation frequency of the multiple kernel units is collected;

[0025] The target voltage value is determined based on the voltage-frequency lookup table and the oscillation frequencies of the multiple core units;

[0026] The startup interval period of the plurality of kernel units is determined based on the target voltage value.

[0027] This embodiment collects the oscillation frequency corresponding to the voltage drop of multiple core units when they start up in the working state, obtains the target voltage value through a voltage-frequency lookup table, and thus determines the start-up interval period of each core unit. By setting the start-up interval period of each core unit, the start-up time of each core unit in the same partition is staggered, thereby avoiding the IR voltage drop problem caused by large load and large current due to the simultaneous start-up of each core unit in related technologies, effectively reducing the IR voltage drop of the chip and improving the stability of the chip.

[0028] Furthermore, determining the startup interval period of the plurality of kernel units based on the target voltage value further includes;

[0029] In response to the target voltage value being less than a preset voltage threshold and the current startup interval being less than a preset period threshold, the startup interval of the plurality of kernel units is determined based on the adjustment step size and the current startup interval.

[0030] In this embodiment, the startup interval period is determined to be adjustable based on a preset voltage threshold and a cycle threshold, and if it is adjustable, the startup interval period of each kernel unit is adjusted according to the adjustment step size.

[0031] Furthermore, before acquiring the oscillation frequency of the multiple kernel units in response to the voltage drop generated by the startup of the multiple kernel units, the debugging method further includes;

[0032] During the startup process of the multiple kernel units in an idle state, the frequencies of the multiple kernels are obtained according to multiple preset voltage detection values, and the voltage-frequency lookup table is generated and stored.

[0033] In this implementation, the acquisition circuit is used to obtain the oscillation frequency of the core units under multiple voltage detection values ​​when multiple core units are in an unloaded state, so as to form a voltage-frequency comparison table as the basis for adjusting the start-up interval of each core unit, which can accurately measure the target voltage value of each core unit.

[0034] Furthermore, the multi-core chip includes at least one partition, each partition including multiple kernel units, and the debugging method further includes: sequentially adjusting the startup interval period of the multiple kernel units in each partition.

[0035] This embodiment avoids the noise caused by adjusting multiple partitions simultaneously by adjusting the startup interval period of each kernel unit in each partition separately, and effectively improves the accuracy of adjusting the startup interval period of each kernel unit.

[0036] Furthermore, the multi-core chip includes a power supply unit, and the step of sequentially adjusting the startup interval period of the multiple core units in each partition further includes: adjusting the startup interval period of the multiple core units in each partition sequentially from the nearest to the farthest according to the distance between each partition and the power supply unit.

[0037] This embodiment takes into account the phenomenon that the IR voltage drop of multiple core units in the partition far from the power unit is higher than that of multiple core units in the partition close to the power unit. The startup interval period of each core unit in each partition is adjusted in order of distance from the power unit, thereby effectively improving the adjustability of the startup interval period of each core unit.

[0038] Furthermore, before acquiring the oscillation frequency of the multiple kernel units in response to the voltage drop generated during the startup of the multiple kernel units, the debugging method further includes:

[0039] Set the boot interval for multiple kernel units in each partition according to the preset boot cycle interval value.

[0040] This embodiment further optimizes the startup interval of each kernel unit by pre-setting the initial value of the startup interval period of each kernel unit, effectively improving the adjustability and accuracy of the startup interval period adjustment of each kernel unit.

[0041] A third embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the second embodiment.

[0042] A fourth embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the method described in the second embodiment. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This diagram illustrates a structural block diagram of a multi-core chip according to an embodiment of the present invention.

[0045] Figure 2 This diagram illustrates the structure of the acquisition circuit according to an embodiment of the present invention.

[0046] Figure 3 This diagram illustrates the voltage change curve during the chip startup process according to an embodiment of the present invention.

[0047] Figure 4 A flowchart illustrating a debugging method for a multi-core chip according to another embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the structure of a computer device according to another embodiment of the present invention is shown. Detailed Implementation

[0049] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0050] To address the issue of increased power consumption caused by IR-Drop in related technologies that dynamically adjust the supply voltage according to the load, the inventors, after extensive research and experimentation, proposed a multi-core chip. By staggering the startup times of the core units within the same partition of the multi-core chip, the IR voltage drop problem caused by the large load and high current resulting from the simultaneous startup of each core unit is avoided, effectively reducing the IR voltage drop of the chip and improving its stability.

[0051] like Figure 1 As shown, one embodiment of the present invention provides a multi-core chip, including at least one partition, such as partition 1 to partition m. Each partition includes a control unit and multiple core units; for example, partition 1 includes control unit 1 and core units 1 to n. The number of core units included in each partition may be the same or different. Each core unit in each partition is supplied with a voltage within the same voltage range, for example, from 0.5V to 0.7V, meaning the supply voltage of each core unit is essentially the same with very little fluctuation.

[0052] With the power supply voltage of each kernel unit in each partition being basically the same, the startup interval of each kernel unit in each partition is controlled by a control unit.

[0053] Specifically, a startup interval period is set between the multiple core units in each partition. The startup interval period represents the staggered startup time of the multiple core units. For example, a chip has 4 partitions, each partition includes 8 core units. When the 32 core units of the chip start up simultaneously, the large current caused by the instantaneous large load can easily lead to a large IR voltage drop. By setting the startup interval period of each core unit, the large current caused by the instantaneous large load can be reduced, thereby reducing the IR voltage drop.

[0054] In an optional embodiment, the startup interval ranges from 0 to 256, meaning that the startup of each kernel unit can be staggered by 0 to 256 cycles. This means that the kernel units can start simultaneously (i.e., staggered by 0 cycles), staggered by 128 cycles, staggered by 256 cycles, and so on. For example, if the startup interval of 8 kernel units in a partition is 25, then after the first kernel unit starts, it waits for the 25th time segment (cycle) before the second kernel unit starts, and so on. The third kernel unit either waits for 25 time segments after the second kernel unit starts or waits for the 50th time segment after the first kernel unit starts before starting. That is, the startup nodes of the 8 kernel units in this partition are node 0, node 25, node 50, node 75, node 100, node 125, node 150, and node 175, respectively. This avoids multiple kernel units starting simultaneously and prevents large IR voltage drops caused by high current due to instantaneous large loads.

[0055] It is worth noting that this application does not specifically limit the definition and segmentation of chip startup time. The initial value of the startup time node of each kernel unit in a partition can be the same or different. This application does not specifically limit this either. Those skilled in the art should set it according to the actual application requirements.

[0056] Each core unit in each partition includes a data acquisition circuit to determine the voltage drop generated during the startup of the core unit and transmit it to the control unit. This allows the control unit to determine the startup interval period for each core unit in the partition and control each core unit to start up according to the startup interval period. In this embodiment, by setting startup interval periods among multiple core units, the startup times of core units within the same partition are staggered. That is, each core unit within the same partition is sequentially set to different startup time nodes according to the startup interval period. This avoids the IR voltage drop problem caused by large loads and high currents due to the simultaneous startup of multiple core units, effectively reducing the IR voltage drop of the chip and improving its stability.

[0057] In an optional embodiment, the acquisition circuit is further configured to acquire the oscillation frequency of the kernel unit; the control unit is further configured to determine a target voltage value based on the voltage-frequency lookup table and the oscillation frequencies of the plurality of kernel units, and to determine the startup interval period based on the target voltage value, wherein the voltage-frequency lookup table is stored in the control unit. Here, the oscillation frequency refers to the frequency of the supply voltage at which the kernel unit operates, given the voltage drop generated during kernel unit startup. The voltage-frequency lookup table characterizes the correspondence between voltage and frequency. The target voltage value refers to the voltage value corresponding to the frequency of the kernel unit, given the voltage drop generated during kernel unit startup.

[0058] In this embodiment, the acquisition circuit generates an oscillation frequency based on the operating voltage of the corresponding kernel unit. Specifically, the acquisition circuit outputs the oscillation frequency based on the input operating voltage. That is, the acquisition circuit transmits the oscillation frequency of each kernel unit to the control unit, so that the control unit determines the target voltage value based on the stored voltage-frequency lookup table, thereby determining the start-up interval period of each kernel unit in the corresponding partition.

[0059] In an optional embodiment, the acquisition circuit of each core unit acquires an oscillation frequency set, meaning the acquisition circuit acquires multiple frequencies and transmits these frequencies to the control unit. Further, after receiving these multiple frequencies, the control unit determines the voltage value corresponding to each frequency and selects a target voltage value from the determined voltage values. Optionally, the target voltage value is the minimum voltage among the multiple voltage values. This application does not specifically limit the number of frequencies acquired; those skilled in the art should select an appropriate number based on actual application requirements, which will not be elaborated further here.

[0060] In an optional embodiment, the control unit is further configured to form a boot cycle table based on the boot interval period and configure the registers of the kernel unit according to the boot cycle table.

[0061] In an optional embodiment, during the configuration of the kernel unit's registers according to the boot cycle table, the boot cycle table can be directly configured into the register of each kernel unit. In this embodiment, during the boot process, multiple kernel units determine the boot node according to the boot cycle table stored in the registers of each kernel unit, and then each kernel unit boots according to its boot node. In other words, this embodiment, by forming a boot cycle table of boot intervals and setting it in the registers of each kernel unit, facilitates the adjustment and modification of the boot interval of each kernel unit, thereby improving the flexibility of adjusting the boot interval of multi-core chips.

[0062] In an optional embodiment, during the process of configuring the registers of the kernel units according to the boot cycle table, the boot node of each kernel unit is configured into the registers of that kernel unit according to the boot cycle table. In this embodiment, multiple kernel units are started during the boot process according to the boot nodes stored in the registers of each kernel unit.

[0063] In an optional embodiment, the control unit is further configured to, during the startup process of the multiple kernel units in the idle state of each partition, obtain the oscillation frequency of the multiple kernel units according to a plurality of preset voltage detection values, and generate and store the voltage-frequency lookup table. Here, the idle state refers to the state in which the kernel units are not performing computational work.

[0064] In this embodiment, the startup of multiple core units in each partition under no-load conditions serves as the basis for adjusting the startup interval period of each core unit. Multiple voltage detection values ​​are applied to the acquisition circuit to obtain the corresponding oscillation frequencies, and a voltage-frequency lookup table is formed based on the actual applied voltage detection values ​​and the obtained oscillation frequencies. In other words, during the startup process of multiple core units under no-load conditions, this embodiment utilizes the acquisition circuit to obtain the oscillation frequencies of the core units under multiple voltage detection values, thereby forming a voltage-frequency lookup table that serves as the basis for adjusting the startup interval period of each core unit, accurately measuring the target voltage value of each core unit.

[0065] In an optional embodiment, such as Figure 2 As shown, each kernel unit includes a data acquisition circuit, which includes a NAND gate A1, an even number of NOT gates N1-N4, a buffered NOT gate N5, and a sampling unit.

[0066] In this embodiment, the NAND gate A1 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the NAND gate is connected to an enable signal En, which is the operating voltage of the kernel unit to which it belongs. For example, the kernel unit includes a computing circuit, and the operating voltage signal of the computing circuit is used as the enable signal En and connected to the first input terminal of the NAND gate. The second input terminal and the output terminal of the NAND gate A1 are connected end to end with the even number of NOT gates N1-N4 to form a ring oscillator. That is, the NAND gate A1 forms a NOT gate based on the enable signal En. The odd number of NOT gates are connected end to end using the inherent propagation delay time of the gate circuit to form a ring oscillator. That is, the ring oscillator generates a corresponding oscillation signal clk-dll according to the input operating voltage signal and outputs it to the buffered NOT gate. The buffered NOT gate N5 includes an input terminal and an output terminal. The input terminal of the buffered NOT gate is connected to the oscillation signal clk-dll output by the ring oscillator and transmitted to the sampling unit. The sampling unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sampling unit is connected to the output terminal of the buffered NOT gate, and the second input terminal of the sampling unit is connected to a preset clock signal clk. The sampling unit generates an oscillation frequency Fn based on the oscillation signal clk-dll and the clock signal clk and outputs it to the control unit. The preset clock signal clk connected to the second input terminal of the sampling unit is a signal of fixed frequency.

[0067] When the core unit operates under high load and generates an IR voltage drop, the enable signal En is set high. At this time, the ring oscillator generates a high-frequency oscillation signal clk_dll. Based on the fixed-frequency clock signal clk of the sampling unit, the oscillation signal clk_dll is continuously acquired at uniform intervals, and the frequency value of the oscillation signal clk_dll (i.e., the oscillation frequency Fn) is calculated. Since the IR voltage drop affects the operating voltage, the acquisition circuit characterizes the operating voltage of the core unit by the oscillation frequency.

[0068] In an optional embodiment, the sampling unit includes a counter, which forms a sampling period based on the incoming clock signal, samples the number of oscillation signals by the counter during the sampling period, and determines the oscillation frequency based on the sampling period and the number of oscillation signals.

[0069] For example, if the frequency of the input clock signal clk is 1GHz, then the clock signal's time period is 1ns. Every 20 clock cycles constitute a sampling period, resulting in a 20ns sampling period. When the core unit operates under high load, generating an IR voltage drop, the enable signal En is set high. At this time, the oscillator ring generates a high-frequency oscillation signal clk_dll of approximately 4GHz. Therefore, within a 20ns sampling period, approximately 80 oscillation signals clk_dll can be received. The number of received oscillation signals clk_dll is recorded by a counter, thus yielding the frequency value of the oscillation signal clk_dll (i.e., the oscillation frequency Fn). For example, if the ideal operating voltage of the core unit is 0.5V, and the operating voltage drops to 0.45V due to the IR voltage drop, the number of oscillation signals collected by the sampling unit's counter in the acquisition circuit decreases, and the oscillation frequency decreases. Figure 2 The acquisition circuit consists of A1 and N1 to N4. These gate circuits are affected by the supply voltage of the core unit: the higher the supply voltage, the shorter the delay of the signal passing through each gate circuit. That is, if the supply voltage decreases, the delay of the signal passing through each gate circuit will increase, resulting in a larger oscillation period, or a smaller oscillation frequency. Therefore, the oscillation frequency represents the operating voltage of the core unit, and further represents the IR voltage drop of the core unit.

[0070] In an optional embodiment, the frequency of the oscillation signal output by the ring oscillator is at least an order of magnitude greater than the frequency of the preset clock signal.

[0071] In this embodiment, by limiting the multiple relationship between the frequency of the oscillation signal and the frequency of the clock signal, for example, by having a multiple relationship of more than ten times that the two differ by an order of magnitude, it is ensured that the oscillation signal can be effectively acquired by the counter during the sampling period to characterize the operating voltage of each core unit.

[0072] The following is a specific example to illustrate the debugging process of this embodiment:

[0073] First, the control unit acquires the voltage-frequency lookup table under no-load conditions on the chip. This process is a pre-setting process to calibrate the correspondence between voltage and frequency. The reason for no-load conditions during the pre-setting process is to ensure that the pre-set voltage is stable and that no voltage drop occurs. Therefore, the voltage value during the pre-setting process can be considered a stable value, and the oscillation frequency value corresponding to this stable voltage value is obtained through the sampling circuit.

[0074] This embodiment obtains a voltage-frequency lookup table when each core unit of the chip is in an unloaded state. Multiple preset voltage detection values ​​are sequentially loaded into a data acquisition circuit. The chip is started in the unloaded state of each core unit, and the acquisition circuit outputs the oscillation frequency corresponding to each voltage detection value. With an ideal supply voltage of 0.5V for the core unit, frequency values ​​corresponding to 0.3V-0.7V can be obtained, thus forming a voltage-frequency lookup table. For example, a voltage detection value of 0.35V is loaded onto the acquisition circuit; that is, the 0.35V voltage detection signal is transmitted as an enable signal to the first input of the NAND gate in the acquisition circuit to obtain the frequency value corresponding to the 0.35V voltage during the chip's unloaded startup process. This embodiment uses the startup of multiple core units in each partition in an unloaded state as the basis for adjusting the startup interval period of each core unit, forming a voltage-frequency lookup table that accurately measures the target voltage value of each core unit.

[0075] Secondly, the controller collects the oscillation frequency of each core unit when the chip is in the working startup state, obtains the corresponding working voltage through the acquired voltage-frequency lookup table, and then adjusts the startup interval period of each core unit according to the preset voltage threshold and period threshold.

[0076] In this embodiment, the 32 core units of the four partitions of the chip are started in a high-load state. The acquisition circuit of each core unit acquires the oscillation signal according to the acquisition period formed by the clock signal connected to the sampling unit and outputs the oscillation frequency to the control unit.

[0077] Specifically, the data collection process for eight kernel units in one partition will be explained, for example... Figure 1 As shown, partition 1 includes kernel units 1 to 8, and each kernel unit includes a data acquisition circuit.

[0078] During startup, such as Figure 3 As shown, in the first acquisition cycle t1, the acquisition circuit of each core unit obtains the number of oscillation signals from a counter. The counter records the minimum number of oscillation signals during startup, which corresponds to the minimum point of the voltage parabola during startup, and is the number of oscillation signals in acquisition cycle t7, representing the minimum operating voltage of the corresponding core unit. Then, based on the acquisition cycle and the minimum number of oscillation signals, the minimum oscillation frequency is obtained and transmitted to the control unit.

[0079] The control unit obtains the eight lowest oscillation frequencies transmitted by the eight core units, and then finds the smallest voltage value from the eight lowest oscillation frequencies as the lowest voltage value of the corresponding partition, and uses it as the reference voltage for partition 1.

[0080] When the minimum voltage value is less than the voltage threshold, it means that during the high-load startup process of partition 1, the operating voltage of the eight core units is not functioning properly. In other words, the voltage threshold is the minimum operating voltage for the core units to operate normally. When the operating voltage of a core unit is less than the voltage threshold, it indicates that the IR voltage drop generated during startup has affected the normal operation of the core units. It is necessary to adjust the startup interval of each core unit in partition 1 to stagger the startup time of the eight core units in partition 1, thereby reducing the IR voltage drop generated by partition 1 during startup.

[0081] If the minimum voltage value is less than the voltage threshold, it is also necessary to determine whether there is still room for adjustment in the startup interval period of each kernel unit. Specifically, based on the startup interval period stored in the registers of each kernel unit, it is determined whether the startup interval period is less than a preset period threshold. For example, if the period threshold is 36, a startup interval period less than 36 indicates that there is still room for adjustment in the startup interval period of each kernel unit in partition 1.

[0082] When the lowest voltage value of the 8 core units in partition 1 is less than the voltage threshold, and the startup interval period of the 8 core units in partition 1 is less than the period threshold, the startup interval period is adjusted according to the preset adjustment step size. In this embodiment, the adjustment step size is 1, that is, each time segment is added by 1, and the startup interval period of the 8 core units in partition 1 is added by 1 on the current basis. That is, the startup interval period of the 8 core units is adjusted synchronously according to the adjustment step size and the current startup interval period, further staggering the startup nodes of the 8 core units, further widening the startup interval of each core unit, thereby reducing the IR voltage drop generated by partition 1 during startup.

[0083] After adjusting the boot interval period of the 8 core units in partition 1, the chip boot process is restarted. The minimum voltage value of the 8 core units in partition 1 during the boot process is checked again. If the minimum voltage value is not less than the voltage threshold, it is determined that the boot interval period of each core unit in partition 1 has been adjusted and the boot interval period of the 8 core units in partition 1 is recorded. If the minimum voltage value is still less than the voltage threshold, the above adjustment process is repeated until the minimum voltage value is not less than the voltage threshold or the boot interval period is equal to the period threshold.

[0084] It is worth noting that when the boot interval period equals the period threshold, it indicates that the method of reducing IR voltage drop by adjusting the boot interval period of the eight kernel units in partition 1 has reached its limit. Further reduction of IR voltage drop by staggering the boot interval periods of each kernel unit is no longer possible. The boot interval period of each kernel unit in partition 1 at this point is recorded as the final adjusted boot interval period. Those skilled in the art should understand that, based on reducing IR voltage drop by adjusting the boot interval period of each kernel unit, additional operations are required to further reduce IR voltage drop, which will not be elaborated upon here.

[0085] In an optional embodiment, the startup interval of each kernel unit is set according to a preset startup interval value.

[0086] In this embodiment, with 16 time segments as the startup cycle interval value, the startup nodes of the 8 kernel units in a partition are node 0, node 16, node 32, node 64, node 80, node 96, node 112, and node 128, respectively. That is, each kernel unit is started with the same time segment interval, which can optimize the startup node of each kernel unit and effectively improve the adjustability and accuracy of the startup interval adjustment of each kernel unit.

[0087] In an optional embodiment, the boot interval period of multiple kernel units in each partition is adjusted sequentially.

[0088] In this embodiment, by adjusting the boot interval period of each kernel unit in each partition separately, the noise generated by adjusting multiple partitions at the same time can be avoided, and the accuracy of adjusting the boot interval period of each kernel unit can be effectively improved.

[0089] In an optional embodiment, the startup interval period of multiple kernel units in each partition is adjusted sequentially from closest to furthest, based on the distance between each partition and the power supply unit.

[0090] In this embodiment, considering that the IR voltage drop of multiple core units in the partition far from the power unit is higher than that of multiple core units in the partition close to the power unit, the startup interval period of each core unit in each partition is adjusted in order of distance from the power unit. That is, the startup interval period of each core unit in the partition closest to the power unit is adjusted first, and then the startup interval period of each core unit in the partition farther from the power unit is adjusted. This can effectively improve the adjustability of the startup interval period of each core unit.

[0091] Finally, the control unit forms a boot cycle table based on the adjusted boot interval periods of the multiple kernel units in each partition, and sets the boot cycle table into the registers of the multiple kernel units in each partition. This embodiment, by forming a boot cycle table and setting it in the registers of each kernel unit, facilitates the adjustment and modification of the boot interval periods of each kernel unit, thus improving the flexibility of multi-core chip boot interval period adjustment.

[0092] In this embodiment, the optimal startup interval period for each core unit in each partition of the chip is obtained by adjusting the startup interval period of multiple core units in each partition, and a startup cycle table is formed. The registers of each core unit of the chip are set according to the startup cycle table, that is, the initial value of the startup node of each core unit is determined according to the optimal startup interval period, so that each core unit in each partition of the chip is in the setting of minimum IR voltage drop, thereby reducing IR voltage drop while keeping the chip power supply voltage unchanged, effectively reducing the IR voltage drop and chip power consumption, and improving the stability of the chip.

[0093] Corresponding to the chips provided in the above embodiments, one embodiment of this application also provides a debugging method for a multi-core chip. Since the debugging method provided in this application corresponds to the multi-core chips provided in the above embodiments, the debugging method provided in this embodiment is also applicable to the previous implementation methods, and will not be described in detail in this embodiment.

[0094] like Figure 4 As shown, one embodiment of this application also provides a debugging method for a multi-core chip, including:

[0095] In response to the voltage drop generated by the startup of multiple kernel units, the oscillation frequency of the multiple kernel units is collected;

[0096] The target voltage value is determined based on the voltage-frequency lookup table and the oscillation frequencies of the multiple core units;

[0097] The startup interval period of the plurality of kernel units is determined based on the target voltage value.

[0098] This embodiment collects the oscillation frequency corresponding to the voltage drop of multiple core units during startup, and obtains the target voltage value through a voltage-frequency lookup table to determine the startup interval period of each core unit. By setting the startup interval period of each core unit, the startup times of each core unit within the same partition are staggered, thereby avoiding the IR voltage drop problem caused by large loads and large currents due to the simultaneous startup of multiple core units in related technologies. This effectively reduces the IR voltage drop of the chip and improves the stability of the chip. For specific implementation details, please refer to the foregoing embodiment, which will not be repeated here.

[0099] In an optional embodiment, determining the startup interval period of the plurality of kernel units based on the target voltage value further includes;

[0100] In response to the target voltage value being less than a preset voltage threshold and the current startup interval being less than a preset period threshold, the startup interval of the plurality of kernel units is determined based on the adjustment step size and the current startup interval.

[0101] In this embodiment, the startup interval period is determined to be adjustable based on a preset voltage threshold and a cycle threshold. If adjustable, the startup interval period of each core unit is adjusted according to the adjustment step size. For specific implementation details, please refer to the foregoing embodiments, which will not be repeated here.

[0102] In an optional embodiment, before acquiring the oscillation frequency of the plurality of kernel units in response to the voltage drop generated by the startup of the plurality of kernel units, the debugging method further includes;

[0103] During the startup process of the multiple kernel units in an idle state, the frequencies of the multiple kernels are obtained according to multiple preset voltage detection values, and the voltage-frequency lookup table is generated and stored.

[0104] In this embodiment, the acquisition circuit is used to obtain the oscillation frequency of the core units under multiple voltage detection values ​​when multiple core units are in an unloaded state, so as to form a voltage-frequency reference table as the basis for adjusting the start-up interval period of each core unit, which can accurately measure the target voltage value of each core unit. For specific implementation details, please refer to the foregoing embodiments, which will not be repeated here.

[0105] In an optional embodiment, the multi-core chip includes at least one partition, each partition including multiple kernel units, and the debugging method further includes: sequentially adjusting the boot interval period of the multiple kernel units in each partition.

[0106] This embodiment, by adjusting the boot interval period of each kernel unit in each partition separately, avoids the noise generated by adjusting multiple partitions simultaneously, effectively improving the accuracy of the boot interval period adjustment for each kernel unit. For specific implementation details, please refer to the foregoing embodiment, which will not be repeated here.

[0107] In an optional embodiment, the multi-core chip includes a power supply unit, and the step of sequentially adjusting the startup interval period of the multiple core units of each partition further includes: adjusting the startup interval period of the multiple core units of each partition sequentially from the nearest to the farthest according to the distance between each partition and the power supply unit.

[0108] This embodiment takes into account the phenomenon that the IR voltage drop of multiple core units in the partition far from the power supply unit is higher than that of multiple core units in the partition close to the power supply unit. The startup interval period of each core unit in each partition is adjusted in order of distance from the power supply unit, effectively improving the adjustability of the startup interval period of each core unit. For specific implementation details, please refer to the foregoing embodiment, which will not be repeated here.

[0109] In an optional embodiment, before acquiring the oscillation frequency of the plurality of kernel units in response to the voltage drop generated by the startup of the plurality of kernel units, the debugging method further includes:

[0110] The startup interval of the multiple kernel units is set according to the preset startup interval value.

[0111] This embodiment further optimizes the startup interval of each kernel unit by setting an initial value for the startup interval period, effectively improving the adjustability and accuracy of the startup interval adjustment. For specific implementation details, please refer to the foregoing embodiment, which will not be repeated here.

[0112] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following: in response to a voltage drop generated by the startup of a plurality of core units, acquiring the oscillation frequency of the plurality of core units; determining a target voltage value according to a voltage-frequency lookup table and the oscillation frequency of the plurality of core units; and determining the startup interval period of the plurality of core units according to the target voltage value.

[0113] In practical applications, the computer-readable storage medium can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0114] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0115] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0116] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0117] like Figure 5 As shown, another embodiment of the present invention provides a structural schematic diagram of a computer device. Figure 5 The computer device 12 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present invention.

[0118] like Figure 5 As shown, the computer device 12 is represented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0119] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0120] Computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0121] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 5 Not shown; usually referred to as a "hard drive"). Although Figure 5 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0122] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.

[0123] Computer device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable a user to interact with the computer device 12, and / or with any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed through input / output (I / O) interface 22. Furthermore, computer device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) through network adapter 20. Figure 5 As shown, network adapter 20 communicates with other modules of computer device 12 via bus 18. It should be understood that, although... Figure 5 As not shown, it can be used in conjunction with computer device 12 with other hardware and / or software modules, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0124] The processor unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing a debugging method for a multi-core chip provided in an embodiment of the present invention.

[0125] This application addresses the problems existing in related technologies by proposing a multi-core chip and a multi-core chip debugging method. It determines the voltage drop generated during the startup of each core unit through a data acquisition circuit in each core unit, and determines the startup interval period for each core unit based on the voltage drop through a control unit. Startup is then performed according to the startup interval period, which reduces the IR voltage drop while maintaining a constant chip supply voltage. Specifically, this embodiment staggers the startup times of core units within the same partition by setting the startup interval period for each core unit, thereby avoiding the IR voltage drop problem caused by large loads and currents due to simultaneous startup of core units in related technologies. This effectively reduces the chip's IR voltage drop and improves chip stability. Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all embodiments here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A multi-core chip, characterized in that, It includes at least one partition, said partition comprising a control unit and multiple kernel units, wherein, The kernel unit includes a data acquisition circuit, which is used to determine the voltage drop generated during the startup of the kernel unit and to acquire the oscillation frequency of the kernel unit. The control unit is connected to the acquisition circuit of each of the core units and is used to determine the start-up interval period of the multiple core units according to the voltage drop determined by the acquisition circuit. The multiple core units start up according to the start-up interval period, which represents the time during which the multiple core units start up separately. The control unit is also used to determine a target voltage value according to a voltage-frequency lookup table and the oscillation frequency of the multiple core units, and to determine the start-up interval period according to the target voltage value. The voltage-frequency lookup table is stored in the control unit. The acquisition circuit includes NAND gates, an even number of NOT gates, a buffered NOT gate, and a sampling unit, wherein... The NAND gate includes a first input terminal, a second input terminal, and an output terminal. An enable signal is connected to the first input terminal of the NAND gate. The second input terminal and the output terminal of the NAND gate are connected end to end with the even number of NOT gates to form a ring oscillator. The buffered NOT gate includes an input terminal and an output terminal, and the input terminal of the buffered NOT gate is connected to the oscillation signal output by the ring oscillator; The sampling unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the sampling unit is connected to the output terminal of the buffer NOT gate. The second input terminal of the sampling unit is connected to a preset clock signal. The output terminal of the sampling unit is connected to the control unit.

2. The multi-core chip according to claim 1, characterized in that, The control unit is also configured to form a startup cycle table based on the startup interval period, and configure the registers of the kernel unit based on the startup cycle table.

3. The multi-core chip according to claim 2, characterized in that, The control unit is also used to obtain the oscillation frequency of the multiple kernel units in the idle state during the startup process of the multiple kernel units in each partition according to the preset multiple voltage detection values, and generate and store the voltage-frequency lookup table.

4. The multi-core chip according to claim 3, characterized in that, The sampling unit includes a counter. The sampling unit forms a sampling period based on the incoming clock signal, collects the number of oscillation signals through the counter during the sampling period, and determines the oscillation frequency based on the sampling period and the number of oscillation signals.

5. A debugging method for a multi-core chip as described in any one of claims 1-4, characterized in that, include: In response to the voltage drop generated by the startup of multiple kernel units, the oscillation frequency of the multiple kernel units is collected; The target voltage value is determined based on the voltage-frequency lookup table and the oscillation frequencies of the multiple core units; The startup interval period of the plurality of kernel units is determined based on the target voltage value.

6. The debugging method according to claim 5, characterized in that, The step of determining the startup interval period of the plurality of kernel units based on the target voltage value further includes: In response to the target voltage value being less than a preset voltage threshold and the current startup interval being less than a preset period threshold, the startup interval of the plurality of kernel units is determined based on the adjustment step size and the current startup interval.

7. The debugging method according to claim 5 or 6, characterized in that, Before acquiring the oscillation frequency of the multiple kernel units in response to the voltage drop generated during the startup of the multiple kernel units, the debugging method further includes: During the startup process of the multiple kernel units in an idle state, the frequencies of the multiple kernel units are obtained according to multiple preset voltage detection values, and the voltage-frequency lookup table is generated and stored.

8. The debugging method according to claim 5, characterized in that, The multi-core chip includes at least one partition, and each partition includes multiple kernel units. The debugging method further includes: sequentially adjusting the startup interval period of the multiple kernel units in each partition.

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