A real-time task schedulability analysis method and device

Abstract

The application provides a real-time task schedulability analysis method and device, the method comprises the following steps: obtaining a task set comprising a plurality of real-time tasks; determining a maximum deadline from the task set according to the relative deadline of the real-time tasks; determining an initial binary sequence of a processor time axis and a task binary sequence of the real-time tasks according to the maximum deadline; and performing schedulability analysis according to the initial binary sequence and the task binary sequence in the order from high to low priority of the real-time tasks. The scheme can quickly and accurately obtain the schedulability analysis result of the real-time tasks.

Description

Technical Field

[0001] This invention relates to the field of embedded systems technology, and in particular to a method and apparatus for real-time task schedulability analysis. Background Technology

[0002] Spacecraft systems are safety-critical real-time systems, and their application software (often referred to as tasks in embedded systems) has strong real-time requirements. Missing deadlines or unreliability of application software (or real-time tasks) may lead to catastrophic consequences. Therefore, ensuring the real-time performance and reliability of application software is the most critical issue in space-based embedded operating systems for spacecraft.

[0003] In aerospace control systems, high-safety-critical tasks such as data acquisition, control calculation, and control output all have strict deadline requirements. Missing these deadlines can have devastating consequences for the entire spacecraft system, leading to significant losses. Therefore, deadline fulfillment analysis is crucial, and this process is achieved through schedulability analysis methods. Currently, schedulability analysis in spacecraft primarily employs methods such as manual walkthroughs, system simulations, and response time calculations. However, these methods suffer from high operational overhead, insufficient accuracy, and are prone to errors, resulting in low efficiency when applied to real-time systems. Therefore, to meet the need for rapid mission schedulability analysis in spacecraft systems, a more efficient real-time mission schedulability analysis method is required. Summary of the Invention

[0004] This invention provides a method and apparatus for real-time task schedulability analysis, which can quickly and accurately obtain the schedulability analysis results of real-time tasks.

[0005] In a first aspect, the present invention provides a method for analyzing the schedulability of real-time tasks, comprising:

[0006] Retrieve a task set that includes multiple real-time tasks;

[0007] Based on the relative deadlines of the real-time tasks, determine the maximum deadline from the task set;

[0008] Based on the maximum deadline, determine the initial binary sequence of the processor timeline and the task binary sequence of the real-time task;

[0009] Based on the initialization binary sequence and the task binary sequence, schedulability analysis is performed in descending order of priority of the real-time tasks.

[0010] Optionally, the number of bits in the initial binary sequence is the same as the maximum cutoff period;

[0011] Each bit in the initial binary sequence is 0; each bit corresponds to a unit of time in the processor time axis.

[0012] Optionally, the real-time task is represented using a triplet of information including period, worst-case execution time, and relative deadline.

[0013] The number of bits in the task's binary sequence is the same as the maximum deadline;

[0014] Based on the stated period and the worst-case execution time, the binary sequence of the task is determined to be B = b1, ..., b k ,…,b L Where L is the number of units of time in the processor timeline, and this number is the same as the number of bits in the task binary sequence; b k b represents the binary bits in the k-th unit of time. k When b = 0, the request status of the real-time task in the k-th unit of time is idle. k When = 1, the request status of the real-time task in the k-th unit of time is occupied.

[0015] Optionally, the step of performing schedulability analysis based on the initialization binary sequence and the task binary sequence, in descending order of priority of the real-time tasks, includes:

[0016] S1: Determine the highest priority real-time task among the unanalyzed real-time tasks in the task set in the current analysis as the first real-time task, and determine the number of zeros in the task binary sequence of the first real-time task in the initial binary sequence;

[0017] S2: When the worst execution time of the first real-time task is not greater than the zero number, the first real-time task is determined to be schedulable;

[0018] S3: Update the initial binary sequence according to the task binary sequence of the first real-time task to obtain the updated binary sequence, and mark the first real-time task as analyzed;

[0019] S4: Determine whether the number of unanalyzed real-time tasks in the task set is zero; if not, determine the updated binary sequence as the initial binary sequence for the next analysis and return to step S1; if yes, determine that the task set is schedulable.

[0020] Optionally, determining the number of zeros in the initialization binary sequence of the first real-time task includes:

[0021] Determine the first number of binary bits that are 1 in the initial binary sequence described in the current analysis;

[0022] The zero number is obtained by performing a difference operation on the relative deadline time and the first quantity of the first real-time task.

[0023] Optionally, updating the initial binary sequence based on the task binary sequence of the first real-time task to obtain the updated binary sequence includes:

[0024] The first binary bit in the initial binary sequence is determined as the starting unit time;

[0025] The initial binary sequence, with the starting unit time as the first bit, is added to the task binary sequence to obtain the processor update binary sequence; wherein the number of bits in the processor update binary sequence is the same as the number of bits in the initial binary sequence; in the addition operation, 0+0=0, 0+1=1, 1+0=1, 1+1=1.

[0026] Optionally, after determining that the task set is schedulable, the method further includes:

[0027] Obtain the updated binary sequence corresponding to the condition that the number of unanalyzed real-time tasks in the task set is zero;

[0028] Determine whether there is a 0 bit in the updated binary sequence;

[0029] If so, then it is determined that the unit of time in which the binary bit that is 0 is located is in an idle state.

[0030] In a second aspect, the present invention provides a real-time task schedulability analysis apparatus, comprising:

[0031] The acquisition module is used to acquire a task set that includes multiple real-time tasks;

[0032] An initialization module is used to determine the maximum deadline from the task set based on the relative deadline time of the real-time tasks; and to determine the initialization binary sequence of the processor time axis and the task binary sequence of the real-time tasks based on the maximum deadline.

[0033] The analysis and processing module is used to perform schedulability analysis based on the initialization binary sequence and the task binary sequence, in descending order of priority of the real-time tasks.

[0034] Thirdly, embodiments of the present invention also provide a computing device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the method described in any of the first aspects of this specification.

[0035] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the methods described in any of the first aspects of this specification.

[0036] This invention provides a method and apparatus for real-time task schedulability analysis. The method establishes a binary sequence timeline of processor load (initializing the binary sequence) and represents the execution request of each real-time task as a binary sequence. Then, based on the initializing binary sequence and the task binary sequence, schedulability analysis is performed on the entire task set in descending order of real-time task priority. Thus, schedulability analysis based on task binary sequences not only provides a comprehensive analysis of task schedulability but also fulfills a necessary condition for task schedulability, enabling accurate analysis of task schedulability. Furthermore, this method has the lowest time complexity, allowing for fast and accurate analysis of real-time task schedulability. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart of a real-time task schedulability analysis method provided in an embodiment of the present invention;

[0039] Figure 2 This is a real-time task model provided in an embodiment of the present invention;

[0040] Figure 3 This is a diagram showing the schedulability analysis results obtained from a real-time task schedulability analysis method provided in an embodiment of the present invention;

[0041] Figure 4 This is a hardware architecture diagram of a computing device provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the structure of a real-time task schedulability analysis device provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0044] Please refer to Figure 1 This invention provides a method for analyzing the schedulability of real-time tasks, the method comprising:

[0045] Step 100: Obtain a task set that includes multiple real-time tasks;

[0046] Step 102: Determine the maximum deadline from the task set based on the relative deadlines of the real-time tasks;

[0047] Step 104: Determine the initial binary sequence of the processor timeline and the task binary sequence of the real-time task based on the maximum deadline.

[0048] Step 106: Based on the initial binary sequence and the task binary sequence, perform schedulability analysis in descending order of priority of real-time tasks.

[0049] In this invention, real-time task schedulability analysis, as a component of the spacecraft embedded operating system, implements an efficient real-time task schedulability analysis method based on binary addition, building upon the core scheduling strategy. This solves the problem of rapidly and accurately determining the schedulability of task sets in real-time systems such as spacecraft, ensuring system real-time performance. This method uses binary sequences as a quantitative representation of task preemption relationships, fundamentally revealing the principle of task scheduling, thus enabling a concise and efficient determination of task set schedulability. Furthermore, this operating system supports both traditional task scheduling methods and efficient task schedulability analysis, meeting the diverse schedulability analysis needs of different spacecraft.

[0050] It should be noted that schedulability analysis uses mathematical methods to determine whether a task can be completed before the deadline. If the task can be completed before the deadline, it is schedulable. Otherwise, it is not schedulable. If all tasks in a task set are schedulable, then the task set is schedulable. Otherwise, the task set is not schedulable.

[0051] Exact schedulability analysis: This means that if a schedulability analysis algorithm determines that a task is schedulable, then the task is definitely schedulable, and vice versa. In other words, the schedulability analysis algorithm is a necessary and sufficient condition for determining that a task is schedulable. Therefore, exact schedulability analysis is often also called necessary and sufficient schedulability analysis.

[0052] For step 100, in a preferred embodiment, the real-time task is represented using a triplet of information including period, worst-case execution time, and relative deadline.

[0053] In this embodiment of the invention, a real-time task is a task with strict deadline constraints, where missing the deadline will lead to catastrophic consequences. For example... Figure 2 As shown, real-time tasks are typically modeled using a triple (T, C, D), where T represents the period of the real-time task, C represents the worst-case execution time of the real-time task, and D represents the relative deadline of the real-time task; and each arrival of a real-time task is called an instance of the real-time task.

[0054] For step 102, find the maximum deadline for real-time tasks from the task set.

[0055] In a preferred embodiment, the number of bits in the initial binary sequence is the same as the maximum cutoff period;

[0056] Each bit in the initialized binary sequence is 0; each bit corresponds to a unit of time in the processor timeline.

[0057] It should be noted that the processor timeline: PTL(L) represents the state of the processor occupied by tasks in each unit of time from time 0 to L. It is represented by a binary number B0 consisting of L bits, which represents L units of time within (0,L), forming the set ST = {st1, st2, ... st...}. L}, st k Let B represent the k-th time unit, where 1 ≤ k ≤ L. The corresponding binary number B0, composed of L bits, is denoted as B = b1, ..., b2. k ,…,b L This represents the k-th binary bit of B, where 1 ≤ k ≤ L. If time slice st k If it is occupied by a task, then the corresponding binary bit b k =1, otherwise b k =0. That is Where L = the maximum deadline for real-time tasks identified in the task set.

[0058] In step 104, in a preferred embodiment, the number of bits in the task binary sequence is the same as the maximum deadline;

[0059] Based on the period and worst-case execution time, the binary sequence of the task is determined as B = b1, ..., b k ,…,b L Where L is the number of time units in the processor timeline, and this number is the same as the number of bits in the task's binary sequence; b k b represents the binary bits in the k-th unit of time. k When b = 0, the request status of the real-time task in the k-th unit of time is idle. k When = 1, the request status of the real-time task in the k-th unit of time is occupied.

[0060] Specifically, the task binary sequence: TBS(τ) i L) refers to task τ i A binary sequence is obtained by representing the request status of the processor for each unit of time from time 0 to L using binary bits. This sequence corresponds to a binary number B consisting of L binary bits, denoted as B = b1, ..., b k ,…,b L If τ i Request time slice st k Then the corresponding binary bit b k =1, otherwise b k =0. The binary number B represents task τ. i The request status for each time slice of the processor within time 0 to L, i.e.

[0061] In this embodiment of the invention, the binary sequence of tasks is arranged in the following order: worst execution time 1, period - worst execution time 0, worst execution time 1, period - worst execution time 0, ..., where 0 indicates that the request status of the real-time task in the k-th unit of time is idle, and 1 indicates that the request status of the real-time task in the k-th unit of time is occupied.

[0062] For step 106, based on the initialization binary sequence and the task binary sequence, schedulability analysis is performed in descending order of real-time task priority, including:

[0063] S1: Determine the highest priority real-time task among the unanalyzed real-time tasks in the task set in the current analysis as the first real-time task, and determine the number of zeros in the initial binary sequence of the task binary sequence of the first real-time task.

[0064] S2: Determine that the first real-time task is schedulable when the worst execution time of the first real-time task is no greater than zero.

[0065] S3: Update the initial binary sequence according to the task binary sequence of the first real-time task to obtain the updated binary sequence, and mark the first real-time task as analyzed;

[0066] S4: Determine if the number of unanalyzed real-time tasks in the task set is zero; if not, update the binary sequence to be the initial binary sequence for the next analysis and return to step S1; if yes, determine that the task set is schedulable.

[0067] It should be noted that, as mentioned in the previous example, the zero number refers to the number of 0s counted from the first binary bit to the Lth binary bit in the binary number B.

[0068] In this embodiment of the invention, for unanalyzed real-time tasks, according to their priority, the highest-priority real-time task in the current analysis is selected first. The number of zeros in the initialization binary sequence for that real-time task is determined. If the worst-case execution time is no greater than zero, the real-time task is determined to be schedulable; otherwise, the task set is unschedulable, and the process terminates directly. After determining that the real-time task is schedulable, the initialization binary sequence is updated using the task's binary sequence to obtain an updated binary sequence. Simultaneously, the real-time task is marked as analyzed, and the updated binary sequence is used as the initialization binary sequence for the next analysis. Steps S1 to S3 are repeated until all real-time tasks are schedulable, and the task set is determined to be schedulable.

[0069] In a preferred embodiment, step S1 includes:

[0070] Determine the first number of binary bits that are 1 in the initial binary sequence during the current analysis;

[0071] The difference between the relative deadline and the first quantity of the first real-time task is calculated to obtain a zero number.

[0072] Specifically, for example, if the maximum deadline is 7, and the initial binary sequence is 0000000 during the first analysis, and the relative deadline of the first real-time task is 5, then the number of zeros is 5-0=5; for example, if the maximum deadline is 7, and the initial binary sequence is 1000000 during the first analysis, and the relative deadline of the first real-time task is 7, then the number of zeros is 7-1=6.

[0073] In a preferred embodiment, step S3 includes:

[0074] The first binary bit in the initial binary sequence is determined as the starting unit time.

[0075] The initial binary sequence, with the starting unit time as the first bit, is added to the task binary sequence to obtain the processor update binary sequence. The number of bits in the processor update binary sequence is the same as the number of bits in the initial binary sequence. In the addition operation, 0+0=0, 0+1=1, 1+0=1, and 1+1=1.

[0076] Specifically, addition is the operation of aligning the binary bit at the starting unit time of the initial binary sequence with the first unit time of the task binary sequence and then adding them together. In other words, the initial binary sequence is shifted to the starting unit time and then added. Shift addition: PA(B1,B2) means that the binary number B2 is added to B1 in a shifting manner, so that B1 becomes a new binary number. The shift addition rules are as follows: (1) Add corresponding binary bits; (2) The addition order is from the high bit to the low bit; (3) 0+0=0, 0+1=1, 1+0=1, 1+1=1; (4) 1+1 will carry 1 to the low bit, and the carry will be accumulated to the lower bit.

[0077] For example, if the initial binary sequence is 10000 and the task binary sequence is 10000, then the processor's updated binary sequence obtained by this addition operation is 11000. In other words, in this shifting addition operation, the real-time tasks being added start occupying idle positions, and then the processor's timeline is updated sequentially according to the priority of the real-time tasks to obtain the task binary sequence corresponding to the task set. This allows for a direct determination of whether the task set is schedulable and whether there is idle time, enabling efficient real-time task schedulability analysis.

[0078] In step 106, after determining that the task set is schedulable, the following steps are also included:

[0079] Obtain the updated binary sequence when the number of unanalyzed real-time tasks in the task set is zero;

[0080] Determine if there is a 0 bit in the updated binary sequence;

[0081] If so, then the unit of time in which the binary bit that is 0 is located is in an idle state.

[0082] This invention proposes a schedulability determination method based on binary task sequences. By establishing a processor timeline (PTL) representing the binary sequence of processor load, task execution requests are represented as binary sequences. A shift-addition method is used to represent the preemption relationship of high-priority tasks, and zeros are used to quickly calculate the worst-case response time of a task. Accurate schedulability analysis is performed on each task, thus achieving a fast and accurate determination of the schedulability of a real-time task set. This is a necessary and sufficient condition for schedulability determination. This method directly uses binary shift-addition operations as the schedulability analysis process, which can be easily accelerated by GPUs or dedicated chips. It has great application potential in large-scale open real-time operating systems with high multi-tasking and high loads.

[0083] Existing technologies typically employ utilization upper bound analysis methods, which only support the sufficiency and schedulability analysis of tasks. In contrast, this invention adopts a schedulability analysis method based on binary addition, which not only provides a sufficiency analysis of task schedulability but is also a necessary condition for task schedulability, enabling precise analysis of task schedulability.

[0084] Existing technologies for accurate schedulability analysis typically employ response time analysis methods, which have exponentially increasing time complexity. In contrast, this invention uses a schedulability analysis method based on binary addition, which has linear time complexity and is currently the most time-efficient accurate schedulability analysis algorithm, enabling rapid analysis of task schedulability.

[0085] Existing technologies typically do not support schedulability analysis for task sets with varying numbers of tasks and are only applicable to closed systems; however, this invention supports schedulability analysis for task sets with different numbers of tasks and can be used in online open systems.

[0086] Existing technologies typically employ iterative computation methods, where the current result is interdependent with historical results, making parallel computation difficult. In contrast, this invention utilizes a schedulable analysis method based on binary addition, enabling parallel acceleration via FPGA or GPU, thus further improving analysis efficiency.

[0087] In one specific embodiment, the spacecraft has four real-time tasks, and the schedulability analysis results are as follows: Figure 3 As shown, specific methods for analyzing the schedulability of real-time tasks include:

[0088] Step 301: Task set initialization;

[0089] 11) Initialize the operating system and reset all states;

[0090] 12) Create real-time tasks Task1, Task2, Task3, and Task4 sequentially. Assume the operating system task creation API interface is Taski_ID = OSTaskSpawn(Ti, Ci, Ji, Di, func_Taski), where 1 ≤ i ≤ 4, func_Taski represents the task body function corresponding to the real-time task Taski, and Taski_ID represents the identifier ID of the real-time task Taski in the system; Task1 = (C1 = 1, D1 = 5, T1 = 11), Task2 = (C2 = 3, D2 = 7, T2 = 9), Task3 = (C3 = 1, D3 = 6, T3 = 6), Task4 = (C3 = 2, D3 = 11, T3 = 12); where the priority of each real-time task from high to low is Task1, Task2, Task3, and Task4.

[0091] 13) Tasks Task1, Task2, Task3, and Task4 constitute task set S;

[0092] Step 302: Calculate the maximum deadline of task set S, and find the maximum deadline D of real-time tasks from task set S. max =11;

[0093] Step 303: Initialize the processor timeline. Define an 11-bit binary number as the processor timeline and assign it the value 0 to obtain the initial binary sequence PTL(11) = 00000000000; the task binary sequences of the real-time tasks are TBS(τ1,11) = 10000000000, TBS(τ2,11) = 11100000011, TBS(τ3,11) = 10000010000, and TBS(τ4,11) = 11000000000.

[0094] Step 304: Calculate the number of zeros. Select Task1, the highest priority real-time task in the task set that has not been analyzed in the current analysis, and calculate the number of zeros m = 5 in the initial binary sequence within the deadline interval of real-time task Task1;

[0095] Step 305: Determine schedulability. Compare the worst execution time C1 = 1 of Task1 with the zero number m. Since 1 < 5, Task1 is schedulable.

[0096] Step 306: Update the processor time axis PTL; add the currently analyzed initial binary sequence TBS(τ1,11) to the initial binary sequence PTL(11) by shifting and adding, and then update the binary sequence PTL' = 10000000000; mark Task1 as analyzed;

[0097] Step 307: The number of unanalyzed real-time tasks in task set S is 3; determine the updated binary sequence as the initial binary sequence for the next analysis, and return to step S304;

[0098] Step 304: Calculate the number of zeros. Select Task2, the highest priority real-time task in the task set that has not been analyzed in the current analysis, and calculate the number of zeros m = 6 in the initial binary sequence within the deadline interval of real-time task Task2;

[0099] Step 305: Determine schedulability. Compare the worst execution time C2 = 3 of Task2 with the zero number m. Since 3 < 6, Task2 is schedulable.

[0100] Step 306: Update the processor time axis PTL; add the currently analyzed initial binary sequence TBS(τ2,11) to the initial binary sequence PTL=10000000000 using a shift addition method, and then update the binary sequence PTL'=11110000011; mark Task2 as analyzed;

[0101] Step 307: The number of unanalyzed real-time tasks in task set S is 2; determine the updated binary sequence as the initial binary sequence for the next analysis, and return to step S304;

[0102] Step 304: Calculate the number of zeros. Select Task3, the highest priority real-time task in the task set that has not been analyzed in the current analysis, and calculate the number of zeros m = 2 in the initial binary sequence within the deadline interval of real-time task Task3;

[0103] Step 305: Determine schedulability. Compare the worst execution time C3 = 1 of Task3 with the zero number m. Since 1 < 2, Task3 is schedulable.

[0104] Step 306: Update the processor time axis PTL; add the currently analyzed initial binary sequence TBS(τ3,11) to the initial binary sequence PTL==11110000011 using shift addition, and then update the binary sequence PTL'=11111010011; mark Task3 as analyzed;

[0105] Step 307: The number of unanalyzed real-time tasks in task set S is 1; determine the updated binary sequence as the initial binary sequence for the next analysis, and return to step S304;

[0106] Step 304: Calculate the number of zeros. Select Task4, the highest priority real-time task in the task set that has not been analyzed in the current analysis, and calculate the number of zeros m = 6 in the deadline interval of the initial binary sequence in the real-time task Task4;

[0107] Step 305: Determine schedulability. Compare the worst-case execution time C3 = 2 of Task4 with the zero number m. Since 2 < 6, Task4 is schedulable.

[0108] Step 306: Update the processor time axis PTL; add the currently analyzed initial binary sequence TBS(τ4,11) to the initial binary sequence PTL==11111010011 using shift addition, and then update the binary sequence PTL'=111111111011; mark Task4 as analyzed;

[0109] Step 307: The number of unanalyzed real-time tasks in task set S is 0; it is determined that task set S is schedulable, and the 9th unit of time is not occupied, so the processor is in an idle state.

[0110] like Figure 4 , Figure 5 As shown, this embodiment of the invention provides a real-time task schedulability analysis device. The device embodiment can be implemented through software, hardware, or a combination of both. From a hardware perspective, such as... Figure 4 The diagram shown is a hardware architecture diagram of a computing device containing a real-time task schedulability analysis device provided in an embodiment of the present invention. Except for... Figure 4 In addition to the processor, memory, network interface, and non-volatile memory shown, the computing device in the embodiment may also include other hardware, such as a forwarding chip responsible for processing packets. Taking software implementation as an example, such as... Figure 5 As shown, a device, in a logical sense, is formed by the CPU of its computing device reading the corresponding computer program from non-volatile memory into memory for execution. This embodiment provides a real-time task schedulability analysis device, which includes:

[0111] Module 500 is used to acquire a task set that includes multiple real-time tasks;

[0112] The initialization module 502 is used to determine the maximum deadline from the task set based on the relative deadline of the real-time tasks; and to determine the initialization binary sequence of the processor time axis and the task binary sequence of the real-time tasks based on the maximum deadline.

[0113] The analysis and processing module 504 is used to perform schedulability analysis based on the initialization binary sequence and the task binary sequence, in descending order of priority of the real-time tasks.

[0114] In some specific implementations, the acquisition module 500 can be used to perform the above step 100, the initialization module 502 can be used to perform the above steps 102 and 104, and the analysis and processing module 504 can be used to perform the above step 106.

[0115] In one embodiment of the present invention, the number of bits in the initial binary sequence is the same as the maximum cutoff period;

[0116] Each bit in the initialized binary sequence is 0; each bit corresponds to a unit of time in the processor timeline.

[0117] In one embodiment of the present invention, the real-time task is represented using a triplet of information including period, worst-case execution time, and relative deadline.

[0118] The number of bits in the task's binary sequence is the same as the maximum deadline;

[0119] Based on the period and worst-case execution time, the binary sequence of the task is determined as B = b1, ..., b k ,…,b L Where L is the number of time units in the processor timeline, and this number is the same as the number of bits in the task's binary sequence; b k b represents the binary bits in the k-th unit of time. k When b = 0, the request status of the real-time task in the k-th unit of time is idle. k When = 1, the request status of the real-time task in the k-th unit of time is occupied.

[0120] In one embodiment of the present invention, the analysis and processing module 504 is further configured to perform the following operations:

[0121] S1: Determine the highest priority real-time task among the unanalyzed real-time tasks in the task set in the current analysis as the first real-time task, and determine the number of zeros in the initial binary sequence of the task binary sequence of the first real-time task.

[0122] Determine the first number of binary bits that are 1 in the initial binary sequence during the current analysis;

[0123] The difference between the relative deadline and the first quantity of the first real-time task is calculated to obtain a zero number;

[0124] S2: Determine that the first real-time task is schedulable when the worst execution time of the first real-time task is no greater than zero.

[0125] S3: Update the initial binary sequence according to the task binary sequence of the first real-time task to obtain the updated binary sequence, and mark the first real-time task as analyzed;

[0126] The first binary bit in the initial binary sequence is determined as the starting unit time.

[0127] The initial binary sequence, with the starting unit time as the first bit, is added to the task binary sequence to obtain the processor update binary sequence. The number of bits in the processor update binary sequence is the same as the number of bits in the initial binary sequence. In the addition operation, 0+0=0, 0+1=1, 1+0=1, 1+1=1.

[0128] S4: Determine if the number of unanalyzed real-time tasks in the task set is zero; if not, update the binary sequence to be the initial binary sequence for the next analysis and return to step S1; if yes, determine that the task set is schedulable.

[0129] In one embodiment of the present invention, the device further includes a scheduling module, which is also configured to perform the following operations:

[0130] After determining that the task set is schedulable, obtain the updated binary sequence corresponding to the condition that the number of unanalyzed real-time tasks in the task set is zero;

[0131] Determine if there is a 0 bit in the updated binary sequence;

[0132] If so, then the unit of time in which the binary bit that is 0 is located is in an idle state.

[0133] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on a real-time task schedulability analysis device. In other embodiments of the present invention, a real-time task schedulability analysis device may include more or fewer components than illustrated, or combine some components, split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0134] The information interaction and execution process between the modules in the above-mentioned device are based on the same concept as the method embodiment of the present invention, and the specific details can be found in the description of the method embodiment of the present invention, and will not be repeated here.

[0135] This invention also provides a computing device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements a real-time task schedulability analysis method according to any embodiment of this invention.

[0136] This invention also provides a computer-readable storage medium storing a computer program. When executed by a processor, the computer program causes the processor to perform a real-time task schedulability analysis method according to any embodiment of this invention.

[0137] Specifically, a system or apparatus equipped with a storage medium may be provided, on which software program code implementing the functions of any of the embodiments described above is stored, and the computer (or CPU or MPU) of the system or apparatus may read and execute the program code stored in the storage medium.

[0138] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute part of the present invention.

[0139] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0140] Furthermore, it should be clear that not only can the program code read by the computer be executed, but also the operating system on the computer can be instructed based on the program code to perform some or all of the actual operations, thereby realizing the function of any of the embodiments described above.

[0141] Furthermore, it is understood that the program code read from the storage medium is written to the memory set in the expansion board inserted into the computer or to the memory set in the expansion module connected to the computer. Then, based on the instructions of the program code, the CPU or other components installed on the expansion board or expansion module execute some and all of the actual operations, thereby realizing the function of any of the above embodiments.

[0142] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0143] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for analyzing the schedulability of real-time tasks, characterized in that, include: Retrieve a task set that includes multiple real-time tasks; The real-time task is represented using a triplet of information including period, worst-case execution time, and relative deadline. Based on the relative deadlines of the real-time tasks, determine the maximum deadline from the task set; Based on the maximum deadline, determine the initial binary sequence of the processor timeline and the task binary sequence of the real-time task; the number of bits in the initial binary sequence is the same as the maximum deadline; all binary bits are initially 0; each binary bit corresponds to a unit of time in the processor timeline; Based on the initialization binary sequence and the task binary sequence, schedulability analysis is performed in descending order of priority of the real-time tasks; The schedulability analysis, performed according to the priority of the real-time tasks from high to low, includes: S1: Determine the highest priority real-time task among the unanalyzed real-time tasks in the task set described in the current analysis as the first real-time task, and determine the first number of binary bits with 1 in the initial binary sequence described in the current analysis; perform a difference operation on the relative deadline time of the first real-time task and the first number to obtain a zero number; S2: When the worst execution time of the first real-time task is not greater than the zero number, the first real-time task is determined to be schedulable; S3: Determine the first binary bit in the initialization binary sequence as the starting unit time; perform an addition operation between the initialization binary sequence with the starting unit time as the first bit and the task binary sequence to obtain the processor update binary sequence, and mark the first real-time task as analyzed; wherein, the number of bits in the processor update binary sequence is the same as the number of bits in the initialization binary sequence; in the addition operation, 0+0=0, 0+1=1, 1+0=1, 1+1=1; S4: Determine whether the number of unanalyzed real-time tasks in the task set is zero; if not, determine the updated binary sequence as the initial binary sequence for the next analysis and return to step S1; if yes, determine that the task set is schedulable.

2. The method according to claim 1, characterized in that, The number of bits in the task's binary sequence is the same as the maximum deadline; Based on the period and the worst-case execution time, the task binary sequence is determined as follows: where L is the number of units of time in the processor time axis, and this number is the same as the number of bits in the task binary sequence. b k This represents the binary bits at the k-th unit of time. b k When = 0, the request status of the real-time task in the k-th unit of time is idle. b k When =1, the request status of the real-time task in the k-th unit of time is occupied.

3. The method according to any one of claims 1 to 2, characterized in that, After determining that the task set is schedulable, the method further includes: Obtain the updated binary sequence corresponding to the condition that the number of unanalyzed real-time tasks in the task set is zero; Determine whether there is a 0 bit in the updated binary sequence; If so, then it is determined that the unit of time in which the binary bit that is 0 is located is in an idle state.

4. A real-time task schedulability analysis device, characterized in that, For implementing the method as described in any one of claims 1 to 3, comprising: The acquisition module is used to acquire a task set that includes multiple real-time tasks; An initialization module is used to determine a maximum deadline from the task set based on the relative deadlines of the real-time tasks; and to determine an initialization binary sequence of the processor time axis and a task binary sequence of the real-time tasks based on the maximum deadline. The analysis and processing module is used to perform schedulability analysis based on the initialization binary sequence and the task binary sequence, in descending order of priority of the real-time tasks.

5. A computing device comprising a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the method as described in any one of claims 1-3.

6. A computer-readable storage medium having a computer program stored thereon, which, when executed in a computer, causes the computer to perform the method of any one of claims 1-3.

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