FinFET devices and methods of making the same

Abstract

The application provides a FinFET device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, the substrate is provided with a plurality of dummy gates and a first sidewall covering the sidewall of the dummy gate; oxidizing a partial thickness of the first sidewall to form a sidewall oxide layer, and removing the sidewall oxide layer; forming a second sidewall covering the first sidewall; forming an interlayer dielectric layer filling the gap between adjacent dummy gates; and removing the dummy gate and the first sidewall to form a groove. In the process of removing the dummy gate and the first sidewall, although over-etching of the second sidewall will cause the size of the groove to increase, the overall size of the dummy gate and the first sidewall will decrease after the partial thickness of the first sidewall is oxidized to form the sidewall oxide layer and then removed, so that the size of the groove will decrease, so that the size of the finally formed groove reaches the process target, and the performance of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit fabrication technology, and in particular to a FinFET device and its fabrication method. Background Technology

[0002] With the continuous development of semiconductor technology, traditional planar devices can no longer meet people's needs for high-performance devices. Fin-Field-Effect Transistor (FinFET) is a three-dimensional device, which includes fins formed vertically on the substrate and a high-dielectric-constant metal gate intersecting the fins. This design can significantly improve circuit control and reduce leakage current, while also significantly shortening the gate length of the transistor.

[0003] In advanced FinFET manufacturing processes, after the source / drain epitaxial process and the intermediate dielectric layer process are completed, the dummy gate needs to be removed to form a trench. The metal gate of the FinFET is then formed within the trench. The size (CD) of the trench after removing the dummy gate determines the final size of the metal gate. However, the removal of the dummy gate inevitably causes damage to the low-k dielectric layer on both sides of the dummy gate, resulting in a larger trench size. This leads to a larger final metal gate size, thus affecting device performance.

[0004] In existing technologies, the size of the groove is usually reduced by decreasing the size of the dummy gate, so that the size of the groove meets the process target. However, reducing the size of the dummy gate will increase the aspect ratio of the dummy gate, thereby increasing the process difficulty of removing the dummy gate in the later stage. Summary of the Invention

[0005] The purpose of this invention is to provide a FinFET device and its fabrication method, which enables the groove size to meet the process target and improve device performance, without increasing the process difficulty.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a FinFET device, comprising the following steps:

[0007] A substrate is provided on which a plurality of dummy gates and a first sidewall covering the sidewalls of the dummy gates are formed;

[0008] The first sidewall of a certain thickness is oxidized to form a sidewall oxide layer, and the sidewall oxide layer is removed;

[0009] A second side wall is formed, which covers the remaining first side wall;

[0010] An interlayer dielectric layer is formed, the interlayer dielectric layer filling the gap between adjacent dummy gates; and

[0011] Remove the dummy gate to form a groove with the first sidewall.

[0012] Optionally, a mask layer is formed on the dummy gate, and the first sidewall covers the sidewall and top of the mask layer and the surface of the substrate.

[0013] Optionally, after forming the interlayer dielectric layer and before removing the dummy gate and the first sidewall, the fabrication method further includes: planarizing the interlayer dielectric layer and the mask layer to expose the dummy gate.

[0014] Optionally, the dummy gate is made of polysilicon, and the mask layer comprises a nitride layer and an oxide layer sequentially located on the dummy gate.

[0015] Optionally, during the process of removing the dummy gate and the first sidewall, the second sidewall is over-etched, and the thickness of the oxidized first sidewall is determined by the amount of over-etching.

[0016] Optionally, the thickness of the oxidized first sidewall is half the thickness of the first sidewall.

[0017] Optionally, the first sidewall is made of SICN, the second sidewall is made of SIOCN, and the interlayer dielectric layer is made of silicon oxide.

[0018] Optionally, a cleaning process can be used to remove the oxide layer on the sidewall.

[0019] Optionally, the cleaning solution in the cleaning process contains HF.

[0020] Accordingly, the present invention also provides a semiconductor device fabricated using the FinFET device fabrication method described above.

[0021] In the FinFET device and its fabrication method provided by this invention, a sidewall oxide layer is formed by oxidizing a portion of the first sidewall thickness. This sidewall oxide layer is then removed, thereby reducing the overall size of the dummy gate and the first sidewall. Although over-etching of the second sidewall during the removal of the dummy gate and the first sidewall can increase the size of the groove, the reduction in the overall size of the dummy gate and the first sidewall results in a smaller groove size. This ensures that the final groove size meets the process target, thus improving device performance. Furthermore, compared to existing technologies, the size of the dummy gate is not reduced, and the aspect ratio remains unchanged during dummy gate removal, thus increasing the process window without increasing process difficulty. Attached Figure Description

[0022] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0023] Figure 1 This is a flowchart of a method for fabricating a FinFET device according to an embodiment of the present invention.

[0024] Figures 2 to 7 This is a schematic diagram of the steps in the fabrication method of a FinFET device provided in an embodiment of the present invention.

[0025] Figure label:

[0026] 10-Substrate; 11-Dummy gate; 12-Nitride layer; 13-Oxide layer; 14-First sidewall; 15-Sidewall oxide layer; 16-Second sidewall; 17-Interlayer dielectric layer; 18-Groove. Detailed Implementation

[0027] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0028] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0029] Figure 1 This is a flowchart of a method for fabricating a FinFET device according to an embodiment of the present invention.

[0030] like Figure 1 As shown, the method for fabricating the FinFET device includes the following steps:

[0031] S1: A substrate is provided, on which a plurality of dummy gates and a first sidewall covering the sidewalls of the dummy gates are formed;

[0032] S2: The first sidewall of a certain thickness is oxidized to form a sidewall oxide layer, and the sidewall oxide layer is removed;

[0033] S3: Form a second side wall, which covers the remaining first side wall;

[0034] S4: Form an interlayer dielectric layer, which fills the gap between adjacent dummy gates;

[0035] S5: Remove the dummy gate and the groove formed with the first sidewall.

[0036] Figures 2 to 7 This is a schematic diagram illustrating the steps of a method for fabricating a FinFET device according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2-7 The fabrication method of a FinFET device provided in an embodiment of the present invention will be described in detail.

[0037] In step S1, please refer to Figure 2 As shown, a substrate 10 is provided, on which a plurality of dummy gates 11 and a first sidewall 14 covering the sidewalls of the dummy gates 11 are formed.

[0038] The substrate 10 can be made of silicon, germanium, germanium silicon, silicon carbide, gallium arsenide or indium gallium arsenide, or silicon-on-insulator or germanium-on-insulator; or it can be made of other materials, such as gallium arsenide or other III-V compounds.

[0039] Multiple fins (not shown) may be formed within the substrate 10, and adjacent fins are isolated by an isolation structure. The dummy gate 11 spans across the fins. In this embodiment, a mask layer is formed on the dummy gate 11. The mask layer acts as a mask during the formation of the dummy gate, i.e., the dummy gate material layer is etched using the mask layer as a mask to form the dummy gate. Exemplarily, the mask layer includes a nitride layer 12 and an oxide layer 13 sequentially located on the dummy gate 11. The nitride layer 12 is preferably silicon nitride, and the oxide layer 13 is preferably silicon oxide.

[0040] The dummy gate electrode 11 can be formed by suitable deposition processes such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, additional dielectric and / or conductive layers, such as interface layers, capping layers, diffusion / barrier layers, other suitable layers, and / or combinations thereof, can also be formed on the dummy gate 11, which is not limited by the present invention.

[0041] To prepare for subsequent shallow doping implantation processes at the source and drain ends (not shown), a first sidewall 14 needs to be formed on the sidewalls of the dummy gate 11. The first sidewall 14 covers the sidewalls of the dummy gate 11, as well as the sidewalls and top of the mask layer, and the exposed surface of the substrate 10. The material of the first sidewall 14 comprises SICN (silicon carbonitride).

[0042] In step S2, please refer to Figure 3 and Figure 4 As shown, the first sidewall 14 of the oxidized portion thickness forms a sidewall oxide layer 15, and the sidewall oxide layer 15 is removed.

[0043] After the first sidewall 14 is formed, photolithography is performed on the remaining areas of the device. To prevent organic materials such as photoresist from directly contacting the first sidewall 14, an oxidation process is required. This oxidation process oxidizes a portion of the thickness of the first sidewall 14 to form a sidewall oxide layer 15, forming a structure as shown below. Figure 3 The structure shown.

[0044] Next, as Figure 4 As shown, the sidewall oxide layer 15 is removed, thus reducing the overall size of the dummy gate 11 and the first sidewall 14 (overall size refers to the area within the first sidewall). Figure 4 The total width in the horizontal direction is considered. Therefore, the size of the groove formed after removing the dummy gate 11 and the first sidewall 14 will also decrease. Although the size of the groove will increase due to over-etching during the removal of the dummy gate 11 and the first sidewall 14, the two cancel each other out, allowing the groove to reach the target size. Therefore, the thickness of the oxidized first sidewall 14 can be determined by the amount of over-etching. If the amount of over-etching is large, the thickness of the oxidized first sidewall 14 can be increased, further reducing the total size of the dummy gate 11 and the remaining first sidewall 14. If the amount of over-etching is small, the thickness of the oxidized first sidewall 14 can be reduced, increasing the total size of the dummy gate 11 and the remaining first sidewall 14.

[0045] In one embodiment of the present invention, the size of the dummy gate 11 is 19 nm, the size of the first sidewall 14 is 2 nm, and the total size of the dummy gate 11 and the first sidewall 14 is 23 nm. Subsequently, during the etching process to form a groove between the dummy gate 11 and the first sidewall 14, the over-etching amount is 1 nm, meaning the groove size expands by 2 nm to both sides, reaching a groove size of 25 nm, while the ideal size is 23 nm. Therefore, in this step, the first sidewall 14 is oxidized by 1 nm, meaning the thickness of the oxidized first sidewall 14 is half the thickness of the first sidewall 14. After removing the sidewall oxide layer 15, the total size of the dummy gate 11 and the remaining first sidewall 14 is reduced by 2 nm to 21 nm. It is understood that the dimensions referred to in this embodiment are... Figure 4 The width in the horizontal direction is only a standard size listed in this embodiment; the actual size can fluctuate within a certain range around this standard size, depending on the actual process conditions. Of course, the dimensions of the dummy gate 11, the first sidewall 14, and the oxidized first sidewall 14 are not limited to this.

[0046] In this embodiment, a cleaning process can be used to remove the sidewall oxide layer 15. The cleaning solution used in the cleaning process includes HF (hydrofluoric acid), but is not limited to this.

[0047] In step S3, as Figure 5 As shown, a second sidewall 16 is formed, which covers the remaining first sidewall 14.

[0048] The second sidewall 16 is a low-k dielectric layer. The material of the second sidewall 16 includes SiOCN (silicon oxycarbonate). The second sidewall 16 can be formed using plasma-enhanced atomic layer deposition (PEALD). The second sidewall 16 covers the first sidewall 14, that is, it covers the sidewalls and top of the dummy gate 11, the nitride layer 12, and the oxide layer 13, and also covers the exposed surface of the substrate 10. The thickness of the second sidewall 16 can be 7 nm.

[0049] In step S4, as Figure 6 As shown, an interlayer dielectric layer 17 is formed, which fills the gap between adjacent dummy gates 11.

[0050] In this embodiment, the interlayer dielectric layer 17 fills the gap between adjacent dummy gates 11 and also fills the gap between the mask layers; that is, the interlayer dielectric layer 17 fills as shown in the figure. Figure 5 The gap shown is then planarized between the interlayer dielectric layer 17 and the mask layer until the dummy gate 11 is exposed, forming a gap as shown. Figure 6The structure shown can be planarized, for example, by using chemical mechanical polishing to process the interlayer dielectric layer 17 and the mask layer.

[0051] The interlayer dielectric layer 17 is made of silicon oxide, and may include, for example, doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric layer 17 may be deposited using a PECVD process or other suitable deposition techniques. In one embodiment, the interlayer dielectric layer 17 is formed by flow chemical vapor deposition (FCVD). The FCVD process includes depositing a flowable material (such as a liquid compound) on the substrate 10 to fill the gap between the dummy gate 11 (having a first sidewall 14 and a second sidewall 16 located on its sidewalls) and converting the flowable material into a solid material using a suitable technique (such as annealing in one example). Of course, in other embodiments, the interlayer dielectric layer 17 may also be formed using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0052] In step S6, as Figure 7 As shown, the dummy gate 11 is removed to form a groove 18 with the first sidewall 14.

[0053] The dummy gate 11 and the first sidewall 14 can be removed by an etching process, which is selectively tailored to remove the dummy gate 11 and the first sidewall 14 while substantially preserving the second sidewall 16. The etching process can include suitable wet etching, dry (plasma) etching, and / or other processes. For example, a dry etching process can use chlorine-containing gases, fluorine-containing gases, other etching gases, or combinations thereof. Wet etching solutions can include NH4OH, HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof.

[0054] During this etching process, some loss is inevitable to the second sidewall 16, for example, a loss of 1 nm on one side. After forming the sidewall oxide layer 15 by oxidizing a portion of the first sidewall 14, removing the sidewall oxide layer 15 reduces the thickness of the dummy gate 11 and the remaining first sidewall 14 by 2 nm. The total size of the dummy gate 11 and the remaining first sidewall 14 is 21 nm. This step causes a 2 nm over-etch, resulting in a final groove 18 with a size of 23 nm, which is exactly equal to the total size of the dummy gate 11 and the first sidewall 14 in step S1. That is, the size of the groove 18 is not increased, thus achieving the process objective.

[0055] In the method for fabricating a FinFET device provided by this invention, after forming the first sidewall 14, a sidewall oxide layer 15 is formed by oxidizing a portion of the thickness of the first sidewall 14. The sidewall oxide layer 15 is then removed, thereby reducing the overall size of the dummy gate 11 and the first sidewall 14. During the removal of the dummy gate 11 and the first sidewall 14, although over-etching of the second sidewall 16 may increase the size of the recess 18, the reduction in the overall size of the dummy gate 11 and the first sidewall 14 reduces the size of the recess 18. This ensures that the final size of the recess 18 meets the process target, thus improving device performance. Furthermore, compared to existing technologies, the size of the dummy gate 11 is not reduced, and the aspect ratio remains unchanged during the removal of the dummy gate 11, thus increasing the process window without increasing process difficulty.

[0056] Accordingly, the present invention also provides a FinFET device, fabricated using the FinFET device fabrication method described above. Please refer to... Figure 7 As shown, the FinFET device includes:

[0057] Substrate 10, and multiple phase-spaced interlayer dielectric layers 17 located on substrate 10;

[0058] The second sidewall 16 covers the sidewall and bottom of the interlayer medium layer 17;

[0059] The first sidewall 14 is located at the bottom of the interlayer dielectric layer 17 and between the substrate 10 and the second sidewall 16;

[0060] The groove 18 is located between adjacent interlayer dielectric layers 17.

[0061] The FinFET device fabricated using the method described above has a recess 18 with dimensions (i.e., in...) Figure 7The cross-sectional width in the horizontal direction can meet the process target, and the size of the metal gate subsequently formed in the groove 18 can also meet the process target, thereby improving the performance of the final device.

[0062] In summary, the FinFET device and its fabrication method provided by this invention form a sidewall oxide layer by oxidizing a portion of the first sidewall thickness, and then removing the sidewall oxide layer, thereby reducing the overall size of the dummy gate and the first sidewall. Although over-etching of the second sidewall during the removal of the dummy gate and the first sidewall can increase the size of the groove, the reduction in the overall size of the dummy gate and the first sidewall results in a smaller groove size. This ensures that the final groove size meets the process target, thus improving device performance. Furthermore, compared to existing technologies, the size of the dummy gate is not reduced, and the aspect ratio remains unchanged during dummy gate removal, thus increasing the process window without increasing process difficulty.

[0063] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a FinFET device, characterized in that, Includes the following steps: A substrate is provided on which a plurality of dummy gates and a first sidewall covering the sidewalls of the dummy gates are formed; The first sidewall of a certain thickness is oxidized to form a sidewall oxide layer, and the sidewall oxide layer is removed, thereby reducing the overall size of the dummy gate and the first sidewall. A second side wall is formed, which covers the remaining first side wall; An interlayer dielectric layer is formed, which fills the gap between adjacent dummy gates; as well as The dummy gate and the first sidewall are removed to form a groove; during the removal of the dummy gate and the first sidewall, the second sidewall is over-etched, and the thickness of the oxidized first sidewall is determined by the amount of over-etching so that the groove reaches the target size.

2. The method for fabricating a FinFET device as described in claim 1, characterized in that, A mask layer is formed on the dummy gate, and the first sidewall covers the sidewall and top of the mask layer and the surface of the substrate.

3. The method for fabricating a FinFET device as described in claim 2, characterized in that, After forming the interlayer dielectric layer and before removing the dummy gate and the first sidewall, the fabrication method further includes: planarizing the interlayer dielectric layer and the mask layer to expose the dummy gate.

4. The method for fabricating a FinFET device as described in claim 2, characterized in that, The dummy gate is made of polysilicon, and the mask layer comprises a nitride layer and an oxide layer sequentially located on the dummy gate.

5. The method for fabricating a FinFET device as described in claim 1, characterized in that, The thickness of the oxidized first sidewall is half the thickness of the first sidewall.

6. The method for fabricating a FinFET device as described in claim 1, characterized in that, The first sidewall is made of SiCN, the second sidewall is made of SiOCN, and the interlayer dielectric layer is made of silicon oxide.

7. The method for fabricating a FinFET device as described in claim 1, characterized in that, The oxide layer on the sidewall is removed using a cleaning process.

8. The method for fabricating a FinFET device as described in claim 7, characterized in that, The cleaning solution used in the cleaning process contains HF.

9. A FinFET device, characterized in that, It is manufactured using the method for manufacturing a FinFET device as described in any one of claims 1 to 8.

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