Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and a method for fabricating the same. The method includes: providing a substrate containing a PMOS device region and / or an NMOS device region, wherein alternating layers of silicon-germanium and silicon are formed on the substrate; removing the silicon-germanium layers; ion-doping the surface of the silicon layers, wherein the doping concentration of the silicon layers in device regions with different threshold voltage requirements is different, and the silicon layers in the PMOS device regions are N-type doped and the silicon layers in the NMOS device regions are P-type doped; forming a silicon capping layer on the surface of the silicon layers; and performing heat treatment to give the silicon layers in device regions with different threshold voltage requirements different concentrations of doped ions. This invention achieves threshold voltage regulation through differences in doping concentration, thereby forming a multi-threshold voltage device. The method is simple and, compared with existing technologies, is not affected by the distance between adjacent silicon layers, thus improving device performance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the development of integrated circuit manufacturing process technology nodes, higher requirements have been placed on the gate control capability, size and power consumption of transistors. Compared with FinFET (Fin Field-Effect Transistor), GAA (Gate All Around) can achieve better transistor performance by wrapping the channel on all four sides with a metal gate (MG).

[0003] GAA devices control the turn-on of the device by controlling the metal gate voltage to reach a threshold voltage (Vt). As devices have evolved, GAA devices with multiple threshold voltages have found wider applications than those with single threshold voltages.

[0004] The current industry standard for constructing multi-threshold voltage (GTA) devices involves adjusting the thickness of the titanium nitride (TiN) layer in different devices to achieve varying threshold voltages. The deposition method for different TiN layer thicknesses involves growing a uniform TiN layer, defining different regions using a photomask, and then removing portions of the TiN layer using wet etching. By combining different combinations of TiN layer growth and removal, varying TiN layer thicknesses can be achieved in different regions, thereby constructing multi-threshold voltage GAA devices.

[0005] However, the technical challenges currently encountered by this method are: the distance between adjacent channels is very close, making it difficult to ensure the thickness uniformity when growing titanium nitride layers multiple times; and during wet removal of titanium nitride layers, due to surface tension, the etching liquid cannot flow into the small space between the channels, resulting in the titanium nitride layer not being etched away, thus affecting the thickness of the titanium nitride layer and consequently affecting the threshold voltage of the device. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device and its fabrication method, which achieves control of the threshold voltage by varying the doping concentration of the silicon layer, thereby obtaining a multi-threshold voltage device and improving the device's performance.

[0007] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0008] A substrate is provided, the substrate including a PMOS device region and / or an NMOS device region, and alternating layers of silicon-germanium and silicon are formed on the substrate;

[0009] Remove the silicon-germanium layer;

[0010] The silicon layer surface is ion-doped, and the doping concentration of the silicon layer in the device region with different threshold voltage requirements is different. In addition, the silicon layer in the PMOS device region is N-type doped and the silicon layer in the NMOS device region is P-type doped.

[0011] A silicon capping layer is formed on the surface of the silicon layer; and

[0012] Heat treatment is performed to give the silicon layer different concentrations of doped ions in device regions with different threshold voltage requirements.

[0013] Optionally, methods for ion doping the silicon layer surface to achieve different doping concentrations in device regions with different threshold voltage requirements include:

[0014] A patterned mask layer is formed, which exposes the silicon layers within the same device region that require the same threshold voltage, while masking the remaining silicon layers.

[0015] Using the patterned mask layer as a mask, the exposed silicon layer is ion-doped;

[0016] Remove the patterned mask layer; and

[0017] Repeat the above steps sequentially until the doping of the silicon layer in all device regions is complete.

[0018] Optionally, the silicon layer can be doped using plasma immersion ion implantation technology.

[0019] Optionally, the material of the patterned mask layer may include photoresist.

[0020] Optionally, the silicon capping layer is formed using an epitaxial process to prevent dopant ions from diffusing out of the silicon layer.

[0021] Optionally, methods for performing heat treatment to give the silicon layer different concentrations of doped ions in device regions with different threshold voltage requirements include:

[0022] A first heat treatment is performed to allow dopant ions on the surface of the silicon layer to diffuse into the silicon layer; and

[0023] A second heat treatment is performed to activate the dopant ions.

[0024] Optionally, the first heat treatment lasts longer than the second heat treatment, and the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

[0025] Optionally, after performing heat treatment to give the silicon layer in device regions with different threshold voltage requirements different concentrations of doped ions, the fabrication method further includes:

[0026] A dielectric layer is formed, wherein the dielectric layer covers the silicon layer;

[0027] A titanium nitride layer is formed, wherein the titanium nitride layer covers the dielectric layer; and

[0028] A metal gate is formed, wherein the metal gate is coated with the titanium nitride layer.

[0029] Optionally, the titanium nitride layers on different silicon layers may have the same thickness.

[0030] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0031] In the semiconductor device and its fabrication method provided by this invention, after removing the silicon-germanium layer, the surface of the silicon layer is ion-doped. The doping concentration of the silicon layer in the device regions with different threshold voltage requirements is different, and the silicon layer in the PMOS device region is N-type doped, while the silicon layer in the NMOS device region is P-type doped. Then, a silicon capping layer is formed on the surface of the silicon layer. Next, heat treatment is performed to make the silicon layer in the device regions with different threshold voltage requirements have different concentrations of doped ions. The threshold voltage is controlled by the difference in doping concentration, thereby forming a multi-threshold voltage device. The method is simple and, compared with the prior art, is not affected by the distance between adjacent silicon layers, thereby improving the performance of the device. Attached Figure Description

[0032] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0033] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0034] Figures 2 to 6 This is a schematic diagram of the steps in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0035] Figure label:

[0036] 10-Substrate; 11-Silicon-germanium layer; 12-Silicon layer; 13-Spacer; 14-Epipolar layer; 15-Ion-doped layer; 16-Silicon capping layer. Detailed Implementation

[0037] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0038] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0039] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0040] like Figure 1 As shown, the method for fabricating the semiconductor device includes the following steps:

[0041] S1: A substrate is provided, the substrate including a PMOS device region and / or an NMOS device region, and alternating layers of silicon-germanium and silicon are formed on the substrate;

[0042] S2: Remove the silicon-germanium layer;

[0043] S3: The silicon layer surface is ion-doped, and the doping concentration of the silicon layer in the device region with different threshold voltage requirements is different. The silicon layer in the PMOS device region is N-type doped, and the silicon layer in the NMOS device region is P-type doped.

[0044] S4: Form a silicon capping layer on the surface of the silicon layer;

[0045] S5: Perform heat treatment to give the silicon layer in the device region with different threshold voltage requirements different concentrations of doped ions.

[0046] Figures 2 to 6 This is a schematic diagram illustrating the structural steps of a semiconductor device fabrication method according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2-6A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.

[0047] In step S1, please refer to Figure 2 As shown, a substrate 10 is provided, the substrate 10 including a PMOS device region and / or an NMOS device region, and alternating layers of silicon-germanium layer 11 and silicon layer 12 are formed on the substrate.

[0048] The substrate 10 can be made of silicon, germanium, a silicon-germanium layer, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is preferably made of silicon. The substrate 10 includes a PMOS device region and / or an NMOS device region, on which PMOS devices are subsequently formed, and NMOS devices are subsequently formed. The substrate 10 may contain only a PMOS device region, only an NMOS device region, or both a PMOS device region and an NMOS device region. For example, the substrate 10 may contain multiple PMOS device regions and multiple NMOS device regions. Figure 2 Only a portion of a device area is shown in the image.

[0049] Alternating layers of silicon-germanium (SiGe) 11 and silicon 12 are formed on the substrate 10 of both the PMOS device region and the NMOS device region. This embodiment shows only three layers of silicon-germanium 11 and three layers of silicon 12; in other embodiments, there may be two, four, or more layers, which is not limited by this invention. Multiple stacked structures can be formed on the substrate 10, referring to alternating layers of silicon-germanium 11 and silicon 12. For example, two stacked structures can be formed, and the number of stacked structures and the number of layers can be determined according to actual needs. One or more of the stacked structures can be formed in the PMOS device region, and one or more of the stacked structures can also be formed in the NMOS device region.

[0050] In this embodiment, the silicon-germanium layer 11 and the silicon layer 12 can be epitaxially formed. The silicon layer 12 subsequently serves as a channel layer, and the thickness of each silicon layer 12 can be the same or different. The silicon-germanium layer 11 is subsequently removed as a sacrificial layer, and the thickness of each silicon-germanium layer 12 can be the same or different. The thickness of the silicon-germanium layer 11 and the silicon layer 12 can be the same, for example, the thickness of each silicon-germanium layer 11 and the thickness of each silicon layer 12 are both 3 nm, or they can be different, for example, the thickness of each silicon-germanium layer 11 is 5 nm and the thickness of each silicon layer 12 is 3 nm, but it is not limited to this.

[0051] Spacers 13 are formed on both sides of the silicon-germanium layer 11, and an epitaxial layer 14 is formed on the substrate 10, the epitaxial layer 14 being located on both sides of the silicon-germanium layer 11 and the silicon layer 12.

[0052] For example, alternating layers of silicon-germanium layer 11 and silicon layer 12 are sequentially formed on substrate 10. Then, a portion of the silicon-germanium layer 11 is laterally etched away to form grooves on both sides of the silicon-germanium layer 11, and an insulating material is filled into the grooves to form spacers 13. Finally, an epitaxial layer 14 is formed on both sides of the silicon-germanium layer 11 and silicon layer 12.

[0053] The spacer 13 may be made of an oxide or nitride, such as silicon oxide or silicon nitride. The spacer 13 may be fabricated by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or a combination thereof, or by other known methods. The spacer 13 serves as physical isolation between the subsequently formed source / drain electrode and the silicon-germanium layer 11.

[0054] In step S2, please refer to Figure 3 As shown, the silicon-germanium layer 11 is removed.

[0055] Specifically, taking advantage of the principle that the etching rate of silicon-germanium is much higher than that of silicon, the silicon-germanium layer 11 is selectively etched while the silicon layer 12 is retained. For example, the silicon-germanium layer 11 can be removed by wet etching or dry etching.

[0056] In this embodiment, the silicon-germanium layer 11 can be removed by wet etching. The etching solution used in the wet etching process has a high etching rate for the silicon-germanium layer 11 and a low etching rate for the silicon layer 12. Here, "high etching rate" and "low etching rate" are relative terms, so that the silicon-germanium layer 11 is etched away, while the silicon layer 12 is not etched or is only slightly etched. The etching solution may contain hydrogen peroxide (H2O2), hydrochloric acid (HCl), citric acid (C6H8O7), or ammonium hydroxide (NH4OH), or other etching solutions known to those skilled in the art.

[0057] In another embodiment of the present invention, dry etching can also be used to remove part of the silicon-germanium layer 11. For example, reactive ion etching (RIE) can be used to remove part of the silicon-germanium layer 11, where the etching gas has a high etching rate on the silicon-germanium layer 11 and a low etching rate on the silicon layer 12. The etching gas may contain hydrogen chloride (HCl), silicon chloride (SiCl4), sulfur hexafluoride (SF6), boron trichloride (BCl3), or chlorine (Cl2), but is not limited thereto, and may also be other etching gases known to those skilled in the art.

[0058] In step S3, please refer to Figure 4 As shown, the silicon layer 12 is ion-doped on its surface. The doping concentration of the silicon layer 12 in the device regions with different threshold voltage requirements is different. The silicon layer 12 in the PMOS device region is N-type doped, and the silicon layer 12 in the NMOS device region is P-type doped.

[0059] For example, plasma immersion ion implantation can be used to dope the silicon layer 12, forming an ion-doped layer 15 on the surface of the silicon layer 12. Different concentrations of doping are applied to the silicon layer 12 in device regions with different threshold voltage requirements; that is, the threshold voltage is controlled by the difference in doping concentration. One doping concentration corresponds to one threshold voltage. For example, the higher the threshold voltage requirement, the higher the doping concentration of the silicon layer 12, but this is not limited to this. The silicon layer 12 in the PMOS device region is N-type doped, for example, with phosphorus ions, and the silicon layer 12 in the NMOS device region is P-type doped, for example, with boron ions, but this is not limited to this.

[0060] Because the types of ion doping performed in the PMOS device region and the NMOS device region are different, doping needs to be performed in stages. Furthermore, within the same device, the threshold voltage requirements for devices formed in different regions may differ, thus requiring staged doping as well. For example, when doping the silicon layer 12 in the PMOS device region, firstly, the silicon layer 12 is grouped according to the required threshold voltage, with silicon layers having the same threshold voltage forming a group. Then, a mask layer is formed, covering the substrate 10 and the stacked structure. The mask layer is then patterned to form a patterned mask layer. In this embodiment, the mask layer is preferably made of photoresist; that is, a photoresist layer is formed on the silicon layer 12, and the photoresist layer is exposed and developed to form a patterned photoresist layer, i.e., a patterned mask layer. The patterned mask layer exposes a set of silicon layers 12, that is, exposes the stacked structures that need to form the same threshold voltage within the same device region (in this embodiment, the PMOS device region), while blocking the other stacked structures, including the stacked structures within the NMOS device region.

[0061] Next, using the patterned mask layer as a mask, the exposed silicon layer 12 is ion-doped to form an ion-doped layer 15 on the surface of the silicon layer 12. The doping type of the ion doping is opposite to the doping type of the device within the PMOS device region, that is, the silicon layer 12 within the PMOS device region is N-type doped. Finally, the patterned mask layer is removed.

[0062] The above steps (forming a mask layer, performing ion doping, and removing the patterned mask layer) are then repeated sequentially until all silicon layers 12 within the PMOS device region are doped, with a different doping concentration each time. That is, by repeating the above steps to perform ion doping on each group of silicon layers 12, and with a different doping concentration each time, ion-doped layers 15 with different doping concentrations are formed on the surface of different groups of silicon layers 12.

[0063] Next, the same method can be used to dope the silicon layer 12 in the NMOS device region, thereby forming ion-doped layers 15 with different doping concentrations on the surface of the silicon layers 12 in different groups.

[0064] In step S4, please refer to Figure 5 As shown, a silicon capping layer 16 is formed on the surface of the silicon layer 12. That is, the silicon capping layer 16 covers the ion-doped layer 15.

[0065] Specifically, the silicon capping layer 16 can be formed using an epitaxial process. The silicon capping layer 16 covers the surface of the ion-doped layer 15 to prevent doped ions in the ion-doped layer 15 from diffusing outward during subsequent heat treatment. The material of the silicon capping layer 16 includes monocrystalline silicon.

[0066] In step S5, please refer to Figure 6 As shown, heat treatment is performed to give the silicon layer 12 in device regions with different threshold voltage requirements different concentrations of doped ions.

[0067] Specifically, firstly, a first heat treatment is performed to allow the doped ions on the surface of the silicon layer 12 to diffuse into the silicon layer 12, thereby allowing the doped ions in the ion-doped layer 15 to diffuse into the silicon layer 12, while the silicon capping layer 16 can prevent the doped ions from diffusing out of the silicon layer 12.

[0068] Next, a second heat treatment is performed to activate the dopant ions, thereby resulting in different concentrations of dopant ions in the silicon layer 12 within the device regions with different threshold voltage requirements. The duration of the first heat treatment is longer than that of the second heat treatment, and the temperature of the second heat treatment is higher than that of the first heat treatment. The first heat treatment can be performed in a furnace tube, and the second heat treatment can be, for example, RTP (rapid thermal processing).

[0069] It is understood that in this embodiment, please refer to Figure 6As shown, due to the presence of the spacers 13, not all areas of the silicon layer 12 are doped. The silicon layers 12 between adjacent spacers 13 are not ion-doped. Although lateral diffusion of doped ions occurs during heat treatment, the diffusion is limited, and the silicon layers 12 between adjacent spacers 13 are not completely doped. Of course, in other embodiments, the silicon layers 12 between adjacent spacers 13 may be completely doped, and this invention does not limit this.

[0070] This invention uses ion implantation to introduce different concentrations of doped ions into the silicon layer 12 within device regions with different threshold voltage requirements. By controlling the threshold voltage through the difference in doping concentration, a multi-threshold voltage device can be formed.

[0071] Next, the fabrication method further includes forming an interface layer (IL) that covers the silicon layer 12. The interface layer may be made of silicon oxide, silicon nitride, or silicon oxynitride, or other suitable materials. The interface layer may be fabricated using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof.

[0072] Next, the fabrication method further includes: forming a dielectric layer, wherein the dielectric layer covers the interface layer. The dielectric layer is preferably an HK dielectric layer, and the material of the HK dielectric layer may include tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2), etc., preferably hafnium oxide. The HK dielectric layer can be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. In some embodiments, ALD may be preferred.

[0073] Next, the fabrication method further includes forming a titanium nitride layer, which covers the dielectric layer. Since the threshold voltage is controlled by the different doping concentrations of the silicon layers 12, the thickness of the titanium nitride layers on different silicon layers 12 can be the same, eliminating the need for etching the titanium nitride layers. Therefore, compared with the prior art, it is not affected by the distance between adjacent silicon layers 12, nor by the growth and removal of the titanium nitride layers, thereby improving the device performance.

[0074] The fabrication method further includes forming a metal gate, wherein the metal gate is coated with the titanium nitride layer. The gate is made of aluminum or tungsten and can be formed using processes such as chemical vapor deposition or physical vapor deposition.

[0075] In the semiconductor device fabrication method provided by this invention, after removing the silicon-germanium layer 11, the surface of the silicon layer 12 is ion-doped. The doping concentration of the silicon layer 12 in device regions with different threshold voltage requirements is different. The silicon layer in the PMOS device region is N-type doped, and the silicon layer in the NMOS device region is P-type doped. Then, a silicon capping layer 16 is formed on the surface of the silicon layer 12. Next, heat treatment is performed to give the silicon layer 12 in device regions with different threshold voltage requirements a concentration of doped ions. The threshold voltage is controlled by the difference in doping concentration, thereby forming a multi-threshold voltage device. The method is simple and, compared with the prior art, is not affected by the distance between adjacent silicon layers 12, thereby improving the performance of the device.

[0076] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0077] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a PMOS device region and / or an NMOS device region, and alternating layers of silicon-germanium and silicon are formed on the substrate; Remove the silicon-germanium layer; The silicon layer surface is ion-doped, and the doping concentration of the silicon layer in the device region with different threshold voltage requirements is different. In addition, the silicon layer in the PMOS device region is N-type doped and the silicon layer in the NMOS device region is P-type doped. A silicon capping layer is formed on the surface of the silicon layer; as well as Heat treatment is performed to give the silicon layer different concentrations of doped ions in device regions with different threshold voltage requirements.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Methods for ion doping the surface of the silicon layer to achieve different doping concentrations in device regions with different threshold voltage requirements include: A patterned mask layer is formed, which exposes the silicon layers within the same device region that require the same threshold voltage, while masking the remaining silicon layers. Using the patterned mask layer as a mask, the exposed silicon layer is ion-doped; Remove the patterned mask layer; and Repeat the above steps sequentially until the doping of the silicon layer in all device regions is complete.

3. The method for fabricating a semiconductor device as described in claim 1 or 2, characterized in that, The silicon layer was doped using plasma immersion ion implantation technology.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The patterned mask layer is made of photoresist.

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The silicon capping layer is formed using an epitaxial process to prevent dopant ions from diffusing out of the silicon layer.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, Methods for performing heat treatment to give the silicon layer different concentrations of doped ions in device regions with different threshold voltage requirements include: A first heat treatment is performed to allow dopant ions on the surface of the silicon layer to diffuse into the silicon layer; and A second heat treatment is performed to activate the dopant ions.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The first heat treatment lasts longer than the second heat treatment, and the temperature of the second heat treatment is higher than the temperature of the first heat treatment.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, After performing heat treatment to give the silicon layer in device regions with different threshold voltage requirements different concentrations of doped ions, the fabrication method further includes: A dielectric layer is formed, wherein the dielectric layer covers the silicon layer; A titanium nitride layer is formed, wherein the titanium nitride layer covers the dielectric layer; and A metal gate is formed, wherein the metal gate is coated with the titanium nitride layer.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, The titanium nitride layers on the different silicon layers have the same thickness.

10. A semiconductor device, characterized in that, It is manufactured using the method for manufacturing a semiconductor device as described in any one of claims 1 to 9.

Images