Structure and method for passivation layer breakage detection in semiconductor structures

Abstract

The application provides a structure and a method for detecting breakage of a passivation layer in a semiconductor structure. The detection structure comprises at least one detection MOM capacitor structure and a reference MOM capacitor structure located at the periphery of the detection MOM capacitor structure. The detection MOM capacitor structure comprises at least one detection interdigital group, a plurality of detection metals and a detection passivation unit. The detection metals are located on both sides of the detection interdigital group in a first direction. The detection passivation unit is embedded in at least one of the detection interdigital group and the space between the detection interdigital group and the detection metals. The reference MOM capacitor structure comprises at least one reference interdigital group and a reference passivation unit. The reference passivation unit is embedded in at least one of the reference interdigital group. The structure is obtained synchronously in the manufacturing process of the top metal layer and the passivation layer of the conventional semiconductor structure. The structure is simple and does not increase additional mask processes and process costs. The method can effectively determine whether the passivation layer is broken by detecting the electrical parameters of the detection structure, thereby effectively improving the efficiency and convenience of defect detection.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor fabrication and defect detection technology, and relates to a structure and method for detecting passivation layer fracture in semiconductor structures. Background Technology

[0002] In the chip manufacturing process, after the functional devices are fabricated on the wafer, a metal interconnect layer for electrical lead-out or electrical connection is usually fabricated in the dielectric layer above the wafer. The metal interconnect layer may include multiple interconnect metals and conductive pillars that realize the connection of the multiple interconnect metals. After the metal interconnect layer is fabricated, a passivation layer needs to be fabricated on the upper surface of the wafer to achieve insulation protection. Since the top metal layer usually applies stress to the passivation layer embedded in the gap of the top metal layer, the passivation layer at the weak point may break.

[0003] Please see Figure 1 The diagram shows a partial cross-sectional view of a typical semiconductor structure. The top of the wafer typically has a top metal layer 101 and a passivation layer 102 covering the top metal layer 101. The passivation layer 102 usually needs to withstand the stress from the top metal layer 101 and is prone to fracture, especially when the thickness of the top metal layer 101 increases, at specific weak points (such as...). Figure 1 The passivation layer 102 (shown in dashed box I) is more prone to fracture. This fracture defect can significantly impact chip packaging and its reliability verification. Currently, the main method for monitoring whether the passivation layer has fractured relies on product yield engineers scanning the product's passivation layer to obtain SEM images of the fracture location (e.g., ...). Figure 2 and Figure 3 As shown, Figure 2 The image shown is a top-view SEM image of the location where the passivation layer fractures in a semiconductor structure. Figure 3 for Figure 2 Longitudinal cross-sectional structural diagram, Figure 3 The area shown in the dashed box II corresponds to Figure 1 The method of judging and analyzing failures in the area shown in the dashed box I requires additional detection steps and dedicated defect detection equipment. The detection steps are cumbersome and time-consuming, resulting in limited detection efficiency.

[0004] Therefore, how to provide a structure and method for detecting passivation layer fracture in semiconductor structures, so as to achieve efficient and convenient detection of whether the passivation layer is fractured, has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a structure and method for detecting passivation layer fracture in semiconductor structures, which solves the problem that the detection steps are cumbersome and the detection efficiency is limited when using special defect detection equipment such as scanning electron microscopes to detect whether the passivation layer is fractured.

[0007] To achieve the above and other related objectives, the present invention provides a structure for detecting passivation layer fracture in a semiconductor structure, comprising:

[0008] At least one detection MOM capacitor structure is provided, the detection MOM capacitor structure includes at least one detection interdigital group, a plurality of detection metals and detection passivation units, the detection metals are located on both sides of the detection interdigital group in a first direction, the detection passivation units are embedded at least in the detection interdigital group and in the gap between the detection interdigital group and the detection metals, the detection interdigital group includes at least one first detection interdigit and at least one second detection interdigit extending in a second direction, the first detection interdigit and the second detection interdigit are spaced apart and staggered in the first direction;

[0009] At least one reference MOM capacitor structure is located on the periphery of the detection MOM capacitor structure. The reference MOM capacitor structure includes at least one reference interdigital group and a reference passivation unit. The reference passivation unit is at least embedded in the reference interdigital group. The reference interdigital group includes at least one first reference interdigit and at least one second reference interdigit extending in a second direction. The first reference interdigit and the second reference interdigit are spaced apart and staggered in the first direction.

[0010] Optionally, there are multiple first detection forks and multiple second detection forks, with the multiple first detection forks and multiple second detection forks spaced apart and arranged alternately in a first direction. The detection fork group also includes a first detection busbar and a second detection busbar extending in the first direction and arranged opposite to each other in the second direction. The multiple first detection forks are all connected to the first detection busbar, and the multiple second detection forks are all connected to the second detection busbar.

[0011] Optionally, the length of the first detection fork is the same as the length of the second detection fork, the width of the first detection fork is the same as the width of the second detection fork, and the plurality of the first detection forks and the plurality of the second detection forks are arranged at equal intervals.

[0012] Optionally, the width and length of the detected metal are both greater than the width of the first detection fork and the width of the second detection fork.

[0013] Optionally, the length of the detected metal is greater than or equal to 11 times the width of the first detection interdigitator, and the length of the detected metal is greater than or equal to 11 times the width of the second detection interdigitator.

[0014] Optionally, the detection MOM capacitor structure includes multiple detection interdigital groups, which are spaced apart in a first direction; the reference MOM capacitor structure includes multiple reference interdigital groups, which are spaced apart in a first direction.

[0015] Optionally, the reference MOM capacitor structure further includes at least one reference metal group, the reference metal group being located between two adjacent reference interdigital groups and the reference metal group comprising a plurality of reference metals spaced apart in a first direction.

[0016] The present invention also provides a method for detecting passivation layer fracture in a semiconductor structure, comprising the following steps:

[0017] Provide a semiconductor layer;

[0018] At least one detection MOM capacitor structure and at least one reference MOM capacitor structure are formed on the semiconductor layer. The reference MOM capacitor structure is located around the detection MOM capacitor structure. The detection MOM capacitor structure includes at least one detection interdigital group, a plurality of detection metals, and detection passivation units. The detection metals are located on both sides of the detection interdigital group in a first direction. The detection passivation units are embedded at least within the detection interdigital group and in the gap between the detection interdigital group and the detection metals. The detection interdigital group includes at least one first detection interdigit and at least one second detection interdigit extending in a second direction. The first detection interdigit and the second detection interdigit are spaced apart and staggered in the first direction. The reference MOM capacitor structure includes at least one reference interdigital group and a reference passivation unit. The reference passivation unit is embedded at least within the reference interdigit. The reference interdigital group includes at least one first reference interdigit and at least one second reference interdigit extending in a second direction. The first reference interdigit and the second reference interdigit are spaced apart and staggered in the first direction.

[0019] Collect the capacitance value of the detected MOM capacitor structure and the capacitance value of the reference MOM capacitor structure;

[0020] The capacitance value of the detected MOM capacitor structure is compared with the capacitance value of the reference MOM capacitor structure to detect passivation layer fracture.

[0021] Optionally, forming at least one detection MOM capacitor structure and at least one reference MOM capacitor structure on the semiconductor layer includes the following steps:

[0022] A metal layer is formed on top of the semiconductor layer and the metal layer is patterned to obtain a top metal layer. The top metal layer includes at least one separately disposed detection metal group, a detection metal and at least one reference interdigital group. In a first direction, the detection metal is located on both sides of the detection interdigital group.

[0023] A passivation layer is formed above the top metal layer. The passivation layer also fills the detection interdigitated group, the space between the detection interdigitated group and the detection metal, and the reference interdigitated group. The portion of the passivation layer filling the detection interdigitated group and the space between the detection interdigitated group and the detection metal serves as a detection passivation unit. The detection passivation unit, the detection interdigitated group, and the detection metal constitute a detection MOM capacitor structure. The portion of the passivation layer filling the reference interdigitated group serves as a reference passivation unit. The reference passivation unit and the reference interdigitated group constitute a reference MOM capacitor structure.

[0024] Optionally, the semiconductor layer includes a scribe line region, and the detection MOM capacitor structure and the reference MOM capacitor structure are both located within the scribe line region.

[0025] As described above, the structure for detecting passivation layer fracture in semiconductor structures of the present invention is fabricated simultaneously during the fabrication of the top metal layer and passivation layer in conventional semiconductor structures. The structure is simple and novel, requiring no additional masking process and incurring no additional processing costs. It is convenient to operate and highly practical for detecting whether the passivation layer has fractured. The method for detecting passivation layer fracture in semiconductor structures of the present invention fabricates a detection structure consisting of at least one detection MOM capacitor structure and at least one reference MOM capacitor structure during the fabrication of the top metal layer and passivation layer in conventional semiconductor fabrication. The detection of whether the passivation layer has fractured is achieved by collecting and comparing the capacitance values ​​of the detection MOM capacitor structure and the reference MOM capacitor structure. This detection method is convenient to operate; the electrical parameters of the detection structure can effectively determine whether the passivation layer has fractured, without requiring additional detection steps or dedicated defect detection equipment, effectively improving the efficiency of defect detection. Attached Figure Description

[0026] Figure 1 The diagram shows a partial cross-sectional view of a typical semiconductor structure.

[0027] Figure 2 The image shown is a top-view scanning electron microscope image of a passivation layer fracture in a typical semiconductor structure.

[0028] Figure 3 Displayed as Figure 2 The longitudinal cross-sectional structural diagram. Figure 4 The diagram shown is a top view of the MOM (Metal Oxide Mesh) detection structure in Embodiment 1 of the present invention for detecting passivation layer fracture in semiconductor structures.

[0029] Figure 5 The diagram shown is a top view of the reference MOM structure in Embodiment 1 of the structure for detecting passivation layer fracture in a semiconductor structure according to the present invention.

[0030] Figure 6 The diagram shown is a top view of the reference interdigitated structure in the structure for detecting passivation layer fracture in a semiconductor structure according to the present invention.

[0031] Figure 7 The diagram shown is a top view of the MOM (Metal Oxide Mesh) detection structure in Embodiment 2 of the present invention for detecting passivation layer fracture in semiconductor structures.

[0032] Figure 8 The diagram shown is a top view of the reference MOM structure in Embodiment 2 of the structure for detecting passivation layer fracture in a semiconductor structure according to the present invention.

[0033] Figure 9 The diagram shows the steps of the method for detecting passivation layer fracture in a semiconductor structure according to the present invention.

[0034] Figure 10 The diagram shown is a longitudinal cross-sectional view of the structure obtained after performing step S2 in the method for detecting passivation layer fracture in a semiconductor structure according to the present invention.

[0035] Explanation of reference numerals in the attached figures

[0036] 101 Top Metal Layer

[0037] 102 Passivation layer

[0038] 10 Semiconductor Layer

[0039] 20 Top metal layer

[0040] 21. Inspecting the structure of MOM capacitors

[0041] 211 Testing the interdigital group

[0042] 211a First detection interdigitated finger

[0043] 211b Second detection interdigitated finger

[0044] 211c First detection busbar

[0045] 211d Second Detection Busbar

[0046] 212 Metal Detection

[0047] 22 Refer to the MOM capacitor structure

[0048] 221 Refer to the interdigital group

[0049] 222 Reference Metals Group

[0050] 30 passivation layer

[0051] 31 Detection passivation unit

[0052] 32 Reference passivation unit

[0053] 40 pads Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] Please see Figures 4 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] Example 1

[0057] This embodiment provides a structure for detecting passivation layer fracture in semiconductor structures (hereinafter referred to as the "detection structure"). Please refer to [link to relevant documentation]. Figure 4 and Figure 5 The detection structure includes at least one detection MOM capacitor structure 21 and at least one reference MOM capacitor structure 22. The reference MOM capacitor structure 22 is located around the detection MOM capacitor structure 21. It should be noted that the semiconductor structure includes a top metal layer 20 and a passivation layer 30 (see reference). Figure 10The detection MOM capacitor structure 21 and the reference MOM capacitor structure 22 are formed during the fabrication of the top metal layer 20 and the passivation layer 30 to simulate the stress generated by the top metal layer 20 on the passivation layer 30 and to detect the possibility of the passivation layer 30 breaking. The distance between the reference MOM capacitor structure 22 and the detection MOM capacitor structure 21 is kept as small as possible to ensure that the stress environment of the two is extremely similar, thereby effectively simulating the actual situation.

[0058] For details, please refer to Figure 4 The diagram shows a top view of the MOM capacitor detection structure 21. The MOM capacitor detection structure 21 includes at least one detection interdigital group 211, multiple detection metals 212, and a detection passivation unit 31. The detection metals 212 are located in a first direction (…). Figure 4 (As shown in the X direction) Located on both sides of the detection interdigital group 211, the detection passivation unit 31 is at least embedded in the detection interdigital group 211 and the gap between the detection interdigital group 211 and the detection metal 212, the detection interdigital group 211 includes in the second direction ( Figure 4 At least one first detection fork 211a and at least one second detection fork 211b extending in the Y direction (as shown in the middle Y direction) are perpendicular to the first direction. The first detection fork 211a and the second detection fork 211b are spaced apart and staggered in the first direction ("staggered arrangement" means that the projection portions of the first detection fork 211a and the second detection fork 211b in the second direction overlap).

[0059] For details, please refer to Figure 5 The diagram shows a top view of a reference MOM capacitor structure 22. The reference MOM capacitor structure 22 includes at least one reference interdigital group 221 and a reference passivation unit 32. The reference passivation unit 32 is at least embedded in the reference interdigital group 221. The reference interdigital group 221 includes at least one first reference interdigit and at least one second reference interdigit extending in a second direction. The first reference interdigit and the second reference interdigit are spaced apart and staggered in the first direction.

[0060] Specifically, in this embodiment, by designing a detection MOM capacitor structure and a reference MOM capacitor structure, the passivation layer at the corresponding position can be effectively detected by comparing the capacitance values ​​of the two MOM capacitor structures. The specific technical principle is as follows: The detection MOM capacitor structure includes multiple first detection interdigitates and multiple second detection interdigitates arranged in parallel intervals (the first detection interdigitates and the second detection interdigitates serve as two electrode plates respectively). A portion of the detection passivation unit (serving as a dielectric) is also filled between adjacent first detection interdigitates and second detection interdigitates, thereby forming multiple capacitor structures (similar to the reference MOM capacitor structure). Under normal circumstances, based on the capacitance calculation formula C=εS / 4πkd, when the passivation layer material is silicon oxide (dielectric constant is about 4), the dielectric constant of air is about 1. When a break occurs, air will enter the gap of the silicon oxide layer at the break, which increases the distance d between adjacent detection interdigitates and decreases the dielectric constant ε, resulting in a decrease in the capacitance value output by the detection MOM capacitor structure. By comparing the capacitance value output by the detection MOM capacitor structure with the capacitance value output by the reference MOM capacitor structure, the passivation layer can be detected as broken.

[0061] As an example, the structure of the reference interdigital group 221 may be the same as or different from the structure of the detection interdigital group 211. Preferably, the structures of the two are consistent to improve detection accuracy. In this embodiment, the structure of the reference interdigital group is consistent with the structure of the detection interdigital group. The structure of the detection interdigital group will be described in detail below. The structure of the reference interdigital group is designed with reference to the structure of the detection interdigital group.

[0062] As an example, the first detection interdigitator 211a and the second detection interdigitator 211b are one or more, preferably multiple, which can reduce detection errors and ensure detection accuracy. In actual applications, they can be reasonably selected based on actual needs.

[0063] Furthermore, when there are multiple first detection interdigitates 211a and second detection interdigitates 211b, please refer to [reference needed]. Figure 6The diagram shows a top view of the detection interdigitation group. Multiple first detection interdigitates 211a and multiple second detection interdigitates 211b are spaced apart and alternately arranged in a first direction. The detection interdigitation group 211 also includes a first detection busbar 211c and a second detection busbar 211d extending in the first direction and arranged opposite to each other in the second direction. All first detection interdigitates 211a are connected to the first detection busbar 211c, and all second detection interdigitates 211b are connected to the second detection busbar 211d. That is, with multiple detection interdigitates, since the first detection interdigitates 211a and second detection interdigitates 211b are spaced apart and alternately arranged in the first direction, it is equivalent to the second detection interdigitates 211b being embedded in the gap between two adjacent first detection interdigitates 211a and maintaining a preset distance from the first detection busbar 211c. Simultaneously, the first detection interdigitates 211a are embedded in the gap between two adjacent second detection interdigitates 211b and maintain a preset distance from the second detection busbar 211d.

[0064] Correspondingly, the first reference fork and the second reference fork may include one or more, and in the case of multiple reference forks, the reference fork group 221 may also include a first reference bus bar and a second reference bus bar, which are arranged and connected in the same manner as described above (to avoid redundancy, the relevant content will not be repeated below).

[0065] As an example, the length of the first detected interdigitated finger 211a ( Figure 6 L1 shown in the figure and the second detection interdigit 211b ( Figure 6 The length of L2 shown is the same as that of the first detection interdigital finger 211a. Figure 6 The width of W1 shown in the figure is the same as the width of the second detection interdigitated finger 211b. Figure 6 As shown in W2), multiple first detection forks 211a and multiple second detection forks 211b are arranged at equal intervals (the distance between each first detection fork 211a and its adjacent second detection fork 211b is consistent). This arrangement improves consistency during manufacturing, and maintaining the same length means that the distance between the first detection fork and the second detection busbar is equal to the distance between the second detection fork and the first detection busbar. This reduces the overall area of ​​the monitoring structure, allowing for more flexible placement of the detection structure and enabling a larger number of detection forks within a limited area to improve detection accuracy. It should be noted that, to avoid ambiguity, "width" in this text refers to the dimension in the first direction, and "length" refers to the dimension in the second direction.

[0066] As an example, the width of the detected metal 212 ( Figure 4 W3 as described in the text) and length ( Figure 4The L3 mentioned above is greater than the width of the first detection interdigit 211a and the width of the second detection interdigit 211b, thus more closely resembling the stress exerted by a bulk metal on the passivation layer at a weak location in a real semiconductor structure in different directions, in order to simulate the situation where the passivation layer in a semiconductor structure breaks.

[0067] Furthermore, the length of the detection metal 212 is greater than or equal to 11 times the width of the first detection interdigitator 211a, and the length of the detection metal 212 is greater than or equal to 11 times the width of the second detection interdigitator 211b. Based on multiple experimental verifications, it has been found that only larger pieces of metal can cause stress concentration on the passivation layer located between slender metal strips, and further lead to the breakage of the passivation layer. Therefore, limiting the length of the detection metal to the above range is closer to the actual situation where the top layer metal causes stress on the surrounding passivation layer and causes it to break.

[0068] Furthermore, the length of the detection interdigitated finger group 211 (which, in the case of multiple detection interdigitated fingers, is the distance between the two opposite sides of the two detection busbars) is equal to or unequal to the length of the detection metal 212, preferably equal, so as to minimize the overall area of ​​the detection structure and achieve flexible position setting.

[0069] It is important to note that, in order to ensure successful fabrication, the width of the detection interdigitates and the spacing between adjacent detection interdigitates must meet the minimum requirements of chip design rules (below these dimensions may result in failure of the patterning process).

[0070] As an example, the number of the detection MOM capacitor structure 21 and the reference MOM capacitor structure 22 each includes one or more, and the number of the detection MOM capacitor structure 21 is greater than or equal to the number of the reference MOM capacitor structure 22. Preferably, the number of the detection MOM capacitor structure 21 is equal to the number of the reference MOM capacitor structure 22.

[0071] Furthermore, when there are multiple detection MOM capacitor structures 21 and reference MOM capacitor structures 22, a detection structure is formed by at least one detection MOM capacitor structure 21 and one reference MOM capacitor structure 22. When the area of ​​the placement location is limited, it is preferable that one detection structure includes one detection MOM capacitor structure and one reference MOM capacitor structure; while when the area of ​​the placement location is ample, it is preferable that one detection structure includes one reference MOM capacitor structure and multiple detection MOM capacitor structures, with the multiple detection MOM capacitor structures distributed at different locations of the reference MOM capacitor structure to improve detection accuracy.

[0072] As an example, the thickness of the detection interdigitated group 211, the detection metal 212 and the reference interdigitated group 221 is greater than 3 μm. Within the above thickness range, the phenomenon of passivation layer fracture is more obvious, and thus the fracture detection result is also more obvious.

[0073] As an example, the structure also includes a plurality of separately arranged pads 40, each of which is electrically connected to the first detection fork finger 211a and the second detection fork finger 211b to realize the electrical lead-out of the detection fork finger and thus output a capacitance signal. When a detection bus bar is provided, the pads 40 are connected to the detection bus bar to simplify the circuit structure.

[0074] The structure for detecting passivation layer fracture in semiconductor structures in this embodiment is fabricated simultaneously during the fabrication of the top metal layer and passivation layer in conventional semiconductor structures. The structure is simple and novel, does not require additional masking processes or increase process costs, and is convenient and practical for detecting whether the passivation layer has fractured.

[0075] Example 2

[0076] This embodiment provides a structure for detecting passivation layer fracture in a semiconductor structure. The difference from Embodiment 1 is that the detection MOM capacitor structure in this embodiment includes multiple detection interdigitated groups, and the reference MOM capacitor structure correspondingly includes multiple reference interdigitated groups, while the detection MOM capacitor structure in Embodiment 1 includes only one detection interdigitated group, and the reference MOM capacitor structure includes only one reference interdigitated group. Please refer to... Figure 7 and Figure 8 The detection structure includes at least one detection MOM capacitor structure 21 and at least one reference MOM capacitor structure 22. The reference MOM capacitor structure 22 is located around the detection MOM capacitor structure 21. It should be noted that due to different design habits of different chip design companies, the orientation within the chip is divided into vertical and horizontal. Therefore, Embodiment 1 uses the horizontal orientation as an example, and Embodiment 2 uses the vertical orientation as an example (i.e., Figure 4 / Figure 5 The X direction is the first direction. Figure 7 / Figure 8 The Y-direction is the first direction.

[0077] As an example, the detection MOM capacitor structure 21 includes a plurality of detection interdigital groups 211, which are spaced apart in a first direction; the reference MOM capacitor structure 22 includes a plurality of reference interdigital groups 221, which are spaced apart in a first direction.

[0078] Furthermore, such as Figure 8As shown, when the reference MOM capacitor structure 22 includes multiple reference interdigital groups 221, the reference MOM capacitor structure 22 also includes at least one reference metal group 222. The reference metal group 222 is located between two adjacent reference interdigital groups 221 and includes multiple reference metals spaced apart in a first direction. Similarly, when the reference metal group 222 is present, the reference passivation unit 32 is also embedded between the reference metal group 222 and the reference interdigital groups 221, and between each reference metal of the reference metal group 222. The reference metal group is set up to control variables and maintain the consistency between the reference MOM capacitor and the detection MOM capacitor structure as much as possible, so as to reduce the influence of other variables. For example, a detection metal is set between the two detection interdigital groups of the detection MOM capacitor structure, and the detection metal occupies a large area. If the reference MOM capacitor structure does not have the above-mentioned reference metal group, the reference MOM capacitor structure and the detection MOM capacitor structure will have a large difference in structure, which may affect the test results. Therefore, setting up a reference metal group composed of multiple reference metals can reduce the structural differences between the two capacitor structures, and the filling metal strip (i.e., the reference metal) is more friendly to the etching process.

[0079] Furthermore, the dimensions of the reference metal group 222 are consistent with the dimensions of the detection metal 212, for example, Figure 8 W4 equals Figure 7 Similarly, the width of each reference metal in the reference metal group 222 and the spacing between two adjacent reference metals are also greater than or equal to the minimum value of the chip design rules.

[0080] The structure for detecting passivation layer fracture in semiconductor structures in this embodiment further improves the accuracy of passivation layer fracture detection based on the detection structure described in Embodiment 1.

[0081] Example 3

[0082] This embodiment provides a method for detecting passivation layer fracture in semiconductor structures. Please refer to [link to relevant documentation]. Figure 9 The flowchart of this method is shown, including the following steps:

[0083] S1: Provides a semiconductor layer;

[0084] S2: Form at least one detection MOM capacitor structure and at least one reference MOM capacitor structure on the semiconductor layer. The reference MOM capacitor structure is located around the detection MOM capacitor structure. The detection MOM capacitor structure includes at least one detection interdigital group, a plurality of detection metals, and detection passivation units. The detection metals are located on both sides of the detection interdigital group in a first direction. The detection passivation units are embedded at least within the detection interdigital group and in the gap between the detection interdigital group and the detection metal. The detection interdigital group includes at least one first detection interdigit and at least one second detection interdigit extending in a second direction. The first detection interdigit and the second detection interdigit are spaced apart and staggered in the first direction. The reference MOM capacitor structure includes at least one reference interdigital group and a reference passivation unit. The reference passivation unit is embedded at least within the reference interdigit. The reference interdigital group includes at least one first reference interdigit and at least one second reference interdigit extending in a second direction. The first reference interdigit and the second reference interdigit are spaced apart and staggered in the first direction.

[0085] S3: Collect the capacitance value of the detected MOM capacitor structure and the capacitance value of the reference MOM capacitor structure;

[0086] S4: Compare the capacitance value of the detected MOM capacitor structure with the capacitance value of the reference MOM capacitor structure to detect passivation layer fracture.

[0087] Please see Figure 10 ( Figure 4 It can be seen as along Figure 10 (See the schematic diagram of the transverse cross-sectional structure at point A-A'). Steps S1 to S2 are executed to provide a semiconductor layer 10; at least one detection MOM capacitor structure 21 and at least one reference MOM capacitor structure 22 are formed on the semiconductor layer 10. The reference MOM capacitor structure 22 is located around the detection MOM capacitor structure 21. In other words, this embodiment actually provides a method for fabricating a structure for detecting passivation layer fracture in a semiconductor structure as described in either Embodiment 1 or Embodiment 2 (steps S1 and S2) and a detection method based on the above detection structure (steps S3 and S4).

[0088] As an example, forming at least one detection MOM capacitor structure 21 and at least one reference MOM capacitor structure 22 on the semiconductor layer 10 includes the following steps:

[0089] Forming a metal layer ( Figure 10(Not shown in the image) Above the semiconductor layer 10, the metal layer is patterned to obtain a top metal layer 20. The top metal layer 20 includes at least one separately disposed detection metal 212 group, detection metal 212 and at least one reference interdigital group 221. In a first direction, the detection metal 212 is located on both sides of the detection interdigital group 211.

[0090] A passivation layer 30 is formed above the top metal layer 20. The passivation layer 30 also fills the detection interdigitated group 211, the space between the detection interdigitated group 211 and the detection metal 212, and the reference interdigitated group. The portion of the passivation layer 30 filled into the detection interdigitated group 211 and the space between the detection interdigitated group 211 and the detection metal 212 serves as a detection passivation unit 31. The detection passivation unit 31, the detection interdigitated group 211, and the detection metal 212 constitute a detection MOM capacitor structure 21. The portion of the passivation layer 30 filled into the reference interdigitated group 221 serves as a reference passivation unit 32. The reference passivation unit 32 and the reference interdigitated group 221 constitute a reference MOM capacitor structure 22. (After the passivation layer is fabricated, the "semiconductor structure" in "Structure and Method for Passivation Layer Fracture Detection in Semiconductor Structures" is obtained.)

[0091] As an example, the semiconductor layer 10 also includes a plurality of functional devices ( Figure 10 (Not shown in the image), the top metal layer 20 also includes multiple top metal units ( Figure 10 (Not shown in the image), the top-layer metal unit is connected to the functional device, and there is a gap between at least two of the top-layer metal units. The passivation layer also fills the gap. The top-layer metal unit refers to the topmost metal structure of the metal interconnect structure used to realize the electrical lead-out or electrical connection of the functional device in the semiconductor structure. That is, in this embodiment, the detection MOM capacitor structure and the reference MOM capacitor structure are fabricated simultaneously during the fabrication of the top-layer metal layer and the passivation layer in the conventional fabrication process steps, without the need for an additional masking step, and without increasing the additional process cost.

[0092] As an example, the structure also includes a plurality of separately arranged pads 40, each of which is electrically connected to the first detection fork finger 211a and the second detection fork finger 211b to realize the electrical lead-out of the detection fork finger and thus output a capacitance signal. When a detection bus bar is provided, the pads 40 are connected to the detection bus bar to simplify the circuit structure.

[0093] As an example, the method for detecting passivation layer fracture by comparing the capacitance value of the detection MOM capacitor structure 21 and the capacitance value of the reference MOM capacitor structure 22 is as follows: when the capacitance value of the detection MOM capacitor structure 21 does not match the capacitance value of the reference MOM capacitor structure 22, it means that the passivation layer around the location of the detection MOM capacitor structure 21 and the reference MOM capacitor structure 22 has fractured or is highly likely to fracture; if the capacitance value of the detection MOM capacitor structure 21 matches the capacitance value of the reference MOM capacitor structure 22, it means that the passivation layer around the location of the detection MOM capacitor structure 21 and the reference MOM capacitor structure 22 has not fractured or is highly unlikely to fracture.

[0094] As an example, the comparison of the capacitance value of the MOM capacitor structure 21 and the capacitance value of the reference MOM capacitor structure 22 to see if they match includes whether the difference between the two is within a preset range. If the difference is within the preset range, the capacitance values ​​are considered to match. If the difference is outside the preset range, the capacitance values ​​are considered to be mismatched, and then it is determined that the passivation layer has broken.

[0095] Furthermore, when there are multiple detection MOM capacitor structures 21 and multiple reference MOM capacitor structures 22 (i.e., multiple sets of detection structures located at different positions are provided in the same semiconductor structure), the method for determining whether the capacitance value of the detection MOM capacitor structure 21 matches the capacitance value of the reference MOM capacitor structure 22 includes: subtracting the capacitance value of the detection MOM capacitor structure in each set of detection structures from the capacitance value of the reference MOM capacitor structure (when there are multiple detection MOM capacitor structures in each set of detection structures, the average capacitance value of multiple detection MOM capacitor structures is taken) to obtain the capacitance difference of the detection structures, and using the absolute value of the capacitance difference of multiple detection structures to create a trend curve. The capacitance value of the detection MOM capacitor structure in the detection structure corresponding to the obviously abnormal data point in the trend curve does not match the capacitance value of the reference MOM capacitor structure. Conversely, the capacitance value of the detection MOM capacitor in the detection structure corresponding to the normal data point in the trend curve matches the capacitance value of the reference MOM capacitor structure.

[0096] As an example, the semiconductor layer includes a scribe line region ( Figure 10(Not shown in the image), the detection MOM capacitor structure 21 and the reference MOM capacitor structure 22 are both located within the scribe line region (in this embodiment, the scribe line region is considered a three-dimensional region, that is, the scribe line region extends vertically from the semiconductor layer, so that the detection structure is located within the scribe line region; from a two-dimensional perspective, the detection structure in this embodiment is located in the vertical extension direction of the scribe line region of the semiconductor layer). The position of the above structure is limited to the scribe line region to avoid reducing the number of chips ultimately produced, thereby reducing costs. Of course, without considering the final number of chips or cost, the above structure can also be set at other locations within the wafer to be produced (i.e., the semiconductor structure). Semiconductor fabrication is typically performed on the entire wafer. After the basic fabrication process of the functional device is completed (at least the passivation layer is fabricated), the entire wafer needs to be diced into multiple independent chips based on multiple dicing channels. The area occupied by the multiple dicing channels is called the dicing channel region. Basically, the position of each dicing channel is different. Therefore, when the semiconductor structure includes multiple detection MOM capacitor structures 21 and multiple reference MOM capacitor structures 22, the multiple detection MOM capacitor structures 21 and multiple reference MOM capacitor structures 22 are preferably distributed at different positions in the dicing channel region. Since the fracture situation at different positions on the same wafer is different, for example, the stress at the edge of the wafer is greater than the stress at the center of the wafer, and the probability of the passivation layer fracture at the edge of the wafer is also greater than the probability of it fracture at the center of the wafer. Therefore, distributing the above structures at different positions in the dicing channel region can realize the detection of passivation layer fracture at different positions in the semiconductor structure.

[0097] This embodiment of the method for detecting passivation layer fracture in semiconductor structures involves fabricating a detection structure during the conventional semiconductor manufacturing process, during the fabrication of the top metal layer and passivation layer. This structure comprises at least one detection MOM capacitor structure and at least one reference MOM capacitor structure. The method detects whether the passivation layer has fractured by collecting and comparing the capacitance values ​​of the detection MOM capacitor structure and the reference MOM capacitor structure. This detection method is convenient to operate; it can effectively determine whether the passivation layer has fractured by detecting the electrical parameters of the detection structure, without requiring additional detection steps or dedicated defect detection equipment, thus effectively improving the efficiency of defect detection.

[0098] In summary, the structure for detecting passivation layer fracture in semiconductor structures of the present invention is fabricated simultaneously during the fabrication of the top metal layer and passivation layer in conventional semiconductor structures. The structure is simple and novel, requiring no additional masking process and incurring no additional manufacturing costs. It is convenient to operate and highly practical for detecting whether the passivation layer has fractured. The method for detecting passivation layer fracture in semiconductor structures of the present invention fabricates a detection structure consisting of at least one detection MOM capacitor structure and at least one reference MOM capacitor structure during the fabrication of the top metal layer and passivation layer in conventional semiconductor fabrication. The detection of whether the passivation layer has fractured is achieved by collecting and comparing the capacitance values ​​of the detection MOM capacitor structure and the reference MOM capacitor structure. This detection method is convenient to operate; the electrical parameters of the detection structure can effectively determine whether the passivation layer has fractured, without requiring additional detection steps or dedicated defect detection equipment, effectively improving the efficiency of defect detection. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A structure for detecting passivation layer fracture in a semiconductor structure, characterized in that, include: At least one detection MOM capacitor structure is provided, the detection MOM capacitor structure including at least one detection interdigital group, a plurality of detection metals and detection passivation units, the detection metals being located on both sides of the detection interdigital group in a first direction, the detection passivation units being embedded at least within the detection interdigital group and in the gap between the detection interdigital group and the detection metals, the detection interdigital group including at least one first detection interdigit and at least one second detection interdigit extending in a second direction, the first detection interdigit and the second detection interdigit are spaced apart and staggered in the first direction; wherein, the second direction is perpendicular to the first direction; At least one reference MOM capacitor structure is located on the periphery of the detection MOM capacitor structure. The reference MOM capacitor structure includes at least one reference interdigital group and a reference passivation unit. The reference passivation unit is at least embedded in the reference interdigital group. The reference interdigital group includes at least one first reference interdigit and at least one second reference interdigit extending in a second direction. The first reference interdigit and the second reference interdigit are spaced apart and staggered in the first direction.

2. The structure for detecting passivation layer fracture in a semiconductor structure according to claim 1, characterized in that: There are multiple first detection forks and multiple second detection forks. The multiple first detection forks and multiple second detection forks are spaced apart and alternately arranged in a first direction. The detection fork group also includes a first detection busbar and a second detection busbar that extend in the first direction and are arranged opposite to each other in the second direction. The multiple first detection forks are all connected to the first detection busbar, and the multiple second detection forks are all connected to the second detection busbar.

3. The structure for detecting passivation layer fracture in a semiconductor structure according to claim 1, characterized in that: The length of the first detection fork is the same as the length of the second detection fork, and the width of the first detection fork is the same as the width of the second detection fork. The plurality of the first detection forks and the plurality of the second detection forks are arranged at equal intervals.

4. The structure for detecting passivation layer fracture in a semiconductor structure according to claim 1, characterized in that: The width and length of the detected metal are both greater than the width of the first detection fork and the width of the second detection fork.

5. The structure for detecting passivation layer fracture in a semiconductor structure according to claim 4, characterized in that: The length of the detected metal is greater than or equal to 11 times the width of the first detection interdigitator, and the length of the detected metal is greater than or equal to 11 times the width of the second detection interdigitator.

6. The structure for detecting passivation layer fracture in a semiconductor structure according to claim 1, characterized in that: The detection MOM capacitor structure includes multiple detection interdigital groups, which are spaced apart in a first direction; the reference MOM capacitor structure includes multiple reference interdigital groups, which are spaced apart in a first direction.

7. The structure for detecting passivation layer fracture in a semiconductor structure according to claim 1, characterized in that: The reference MOM capacitor structure further includes at least one reference metal group, which is located between two adjacent reference interdigitated groups and includes a plurality of reference metals spaced apart in a first direction.

8. A method for detecting passivation layer fracture in a semiconductor structure, characterized in that, Includes the following steps: Provide a semiconductor layer; At least one detection MOM capacitor structure and at least one reference MOM capacitor structure are formed on the semiconductor layer. The reference MOM capacitor structure is located around the detection MOM capacitor structure. The detection MOM capacitor structure includes at least one detection interdigital group, multiple detection metals, and detection passivation units. The detection metals are located on both sides of the detection interdigital group in a first direction. The detection passivation units are embedded at least within the detection interdigital group and in the gap between the detection interdigital group and the detection metal. The detection interdigital group includes at least one first detection interdigit and at least one second detection interdigit extending in a second direction, spaced apart and staggered in the first direction. The reference MOM capacitor structure includes at least one reference interdigital group and a reference passivation unit. The reference passivation unit is embedded at least within the reference interdigital group. The reference interdigital group includes at least one first reference interdigit and at least one second reference interdigit extending in a second direction, spaced apart and staggered in the first direction. The second direction is perpendicular to the first direction. Collect the capacitance value of the detected MOM capacitor structure and the capacitance value of the reference MOM capacitor structure; The capacitance value of the detected MOM capacitor structure is compared with the capacitance value of the reference MOM capacitor structure to detect passivation layer fracture.

9. The method for detecting passivation layer fracture in a semiconductor structure according to claim 8, characterized in that, Forming at least one detection MOM capacitor structure and at least one reference MOM capacitor structure on the semiconductor layer includes the following steps: A metal layer is formed on top of the semiconductor layer and the metal layer is patterned to obtain a top metal layer. The top metal layer includes at least one separately disposed detection metal group, a detection metal and at least one reference interdigital group. In a first direction, the detection metal is located on both sides of the detection interdigital group. A passivation layer is formed above the top metal layer. The passivation layer also fills the detection interdigitated group, the space between the detection interdigitated group and the detection metal, and the reference interdigitated group. The portion of the passivation layer filling the detection interdigitated group and the space between the detection interdigitated group and the detection metal serves as a detection passivation unit. The detection passivation unit, the detection interdigitated group, and the detection metal constitute a detection MOM capacitor structure. The portion of the passivation layer filling the reference interdigitated group serves as a reference passivation unit. The reference passivation unit and the reference interdigitated group constitute a reference MOM capacitor structure.

10. The method for detecting passivation layer fracture in a semiconductor structure according to claim 8, characterized in that: The semiconductor layer includes a scribe line region, and both the detection MOM capacitor structure and the reference MOM capacitor structure are located within the scribe line region.

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