Display panel and display device

Abstract

This application discloses a display panel and a display device. The display panel has a light-shielding layer disposed in a first substrate. The light-shielding layer includes a first light-shielding trace and a second light-shielding trace. The first light-shielding trace and the second light-shielding trace intersect to form a grid. The orthographic projection of the first gate is located within the orthographic projection of the first light-shielding trace, and at least a portion of the orthographic projection of the first source-drain electrode is located within the orthographic projection of the second light-shielding trace. Through the grid structure formed by the intersecting first and second light-shielding traces, light rays from the backlight directed towards the first gate and the first source-drain electrode are blocked, reducing the intensity of reflected light from the first source-drain electrode and the first gate, avoiding photo-generated leakage current caused by reflected light, improving anti-crosstalk capability, and enhancing the display quality of the display panel. In addition, a color resist layer is disposed on the side of the first source-drain electrode facing away from the first gate, thereby effectively solving the problems of uneven light emission and color shift of the first gate and the first source-drain electrode.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Virtual Reality (VR) displays currently have two main structural types: LTPS-VR panels and LTPO-VR panels. Because VR displays require high resolution (>1000 PPI) to enhance immersion and realism, VR panels need extremely high PPI and extremely small pixel sizes to meet current VR requirements. However, LTPS (Low Temperature Poly-Si and Oxide)-VR panels and LTPO (Low Temperature Poly-Silicon)-VR panels are limited by their high PPI structural design, resulting in lower in-plane aperture ratios compared to conventional products. This leads to lower brightness. Currently, brightness is compensated for by increasing backlight brightness, but high backlight brightness can degrade channel leakage current, affecting display quality. Summary of the Invention

[0003] This application provides a display panel and display device that can solve the problem of poor anti-crosstalk capability of existing display panels.

[0004] A first aspect of this application provides a display panel, including a display area and a border area disposed on at least one side of the display area. The display panel further includes a first substrate and a second substrate disposed opposite to each other. The first substrate includes a substrate substrate and a plurality of thin-film transistors spaced apart on the substrate substrate. The plurality of thin-film transistors includes a first thin-film transistor disposed within the display area. The first thin-film transistor includes a first gate and a first source / drain. The first source / drain is insulated and spaced apart above the side of the first gate substrate facing away from the substrate substrate in the thickness direction. The display panel further includes: a light-shielding layer disposed between the substrate substrate and the first gate, the light-shielding layer including a first light-shielding trace and a second light-shielding trace disposed within the display area; and a color resist layer disposed in the first substrate. The color resist layer is disposed on the side of the first source / drain electrode facing away from the first gate electrode in the thickness direction; wherein, the orthographic projection of the first light-shielding trace on the substrate and the orthographic projection of the second light-shielding trace on the substrate intersect each other to form a grid; the orthographic projection of the first gate electrode on the substrate is located within the orthographic projection of the first light-shielding trace on the substrate, or the orthographic projection of the first gate electrode on the substrate is located within the orthographic projection of the second light-shielding trace on the substrate; at least a portion of the orthographic projection of the first source / drain electrode on the substrate is located within the orthographic projection of the first light-shielding trace on the substrate, or at least a portion of the orthographic projection of the first source / drain electrode on the substrate is located within the orthographic projection of the second light-shielding trace on the substrate.

[0005] Optionally, the first thin-film transistor further includes a first active layer; along the thickness direction, the first active layer is disposed between the first gate layer and the light-shielding layer, or along the thickness direction, the first active layer is disposed between the first source / drain and the first gate; wherein at least a portion of the orthographic projection of the first active layer on the substrate falls within the orthographic projection of the first light-shielding trace on the substrate.

[0006] Optionally, the first substrate further includes a buffer layer, a barrier layer, and an insulating layer stacked on the substrate along the thickness direction, wherein the color resist layer is disposed on the side of the insulating layer facing away from the insulating layer in the thickness direction; the first light-shielding trace and the second light-shielding trace are respectively disposed on the side of the buffer layer facing away from the substrate in the thickness direction, and the barrier layer covers the first light-shielding trace and the second light-shielding trace; the first gate is disposed in the insulating layer, the first source / drain is disposed on the side of the insulating layer facing away from the barrier layer in the thickness direction, and the color resist layer covers the first source / drain; the first active layer is disposed on the side of the barrier layer facing away from the buffer layer in the thickness direction, and the insulating layer covers the first active layer, or the first active layer is disposed in the insulating layer.

[0007] Optionally, the display panel further includes a light-blocking layer disposed on the side of the first substrate facing the second substrate. The light-blocking layer includes a first light-blocking trace and a second light-blocking trace disposed within the display area. The orthographic projections of the first light-blocking trace and the second light-blocking trace on the substrate intersect to form a grid. The orthographic projection of the first gate electrode on the substrate is located within the orthographic projection of the first light-blocking trace on the substrate, or the orthographic projection of the first gate electrode on the substrate is located within the orthographic projection of the second light-blocking trace on the substrate. At least a portion of the orthographic projection of the first source / drain electrode on the substrate is located within the orthographic projection of the first light-blocking trace on the substrate, or at least a portion of the orthographic projection of the first source / drain electrode on the substrate is located within the orthographic projection of the second light-blocking trace on the substrate.

[0008] Optionally, the display panel further includes a planarization layer and a passivation layer stacked along the thickness direction on the side of the color resist layer facing away from the insulating layer; the display panel further includes a common electrode layer, which is disposed on the side of the passivation layer facing away from the planarization layer in the thickness direction, and the common electrode layer includes a plurality of spaced common electrodes; the light-blocking layer is disposed on the side of the passivation layer facing away from the planarization layer in the thickness direction, and along the thickness direction, at least one of the first light-blocking trace and the second light-blocking trace is disposed on the side of the common electrode facing away from the passivation layer.

[0009] Optionally, the thin-film transistor further includes a second thin-film transistor disposed in the frame region, the second thin-film transistor including a second gate and a second source / drain, the second source / drain being insulated and spaced apart above the side of the second gate facing away from the substrate in the thickness direction; the light-shielding layer further includes a third light-shielding trace disposed in the frame region, the third light-shielding trace being disposed on the side of the buffer layer facing away from the substrate in the thickness direction, and the blocking layer covering the third light-shielding trace; wherein, the orthographic projection of the second gate on the substrate falls within the orthographic projection of the third light-shielding trace on the substrate; and / or, at least a portion of the orthographic projection of the second source / drain on the substrate falls within the orthographic projection of the third light-shielding trace on the substrate.

[0010] Optionally, the light-blocking layer further includes a third light-blocking trace, which is disposed in the frame area; at least a portion of the orthogonal projection of the second gate on the substrate falls within the orthogonal projection of the third light-blocking trace on the substrate; at least a portion of the orthogonal projection of the second source / drain on the substrate falls within the orthogonal projection of the third light-blocking trace on the substrate.

[0011] Optionally, the third light-blocking trace surrounds the display area along the circumferential direction of the display area.

[0012] Optionally, the buffer layer has a receiving groove, and the light-shielding layer is disposed in the receiving groove.

[0013] A second aspect of this application provides a display device, the display device including a display panel as described in the first aspect.

[0014] The beneficial effects of this application are that it provides a display panel and a display device having the display panel. The display panel provides a light-shielding layer in a first substrate. The light-shielding layer includes a first light-shielding trace and a second light-shielding trace disposed in the display area. The orthographic projection of the first light-shielding trace on the substrate and the orthographic projection of the second light-shielding trace on the substrate intersect each other to form a grid. Through the grid structure of the intersecting first and second light-shielding traces, light rays from the backlight directed towards the first gate and the first source / drain are blocked, reducing the intensity of reflected light from the first source / drain and the first gate, avoiding photo-generated leakage current caused by reflected light, improving anti-crosstalk capability, and enhancing the display quality of the display panel. In addition, the color resist layer is disposed on the side of the first source / drain away from the first gate, thereby effectively solving the problems of uneven light emission and color shift of the first gate and the first source / drain. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1a This is a schematic diagram of the first structure of the display panel provided in the embodiments of this application;

[0017] Figure 1b This is a schematic diagram of a second structure of the display panel provided in the embodiments of this application;

[0018] Figure 2a This is a schematic diagram of a third structure of the display panel provided in the embodiments of this application;

[0019] Figure 2b This is a schematic diagram of the fourth structure of the display panel provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the combined structure of the substrate and buffer layer in the display panel provided in the embodiments of this application;

[0021] Figure 4 This is a schematic diagram of the combined structure of the substrate, buffer layer and light-shielding layer in the display panel provided in the embodiments of this application;

[0022] Figure 5 This is a schematic diagram of the distribution structure of the light-shielding layer in the display area and the bezel area of ​​the display panel provided in the embodiments of this application;

[0023] Figure 6 This is a schematic diagram of the distribution structure of the light-blocking layer in the display area and the border area of ​​the display panel provided in the embodiments of this application.

[0024] Explanation of reference numerals in the attached figures:

[0025] 1. Display panel; 11. Display area; 12. Border area;

[0026] 10. First substrate; 110. Substrate substrate; 111. Buffer layer; 1111. Receiving trench; 112. Barrier layer; 1131. First gate insulating layer; 1132. Second gate insulating layer; 1141. First interlayer insulating layer; 1142. Second interlayer insulating layer; 115. Color resist layer; 1151. Red photoresist unit; 1152. Green photoresist unit; 1153. Blue photoresist unit; 1161. First planarization layer; 1162. Second planarization layer; 117. Pixel electrode layer; 1171. Pixel electrode; 118. Passivation layer; 119. Common electrode layer; 1191. Common electrode;

[0027] 120. Light-shielding layer; 121. First light-shielding trace; 122. Second light-shielding trace; 123. Third light-shielding trace;

[0028] 131, First thin-film transistor; 1311, First active layer; 1311a, First channel portion; 1311b, First conductor portion; 1312, First gate; 1313, First source; 1314, First drain; 132, Second thin-film transistor; 1321, Second active layer; 1321a, Second channel portion; 1321b, Second conductor portion; 1322, Second gate; 1323, Second source; 1324, Second drain;

[0029] 140. Light-blocking layer; 141. First light-blocking trace; 142. Second light-blocking trace; 143. Third light-blocking trace;

[0030] 20. Second substrate; 21. Support pillar; 22. Encapsulation layer;

[0031] X, thickness direction. Detailed Implementation

[0032] The preferred embodiments of this application are described in detail below with reference to the accompanying drawings to fully introduce the technical content of this application to those skilled in the art, to demonstrate that this application can be implemented, and to make the disclosed technical content of this application clearer, so that those skilled in the art can more easily understand how to implement this application. However, this application can be embodied in many different forms of embodiments, and the protection scope of this application is not limited to the embodiments mentioned herein. The description of the embodiments below is not intended to limit the scope of this application.

[0033] The directional terms used in this application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this application, and not for limiting the scope of protection of this application.

[0034] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and this application does not limit the dimensions and thicknesses of each component.

[0035] In some embodiments of this application, a display device is provided, including a display panel 1.

[0036] In some embodiments of this application, a display panel 1 is provided. The display panel 1 is a liquid crystal display panel, and it is used as a display panel in a VR display. (See also...) Figure 1a , Figure 1b as well as Figures 3-6 The display panel 1 includes a first substrate 10 and a second substrate 20 disposed opposite to each other, and a liquid crystal layer (not shown in the figure) is disposed between the first substrate 10 and the second substrate 20. The liquid crystal layer includes a plurality of liquid crystal molecules. The display panel 1 includes a display area 11 and a border area 12, and the border area 12 is disposed on at least one side of the display area 11.

[0037] In some embodiments of this application, reference is made to Figure 1a and Figure 1b The first substrate 10 includes: a substrate 110, a light-shielding layer 120, and a thin-film transistor.

[0038] Reference Figure 1a and Figure 1b The first substrate 10 is an array substrate, the second substrate 20 is a color filter (CF) substrate, and the substrate 110 has a thickness direction X. The first substrate 10 also includes a buffer layer 111, a barrier layer 112, an insulating layer, a color resist layer 115, and a planarization layer stacked on the surface of the substrate 110 along the thickness direction X. Specifically, as follows... Figure 1a and Figure 1b In the illustrated embodiment, the insulating layer includes a first gate insulating layer 1131 and a first interlayer insulating layer 1141 stacked along the thickness direction X, and the planarization layer includes a first planarization layer 1161. The barrier layer 112 can form a barrier against external moisture to prevent moisture from entering the thin-film transistor. The color resist layer 115 includes a red photoresist unit 1151, a green photoresist unit 1152, and a blue photoresist unit (not shown) arranged sequentially.

[0039] Reference Figure 1a and Figure 1bThe thin-film transistor includes a first thin-film transistor 131, which is disposed in the display area 11. The first thin-film transistor 131 includes a first active layer 1311, a first gate 1312, and a first source / drain. The first active layer 1311 is disposed on the side of the barrier layer 112 facing away from the buffer layer 111 in the thickness direction X. A first gate insulating layer 1131 covers the first active layer 1311. The first active layer 1311 includes a first channel portion 1311a and a conductor portion 1311b. There are two conductor portions 1311b, which are respectively disposed on both sides of the first channel portion 1311a. "Located on both sides of the first channel portion 1311a" refers to both sides in the direction parallel to the surface of the substrate 110. The first gate 1312 is insulated and spaced above the side of the first active layer 1311 facing away from the substrate 110 in the thickness direction X. Specifically, the first gate 1312 is disposed on the side of the first gate insulating layer 1131 facing away from the substrate 110 in the thickness direction X. The first gate 1312 is insulated and spaced from the first active layer 1311 through the first gate insulating layer 1131. The first interlayer insulating layer 1141 covers the first gate 1312. The first source and drain include a first source 1313 and a first drain 1314 disposed on the same layer and spaced apart. The first source and drain are disposed on the side of the first interlayer insulating layer 1141 facing away from the first gate insulating layer 1131 in the thickness direction X. The color resist layer 115 covers the first source and drain.

[0040] In this configuration, the orthographic projection of the first gate electrode 1312 onto the substrate 110 and the orthographic projection of the first source and drain electrodes onto the substrate 110 intersect to form a grid. A through-hole is formed on the first interlayer insulating layer 1141, which passes through the first interlayer insulating layer 1141 and the first gate insulating layer 1131 sequentially along the thickness direction X. The through-hole exposes the first conductor portion 1311b. The first source electrode 1313 is connected to one first conductor portion 1311b through a through-hole, and the first drain electrode 1314 is connected to another first conductor portion 1311b through another through-hole.

[0041] like Figure 1a and Figure 1b In the embodiment shown, the first active layer 1311 in the first thin film transistor 131 is low-temperature polycrystalline silicon (LTPS), the first thin film transistor 131 is a low-temperature polycrystalline silicon thin film transistor, and the display panel 1 is an LTPS-VR display panel.

[0042] Reference Figure 1a and Figure 1b A light-shielding layer 120 is disposed between the substrate 110 and the thin-film transistor. Specifically, the light-shielding layer 120 is disposed in the buffer layer 111. The light-shielding layer 120 includes a first light-shielding trace 121 and a second light-shielding trace 122. Both the first light-shielding trace 121 and the second light-shielding trace 122 are disposed in the display area 11. (Refer to...) Figure 5The first light-shielding trace 121 and the second light-shielding trace 122 intersect each other to form a grid. Specifically, the orthographic projection of the first light-shielding trace 121 on the substrate 110 and the orthographic projection of the second light-shielding trace 122 on the substrate 110 intersect each other to form a grid.

[0043] In some embodiments, refer to Figure 1a and Figure 5 Multiple first thin-film transistors 131 can be disposed in the display area 11. Each first thin-film transistor 131 corresponds to one first light-shielding trace 121 and two second light-shielding traces 122. Specifically, the orthographic projection of the first gate 1312 on the substrate 110 falls within the orthographic projection of the first light-shielding trace 121 on the substrate 110. The orthographic projection of the first source 1313 in the first source-drain electrode falls within the orthographic projection of one second light-shielding trace 122 on the substrate 110. The orthographic projection of the first drain 1314 on the substrate 110 falls within the orthographic projection of another second light-shielding trace 122 on the substrate 110.

[0044] In some embodiments, refer to Figure 1b The orthographic projection of the first gate 1312 on the substrate 110 falls within the orthographic projection of the first light-shielding trace 121 on the substrate 110, and the orthographic projection of the first source / drain on the substrate 110 is located within the orthographic projection of the first light-shielding trace 121 on the substrate 110.

[0045] In some embodiments, the orthographic projection of the first gate 1312 on the substrate 110 falls within the orthographic projection of the second light-shielding trace 122 on the substrate 110, and the orthographic projection of the first source / drain on the substrate 110 lies within the orthographic projection of the first light-shielding trace 121 on the substrate 110. Existing LTPS-VR and LTPO-VR display panels are limited by their high PPI (resolution) structural design characteristics, resulting in a lower in-plane aperture ratio than conventional products, leading to lower brightness. Currently, brightness compensation is achieved by increasing backlight brightness, but high backlight brightness causes deterioration of channel leakage current, resulting in poor crosstalk immunity of VR products.

[0046] Moreover, due to the extremely small pixel size of VR display panels (approximately 5µm per pixel), the bonding precision required when aligning and bonding the second substrate 20 with the first substrate 10 is much higher than that of conventional products. This makes it very easy for color shift and uneven light emission caused by misalignment during bonding. This problem is usually improved by optimizing bonding precision and using a COA (CF on Array) structure. However, the bonding precision is limited by the equipment capabilities, and the room for improvement is limited. The COA structure uses a black matrix (BM) on the Array side, which is usually made of organic BM layer, metal low-overlap layer BM, or low-reflection oxide BMO and other materials. This can greatly improve color shift, but there is still a certain failure rate.

[0047] The display panel 1 provided in this application embodiment uses the mesh structure of the first light-shielding trace 121 and the second light-shielding trace 122 to block the light that shines directly upwards onto the lower surface of the first gate 1312 and the lower surface of the first source and drain, thereby reducing the intensity of reflected light on the first gate 1312 and the first source and drain, avoiding leakage current caused by reflected light, improving anti-crosstalk capability, and enhancing the display quality of the display panel.

[0048] Furthermore, the display panel 1 provided in this application embodiment has a color resist layer 115 disposed in the first substrate 10 to form a COA (CF on Array) structural design, referring to... Figure 1a and Figure 1b as well as Figure 2a and Figure 2b The color resist layer 115 is disposed on the side of the first source and drain electrode facing away from the first gate electrode 1312 in the thickness direction X. The color resist layer 115 covers the first source and drain electrode. The cooperation between the color resist layer 115 and the light-shielding layer 120 can improve the color deviation and uneven light emission of the display panel 1.

[0049] In some embodiments, the material of the light-shielding layer 120 is a metal oxide, or the material of the light-shielding layer 120 is a stacked metal layer and a non-metal dielectric layer. Specifically, the metal oxide is a high-temperature resistant, low-reflectivity metal oxide, so that the first light-shielding trace 121 and the second light-shielding trace 122 in the light-shielding layer 120 have low reflectivity, which can avoid the photogenerated leakage current phenomenon caused by backlight and upper metal reflected light being reflected from the surface of the light-shielding layer 120 to the first channel portion 1311a position of the first active layer 1311, improve anti-crosstalk capability, and enhance the display quality of the display panel.

[0050] In some embodiments, refer to Figure 1a and Figure 1b In the first active layer 1311, the orthographic projections of the two first conductor portions 1311b on the substrate 110 and the orthographic projection of the first channel portion 1311a on the substrate 110 are both located within the orthographic projection of the first light-shielding trace 121 on the substrate 110.

[0051] In some embodiments, in the first active layer 1311, the orthographic projections of the two first conductor portions 1311b on the substrate 110 and the orthographic projections of the first channel portion 1311a on the substrate 110 are both located within the orthographic projection of the second light-shielding trace 122 on the substrate 110.

[0052] In some embodiments, only the orthogonal projection of the first channel portion 1311a on the substrate 110 is within the orthogonal projection of the first light-shielding trace 121 on the substrate 110.

[0053] In some embodiments, only the orthographic projection of the first channel portion 1311a on the substrate 110 is within the orthographic projection of the second light-shielding trace 122 on the substrate 110.

[0054] In some embodiments, refer to Figure 1a and Figure 1b The display panel 1 also includes a light-blocking layer 140, which is disposed on the side of the thin-film transistor facing away from the substrate 110 in the thickness direction X. The light-blocking layer 140 includes a first light-blocking trace 141 and a second light-blocking trace 142. (Refer to...) Figure 6 The first light-blocking trace 141 and the second light-blocking trace 142 are disposed in the display area 11. Specifically, refer to... Figure 1a , Figure 1b as well as Figure 2a and Figure 2bThe display panel 1 further includes a pixel electrode layer 117, a passivation layer 118, and a common electrode layer 119. The pixel electrode layer 117 is disposed in the display area 11 and includes a plurality of pixel electrodes 1171 arranged at intervals. The pixel electrode layer 117 is disposed on the side of the first planarization layer 1161 facing away from the color resist layer 115 in the thickness direction X. The passivation layer 118 is disposed on the side of the pixel electrode layer 117 facing away from the first planarization layer 1161 in the thickness direction X. The common electrode layer 119 is disposed on the side of the passivation layer 118 facing away from the pixel electrode layer 117 in the thickness direction X and includes a plurality of common electrodes 1191 arranged at intervals. The first planarization layer 1161 has a through-hole penetrating the first planarization layer 1161 and the color resist layer 115 on the side of the first planarization layer 1161 facing away from the color resist layer 115 in the thickness direction X. 171 is connected to the first drain 1314 through the via. The passivation layer 118 and the common electrode 1191 are stacked and filled in the via. The via is filled with a second planarization layer 1162. The second planarization layer 1162 extends along the thickness direction X. The end face of the second planarization layer 1162 facing away from the first drain 1314 in the thickness direction X is flush with the side of the common electrode 1191 facing away from the passivation layer 118. The first light-blocking trace 141 is disposed on the side of the common electrode 1191 facing away from the passivation layer 118. The first light-blocking trace 141 and the first light-shielding trace 121 are disposed opposite each other in the thickness direction X. The second light-blocking trace 142 and the second light-shielding trace 122 are disposed opposite each other in the thickness direction X. The orthographic projection of the first light-blocking trace 141 on the substrate 110 and the orthographic projection of the second light-blocking trace 142 on the substrate 110 intersect each other to form a grid.

[0055] In some embodiments, refer to Figure 1a and Figure 1b as well as Figure 2a and Figure 2b The orthographic projection of the first gate 1312 on the substrate 110 is within the orthographic projection of the first light-blocking trace 141 on the substrate 110, and the orthographic projection of the first source / drain on the substrate 110 is within the orthographic projection of the first light-blocking trace 141 on the substrate 110.

[0056] In some embodiments, the orthogonal projection of the first gate 1312 on the substrate 110 is within the orthogonal projection of the second light-blocking trace 142 on the substrate 110, and the orthogonal projection of the first source / drain on the substrate 110 is within the orthogonal projection of the second light-blocking trace 142 on the substrate 110.

[0057] In some embodiments, a first thin-film transistor 131 corresponds to one first light-blocking trace 141 and two second light-blocking traces 142. Specifically, the orthographic projection of the first gate 1312 on the substrate 110 falls within the orthographic projection of the first light-blocking trace 141 on the substrate 110, the orthographic projection of the first source 1313 in the first source-drain electrode falls within the orthographic projection of one second light-blocking trace 142 on the substrate 110, and the orthographic projection of the first drain 1314 on the substrate 110 falls within the orthographic projection of another second light-blocking trace 142 on the substrate 110.

[0058] The display panel 1 provided in this application embodiment has a color resist layer 115 disposed in a substrate 110 to form a COA (CF On Array) structure. A light-shielding layer 120 and a light-blocking layer 140 are also disposed in the substrate 110. The light-shielding layer 120 blocks the light emitted upward from the backlight and can reflect the light emitted from the backlight by the upper metal layer (e.g., the first gate 1312 and the first source / drain). The first light-blocking trace 141 and the second light-blocking trace 142 in the light-blocking layer 140 intersect to form a grid structure to block the upper surface of the first source / drain and the first gate 1312, forming a COA + double light-shielding (light-shielding layer 120 + light-blocking layer 140) structure design, which can effectively solve the problems of uneven light emission and color shift caused by metal leakage. The light-blocking layer 140 and the light-shielding layer 120 are aligned to effectively avoid color shift caused by bonding misalignment and improve the display quality of the display panel 1.

[0059] In some embodiments of this application, reference is made to Figure 2a and Figure 2b The substrate 110 includes a substrate 110, a buffer layer 111, a barrier layer 112, an insulating layer, a color resist layer 115, a first planarization layer 1161, a pixel electrode layer 117, a passivation layer 118, and a common electrode layer 119 stacked along the thickness direction X. The insulating layer includes a first gate insulating layer 1131, a first interlayer insulating layer 1141, a second gate insulating layer 1132, and a second interlayer insulating layer 1142 stacked along the thickness direction X. The color resist layer 115 includes a blue photoresist unit 1153, a red photoresist unit 1151, and a green photoresist unit 1152 arranged sequentially.

[0060] The thin-film transistor includes a first thin-film transistor 131 and a second thin-film transistor 132 arranged at intervals. The first thin-film transistor 131 is a driving thin-film transistor, and the second thin-film transistor 132 is a switching thin-film transistor.

[0061] Reference Figure 2a and Figure 2bThe first active layer 1311 in the first thin film transistor 131 is a low-temperature poly-silicon and oxide active layer. The first thin film transistor 131 is disposed in the display area 11. The first gate 1312 in the first thin film transistor 131 is disposed below the first active layer 1311 in the thickness direction X. Specifically, the first gate 1312 is disposed on the side of the first gate insulating layer 1131 facing away from the barrier layer 112 in the thickness direction X. The first active layer 1311 is disposed on the side of the first interlayer insulating layer 1141 facing away from the first gate insulating layer 1131 in the thickness direction X. The first source and drain are disposed on the side of the second interlayer insulating layer 1142 facing away from the second gate insulating layer 1132 in the thickness direction X.

[0062] Reference Figure 2a and Figure 2b The second thin-film transistor 132 is disposed in the frame region 12. The second thin-film transistor 132 includes a second active layer 1321, a second gate 1322, and a second source / drain. The second active layer 1321 is disposed on the side of the barrier layer 112 facing away from the buffer layer 111 in the thickness direction X. The first gate insulating layer 1131 covers the second active layer 1321. The second active layer 1321 is a low-temperature polysilicon active layer. The second active layer 1321 includes a second channel portion 1321a and a second conductor portion 1321b. There are two second conductor portions 1321b, which are respectively disposed on both sides of the second channel portion 1321a. "Located on both sides of the second channel portion 1321a" refers to both sides in the direction parallel to the surface of the substrate 110. The second gate 1322 is insulated and spaced above the side of the second active layer 1321 facing away from the substrate 110 in the thickness direction X. Specifically, the second gate 1322 is disposed on the side of the first gate insulating layer 1131 facing away from the substrate 110 in the thickness direction X. The second gate 1322 is insulated and spaced from the second active layer 1321 through the first gate insulating layer 1131. The first interlayer insulating layer 1141 covers the second gate 1322. The second source and drain include a second source 1323 and a second drain 1324 spaced apart. The second source and drain are disposed on the side of the second gate insulating layer 1132 facing away from the first interlayer insulating layer 1141 in the thickness direction X. The second interlayer insulating layer 1142 covers the first source and drain. The second gate insulating layer 1132 has a through hole that passes through the second gate insulating layer 1132, the first interlayer insulating layer 1141 and the first gate insulating layer 1131 in sequence along the thickness direction X. The through hole exposes the second conductor portion 1321b. The second source 1323 is connected to one of the second conductor portions 1321b through a through hole, and the second drain 1324 is connected to another second conductor portion 1321b through another through hole.

[0063] In some embodiments of this application, the light-shielding layer 120 includes a third light-shielding trace 123, which is disposed in the border area 12 and is disposed opposite to the second active layer 1321 along the thickness direction X; Figure 2a and Figure 2b In the illustrated embodiment, the orthographic projections of the two second conductor portions 1321b in the second active layer 1321 onto the projection plane and the orthographic projection of the second channel portion 1321a onto the substrate 110 are both located within the orthographic projection of the third light-shielding trace 123 onto the substrate 110. At least a portion of the orthographic projection of the second gate 1322 onto the substrate 110 is located within the orthographic projection of the third light-shielding trace 123 onto the projection plane. At least a portion of the orthographic projections of the second source / drain onto the substrate 110 also fall within the orthographic projection of the third light-shielding trace 123 onto the substrate 110. By providing the third light-shielding trace 123 within the bezel region 12, the second source / drain and the second gate 1322 in the second thin-film transistor 132 located within the bezel region 12 can be shielded, effectively solving the problems of uneven light emission and color shift caused by metal leakage within the bezel region 12, and improving the display quality of the display panel 1.

[0064] In some embodiments of this application, the light-blocking layer 140 further includes a third light-blocking trace 143, which is disposed in the border region 12. At least a portion of the orthogonal projection of the second source / drain electrode onto the substrate 110 lies within the orthogonal projection of the third light-blocking trace 143 onto the substrate 110, and at least a portion of the orthogonal projection of the second gate electrode 1322 onto the substrate 110 lies within the orthogonal projection of the third light-blocking trace 143 onto the substrate 110. (Refer to...) Figure 6 The orthographic projection of the bezel region 12 onto the substrate 110 lies within the orthographic projection of the third light-blocking trace 143 onto the substrate 110. By providing the third light-blocking trace 143 in the bezel region 12, the upper surfaces of the second source / drain and the second gate 1322 in the second thin-film transistor 132 located within the bezel region 12 can be blocked, effectively solving the problems of uneven light emission and color shift caused by metal leakage within the bezel region 12, and improving the display quality of the display panel 1.

[0065] Additionally, refer to Figure 1a and Figure 1b as well as Figure 2a and Figure 2bThe display panel 1 also includes a support pillar 21 and an encapsulation layer 22. The support pillar 21 is disposed in the display area 11 and extends along the thickness direction X. One end of the support pillar 21 abuts against the side of the light-blocking layer 140 facing the second substrate 20 in the thickness direction X, and the other end of the support pillar 21 abuts against the side of the second substrate 20 facing the first substrate 10. The encapsulation layer 22 is disposed in the frame area 12. One end of the encapsulation layer 22 abuts against the third light-blocking trace 143 in the thickness direction X, and the other end of the encapsulation layer 22 abuts against the side of the second substrate 20 facing the first substrate 10 to form an encapsulation.

[0066] In some embodiments of this application, the light-blocking layer 140 is made of metal oxide.

[0067] In some embodiments of this application, the light-blocking layer 140 includes a stacked metal layer and a non-metallic dielectric layer.

[0068] In some embodiments of this application, the metal oxide is a high-temperature resistant, low-reflectivity metal oxide, including one of MoO3, CuO, Ag2O, WO3, and TiO2.

[0069] In some embodiments of this application, the metal in the metal layer includes one of Mo, Cu, Ag, W, and Ti.

[0070] In some embodiments of this application, the non-metallic dielectric in the non-metallic dielectric layer includes SiN. x SiO x One of the ITOs.

[0071] In some embodiments of this application, reference is made to Figure 3 The buffer layer 111 has a receiving groove 1111, as shown in the figure. Figure 4 The light-shielding layer 120 is housed in the receiving groove 1111. The opening of the receiving groove 1111 allows the light-shielding layer 120 to be embedded in the receiving groove 1111, so that the side of the light-shielding layer 120 facing away from the substrate 110 in the thickness direction X is flush with the side of the light-shielding layer 120 facing away from the substrate 110 in the thickness direction X, thereby ensuring the overall flatness of the display panel 1 and ensuring the display quality.

[0072] The above provides a detailed description of a display panel and display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, comprising a display area and a border area disposed on at least one side of the display area, the display panel further comprising a first substrate and a second substrate disposed opposite to each other, the first substrate comprising a substrate substrate and a plurality of thin film transistors spaced apart on the substrate substrate, the plurality of thin film transistors including a first thin film transistor disposed within the display area, the first thin film transistor comprising a first gate and a first source and drain, the first source and drain being insulated and spaced apart above the side of the first gate substrate facing away from the substrate substrate in the thickness direction; Its features are, The display panel also includes: A light-shielding layer is disposed between the substrate and the first gate, and the light-shielding layer includes a first light-shielding trace and a second light-shielding trace disposed within the display area; A color resist layer is disposed in the first substrate, and the color resist layer is disposed on the side of the first source and drain electrode that is away from the first gate electrode in the thickness direction; Wherein, the orthographic projection of the first light-shielding trace on the substrate and the orthographic projection of the second light-shielding trace on the substrate intersect each other to form a grid; The orthogonal projection of the first gate on the substrate is located within the orthogonal projection of the first light-shielding trace on the substrate, or the orthogonal projection of the first gate on the substrate is located within the orthogonal projection of the second light-shielding trace on the substrate; At least a portion of the orthogonal projection of the first source / drain electrode on the substrate is located within the orthogonal projection of the first light-shielding trace on the substrate, or at least a portion of the orthogonal projection of the first source / drain electrode on the substrate is located within the orthogonal projection of the second light-shielding trace on the substrate.

2. The display panel as described in claim 1, characterized in that, The first thin-film transistor further includes a first active layer; Along the thickness direction, the first active layer is disposed between the first gate layer and the light-shielding layer, or, along the thickness direction, the first active layer is disposed between the first source / drain and the first gate. Wherein, at least a portion of the orthographic projection of the first active layer on the substrate falls within the orthographic projection of the first light-shielding trace on the substrate.

3. The display panel as described in claim 2, characterized in that, The first substrate further includes a buffer layer, a barrier layer, and an insulating layer stacked on the substrate along the thickness direction, wherein the color resist layer is disposed on the side of the insulating layer facing away from the insulating layer in the thickness direction; the first light-shielding trace and the second light-shielding trace are respectively disposed on the side of the buffer layer facing away from the substrate in the thickness direction, and the barrier layer covers the first light-shielding trace and the second light-shielding trace. The first gate is disposed in the insulating layer, the first source and drain are disposed on the side of the insulating layer opposite to the barrier layer in the thickness direction, and the color resist layer covers the first source and drain; The first active layer is disposed on the side of the barrier layer opposite to the buffer layer in the thickness direction, and the insulating layer covers the first active layer, or the first active layer is disposed in the insulating layer.

4. The display panel as described in claim 3, characterized in that, The display panel further includes a light-blocking layer, which is disposed on the side of the first substrate facing the second substrate. The light-blocking layer includes a first light-blocking trace and a second light-blocking trace disposed within the display area. The orthographic projection of the first light-blocking trace on the substrate and the orthographic projection of the second light-blocking trace on the substrate intersect each other to form a grid. The orthogonal projection of the first gate on the substrate is located within the orthogonal projection of the first light-blocking trace on the substrate, or the orthogonal projection of the first gate on the substrate is located within the orthogonal projection of the second light-blocking trace on the substrate; At least a portion of the orthogonal projection of the first source / drain electrode on the substrate is located within the orthogonal projection of the first light-blocking trace on the substrate, or at least a portion of the orthogonal projection of the first source / drain electrode on the substrate is located within the orthogonal projection of the second light-blocking trace on the substrate.

5. The display panel as described in claim 4, characterized in that, The display panel further includes a planarization layer and a passivation layer stacked along the thickness direction on the side of the color resist layer facing away from the insulating layer; The display panel further includes a common electrode layer, which is disposed on the side of the passivation layer opposite to the planarization layer in the thickness direction, and the common electrode layer includes a plurality of common electrodes arranged at intervals. The light-blocking layer is disposed on the side of the passivation layer opposite to the planarization layer in the thickness direction. Along the thickness direction, at least one of the first light-blocking trace and the second light-blocking trace is disposed on the side of the common electrode opposite to the passivation layer.

6. The display panel as described in claim 3, characterized in that, The thin-film transistor further includes a second thin-film transistor disposed in the frame region. The second thin-film transistor includes a second gate and a second source and drain. The second source and drain are insulated and spaced apart above the side of the second gate facing away from the substrate in the thickness direction. The light-shielding layer further includes a third light-shielding trace, which is disposed in the frame area and on the side of the buffer layer facing away from the substrate in the thickness direction. The blocking layer covers the third light-shielding trace. Wherein, the orthogonal projection of the second gate on the substrate falls within the orthogonal projection of the third light-shielding trace on the substrate; And / or, at least a portion of the orthogonal projection of the second source / drain electrode onto the substrate falls within the orthogonal projection of the third light-shielding trace onto the substrate.

7. The display panel as described in claim 6, characterized in that, The light-blocking layer also includes a third light-blocking trace, which is disposed in the frame area; At least a portion of the orthogonal projection of the second gate onto the substrate falls within the orthogonal projection of the third light-blocking trace onto the substrate; At least a portion of the orthogonal projection of the second source / drain electrode onto the substrate falls within the orthogonal projection of the third light-blocking trace onto the substrate.

8. The display panel as described in claim 7, characterized in that, The third light-blocking trace surrounds the display area along its circumferential direction.

9. The display panel as described in claim 6, characterized in that, The buffer layer has a receiving groove, and the light-shielding layer is disposed in the receiving groove.

10. A display device, characterized in that, The display device includes a display panel as claimed in any one of claims 1 to 9.

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