A display panel and display terminal

Abstract

This application discloses a display panel and a display terminal. The display panel includes an active portion, a gate insulating layer, a gate, and source / drain layers. The active portion includes a stacked first contact portion, a channel portion, and a second contact portion. The portion of the first contact portion that overlaps with the first contact portion is a first sub-portion, and the portion of the second contact portion that overlaps with the first contact portion is a second sub-portion. The active portion has a first sidewall. The gate at least covers the channel portion on the first sidewall. The source is electrically connected to the first sub-portion through a via, and the drain is electrically connected to the second sub-portion through a via. By staggering the first and second sub-portions, this application ensures that the orthographic projection of the via electrically connected to the first sub-portion on the substrate does not overlap with the second contact portion, and the orthographic projection of the via electrically connected to the second sub-portion on the substrate does not overlap with the first contact portion. This avoids device malfunction caused by either of the two vias simultaneously penetrating the first and second contact portions, thereby improving process yield.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0002] SOG (system on glass) technology integrates gate drive circuits, source drive circuits, timing controllers, and other chip circuits onto a glass substrate. This increases the integration density of display panels, reduces reliance on chips, and lowers costs. Realizing SOG technology requires increasing the maximum operating frequency and current density of thin-film transistors (TFTs). These demands TFTs with shorter channel lengths, higher mobility, and smaller sizes.

[0003] Based on the above reasons, the prior art provides a vertical TFT structure. In order to achieve better device performance, the channel layer of the vertical TFT structure is thinner. When drilling holes in the active layer to connect the source and drain electrodes, the stacked connection layer is easily penetrated, leading to device failure.

[0004] Therefore, there is an urgent need to provide a new array substrate structure to solve the above problems. Summary of the Invention

[0005] This application provides a display panel and a display terminal to solve the technical problem of thin-film transistor device failure in the display panel and improve the process yield.

[0006] To solve the above-mentioned technical problems, the technical solution provided in this application is as follows:

[0007] This application provides a display panel, the display panel comprising:

[0008] Substrate;

[0009] An active portion is disposed on the substrate. The active portion includes a first contact portion, a channel portion, and a second contact portion stacked together. The channel portion is partially disposed on the side of the first contact portion facing away from the substrate, and the second contact portion is disposed on the side of the channel portion facing away from the substrate. On the substrate, the orthographic projection of the second contact portion overlaps with the orthographic projection of the channel portion, and the orthographic projection of the second contact portion partially overlaps with the orthographic projection of the first contact portion. In a direction perpendicular to the substrate, the portion of the first contact portion intersecting with the first contact portion is a first sub-portion, and the portion of the second contact portion intersecting with the first contact portion is a second sub-portion.

[0010] A gate insulating layer is disposed on the side of the active portion away from the substrate;

[0011] A gate is disposed on the side of the gate insulating layer opposite to the substrate. The active portion has a first sidewall, which is an inclined sidewall of the overlapping portion of the first contact portion, the channel portion, and the second contact portion. The gate covers at least the channel portion on the first sidewall on the gate insulating layer.

[0012] A source-drain layer is disposed on the side of the active portion away from the substrate. The source-drain layer includes a source and a drain. The source is electrically connected to the first sub-part, and the drain is electrically connected to the second sub-part.

[0013] In the display panel of this application, the orthogonal projection of the gate on the substrate covers a portion of the orthogonal projection of the first sidewall on the substrate, and one end of the gate extends along the first sidewall to the side surface of the active portion facing away from the substrate, and the other end of the gate extends along the first sidewall to the substrate.

[0014] In the display panel of this application, the first contact portion extends along a first direction, the second contact portion extends along a second direction, and the first direction and the second direction have a preset angle; the orthographic projection of the first sidewall on the substrate extends along the second direction, and in the second direction, the length dimension of the gate is less than or equal to the length dimension of the first sidewall.

[0015] In the display panel of this application, the second contact portion includes a long portion along the second direction and a short portion along the first direction. The first sidewall is located on the inclined side of the short portion and extends along the second direction. In the second direction, the length dimension of the gate is greater than the length dimension of the channel portion.

[0016] In the display panel of this application, the display panel includes a first barrier layer, which is disposed between the first contact portion and the channel portion;

[0017] The first barrier layer covers the first sub-part, and the orthographic projection of the first sidewall on the substrate is spaced apart from the orthographic projection of the first barrier layer on the substrate.

[0018] In the display panel of this application, the via electrically connecting the source to the first sub-part is a first via, and the via electrically connecting the drain to the second sub-part is a second via. The first via is configured to penetrate the gate insulating layer and the first barrier layer, and the second via is configured to penetrate the gate insulating layer.

[0019] In the display panel of this application, the display panel includes a light-shielding layer, which is disposed on the side of the active portion near the substrate, and the orthographic projection of the first sidewall of the channel portion on the light-shielding layer is located within the light-shielding layer.

[0020] In the display panel of this application, a boss is provided on the substrate, and an active part is provided on the boss. The orthographic projection of the active part on the substrate overlaps with the boss.

[0021] In the direction perpendicular to the substrate, the sum of the thickness of the boss and the thickness of the first contact portion is greater than or equal to the thickness of the gate insulating layer.

[0022] In the display panel of this application, the display panel includes a second barrier layer, which is disposed on the side of the second contact portion away from the substrate, and the orthographic projection of the second barrier layer on the second contact portion overlaps with the second contact portion.

[0023] This application provides a display terminal, which includes the display panel described above.

[0024] Beneficial Effects: This application discloses a display panel and a display terminal. The display panel includes a substrate, an active portion, a gate insulating layer, a gate, and a source / drain layer. The active portion is disposed on the substrate and includes a first contact portion, a channel portion, and a second contact portion stacked together. The channel portion is disposed on the side of the first contact portion away from the substrate, and the second contact portion is disposed on the side of the channel portion away from the substrate. On the substrate, the orthographic projection of the second contact portion overlaps with the orthographic projection of the channel portion, and the orthographic projection of the second contact portion partially overlaps with the orthographic projection of the first contact portion. In the direction perpendicular to the substrate, the portion where the first contact portion intersects with the first contact portion forms a first sub-portion, and the second contact portion intersects with the first contact portion... The interlaced portion is the second sub-part; a gate insulating layer is disposed on the side of the active part away from the substrate; a gate is disposed on the side of the gate insulating layer away from the substrate; the active part has a first sidewall, the first sidewall being an inclined side surface of the overlapping portion of the first contact portion, the channel portion, and the second contact portion; the gate at least covers the channel portion on the first sidewall on the gate insulating layer; a source-drain layer is disposed on the side of the active part away from the substrate, the source-drain layer including a source and a drain; the source is electrically connected to the first sub-part through a via, and the drain is electrically connected to the second sub-part through a via. This application alternates the first sub-part of the first contact portion and the second sub-part of the second contact portion, while electrically connecting the source to the first sub-part through a via and the drain to the second sub-part through a via. This ensures that the orthographic projection of the via electrically connected to the first sub-part on the substrate does not overlap with the second contact portion, and the orthographic projection of the via electrically connected to the second sub-part on the substrate does not overlap with the first contact portion. This avoids the device malfunction caused by either of the two vias simultaneously penetrating the first and second contact portions, thereby improving the process yield. Attached Figure Description

[0025] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0026] Figure 1a This is a partial top view of a display panel structure in related technologies;

[0027] Figure 1b for Figure 1a A schematic diagram of the cross-sectional structure of section AA in the diagram;

[0028] Figure 1c for Figure 1a A schematic diagram of the cross-sectional structure of section BB in the diagram;

[0029] Figure 2a A partial top view of the structure of a first type of display panel provided for an embodiment of this application;

[0030] Figure 2b for Figure 2a A schematic diagram of the cross-sectional structure of the first type of display panel in the diagram;

[0031] Figure 2c for Figure 2a A schematic diagram of the cross-sectional structure of the DD section of the first type of display panel in the diagram;

[0032] Figure 3 A partial top view of the structure of a second type of display panel provided for an embodiment of this application;

[0033] Figure 4a for Figure 2a A schematic diagram of the cross-sectional structure of the CC section of the third type of display panel in the diagram;

[0034] Figure 4b for Figure 2a A schematic diagram of the cross-sectional structure of the DD section of the third type of display panel in the diagram;

[0035] Figure 5a for Figure 2a A schematic diagram of the cross-sectional structure of the fourth type of display panel in the diagram (CC section).

[0036] Figure 5b for Figure 2a A schematic diagram of the cross-sectional structure of the DD section of the fourth type of display panel in the diagram;

[0037] Figures 6a to 6c A process flow diagram of the manufacturing process of a first type of display panel provided for embodiments of this application.

[0038] Explanation of reference numerals in the attached figures:

[0039] Active layer 100, first conductor layer 101, channel layer 102, second conductor layer 103, source / drain layer 105, substrate 11, buffer layer 12, boss 13, active portion 20, first contact portion 21, first sub-port 210, channel portion 22, second contact portion 23, second sub-port 230, first sidewall 22A, second sidewall 22B, first pitch d, source 71, drain 72, first via 710, second via 720, first barrier layer 30, first end 31, second barrier layer 40, gate insulating layer 60, gate 50, second direction D2, first direction D1, light shielding layer 90, interlayer insulating layer 80. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in its actual use or working state, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0041] like Figures 1a to 1c As shown, in related technologies, the active layer 100 of a thin-film transistor includes a stacked first conductor layer 101, a channel layer 102, and a second conductor layer 103. Since the channel layer 102 is located between the first conductor layer 101 and the second conductor layer 103 in a direction perpendicular to the substrate 11, the thickness of the channel layer 102 is the channel length. Because the dimensional control precision for the thickness of the film layer in the display panel manufacturing process is greater than the dimensional control precision for the film layer in a plane parallel to the substrate 11, the thickness of the channel layer 102 can be reduced. Through the above configuration, a short-channel thin-film transistor can be realized. The source and drain layers 105 are electrically connected to the first conductor layer 101 and the second conductor layer 103 respectively through perforations. However, as... Figure 1b As shown at point E, because the channel layer 102 between the first conductor layer 101 and the second conductor layer 103 is relatively thin, if the via is too deep when drilling, it is easy to penetrate the first conductor layer 101 and the second conductor layer 103, which will cause the device to fail.

[0042] Based on the aforementioned technical problems, this application proposes the following solutions.

[0043] This application provides a display panel, such as Figures 2a to 2cAs shown, the display panel includes a substrate 11, an active portion 20, a gate insulating layer 60, a gate 50, and a source / drain layer. The active portion 20 is disposed on the substrate 11 and includes a first contact portion 21, a channel portion 22, and a second contact portion 23 stacked together. The channel portion 22 is disposed on the side of the first contact portion 21 facing away from the substrate 11, and the second contact portion 23 is disposed on the side of the channel portion 22 facing away from the substrate 11. On the substrate 11, the orthographic projection of the second contact portion 23 overlaps with the orthographic projection of the channel portion 22, and the orthographic projection of the second contact portion 23 partially overlaps with the orthographic projection of the first contact portion 21. In the direction perpendicular to the substrate 11, the portion where the first contact portions 21 intersect is the first sub-portion 210, and the second contact portion 21... The portion intersecting with the first contact portion 21 is the second sub-part 230; the gate insulating layer 60 is disposed on the side of the active part 20 away from the substrate 11; the gate 50 is disposed on the side of the gate insulating layer 60 away from the substrate 11, the active part 20 has a first sidewall 22A, the first sidewall 22A is an inclined side surface of the overlapping portion of the first contact portion 21, the channel portion 22 and the second contact portion 23; the gate 50 covers at least the channel portion 22 on the first sidewall 22A on the gate insulating layer 60; the source drain layer is disposed on the side of the active part 20 away from the substrate 11, the source drain layer includes a source 71 and a drain 72; the source 71 is electrically connected to the first sub-part 210 through a via, and the drain 72 is electrically connected to the second sub-part 230 through a via.

[0044] In this embodiment, the substrate 11 can be a flexible substrate or a rigid substrate. The flexible substrate can be made of one of the following materials: colorless polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET). The rigid substrate can be made of glass or the like.

[0045] In this embodiment, the display panel can be an OLED panel, a Mini-LED panel, a Micro-LED panel, etc. The display panel includes thin-film transistors (TFTs), which can be used in gate drive circuits, source drive circuits, timing controllers, pixels, etc., but are not limited to these. By integrating various circuit functions originally implemented by chips onto the display panel, the dependence of the display panel on chips can be reduced, the cost of the display panel can be reduced, and SOG technology can be realized.

[0046] In this embodiment, the active portion 20 includes a first contact portion 21, a channel portion 22, and a second contact portion 23 stacked sequentially. With this arrangement, the thickness direction of the channel portion 22 can be used as the channel length. The thickness direction of the channel portion 22 refers to the direction perpendicular to the substrate 11. The bearing surface of the substrate 11 is the plane on the side of the substrate 11 closest to the active portion 20. The bearing surface of the substrate 11 is parallel to the display surface of the display panel. Because the process accuracy of the thickness of the channel portion 22 is greater than the process accuracy of the dimension of the channel portion 22 parallel to the display surface when fabricating the channel portion 22 in the existing process, thin-film transistors with smaller channel lengths can be fabricated.

[0047] The channel portion 22 can be polycrystalline silicon. The first contact portion 21 and the second contact portion 23 can be formed by ion doping of the polycrystalline silicon. After doping, the conductivity of the first contact portion 21 and the second contact portion 23 is improved, enabling them to form ohmic contacts with the source 71 and the drain 72 of the thin-film transistor. The doping ions can be phosphorus ions, boron ions, etc., but are not limited to these. The doping form can be light doping or heavy doping, and this application does not limit this.

[0048] It should be noted that the polycrystalline silicon of the channel portion 22 can be formed from amorphous silicon using an excimer laser annealing (ELA) process. After using the excimer laser annealing process, the amorphous silicon melts and recrystallizes, which can achieve the absence of grain boundaries in the direction of the channel portion 22 perpendicular to the substrate 11, that is, to achieve a single grain in the length direction of the channel, with a grain size of approximately 0.3 micrometers, thereby achieving a short channel and improving the electrical performance of the thin-film transistor.

[0049] In this embodiment, the gate insulating layer 60 can be fabricated using one or more layers of materials such as silicon nitride, silicon oxide, or silicon oxynitride, but is not limited thereto. The gate insulating layer 60 can separate the gate 50 and the active portion 20, thereby achieving insulation between the gate 50 and the active portion 20.

[0050] In this embodiment, the source electrode 71 and the drain electrode 72 can be made of conductive materials. The source electrode 71 and the drain electrode 72 can be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but are not limited thereto.

[0051] In this embodiment, the orthographic projection of the first contact portion 21 on the substrate 11 partially overlaps with the orthographic projection of the second contact portion 23 on the substrate 11. However, the orthographic projections of the first sub-part 210 of the first contact portion 21 and the second sub-part 230 of the second contact portion 23 on the substrate 11 do not overlap. By setting the orthographic projections of the first sub-part 210 and the second sub-part 230 on the substrate 11 to not overlap, the first sub-part 210 can be electrically connected to the source 71 through a via, and the second sub-part 230 can be electrically connected to the drain 72 through a via. Thus, even if the via depth is too deep during its fabrication, the via will not penetrate the second contact portion 23. This avoids the situation where the first contact portion 21 and the second contact portion 23 become conductive and malfunction when the via penetrates.

[0052] In this embodiment, in a portion of the active portion 20, the first contact portion 21, the channel portion 22, and the second contact portion 23 overlap, and the gate 50 is correspondingly disposed at the first sidewall 22A at the overlapping portion. The first sidewall 22A is an inclined side surface of the overlapping portion of the first contact portion 21, the channel portion 22, and the second contact portion 23; that is, the sidewalls of the first contact portion 21, the channel portion 22, and the second contact portion 23 at the first sidewall 22A are flush. The gate 50 is disposed on the side of the gate insulating layer 60 facing away from the substrate 11, and the gate 50 at least covers the channel portion 22 on the first sidewall 22A.

[0053] In this embodiment, the gate 50 is a conductive material. The gate 50 can be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof, but is not limited thereto.

[0054] In the display panel of this application, the orthogonal projection of the gate 50 on the substrate 11 covers the orthogonal projection of the first sidewall 22A on the substrate 11. One end of the gate 50 extends along the first sidewall 22A to cover the side surface of the active portion 20 away from the substrate 11, and the other end of the gate 50 extends along the first sidewall 22A to cover the substrate 11.

[0055] In this embodiment, the gate 50 is disposed corresponding to the first sidewall 22A, and the orthographic projection of the gate 50 on the substrate 11 at least partially overlaps with the first sidewall 22A. That is to say, the gate 50 at least covers a portion of the first sidewall 22A.

[0056] In this embodiment, as Figures 2a to 2cAs shown, after the gate 50 covers the first sidewall 22A, it extends along both ends of the first sidewall 22A in the first direction D1, with one end extending to the upper surface of the active portion 20 and the other end extending to the surface of the substrate 11. With the above arrangement, the gate 50 can more easily cover the first sidewall 22A in the manufacturing process, enhancing the gate 50's control over the channel portion 22.

[0057] In the display panel of this application, as Figures 2a to 2c As shown, the first contact portion 21 extends along the first direction D1, and the second contact portion 23 extends along the second direction D2. The first direction D1 and the second direction D2 have a preset angle. In the second direction D2, the length dimension of the gate 50 is less than or equal to the length dimension of the channel portion 22. The channel portion 22 includes a second sidewall 22B opposite to the first sidewall 22A. The second direction D2 is the direction from the first sidewall 22A to the second sidewall 22B. The orthographic projection of the channel portion 22 on the substrate 11 overlaps with the orthographic projection of the second contact portion 23 on the substrate 11.

[0058] In this embodiment, the preset included angle can be an acute angle, a right angle, or an obtuse angle, and can be adaptively set according to the shape of the space.

[0059] In this embodiment, the length of the gate 50 in the second direction D2 is less than or equal to the length of the channel portion 22 in the second direction D2. By this arrangement, the length of the gate 50 in the second direction D2 can be reduced, thereby decreasing the size of the thin-film transistor. In this case, the length W of the gate 50 in the second direction D2 is equal to the channel width of the thin-film transistor.

[0060] In this embodiment, the orthographic projection of the second contact portion 23 onto the channel portion 22 overlaps with the channel portion 22, that is, the projection shape and area of ​​the second contact portion 23 and the channel portion 22 are the same.

[0061] In this embodiment, the orthogonal projection of the gate 50 onto the substrate 11 does not overlap with either the first sub-part 210 or the second sub-part, thereby avoiding the formation of parasitic capacitance.

[0062] In the display panel of this application, as Figure 3 As shown, Figure 3This is a partial top view of a second type of display panel provided in an embodiment of this application. The second type of display panel differs from the first type of display panel only in the dimensions of the gate 50 and the active portion 20. The cross-sectional view of the second type of display panel is similar to that of the first type of display panel. The second contact portion 23 includes a long portion along the second direction D2 and a short portion along the first direction D1. The first sidewall 22A is located on the inclined side of the short portion and extends along the second direction D2. In the second direction D2, the length of the gate 50 is greater than the length of the channel portion 22. The channel portion 22 includes a second sidewall 22B opposite to the first sidewall 22A. The second direction D2 is the direction from the first sidewall 22A to the second sidewall 22B. The orthographic projection of the channel portion 22 on the substrate 11 overlaps with the orthographic projection of the second contact portion 23 on the substrate 11.

[0063] In this embodiment, to avoid the formation of parasitic capacitance due to the overlap between the gate 50 and the second contact portion 23, the second contact portion 23 is configured as an L-shape. With the above configuration, when the length dimension of the gate 50 in the second direction D2 is greater than the length of the channel portion 22, the corner of the L-shape can form a space to avoid the gate 50.

[0064] In this embodiment, the length of the gate 50 in the second direction D2 is greater than the length of the channel portion 22 in the second direction D2. The orthographic projection of the second contact portion 23 onto the channel portion 22 overlaps with the channel portion 22, meaning that the projection shape and area of ​​the second contact portion 23 and the channel portion 22 are the same. This arrangement increases the width of the channel. The width of the channel is W1 + 2a, where W1 is the length of the second contact portion 23 in the second direction D2, and a is the length of the overlapping portion of the gate 50 and the second contact portion 23 in the first direction D1. The first direction D1 and the second direction D2 are set at an angle; for example, the angle can be a right angle or an acute angle.

[0065] This embodiment increases the width-to-length ratio of the channel by increasing its width, thereby increasing the on-state current of the thin-film transistor and improving its electrical performance. The width-to-length ratio refers to the ratio of the channel's width to its length. In this application, the channel length is the thickness of the channel portion 22 in the direction perpendicular to the substrate 11.

[0066] In the display panel of this application, as Figure 2a and Figure 2b As shown, the display panel includes a first barrier layer 30, which is disposed between the first contact portion 21 and the channel portion 22; the first barrier layer 30 covers the first sub-portion 210, and the orthographic projection of the first sidewall 22A on the substrate 11 is spaced apart from the orthographic projection of the first barrier layer 30 on the substrate 11.

[0067] In this embodiment, the orthographic projection of the first sub-part 210 on the first barrier layer 30 is located inside the first barrier layer 30, and the orthographic projection of the first sidewall 22A on the first barrier layer 30 is located outside the first barrier layer 30.

[0068] In this embodiment, a first barrier layer 30 is disposed between the first contact portion 21 and the channel portion 22. The first end 31 of the first barrier layer 30 is close to the gate 50, and the other end of the first barrier layer 30 extends away from the gate 50, separating the channel portion 22 and the first contact portion 21. The first barrier layer 30 can shorten the leakage current channel length between the first contact portion 21 and the channel portion 22, improving the electrical properties of the thin-film transistor; it can also serve as a protective layer to prevent over-etching of the upper surface of the first contact portion 21 when the channel portion 22 and the second contact portion 23 are etched together, thereby improving the yield of the patterning process.

[0069] In some embodiments, in order to minimize the path length of leakage current between the first contact portion 21 and the channel portion 22, the distance between the first end 31 of the first barrier layer 30 and the first sidewall 22A can be set to a first distance d. The first distance d is 0.01 micrometers to 0.1 micrometers, thereby retaining only a very short contact between the first contact portion 21, the channel portion 22, and the second contact portion 23, further shortening the path length of leakage current.

[0070] In this embodiment, the first barrier layer 30 is an insulating material. For example, the first barrier layer 30 can be made of silicon nitride, silicon oxide, silicon oxynitride, etc., but is not limited to these.

[0071] In the display panel of this application, the via electrically connecting the source 71 to the first sub-part 210 is the first via 710, and the via electrically connecting the drain 72 to the second sub-part 230 is the second via 720. The first via 710 is configured to penetrate the gate insulating layer 60 and the first barrier layer 30, and the second via 720 is configured to penetrate the gate insulating layer 60.

[0072] It should be understood that when there are other insulating layers between the gate insulating layer 60 and the source / drain layer, the first via 710 and the second via 720 also penetrate these other insulating layers.

[0073] In the display panel of this application, as Figures 2a to 2c As shown, the display panel includes a light-shielding layer 90, which is disposed on the side of the active portion 20 near the substrate 11. The orthographic projection of the first sidewall 22A on the light-shielding layer 90 is located within the light-shielding layer 90.

[0074] In this embodiment, the light-shielding layer 90 can be made of a material with light-shielding capabilities. For example, the light-shielding layer 90 can be an opaque metal. Since the first sidewall 22A of the channel portion 22 serves as the channel length in this application, it is necessary for the light-shielding layer 90 to be able to shield the first sidewall 22A from light. That is, the orthographic projection of the first sidewall 22A onto the light-shielding layer 90 is located within the light-shielding layer 90. With the above arrangement, the light-shielding layer 90 can block light incident from the substrate 11 side onto the channel portion 22, thereby preventing electrical degradation of the channel portion 22 after exposure to light.

[0075] Furthermore, in addition to shielding the first sidewall 22A, the light-shielding layer 90 can also simultaneously block the side surface of the gate 50 near the substrate 11, preventing light from entering the first sidewall 22A from the side after reflection or refraction, thereby improving the light-shielding effect of the light-shielding layer 90.

[0076] In the display panel of this application, as Figure 4a and Figure 4b As shown, a boss 13 is provided on the substrate 11, and an active part 20 is provided on the boss 13. The orthogonal projection of the active part 20 on the substrate 11 overlaps with the boss 13. In the direction perpendicular to the substrate 11, the sum of the thickness of the boss 13 and the thickness of the first contact part 21 is greater than or equal to the thickness of the gate insulating layer 60.

[0077] In this embodiment, as Figure 4a and Figure 4b As shown, a protrusion 13 is provided on the substrate 11. The protrusion 13 can be formed by a patterning process. For example, a buffer layer 12 can be provided on the substrate 11, and the protrusion 13 can be formed by patterning the buffer layer 12. In the direction perpendicular to the substrate 11, the sum of the thickness of the protrusion 13 and the thickness of the first contact portion 21 is greater than or equal to the thickness of the gate insulating layer 60. Since the gate 50 is disposed on the gate insulating layer 60, when the sum of the thickness of the protrusion 13 and the thickness of the first contact portion 21 is greater than or equal to the thickness of the gate insulating layer 60, the protrusion 13 can raise the channel portion 22, so that the surface of the gate 50 near the first sidewall 22A can cover the channel portion 22 in the thickness direction of the channel portion 22, thereby improving the control capability of the gate 50 over the channel portion 22 and improving the electrical performance of the thin film transistor.

[0078] In the display panel of this application, as Figure 5a and Figure 5b As shown, the display panel includes a second barrier layer 40, which is disposed on the side of the second contact portion 23 away from the substrate 11, and the orthographic projection of the second barrier layer 40 on the second contact portion 23 overlaps with the second contact portion 23.

[0079] In this embodiment, as Figure 5a and Figure 5bAs shown, by covering the second contact portion 23 with a second barrier layer 40, the second barrier layer 40 can be used to block ion penetration in the second contact portion 23. Specifically, the second contact portion 23 can be ion-doped after the second barrier layer 40 is formed. The material of the second barrier layer 40 can be inorganic, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The thickness of the second barrier layer 40 can be matched with the ion implantation parameters. Optionally, the thickness of the second barrier layer 40 is 100-2000 angstroms. With the above configuration, the channel portion 22 can be prevented from being heavily doped, thus forming a channel.

[0080] Meanwhile, since the active portion 20 comprises a three-layer stack of a first contact portion 21, a channel portion 22, and a second contact portion 23, compared to a conventional single-layer channel structure, the active portion 20 of this application requires more hydrogen replenishment. Therefore, the second barrier layer 40 can be made of silicon nitride material with a high hydrogen content, thereby enabling hydrogen to diffuse into the polycrystalline silicon layer to repair silicon dangling bonds and improve the electrical properties of the thin-film transistor during the hydrogenation process after ion doping.

[0081] like Figures 6a to 6c As shown, the manufacturing process of the display panel of this application will be described next using the first type of display panel as an example.

[0082] Step S10: Provide a substrate 11, and form a light-shielding layer 90 on the substrate 11 using a patterning process.

[0083] In step S20, a buffer layer 12 is formed on the light-shielding layer 90, and a first contact portion 21 is formed on the buffer layer 12 using a patterning process.

[0084] Step S30: A first barrier layer 30 is formed on the first contact portion 21 using a patterning process.

[0085] In step S40, a channel portion 22 and a second contact portion 23 are formed on the first barrier layer 30 using a patterning process.

[0086] The orthographic projections of the channel portion 22 and the second contact portion 23 on the substrate 11 overlap, thereby allowing the active portion 20 to be patterned using a single photomask, simplifying the manufacturing process of the display panel.

[0087] In step S50, a gate insulating layer 60 is formed on the active portion 20, and a gate 50 is formed on the gate insulating layer 60 using a patterning process. The gate 50 at least covers the first sidewall 22A of the channel portion 22.

[0088] In step S60, an interlayer insulating layer 80 is formed on the gate insulating layer 60 using a patterning process, and the via exposes the first contact portion 21 and the second contact portion 23.

[0089] In step S70, a source electrode 71 and a drain electrode 72 are formed in the interlayer insulating layer 80. The source electrode 71 and the drain electrode 72 fill the vias. The source electrode 71 is electrically connected to the first contact portion 21, and the drain electrode 72 is electrically connected to the second contact portion 23.

[0090] In this application, the patterning process includes steps such as coating photoresist, exposure, development, etching, and photoresist stripping. The patterning process can form the desired pattern on the film layer.

[0091] The manufacturing processes for the second, third, and fourth display panels are similar and will not be repeated here.

[0092] This application provides a display terminal, which includes the display panel described above.

[0093] In this embodiment, the display terminal can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0095] The above provides a detailed description of a display panel and display terminal provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: Substrate; An active portion is disposed on the substrate. The active portion includes a first contact portion, a channel portion, and a second contact portion stacked together. The channel portion is partially disposed on the side of the first contact portion facing away from the substrate, and the second contact portion is disposed on the side of the channel portion facing away from the substrate. On the substrate, the orthographic projection of the second contact portion overlaps with the orthographic projection of the channel portion, and the orthographic projection of the second contact portion partially overlaps with the orthographic projection of the first contact portion. In a direction perpendicular to the substrate, the portion of the first contact portion intersecting with the first contact portion is a first sub-portion, and the portion of the second contact portion intersecting with the first contact portion is a second sub-portion. A gate insulating layer is disposed on the side of the active portion away from the substrate; A gate is disposed on the side of the gate insulating layer opposite to the substrate. The active portion has a first sidewall, which is an inclined sidewall of the overlapping portion of the first contact portion, the channel portion, and the second contact portion. The gate covers at least the channel portion on the first sidewall on the gate insulating layer. A source-drain layer is disposed on the side of the active portion away from the substrate. The source-drain layer includes a source and a drain. The source is electrically connected to the first sub-part through a via, and the drain is electrically connected to the second sub-part through a via.

2. The display panel according to claim 1, characterized in that, The orthogonal projection of the gate onto the substrate covers a portion of the orthogonal projection of the first sidewall onto the substrate, and one end of the gate extends along the first sidewall to the active portion on the side surface opposite to the substrate, while the other end of the gate extends along the first sidewall to the substrate.

3. The display panel according to claim 2, characterized in that, The first contact portion extends along a first direction, and the second contact portion extends along a second direction, with the first direction and the second direction having a preset angle; the orthogonal projection of the first sidewall on the substrate extends along the second direction, and in the second direction, the length dimension of the gate is less than or equal to the length dimension of the first sidewall.

4. The display panel according to claim 3, characterized in that, The second contact portion includes a long portion along the second direction and a short portion along the first direction, the first sidewall is located on the inclined side of the short portion and extends along the second direction, and in the second direction, the length dimension of the gate is greater than the length dimension of the channel portion.

5. The display panel according to claim 3 or 4, characterized in that, The display panel includes a first barrier layer, which is disposed between the first contact portion and the channel portion; The first barrier layer covers the first sub-part, and the orthographic projection of the first sidewall on the substrate is spaced apart from the orthographic projection of the first barrier layer on the substrate.

6. The display panel according to claim 5, characterized in that, The via electrically connecting the source to the first sub-part is a first via, and the via electrically connecting the drain to the second sub-part is a second via. The first via is configured to penetrate the gate insulating layer and the first barrier layer, and the second via is configured to penetrate the gate insulating layer.

7. The display panel according to claim 1, characterized in that, The display panel includes a light-shielding layer disposed on the side of the active portion near the substrate, and the orthographic projection of the first sidewall of the channel portion onto the light-shielding layer is located within the light-shielding layer.

8. The display panel according to claim 1, characterized in that, The substrate has a protrusion, the active part is disposed on the protrusion, and the orthographic projection of the active part on the substrate overlaps with the protrusion; Wherein, in the direction perpendicular to the substrate, the sum of the thickness of the boss and the thickness of the first contact portion is greater than or equal to the thickness of the gate insulating layer.

9. The display panel according to claim 1, characterized in that, The display panel includes a second barrier layer, which is disposed on the side of the second contact portion away from the substrate, and the orthographic projection of the second barrier layer on the second contact portion overlaps with the second contact portion.

10. A display terminal, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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