signal generating circuit

Abstract

The present application provides a signal generating circuit and a signal generating method. The signal generating circuit comprises a first synchronization circuit configured to receive a beacon signal and a clock signal, and synchronize a first edge of the beacon signal and the clock signal to generate a first synchronization signal; a frequency division element configured to receive the clock signal and perform a frequency division operation on the clock signal to generate a frequency division signal, wherein an operating period of the frequency division signal is 50%; a second synchronization circuit configured to receive the first synchronization signal and the frequency division signal, and synchronize a second edge of the first synchronization signal and the frequency division signal to generate a second synchronization signal; and a combination circuit configured to receive the second synchronization signal and the frequency division signal, and perform an AND operation on the second synchronization signal and the frequency division signal to output the full period signal.

Description

Technical Field

[0001] This invention relates to the field of signal generation circuits, and in particular to a technology that can output multiple complete cycle signals within a predetermined time length. Background Technology

[0002] When sending test signals, it is often required to send test signals with several complete cycles within a predetermined time, such as the LFPS (Low Frequency Periodic Signaling) signal required by USB 3.0 and later specifications. However, when the period of the test signal changes, existing circuit designs often cannot meet the aforementioned requirements, resulting in incomplete cycle issues. Summary of the Invention

[0003] In view of this, some embodiments of the present invention provide a signal generation circuit and a signal generation method to improve the problems of the prior art.

[0004] One embodiment of the present invention provides a signal generation circuit for outputting multiple complete cycle signals within the signal duration of a beacon signal. The signal generation circuit includes a first synchronization circuit, a frequency division element, a second synchronization circuit, and a synthesis circuit. The first synchronization circuit is configured to receive the beacon signal and a clock signal, and synchronize the first signal edges of the beacon signal and the clock signal to generate a first synchronization signal; the frequency division element is configured to receive the clock signal and perform a frequency division operation on the clock signal to generate a frequency-divided signal, wherein the duty cycle of the frequency-divided signal is 50%; the second synchronization circuit is configured to receive the first synchronization signal and the frequency-divided signal, and synchronize the second signal edges of the first synchronization signal and the frequency-divided signal to generate a second synchronization signal; the synthesis circuit is configured to receive the second synchronization signal and the frequency-divided signal, and perform an AND operation on the second synchronization signal and the frequency-divided signal to output the complete cycle signals.

[0005] An embodiment of the present invention provides a signal generation method for outputting multiple complete cycle signals within the signal duration of a beacon signal. The signal generation method includes: synchronizing a first signal edge of a beacon signal and a clock signal via a first synchronization circuit to generate a first synchronization signal; performing a frequency division operation on the clock signal via a frequency division element to generate a frequency-divided signal, wherein the duty cycle of the frequency-divided signal is 50%; synchronizing a second signal edge of the first synchronization signal and the frequency-divided signal via a second synchronization circuit to generate a second synchronization signal; and performing an AND operation on the second synchronization signal and the frequency-divided signal via a synthesis circuit to output the complete cycle signals.

[0006] Based on the above, some embodiments of the present invention provide a signal generation circuit and a signal generation method that can output multiple complete cycle signals within a predetermined period by using a synchronization circuit and a frequency divider circuit. Attached Figure Description

[0007] Figure 1 This is a block diagram of a signal generation circuit according to an embodiment of the present invention.

[0008] Figure 2-1 This is a schematic diagram of the operation of the first synchronization circuit according to some embodiments of the present invention.

[0009] Figure 2-2 This is a schematic diagram of the operation of the first synchronization circuit according to some embodiments of the present invention.

[0010] Figure 3-1 This is a block diagram of a frequency divider circuit according to some embodiments of the present invention.

[0011] Figure 3-2 This is a block diagram of a frequency divider circuit according to some embodiments of the present invention.

[0012] Figure 4-1 This is a block diagram of a second synchronization circuit shown according to some embodiments of the present invention.

[0013] Figure 4-2 This is a schematic diagram of the operation of the second synchronization circuit according to some embodiments of the present invention.

[0014] Figure 4-3 This is a block diagram of a second synchronization circuit shown according to some embodiments of the present invention.

[0015] Figure 5-1 This is a block diagram of a second synchronization circuit shown according to some embodiments of the present invention.

[0016] Figure 5-2 This is a schematic diagram of the operation of the second synchronization circuit according to some embodiments of the present invention.

[0017] Figure 6 This is a block diagram of a signal generation circuit shown according to some embodiments of the present invention.

[0018] Figure 7 This is a schematic diagram of the operation of a signal generation circuit according to some embodiments of the present invention.

[0019] Figure 8 This is a block diagram of a signal generation circuit shown according to some embodiments of the present invention.

[0020] Figure 9 This is a schematic diagram of the operation of a signal generation circuit according to some embodiments of the present invention.

[0021] Figure 10 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0022] Figure 11 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0023] Figure 12 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0024] Figure 13 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0025] Figure 14 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0026] Figure 15 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0027] Figure 16 This is a flowchart of a signal generation method according to an embodiment of the present invention.

[0028] Symbol Explanation

[0029] 100: Signal generation circuit

[0030] 101: First Synchronization Circuit

[0031] 102: Frequency divider element

[0032] 103: Second Synchronization Circuit

[0033] 104: Synthetic Circuit

[0034] 201, 204, 701, 901: Beacon signals

[0035] 202, 205, 702, 902: Clock signals

[0036] 203, 502, 903, 206, 403, 703: First synchronization signals

[0037] 2021, 2022, 2051, 2052, 4041, 4042, 4051, 4052, 5031, 5032, 7021, 7022, 7041, 7042, 9021, 9022, 9041, 9042: Pulse

[0038] 2031, 2061, 4061, 5041, 7031, 7051, 9031, 9051: Start Time

[0039] 2032, 2062, 4062, 5042, 7032, 7052, 9032, 9052: End Time

[0040] 301, 602: First frequency divider element

[0041] 302, 608: Second frequency divider element

[0042] 303, 305, 401, 501, 601, 603, 605: Positive edge triggered D-type flip-flops (triggers)

[0043] 304, 604: Inverted gate (NAND gate)

[0044] 3031, 3051, 4011, 4071, 5011: Signal input terminals

[0045] 3032, 3052, 4012, 4072, 5012: Clock input terminals

[0046] 3033, 3043, 3053, 4013, 4073, 4073, 5013: Output terminals

[0047] 3034, 3054, 4014, 4074, 5014: Complementary output terminals

[0048] 3041, 3042: Input terminals

[0049] 402, 607: Reverse circuit

[0050] 4021, 6071: Inverters

[0051] 404, 503, 704, 904: Frequency divider signals

[0052] 405: Inverted frequency divider signal

[0053] 406, 504, 705, 905: Second synchronization signals

[0054] 407: Negative-edge triggered D-type flip-flop

[0055] 606: and gate

[0056] 6021: Frequency divider element (6 divider)

[0057] 706, 906: Complete cycle signals

[0058] S1001~S1004, S1101, S1201, S1301~S1302, S1401, S1501, S1601~S1602: Steps Detailed Implementation

[0059] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings. The thickness or dimensions of the elements in the drawings are exaggerated, omitted, or generalized for the understanding and reading of those skilled in the art. Furthermore, the dimensions of each element are not exactly their actual dimensions and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments in size, without affecting the technical effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention. The same reference numerals will be used to denote the same or similar elements in all the drawings.

[0060] Figure 1 This is a block diagram of a signal generation circuit according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1 The signal generation circuit 100 is used to output multiple complete cycle signals within the signal duration of the beacon signal. The signal generation circuit 100 includes a first synchronization circuit 101, a frequency divider element 102, a second synchronization circuit 103, and a synthesis circuit 104. The first synchronization circuit 101 receives the beacon signal and a clock signal, where the clock signal is a periodic pulse and the beacon signal is a high logic level signal. The clock signal can be generated by a clock management unit (CMU) external to the signal generation circuit 100 or by an oscillator external to the signal generation circuit 100. In a periodic pulse, the portion from low potential to high potential is called the positive edge of the periodic pulse; the portion from high potential to low potential is called the negative edge of the periodic pulse. A signal edge of a periodic pulse refers to either the positive edge or the negative edge of the periodic pulse. The portion of a pulse from low potential to high potential is called the positive edge of the pulse, and the portion from high potential to low potential is called the negative edge of the pulse.

[0061] The following describes in detail, with reference to the accompanying drawings, some embodiments of the signal generation method of the present invention and how the modules of the signal generation circuit 100 work together.

[0062] Figure 10 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 1 and Figure 10In step S1001, when the first synchronization circuit 101 receives the beacon signal, it synchronizes the beacon signal with one signal edge (e.g., a positive edge) of the clock signal. Here, the so-called synchronization of the beacon signal with one signal edge (e.g., a positive edge) by the first synchronization circuit 101 means that the first synchronization circuit 101 generates a first synchronization signal corresponding to the beacon signal based on the beacon signal, such that the start time of the first synchronization signal is aligned with the most recent positive edge of the clock signal that is closest to the start time of the beacon signal, and the end time of the first synchronization signal is aligned with the most recent positive edge of the clock signal that is closest to the end time of the beacon signal. Step S1001 will be further described below with reference to some embodiments of the present invention.

[0063] Figure 2-1 This is a schematic diagram of the operation of the first synchronization circuit according to some embodiments of the present invention. Figure 11 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 1 , Figure 2-1 and Figure 11 In this embodiment, the first synchronization circuit 101 includes a positive-edge triggered D-type flip-flop, and the aforementioned step S1001 includes step S1101. In step S1101, the aforementioned positive-edge triggered D-type flip-flop is configured such that its signal input terminal receives a beacon signal 201, and its clock input terminal receives a clock signal 202. Based on the positive-edge triggering characteristic of the positive-edge triggered D-type flip-flop, the positive-edge triggered D-type flip-flop in the first synchronization circuit 101 generates a first synchronization signal 203 based on the beacon signal 201. The start time 2031 of the first synchronization signal 203 is aligned with the positive edge of the clock signal 202 closest to the start time of the beacon signal 201 (the positive edge of pulse 2021), and the end time 2032 of the first synchronization signal 203 is aligned with the positive edge of the clock signal 202 closest to the end time of the beacon signal 201 (the positive edge of pulse 2022). In this embodiment, the beacon signal 201 is referred to as the positive edge synchronized with the clock signal 202.

[0064] Figure 2-2 This is a schematic diagram of the operation of the first synchronization circuit according to some embodiments of the present invention. Figure 12 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 1 , Figure 2-2 and Figure 12In this embodiment, the first synchronization circuit 101 includes a negative-edge triggered D-type flip-flop. The aforementioned step S1001 includes step S1201. In step S1201, the aforementioned negative-edge triggered D-type flip-flop is configured such that its signal input terminal receives a beacon signal 204, and its clock input terminal receives a clock signal 205. Based on the negative-edge triggering characteristic of the negative-edge triggered D-type flip-flop, the first synchronization circuit 101 generates a first synchronization signal 206 based on the beacon signal 204. The start time 2061 of the first synchronization signal 206 is aligned with the negative edge of the clock signal 205 closest to the start time of the beacon signal 204 (the negative edge of pulse 2051), and the end time 2062 of the first synchronization signal 206 is aligned with the negative edge of the clock signal 205 closest to the end time of the beacon signal 204 (the negative edge of pulse 2052). In this embodiment, the beacon signal 204 is referred to as the negative edge synchronized with the clock signal 205.

[0065] Please refer to the following: Figure 1 and Figure 10 In step S1002, the frequency divider 102 receives the clock signal and performs a frequency division operation on the clock signal to generate a frequency-divided signal, wherein the duty cycle of the frequency-divided signal is 50%. Step S1002 is further described below with reference to some embodiments of the present invention.

[0066] Figure 3-1 and Figure 3-2 This is a block diagram of a frequency divider circuit according to some embodiments of the present invention. Figure 13 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 3-1 , Figure 3-2 and Figure 13The frequency divider 102 includes a first frequency divider 301 and a second frequency divider 302. The first frequency divider 301 is a frequency divider. The first frequency divider 301 is used to receive a clock signal and reduce the frequency of the clock signal to generate a first frequency divider signal, wherein the frequency of the first frequency divider signal is twice the predetermined frequency of the frequency divider signal. The second frequency divider 302 is a divide-by-2 frequency divider. The second frequency divider 302 is configured to receive the first frequency divider signal and perform a divide-by-2 frequency division operation on the first frequency divider signal to generate the frequency divider signal. The aforementioned step S1002 includes steps S1601 and S1602. In step S1601, the first frequency divider 301 receives the clock signal and reduces the frequency of the clock signal to generate the first frequency divider signal, wherein, as mentioned above, the frequency of the first frequency divider signal is twice the predetermined frequency. In step S1602, the second frequency divider 302 receives the first frequency divider signal and performs a divide-by-2 frequency division operation on the first frequency divider signal to generate a frequency divider signal.

[0067] Please refer to the following: Figure 3-1 .exist Figure 3-1 In the illustrated embodiment, the second frequency divider 302 includes a positive-edge triggered D-type flip-flop 303 and a NAND gate 304. The clock input 3032 of the positive-edge triggered D-type flip-flop 303 is configured to receive the first frequency divider signal. The inputs 3041 and 3042 of the NAND gate 304 are configured to simultaneously receive the output of the output 3033 of the positive-edge triggered D-type flip-flop 303. The signal input 3031 of the positive-edge triggered D-type flip-flop 303 is configured to receive the output of the output 3043 of the NAND gate 304. The output signal of the complementary output 3034 of the positive-edge triggered D-type flip-flop 303 is not used in this embodiment. The output signal of the output 3043 of the NAND gate 304 serves as the frequency divider signal. It is worth noting that in... Figure 3-1 In the embodiment shown, the configuration of the second frequency divider 302 makes the duty cycle of the output signal of the output terminal 3043 of the reverse gate 304 50%, and therefore the duty cycle of the frequency divider signal is also 50%.

[0068] Please refer to the following: Figure 3-2 .exist Figure 3-2In the illustrated embodiment, the second frequency divider 302 includes a positive-edge triggered D-type flip-flop 305. The clock input 3052 of the positive-edge triggered D-type flip-flop 305 is configured to receive the first frequency divider signal. The signal input 3051 of the positive-edge triggered D-type flip-flop 305 is configured to receive the output signal of the complementary output 3054 of the positive-edge triggered D-type flip-flop 305. The output signal of the output 3053 of the positive-edge triggered D-type flip-flop 305 is not used in this embodiment. The output signal of the complementary output 3054 of the positive-edge triggered D-type flip-flop 305 serves as the frequency divider signal. It is worth noting that in... Figure 3-1 In the embodiment shown, the configuration of the second frequency divider 302 makes the duty cycle of the output signal of the complementary output terminal 3054 of the positive edge triggered D-type flip-flop 305 50%, and therefore the duty cycle of the frequency divider signal is also 50%.

[0069] Please refer to the following: Figure 1 and Figure 10 The second synchronization circuit 103 is configured to receive the first synchronization signal and the frequency-divided signal. In step S1003, the second signal edges of the first synchronization signal and the frequency-divided signal are synchronized via the second synchronization circuit 103 to generate a second synchronization signal. Step S1003 is further described below with reference to some embodiments of the present invention.

[0070] Figure 4-1 This is a block diagram of a second synchronization circuit shown according to some embodiments of the present invention. Figure 4-2 This is a schematic diagram of the operation of the second synchronization circuit according to some embodiments of the present invention. Figure 14 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 4-1 , Figure 4-2 and Figure 14 In this embodiment, the second signal edge of the aforementioned frequency divider signal is the negative edge of the frequency divider signal. That is, the second synchronization circuit 103 is to synchronize the first synchronization signal with the negative edge of the frequency divider signal.

[0071] like Figure 4-1 and Figure 4-2As shown, the second synchronization circuit 103 includes a positive-edge triggered D-type flip-flop 401 and an inverting circuit 402, wherein the inverting circuit 402 is composed of an inverter 4021. The aforementioned step S1003 includes steps S1301 and S1302. In step S1301, the inverter 4021 receives and inverts the frequency-divided signal 404 to generate an inverted frequency-divided signal 405. In step S1302, the signal input terminal 4011 of the positive-edge triggered D-type flip-flop 401 receives the first synchronization signal 403, and the clock input terminal 4012 of the positive-edge triggered D-type flip-flop 401 receives the inverted frequency-divided signal 405. Based on the positive-edge triggering characteristic of the positive-edge triggered D-type flip-flop, the first synchronization signal 403 is synchronized with the positive edge of the inverted frequency-divided signal 405, and the output terminal 4013 of the positive-edge triggered D-type flip-flop 401 generates a second synchronization signal 406. The complementary output 4014 of the positive-edge triggered D-type flip-flop 401 is not used here. That is, the start time 4061 of the second synchronization signal 406 is aligned with the positive edge of the inverted frequency divider signal 405 that is closest to the start time of the first synchronization signal 403 (the positive edge of pulse 4051), and the end time 4062 of the second synchronization signal 406 is aligned with the positive edge of the inverted frequency divider signal 405 that is closest to the end time of the first synchronization signal 403 (the positive edge of pulse 4052).

[0072] Since the reverse frequency divider signal 405 is the inverse of the frequency divider signal 404, the first synchronization signal 403 will be synchronized with the negative edge of the frequency divider signal 404. That is, as Figure 4-2 As shown, the start time 4061 of the second synchronization signal 406 is aligned with the negative edge of the frequency divider signal 404 that is closest to the start time of the first synchronization signal 403 (the negative edge of pulse 4041), and the end time 4062 of the second synchronization signal 406 is aligned with the negative edge of the frequency divider signal 404 that is closest to the end time of the first synchronization signal 403 (the negative edge of pulse 4042).

[0073] Figure 4-3 This is a block diagram of a second synchronization circuit shown according to some embodiments of the present invention. Figure 15 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 4-2 , Figure 4-3 and Figure 15 In this embodiment, the second signal edge of the aforementioned frequency divider signal is the negative edge of the frequency divider signal. That is, the second synchronization circuit 103 is to synchronize the first synchronization signal with the negative edge of the frequency divider signal.

[0074] like Figure 4-3As shown, the second synchronization circuit 103 includes a negative-edge triggered D-type flip-flop 407. The aforementioned step S1003 includes step S1401. In step S1401, the signal input terminal 4071 of the negative-edge triggered D-type flip-flop 407 receives the first synchronization signal 403, and the clock input terminal 4072 of the negative-edge triggered D-type flip-flop 407 is configured to receive the frequency divider signal 404. Based on the negative-edge triggered characteristic of the negative-edge triggered D-type flip-flop 407, the first synchronization signal 403 is synchronized with the negative edge of the frequency divider signal 404, and the output terminal 4073 of the negative-edge triggered D-type flip-flop 407 generates the second synchronization signal 406. The complementary output terminal 4074 of the negative-edge triggered D-type flip-flop 407 is not used in this embodiment.

[0075] Figure 5-1 This is a block diagram of a second synchronization circuit shown according to some embodiments of the present invention. Figure 5-2 This is a schematic diagram of the operation of the second synchronization circuit according to some embodiments of the present invention. Figure 16 This is a flowchart illustrating a signal generation method according to an embodiment of the present invention. Please also refer to... Figure 5-1 , Figure 5-2 and Figure 16 In this embodiment, the second signal edge of the aforementioned frequency divider signal is the positive edge of the frequency divider signal. That is, the second synchronization circuit 103 is to synchronize the first synchronization signal with the positive edge of the frequency divider signal.

[0076] like Figure 5-1 As shown, the second synchronization circuit 103 includes a positive-edge triggered D-type flip-flop 501. The aforementioned step S1003 includes step S1501. In step S1501, the signal input terminal 5011 of the positive-edge triggered D-type flip-flop 501 receives the first synchronization signal 502, and the clock input terminal 5012 of the positive-edge triggered D-type flip-flop 501 receives the frequency division signal 503. Based on the positive-edge triggering characteristic of the positive-edge triggered D-type flip-flop 501, the first synchronization signal 502 is synchronized with the positive edge of the frequency division signal 503, and the output terminal 5013 of the positive-edge triggered D-type flip-flop 501 generates the second synchronization signal 504. That is, the start time 5041 of the second synchronization signal 504 is aligned with the positive edge of the frequency divider signal 503 that is closest to the start time of the first synchronization signal 502 (the positive edge of pulse 5031), and the end time 5042 of the second synchronization signal 504 is aligned with the positive edge of the frequency divider signal 503 that is closest to the end time of the first synchronization signal 502 (the positive edge of pulse 5032). The complementary output terminal 5014 of the positive edge triggered D-type flip-flop 501 is not used in this embodiment.

[0077] Please refer to the following: Figure 1 and Figure 10In step S1004, the synthesis circuit 104 receives the second synchronization signal and the frequency divider signal, and performs an AND operation on the second synchronization signal and the frequency divider signal to output a complete periodic signal. In some embodiments of the present invention, the synthesis circuit 104 includes an AND gate, which performs an AND operation on the second synchronization signal and the frequency divider signal to output a complete periodic signal. It is worth noting that performing an AND operation on the second synchronization signal and the frequency divider signal via an AND gate can avoid the problem of timing skew in the output complete periodic signal.

[0078] Figure 6 This is a block diagram of a signal generation circuit shown according to some embodiments of the present invention. Figure 7 This is a schematic diagram of the signal generation circuit operation according to some embodiments of the present invention. Please also refer to... Figure 1 , Figure 6 , Figure 7 and Figure 10 In this embodiment, Figure 6 The signal generation circuit shown is used to generate the LFPS (Low Frequency Periodic Signaling) signals required for USB 3.0 and above specifications. The beacon signal 701 has a signal duration of 100ns, and the clock signal 702 is a periodic pulse with a frequency of 250MHz and a period of 4ns. The circuit specification requires outputting two complete cycle signals within the signal duration of the beacon signal 701, each with a period of 48ns. Since the period of the frequency divider signal is the same as the period of the complete cycle signal, the divisor of the frequency divider element 102 is chosen to be 12. With this configuration, the period of the frequency divider signal will be 48ns, and the product of the period of the frequency divider signal and the number of complete cycle signals is 48*2 = 96, which is less than the signal duration of the beacon signal 701 (100ns). Therefore, the first frequency divider 602 in the frequency divider 102 is configured to include a divide-by-6 frequency divider 6021, and the second frequency divider 608 in the frequency divider 102 includes a divide-by-2 frequency divider composed of a positive edge triggered D-type flip-flop 603 and a reverse gate 604.

[0079] like Figure 6 As shown, in this embodiment, the first synchronization circuit 101 includes a positive-edge triggered D-type flip-flop 601. The second synchronization circuit 103 includes a positive-edge triggered D-type flip-flop 605 and an inverting circuit 607, wherein the inverting circuit 607 is composed of an inverter 6071. The combining circuit 104 includes a gate 606.

[0080] In step S1001, the positive edge triggered D-type flip-flop 601 generates a first synchronization signal 703 based on the beacon signal 701, such that the start time 7031 of the first synchronization signal 703 is aligned with the positive edge of the clock signal 702 that is closest to the start time of the beacon signal 701 (the positive edge of pulse 7021), and the end time 7032 of the first synchronization signal 703 is aligned with the positive edge of the clock signal 702 that is closest to the end time of the beacon signal 701 (the positive edge of pulse 7022).

[0081] In step S1002, the frequency divider 102 receives the clock signal 702 and performs a frequency division operation on the clock signal 702 to generate a frequency divider signal 704, wherein the working period of the frequency divider signal 704 is 50%.

[0082] In step S1003, the inverter 6071 receives and inverts the frequency divider signal 704 to generate an inverted frequency divider signal. The first synchronization signal 703 is received at the signal input terminal of the positive-edge triggered D-type flip-flop 605, and the inverted frequency divider signal is received at the clock input terminal of the positive-edge triggered D-type flip-flop 605. Based on the positive-edge triggering characteristic of the positive-edge triggered D-type flip-flop 605, the first synchronization signal 703 is synchronized with the positive edge of the inverted frequency divider signal, and the output terminal of the positive-edge triggered D-type flip-flop 605 generates a second synchronization signal 705. Since the inverted frequency divider signal is the inverse of the frequency divider signal 704, the first synchronization signal 703 is synchronized with the negative edge of the frequency divider signal 704. That is, as... Figure 7 As shown, the start time 7051 of the second synchronization signal 705 is aligned with the negative edge of the frequency divider signal 704 that is closest to the start time 7031 of the first synchronization signal 703 (the negative edge of pulse 7041), and the end time 7052 of the second synchronization signal 705 is aligned with the negative edge of the frequency divider signal 704 that is closest to the end time 7032 of the first synchronization signal 703 (the negative edge of pulse 7042).

[0083] In step S1004, the second synchronization signal 705 and the frequency divider signal 704 are received by the AND gate 606 in the synthesis circuit 104. The AND gate 606 in the synthesis circuit 104 performs an AND operation on the second synchronization signal 705 and the frequency divider signal 704 to output a complete periodic signal 706.

[0084] Figure 8 This is a block diagram of a signal generation circuit shown according to some embodiments of the present invention. Figure 9 This is a schematic diagram of the signal generation circuit operation according to some embodiments of the present invention. Please also refer to... Figure 1 , Figure 8 , Figure 9 and Figure 10In this embodiment, the signal duration of beacon signal 901 is 100ns, and clock signal 902 is a periodic pulse with a frequency of 250MHz and a period of 4ns. The circuit specification requires outputting two complete cycle signals within the signal duration of beacon signal 901, each with a period of 48ns. Since the period of the frequency divider signal is the same as the period of the complete cycle signal, the divisor of the frequency divider element 102 is chosen to be 12. Under this configuration, the period of the frequency divider signal will be 48ns, and the product of the period of the frequency divider signal and the number of complete cycle signals is 48*2 = 96, which is less than the signal duration of beacon signal 701 (100ns). Therefore, the first frequency divider 602 in the frequency divider 102 is configured to include a divide-by-6 frequency divider 6021, and the second frequency divider 608 in the frequency divider 102 includes a divide-by-2 frequency divider composed of a positive edge triggered D-type flip-flop 603 and a reverse gate 604.

[0085] like Figure 8 As shown, the first synchronization circuit 101 includes a positive-edge triggered D-type flip-flop 601. The second synchronization circuit 103 includes a positive-edge triggered D-type flip-flop 605. The combining circuit 104 includes a gate 606.

[0086] In step S1001, the positive edge triggered D-type flip-flop 601 generates a first synchronization signal 903 based on the beacon signal 901, such that the start time 9031 of the first synchronization signal 903 is aligned with the positive edge of the clock signal 902 that is closest to the start time of the beacon signal 901 (the positive edge of pulse 9021), and the end time 9032 of the first synchronization signal 903 is aligned with the positive edge of the clock signal 902 that is closest to the end time of the beacon signal 901 (the positive edge of pulse 9022).

[0087] In step S1002, the frequency divider 102 receives the clock signal 902 and performs a frequency division operation on the clock signal 902 to generate a frequency divider signal 904, wherein the working period of the frequency divider signal 904 is 50%.

[0088] In step S1003, the first synchronization signal 903 is received at the signal input terminal of the positive-edge triggered D-type flip-flop 605, and the frequency divider signal 904 is received at the clock input terminal of the positive-edge triggered D-type flip-flop 605. Based on the positive-edge triggering characteristic of the positive-edge triggered D-type flip-flop 605, the first synchronization signal 903 is synchronized with the positive edge of the frequency divider signal 904, and the output terminal of the positive-edge triggered D-type flip-flop 605 generates a second synchronization signal 905. That is, as... Figure 9As shown, the start time 9051 of the second synchronization signal 905 is aligned with the positive edge of the frequency divider signal 904 that is closest to the start time 9031 of the first synchronization signal 903 (the positive edge of pulse 9041), and the end time 9052 of the second synchronization signal 905 is aligned with the positive edge of the frequency divider signal 904 that is closest to the end time 9032 of the first synchronization signal 903 (the positive edge of pulse 9042).

[0089] In step S1004, the second synchronization signal 905 and the frequency divider signal 904 are received by the AND gate 606 in the synthesis circuit 104. The AND gate 606 in the synthesis circuit 104 performs an AND operation on the second synchronization signal 905 and the frequency divider signal 904 to output a complete period signal 906.

[0090] Based on the above, some embodiments of the present invention provide a signal generation circuit and a signal generation method that can output complete periodic signals within a predetermined period by using a synchronization circuit and a frequency divider circuit.

[0091] Although the technical content of the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any changes and modifications made by those skilled in the art without departing from the concept of the present invention should be included within the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A signal generation circuit for outputting multiple complete cycle signals within a signal time length of a beacon signal, the signal generation circuit comprising: A first synchronization circuit is configured to receive the beacon signal and a clock signal, and synchronize a first signal edge of the beacon signal and the clock signal to generate a first synchronization signal; A frequency divider is configured to receive the clock signal and perform a frequency divider operation on the clock signal to generate a frequency divider signal, wherein a duty cycle of the frequency divider signal is 50%. A second synchronization circuit, configured to receive the first synchronization signal and the frequency-divided signal, and synchronize a second signal edge of the first synchronization signal and the frequency-divided signal to generate a second synchronization signal; and A synthesis circuit is configured to receive the second synchronization signal and the frequency divider signal, and to perform an AND operation on the second synchronization signal and the frequency divider signal to output the complete periodic signal.

2. The signal generation circuit of claim 1, wherein a divisor of the frequency divider is configured such that the product of a period of the frequency divider signal and a number of the plurality of complete period signals is less than or equal to the signal duration.

3. The signal generation circuit of claim 1, wherein the first signal edge of the clock signal is a positive edge of the clock signal, the first synchronization circuit includes a positive edge triggered D-type flip-flop, a signal input terminal of the positive edge triggered D-type flip-flop is configured to receive the beacon signal, and a clock input terminal of the positive edge triggered D-type flip-flop is configured to receive the clock signal, so that the positive edge triggered D-type flip-flop synchronizes the beacon signal with the positive edge of the clock signal to generate the first synchronization signal.

4. The signal generation circuit of claim 1, wherein the first signal edge of the clock signal is a negative edge of the clock signal, and the first synchronization circuit includes a negative edge triggered D-type flip-flop, wherein a signal input terminal of the negative edge triggered D-type flip-flop is configured to receive the beacon signal, and a clock input terminal of the negative edge triggered D-type flip-flop is configured to receive the clock signal, so that the negative edge triggered D-type flip-flop synchronizes the beacon signal and the negative edge of the clock signal to generate the first synchronization signal.

5. The signal generation circuit as described in claim 1, wherein, The second signal edge of the frequency divider signal is a negative edge of the frequency divider signal, and the second synchronization circuit includes: A positive-edge triggered D-type flip-flop; and A reverse circuit; The inverting circuit is configured to receive and invert the frequency divider signal to generate an inverted frequency divider signal. A signal input terminal of the positive edge triggered D-type flip-flop is configured to receive the first synchronization signal, and a clock input terminal of the positive edge triggered D-type flip-flop is configured to receive the inverted frequency divider signal, so that the positive edge triggered D-type flip-flop synchronizes the first synchronization signal with the negative edge of the frequency divider signal to generate the second synchronization signal.

6. The signal generation circuit as described in claim 1, wherein, The second signal edge of the frequency divider signal is a negative edge of the frequency divider signal. The second synchronization circuit includes a negative edge triggered D-type flip-flop, wherein a signal input terminal of the negative edge triggered D-type flip-flop is configured to receive the first synchronization signal, and a clock input terminal of the negative edge triggered D-type flip-flop is configured to receive the frequency divider signal, so that the negative edge triggered D-type flip-flop synchronizes the first synchronization signal and the negative edge of the frequency divider signal to generate the second synchronization signal.

7. The signal generation circuit as described in claim 1, wherein, The second signal edge of the frequency divider signal is a positive edge of the frequency divider signal. The second synchronization circuit includes a positive edge triggered D-type flip-flop, wherein a signal input terminal of the positive edge triggered D-type flip-flop is configured to receive the first synchronization signal, and a clock input terminal of the positive edge triggered D-type flip-flop is configured to receive the frequency divider signal, so that the positive edge triggered D-type flip-flop synchronizes the first synchronization signal with the positive edge of the frequency divider signal to generate the second synchronization signal.

8. The signal generation circuit of claim 1, wherein the frequency divider comprises a first frequency divider and a second frequency divider, wherein the first frequency divider is a frequency divider configured to receive the clock signal and reduce a frequency of the clock signal to generate a first frequency divider signal, wherein a frequency of the first frequency divider signal is twice a predetermined frequency; the second frequency divider is a divide-by-two frequency divider configured to receive the first frequency divider signal and perform a divide-by-two frequency divider operation on the first frequency divider signal to generate the frequency divider signal.

9. The signal generation circuit of claim 8, wherein the second frequency divider element comprises a positive edge triggered D-type flip-flop and a reverse gate, wherein a clock input terminal of the positive edge triggered D-type flip-flop is configured to receive the first frequency divider signal, the two input terminals of the reverse gate are configured to simultaneously receive an output of the positive edge triggered D-type flip-flop, a signal input terminal of the positive edge triggered D-type flip-flop is configured to receive an output of the reverse gate, and the output of the reverse gate serves as the frequency divider signal.

10. The signal generation circuit of claim 1, wherein the synthesis circuit includes an AND gate that performs the AND operation on the second synchronization signal and the frequency divider signal to output the plurality of complete cycle signals.

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