Column bus high speed readout circuit for CMOS image sensor

Abstract

The application discloses a column bus high-speed reading circuit applied to a CMOS image sensor, which comprises a current sampling circuit, an input end of the current sampling circuit is connected with a column bus output signal V OUT , and output ends of the current sampling circuit are respectively connected with input ends of a falling time acceleration circuit and a rising time acceleration circuit; and output ends of the rising time acceleration circuit and the falling time acceleration circuit are respectively connected with the column bus output signal V OUT . The application solves the problem of slow column bus signal establishment time in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of CMOS image sensor analog technology, specifically relating to a high-speed readout circuit for column bus applied to CMOS image sensors. Background Technology

[0002] CMOS image sensors have garnered significant attention due to their advantages of low power consumption and high imaging speed. With the rapid development of CMOS image sensor technology, higher demands are being placed on their resolution and frame rate. Increased resolution means a larger CMOS image sensor array size, which significantly enhances parasitic effects on the column bus and slows down column bus signal settling time. Furthermore, as resolution increases, the amount of image data also increases, requiring even faster column bus settling times.

[0003] Increased resolution leads to slower column bus signal settling time, while the system requires even faster column bus signal settling time. This inherent contradiction means that the required settling time for the column bus signal becomes a key bottleneck limiting frame rate improvements in CMOS image sensors. However, currently reported solutions have not effectively addressed this issue. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed readout circuit for column bus in CMOS image sensors, which solves the problem of slow column bus signal setup time in the prior art.

[0005] The technical solution adopted in this invention is a high-speed readout circuit for the column bus of a CMOS image sensor, including a current sampling circuit, wherein the input terminal of the current sampling circuit is connected to the column bus output signal V. OUT The output of the current sampling circuit is connected to the input of the fall time acceleration circuit and the rise time acceleration circuit, respectively; the output of each of the rise time acceleration circuit and the fall time acceleration circuit is connected to the column bus output signal V. OUT .

[0006] The invention is further characterized in that,

[0007] The specific structure of the current sampling circuit is as follows: it includes a sampling capacitor C1, and the upper plate of the sampling capacitor C1 is connected to the output bus to output signal V. OUT The lower plate of sampling capacitor C1 is connected to the upper end V of sampling resistor R1. IN The lower end of the sampling resistor R1 is connected to the reference voltage V. REF When the column bus signal is in the rising or falling phase, the sampling capacitor generates a charging current or a discharging current. The charging current or discharging current generates a voltage signal through the sampling resistor, thereby completing the sampling of the column bus current.

[0008] The specific structure of the fall-time acceleration circuit is as follows: it includes a comparator CMP1, the non-inverting input of which is connected to the reference voltage V. REF The inverting input of comparator CMP1 is connected to the output V of the current sampling circuit. IN The output of comparator CMP1 is connected to the control terminals of MOSFETs MN2 and MN3, the control terminal of MOSFET MN1 is connected to the reset signal RST, and the input terminal of MOSFET MN1 is connected to the reference voltage V. CM The output terminal of MOSFET MN1 is connected to the output terminals of MOSFETs MN2 and MN3, the input terminal of MOSFET MN4, and the upper plate of capacitor C2. The input terminal of MOSFET MN2 is connected to current source I1, and the input terminal of MOSFET MN3 is connected to the column bus output signal V. OUT The lower plate of capacitor C2 is connected to the output terminal of MOSFET MN4. The current sampling circuit output is detected by comparator CMP1. When the output of comparator CMP1 is high, the fall time acceleration circuit outputs discharge current, thereby shortening the fall settling time of the column bus signal.

[0009] The specific structure of the rise time acceleration circuit is as follows: it includes comparator CMP2, and the non-inverting input terminal of comparator CMP2 is connected to the reference voltage V. REF The inverting input of comparator CMP2 is connected to the output V of the current sampling circuit. IN The output of comparator CMP2 is connected to the control terminals of MP2 and MP3, the control terminal of MP1 is connected to the reset signal RST1, and the input terminal of MOSFET MP1 is connected to the reference voltage V. CM1 The output terminal of MOSFET MP1 is connected to the output terminals of MOSFETs MP2 and MP3, the input terminal of MOSFET MP4, and the upper plate of capacitor C3. The input terminal of MOSFET MP2 is connected to current source I2, and the input terminal of MOSFET MP3 is connected to the column bus output signal V. OUT The lower plate of capacitor C3 is connected to the lower output terminal of MOSFET MP4. The current sampling circuit output is detected by comparator CMP2. When the output of comparator CMP2 is low, the rise time acceleration circuit outputs charging current, thereby shortening the rise time of the column bus signal.

[0010] The beneficial effects of this invention are that the high-speed readout circuit for the column bus of a CMOS image sensor has a simple circuit structure, introduces almost no additional power consumption, and is compatible with current mainstream CMOS image sensors. Compared with traditional CMOS image sensor column bus readout schemes, the circuit proposed in this invention can shorten the column bus signal setup time by several times, solving the problem of excessively long column bus signal setup time in ultra-large area CMOS image sensors, and effectively improving the frame rate of ultra-large area CMOS image sensors. Attached Figure Description

[0011] Figure 1 This is a circuit structure diagram of the high-speed readout circuit of the column bus of the present invention applied to a CMOS image sensor;

[0012] Figure 2 This is a schematic diagram illustrating the high-speed readout circuit of the present invention. Detailed Implementation

[0013] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0014] This invention is applied to the high-speed readout circuit of the column bus in a CMOS image sensor, and its structure is as follows: Figure 1 As shown, it includes a current sampling circuit, the input of which is connected to the column bus output signal V. OUT The output of the current sampling circuit is connected to the input of the fall time acceleration circuit and the rise time acceleration circuit, respectively; the output of each of the rise time acceleration circuit and the fall time acceleration circuit is connected to the column bus output signal V. OUT .

[0015] The specific structure of the current sampling circuit is as follows: it includes a sampling capacitor C1, and the upper plate of the sampling capacitor C1 is connected to the output bus to output signal V. OUT The lower plate of sampling capacitor C1 is connected to the upper end V of sampling resistor R1. IN The lower end of the sampling resistor R1 is connected to the reference voltage V. REF When the column bus signal is in the rising or falling phase, the sampling capacitor generates a charging current or a discharging current. The charging current or discharging current generates a voltage signal through the sampling resistor, thereby completing the sampling of the column bus current.

[0016] The specific structure of the fall-time acceleration circuit is as follows: it includes a comparator CMP1, the non-inverting input of which is connected to the reference voltage V. REF The inverting input of comparator CMP1 is connected to the output V of the current sampling circuit. IN The output of comparator CMP1 is connected to the control terminals of MOSFETs MN2 and MN3, the control terminal of MOSFET MN1 is connected to the reset signal RST, and the input terminal of MOSFET MN1 is connected to the reference voltage V. CM The output terminal of MOSFET MN1 is connected to the output terminals of MOSFETs MN2 and MN3, the input terminal of MOSFET MN4, and the upper plate of capacitor C2. The input terminal of MOSFET MN2 is connected to current source I1, and the input terminal of MOSFET MN3 is connected to the column bus output signal V. OUT The lower plate of capacitor C2 is connected to the output terminal of MOSFET MN4. The current sampling circuit output is detected by comparator CMP1. When the output of comparator CMP1 is high, the fall time acceleration circuit outputs discharge current, thereby shortening the fall settling time of the column bus signal.

[0017] The specific structure of the rise time acceleration circuit is as follows: it includes comparator CMP2, and the non-inverting input terminal of comparator CMP2 is connected to the reference voltage V. REF The inverting input of comparator CMP2 is connected to the output V of the current sampling circuit. IN The output of comparator CMP2 is connected to the control terminals of MP2 and MP3, the control terminal of MP1 is connected to the reset signal RST1, and the input terminal of MOSFET MP1 is connected to the reference voltage V. CM1 The output terminal of MOSFET MP1 is connected to the output terminals of MOSFETs MP2 and MP3, the input terminal of MOSFET MP4, and the upper plate of capacitor C3. The input terminal of MOSFET MP2 is connected to current source I2, and the input terminal of MOSFET MP3 is connected to the column bus output signal V. OUT The lower plate of capacitor C3 is connected to the lower output terminal of MOSFET MP4. The current sampling circuit output is detected by comparator CMP2. When the output of comparator CMP2 is low, the rise time acceleration circuit outputs charging current, thereby shortening the rise time of the column bus signal.

[0018] Combined with appendix Figure 2 Describe the entire circuit's operation process in detail.

[0019] Since the readout method of the ultra-large area CMOS image sensor is row-by-row readout, the working process of the column bus high-speed readout circuit is described using one row as an example.

[0020] At the start of each line time, RST is high and RST1 is low. At this time, the voltages on the upper plates of capacitors C2 and C3 are reset to V. CM With V CM1 After the reset operation is completed, RST goes low and RST1 goes high. The circuit then enters the column bus signal acceleration phase.

[0021] The column bus signal acceleration phase is described next. During the column bus acceleration phase, as the column bus transitions from low to high, the lower plate of the sampling capacitor will generate a signal from V... REF To V IN The current at this time V IN Voltage less than V REF When the comparator CMP1 output terminal CN flips to a high level, MN2 and MN3 turn on, and current source I1 discharges capacitor C2, initiating the acceleration process. At this time, the voltage across the upper plate of the capacitor changes from V... CM As the current drops to 0, MN4 outputs a slowly decreasing discharge current to the column bus output terminal V. OUT While accelerating the process, ensure the stability of the entire system.

[0022] During the column bus acceleration phase, when the column bus changes from high to low, the lower plate of the sampling capacitor will generate a voltage drop from V... IN To V REFThe current at this time V REF Voltage less than V IN When the comparator CMP2 output CP flips to low, MP2 and MP3 turn on, and current source I2 discharges capacitor C3, initiating the acceleration process. At this time, the voltage across the upper plate of the capacitor changes from V... CM1 As the voltage rises to the power supply voltage, the MP4 outputs a slowly decreasing charging current to the column bus output terminal V. OUT Then, by repeating the above operation continuously within each row time, the adaptive acceleration of the column bus signal can be completed.

[0023] Example 1

[0024] This invention is applied to the high-speed readout circuit of the column bus in a CMOS image sensor, and its structure is as follows: Figure 1 As shown, it includes a current sampling circuit, the input of which is connected to the column bus output signal V. OUT The output of the current sampling circuit is connected to the input of the fall time acceleration circuit and the rise time acceleration circuit, respectively; the output of each of the rise time acceleration circuit and the fall time acceleration circuit is connected to the column bus output signal V. OUT .

[0025] The specific structure of the current sampling circuit is as follows: it includes a sampling capacitor C1, and the upper plate of the sampling capacitor C1 is connected to the output bus to output signal V. OUT The lower plate of sampling capacitor C1 is connected to the upper end V of sampling resistor R1. IN The lower end of the sampling resistor R1 is connected to the reference voltage V. REF When the column bus signal is in the rising or falling phase, the sampling capacitor generates a charging current or a discharging current. The charging current or discharging current generates a voltage signal through the sampling resistor, thereby completing the sampling of the column bus current.

[0026] Example 2

[0027] This invention is applied to the high-speed readout circuit of the column bus in a CMOS image sensor, and its structure is as follows: Figure 1 As shown, it includes a current sampling circuit, the input of which is connected to the column bus output signal V. OUT The output of the current sampling circuit is connected to the input of the fall time acceleration circuit and the rise time acceleration circuit, respectively; the output of each of the rise time acceleration circuit and the fall time acceleration circuit is connected to the column bus output signal V. OUT .

[0028] The specific structure of the fall-time acceleration circuit is as follows: it includes a comparator CMP1, the non-inverting input of which is connected to the reference voltage V. REF The inverting input of comparator CMP1 is connected to the output V of the current sampling circuit. INThe output of comparator CMP1 is connected to the control terminals of MOSFETs MN2 and MN3, the control terminal of MOSFET MN1 is connected to the reset signal RST, and the input terminal of MOSFET MN1 is connected to the reference voltage V. CM The output terminal of MOSFET MN1 is connected to the output terminals of MOSFETs MN2 and MN3, the input terminal of MOSFET MN4, and the upper plate of capacitor C2. The input terminal of MOSFET MN2 is connected to current source I1, and the input terminal of MOSFET MN3 is connected to the column bus output signal V. OUT The lower plate of capacitor C2 is connected to the output terminal of MOSFET MN4. The current sampling circuit output is detected by comparator CMP1. When the output of comparator CMP1 is high, the fall time acceleration circuit outputs discharge current, thereby shortening the fall settling time of the column bus signal.

[0029] Example 3

[0030] This invention is applied to the high-speed readout circuit of the column bus in a CMOS image sensor, and its structure is as follows: Figure 1 As shown, it includes a current sampling circuit, the input of which is connected to the column bus output signal V. OUT The output of the current sampling circuit is connected to the input of the fall time acceleration circuit and the rise time acceleration circuit, respectively; the output of each of the rise time acceleration circuit and the fall time acceleration circuit is connected to the column bus output signal V. OUT .

[0031] The specific structure of the current sampling circuit is as follows: it includes a sampling capacitor C1, and the upper plate of the sampling capacitor C1 is connected to the output bus to output signal V. OUT The lower plate of sampling capacitor C1 is connected to the upper end V of sampling resistor R1. IN The lower end of the sampling resistor R1 is connected to the reference voltage V. REF When the column bus signal is in the rising or falling phase, the sampling capacitor generates a charging current or a discharging current. The charging current or discharging current generates a voltage signal through the sampling resistor, thereby completing the sampling of the column bus current.

[0032] The specific structure of the rise time acceleration circuit is as follows: it includes comparator CMP2, and the non-inverting input terminal of comparator CMP2 is connected to the reference voltage V. REF The inverting input of comparator CMP2 is connected to the output V of the current sampling circuit. IN The output of comparator CMP2 is connected to the control terminals of MP2 and MP3, the control terminal of MP1 is connected to the reset signal RST1, and the input terminal of MOSFET MP1 is connected to the reference voltage V. CM1The output terminal of MOSFET MP1 is connected to the output terminals of MOSFETs MP2 and MP3, the input terminal of MOSFET MP4, and the upper plate of capacitor C3. The input terminal of MOSFET MP2 is connected to current source I2, and the input terminal of MOSFET MP3 is connected to the column bus output signal V. OUT The lower plate of capacitor C3 is connected to the lower output terminal of MOSFET MP4. The current sampling circuit output is detected by comparator CMP2. When the output of comparator CMP2 is low, the rise time acceleration circuit outputs charging current, thereby shortening the rise time of the column bus signal.

Claims

1. A high-speed readout circuit for a column bus applied to a CMOS image sensor, characterized in that, Includes a current sampling circuit, the input of which is connected to the column bus to output signal V. OUT The output of the current sampling circuit is connected to the input of the fall time acceleration circuit and the rise time acceleration circuit, respectively; the rise time acceleration circuit and the fall time acceleration circuit are each connected to the output signal V of the column bus. OUT ; The specific structure of the current sampling circuit is as follows: it includes a sampling capacitor C1, and the upper plate of the sampling capacitor C1 is connected to the bus to output a signal V. OUT The lower plate of sampling capacitor C1 is connected to the upper terminal V of sampling resistor R1. IN The lower end of the sampling resistor R1 is connected to the reference voltage V. REF When the column bus signal is in the rising or falling phase, the sampling capacitor generates a charging current or a discharging current. The charging current or discharging current generates a voltage signal through the sampling resistor, thereby completing the sampling of the column bus current. The specific structure of the fall time acceleration circuit is as follows: it includes a comparator CMP1, the non-inverting input terminal of which is connected to a reference voltage V. REF The inverting input of comparator CMP1 is connected to the output V of the current sampling circuit. IN The output of comparator CMP1 is connected to the control terminals of NMOS transistors MN2 and MN3. The control terminal of NMOS transistor MN1 is connected to the reset signal RST. The input terminal of NMOS transistor MN1 is connected to the reference voltage V. CM The output terminal of NMOS transistor MN1 is connected to the output terminal of NMOS transistor MN2, the control terminal of NMOS transistor MN4, and the upper plate of capacitor C2. The output terminal of NMOS transistor MN3 is connected to the input terminal of NMOS transistor MN4. The input terminal of NMOS transistor MN2 is connected to current source I1, and the input terminal of NMOS transistor MN3 is connected to the column bus output signal V. OUT ; The lower plate of capacitor C2 is connected to the output terminal of NMOS transistor MN4. The current sampling circuit output is detected by comparator CMP1. When the output of comparator CMP1 is high, the fall time acceleration circuit outputs discharge current, thereby shortening the fall settling time of the column bus signal. The specific structure of the rise time acceleration circuit is as follows: it includes a comparator CMP2, the non-inverting input of which is connected to a reference voltage V. REF The inverting input of comparator CMP2 is connected to the output V of the current sampling circuit. IN The output of comparator CMP2 is connected to the control terminals of PMOS transistors MP2 and MP3. The control terminal of PMOS transistor MP1 is connected to the reset signal RST1. The input terminal of PMOS transistor MP1 is connected to the reference voltage V. CM1 The output terminal of PMOS transistor MP1 is connected to the output terminal of PMOS transistor MP2, the control terminal of PMOS transistor MP4, and the upper plate of capacitor C3. The output terminal of PMOS transistor MP3 is connected to the input terminal of PMOS transistor MP4. The input terminal of PMOS transistor MP2 is connected to current source I2, and the input terminal of PMOS transistor MP3 is connected to the column bus output signal V. OUT ; The lower plate of capacitor C3 is connected to the lower output terminal of PMOS transistor MP4. The current sampling circuit output is detected by comparator CMP2. When the output of comparator CMP2 is low, the rise time acceleration circuit outputs charging current, thereby shortening the rise time of the column bus signal.

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