Method for forming semiconductor structure and method for forming SRAM memory

Abstract

A method for forming a semiconductor structure and a method for forming an SRAM memory are disclosed. The semiconductor structure formation method includes: providing a substrate; forming a first patterned material layer on the substrate; forming a first sidewall and a sacrificial structure on the first patterned material layer, wherein the size of the sacrificial structure is larger than the size of the first sidewall; implanting dopant ions into the first patterned material layer to form a first doped region at the bottom of the first sidewall and a second doped region at the bottom of the sacrificial structure, wherein the dopant ion concentration in the first doped region is greater than the dopant ion concentration in the second doped region; etching the first patterned material layer to form a first core structure in the first doped region and a second core structure in the second doped region; forming a second sidewall located on the sidewall of the first core structure and a third sidewall located on the sidewall of the second core structure; and removing the second core structure. This semiconductor structure formation method balances the small size characteristics of the device with pattern flexibility, improving process compatibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for forming a semiconductor structure and a method for forming an SRAM memory. Background Technology

[0002] With the development of semiconductor technology, the size of semiconductor devices continues to shrink, and the precision of photolithography in semiconductor device manufacturing processes is also constantly improving.

[0003] The 193nm immersion lithography technology widely used in the industry can shrink feature sizes to 76nm. Building on this, by combining it with multiple exposure etching technology (Litho-Etch-Litho-Etch, or LELE for short), feature sizes can be further reduced to 38nm.

[0004] However, as integrated circuit manufacturing processes continue to shrink, especially after entering the 5-nanometer process, the limitations of the traditional 193nm immersion lithography technology are becoming increasingly apparent. Currently, some integrated circuit manufacturing processes employ more advanced technologies to shrink the process, such as extreme ultraviolet (EUV) lithography. However, the industrialization of these advanced technologies faces significant technical barriers and is still difficult to apply on a large scale in mass production.

[0005] Currently, 193nm immersion lithography is still widely used in the fabrication of back-end interconnect processes for integrated circuit devices. While this technology can further reduce the feature size of semiconductor structures by combining it with processes such as dual self-aligned pattern definition (SADP) and quadruple self-aligned pattern definition (SAQP), these techniques are more suitable for forming periodic, regular patterns. In the fabrication of devices with high requirements for pattern flexibility, such as SRAM memory, it is impossible to simultaneously meet the needs of small semiconductor structure size and pattern flexibility, thus limiting the applicability of the process and resulting in poor process compatibility. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a method for forming a semiconductor structure and a method for forming an SRAM memory, which ensures the small size requirement of the semiconductor structure while taking into account the flexibility of the structural pattern, thereby expanding the applicability of the forming process and improving process compatibility.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first patterned material layer on the substrate; forming a first sidewall on the first patterned material layer; forming a sacrificial structure on the first patterned material layer, wherein the size of the sacrificial structure is larger than the size of the first sidewall; using the sacrificial structure and the first sidewall as a mask, implanting dopant ions into the first patterned material layer to form a first doped region and a second doped region within the first patterned material layer, wherein the first doped region is located at the bottom of the first sidewall, the second doped region is located at the bottom of the sacrificial structure, and the dopant ion concentration in the first doped region is greater than the dopant ion concentration in the second doped region; using the sacrificial structure and the first sidewall as a mask, etching the first patterned material layer to form a first core structure in the first doped region and a second core structure in the second doped region; forming a second sidewall located on the sidewall of the first core structure and a third sidewall located on the sidewall of the second core structure; and removing the second core structure after forming the second sidewall and the third sidewall.

[0008] Optionally, the material of the first patterned material layer includes amorphous silicon.

[0009] Optionally, the method for forming the first sidewall includes: forming an initial mandrel structure on the first patterned material layer; depositing an initial first sidewall material layer on the sidewalls and top surface of the initial mandrel structure; etching back the initial first sidewall material layer until the top surface of the initial mandrel structure is exposed; and removing the initial mandrel structure.

[0010] Optionally, the size of the first sidewall ranges from 10 nanometers to 20 nanometers; the size of the sacrificial structure ranges from 30 nanometers to 50 nanometers.

[0011] Optionally, the process parameters for implanting doped ions into the first patterned material layer include: the doped ions include boron ions; and the energy of the doped ion implantation is 8keV to 20keV.

[0012] Optionally, the ion concentration of the first doped region is 10. 15 cm -3 ~10 20 cm -3 The ion concentration in the second doped region is 0–10. 5 cm -3 .

[0013] Optionally, after implanting doped ions into the first patterned material layer and before etching the first patterned material layer, the method for forming the semiconductor structure further includes: thinning the thickness of the sacrificial structure.

[0014] Optionally, after the thickness of the sacrificial structure is reduced, the dimensions of the sacrificial structure are the same as the dimensions of the first sidewall.

[0015] Optionally, the second sidewall and the third sidewall are formed simultaneously; the formation process of the second sidewall includes atomic layer deposition; the formation process of the third sidewall includes atomic layer deposition.

[0016] Optionally, the process for removing the second mandrel structure includes a wet etching process.

[0017] Optionally, before forming the first patterned material layer, the method for forming the semiconductor structure further includes: forming an initial first dielectric layer located on the substrate.

[0018] Optionally, after removing the second mandrel structure, the first mandrel structure and the second sidewall constitute a first graphic structure, and the size of the first graphic structure is larger than the size of the third sidewall.

[0019] Optionally, after removing the second mandrel structure, the method further includes: using the first mandrel structure, the second sidewall, and the third sidewall as masks, etching the initial first dielectric layer to form a first isolation structure located at the bottom of the first mandrel structure and the second sidewall, and a second isolation structure located at the bottom of the third sidewall, with a plurality of isolation gaps between the first isolation structure and the second isolation structure.

[0020] Optionally, after forming the first isolation structure and the second isolation structure, the method for forming the semiconductor structure further includes: removing the first core structure, the second sidewall, and the third sidewall.

[0021] Optionally, the method for forming the semiconductor structure further includes: forming a plurality of electrical interconnect structures within each isolation gap, wherein the dimensions of each electrical interconnect structure are the same or different.

[0022] Optionally, the size range of the electrical interconnect structure is 10 nanometers to 35 nanometers.

[0023] Optionally, the first mandrel structure and the second sidewall constitute a first pattern structure; the size range of the first pattern structure is 35 nanometers to 50 nanometers.

[0024] Optionally, the material of the sacrificial structure includes photoresist, amorphous silicon, or amorphous carbon.

[0025] Optionally, the material of the first sidewall includes silicon nitride or titanium oxide; the material of the second sidewall includes silicon nitride or titanium oxide; and the material of the third sidewall includes silicon nitride or titanium oxide.

[0026] Optionally, the size range of the second sidewall is 10 nanometers to 20 nanometers; the size range of the third sidewall is 10 nanometers to 20 nanometers.

[0027] Accordingly, the present invention also provides a method for forming an SRAM memory, comprising: providing a substrate; forming an initial first dielectric layer and a first pattern material layer on the substrate; forming a first sidewall on the first pattern material layer; forming a sacrificial structure on the first pattern material layer, the size of the sacrificial structure being larger than the size of the first sidewall; using the sacrificial structure and the first sidewall as a mask, implanting dopant ions into the first pattern material layer to form a first doped region and a second doped region within the first pattern material layer, the first doped region being located at the bottom of the first sidewall, the second doped region being located at the bottom of the sacrificial structure, and the dopant ion concentration in the first doped region being greater than the dopant ion concentration in the second doped region. Using the sacrificial structure and the first sidewall as a mask, the first patterned material layer is etched to form a first core structure in the first doped region and a second core structure in the second doped region; a second sidewall and a third sidewall are formed on the sidewall of the first core structure; after forming the second and third sidewalls, the second core structure is removed; using the first core structure, the second sidewall, and the third sidewall as a mask, the initial first dielectric layer is etched to form a first isolation structure at the bottom of the first core structure and the second sidewall, and a second isolation structure at the bottom of the third sidewall, with a plurality of isolation gaps between the first and second isolation structures; a plurality of electrical interconnect structures are formed in each isolation gap.

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0029] In the semiconductor structure formation method provided by the technical solution of the present invention, after forming a first sidewall on the first patterned material layer, a sacrificial structure with a size larger than the first sidewall is also formed on the first patterned material layer. During the implantation of dopant ions into the first patterned material layer, due to the larger size of the sacrificial structure, it acts as a mask to reduce the dopant ions implanted into the first patterned material layer under the sacrificial structure. Since the first sidewall is smaller, its blocking effect on the dopant ions implanted into the first patterned material layer is limited. Therefore, after the dopant ions are implanted, the dopant ion concentration in the first doped region at the bottom of the first sidewall is greater than the dopant ion concentration in the second doped region at the bottom of the sacrificial structure. This results in the ion concentration in the first core structure formed after etching the first patterned material layer being greater than the ion concentration in the second core structure, causing a difference in the material of the first core structure from that of the second core structure. Consequently, the second core structure can be selectively removed in the subsequent process while retaining the first core structure, which is beneficial for forming patterns of different sizes on the substrate, increasing the flexibility of the pattern and improving the compatibility of the process.

[0030] Furthermore, in the semiconductor structure formation method, the process of forming the first sidewall and the second sidewall implements two self-aligned pattern formation processes, that is, the second sidewall is formed through a quadruple self-aligned pattern formation process, while the process of forming the third sidewall only implements one self-aligned pattern formation process, that is, the third sidewall is formed through a dual self-aligned pattern formation process. Therefore, the semiconductor structure formation method combines dual self-aligned pattern formation process and quadruple self-aligned pattern formation process, which further improves the flexibility of pattern size while ensuring a small-size structure.

[0031] In the SRAM memory formation method provided by the technical solution of the present invention, since the first isolation structure is formed by etching with the first mandrel structure and the second sidewall as a mask, and the second isolation structure is formed by etching with the third sidewall as a mask, the size flexibility of the first isolation structure, the second isolation structure, and the electrical interconnection structure formed in each isolation gap is relatively high. Attached Figure Description

[0032] Figures 1 to 12 This is a schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0033] As described in the background section, under current photolithography technology, although the feature size of semiconductor structures can be reduced through processes such as dual self-aligned pattern definition (SADP) and quadruple self-aligned pattern definition (SAQP), these techniques are more suitable for forming periodic and regular patterns. In the fabrication of some devices with high requirements for pattern flexibility, such as SRAM memory, it is impossible to simultaneously meet the requirements of small semiconductor structure size and pattern flexibility, thus resulting in a small process applicability and poor process compatibility.

[0034] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. After forming a first patterned material layer and a first sidewall on the first patterned material layer on a substrate, a sacrificial structure larger than the first sidewall is also formed on the first patterned material layer. Therefore, the sacrificial structure reduces the number of dopant ions implanted into the first patterned material layer beneath it. This results in a higher dopant ion concentration in the first doped region at the bottom of the first sidewall than in the second doped region at the bottom of the sacrificial structure. Consequently, after etching the first patterned material layer, the materials of the first and second core structures are different. By selectively removing the second core structure, patterns of different sizes can be formed on the substrate, increasing pattern flexibility and improving process compatibility.

[0035] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 12 This is a schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0037] Please refer to Figure 1 A substrate (not shown) is provided; an initial first dielectric layer 100 and an initial bottom mask layer 101 are formed on the substrate; a first patterning material layer 102 is formed on the initial bottom mask layer 101.

[0038] The substrate material includes silicon, silicon-germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. Specifically, in this embodiment, the substrate material is silicon.

[0039] The initial first dielectric layer 100 provides raw materials for the subsequently formed first and second isolation structures.

[0040] In subsequent processes, the first patterned material layer 102 is patterned to serve as a mask for etching the initial bottom mask layer 101 and the initial first dielectric layer 100, thereby realizing the patterning of the initial first dielectric layer 100 to form the first isolation structure and the second isolation structure.

[0041] In this embodiment, the material of the first patterned material layer 102 includes amorphous silicon.

[0042] The material of the initial first dielectric layer 100 includes silicon oxide.

[0043] The material of the initial bottom mask layer 101 includes titanium nitride.

[0044] Next, a first sidewall is formed on the first patterned material layer 102. In this embodiment, the specific process of forming the first sidewall is as follows: Figures 2 to 4 As shown.

[0045] Please refer to Figure 2 A first mask material layer 103 is formed on the first pattern material layer 102; an initial mandrel structure 110 is formed on the first mask material layer 103.

[0046] The initial mandrel structure 110 is used to control the relative position of the first sidewalls subsequently formed on both sides thereon, and to enable the first sidewalls to be formed in a self-aligned manner.

[0047] In this embodiment, the initial mandrel structure 110 has a size range of 30 nanometers to 50 nanometers. The size refers to the width of the initial mandrel structure 110 in a direction parallel to the substrate surface.

[0048] In this embodiment, the material of the initial mandrel structure 110 includes amorphous silicon or amorphous carbon.

[0049] The first mask material layer 103 is used as an etching stop layer in the subsequent formation of the first sidewall.

[0050] In this embodiment, the material of the first mask material layer 103 includes silicon oxide.

[0051] Please refer to Figure 3 An initial first sidewall material layer (not shown) is deposited on the sidewalls and top surface of the initial mandrel structure 110; the initial first sidewall material layer is etched back until the initial mandrel structure 110 and the top surface of the first mask material layer 103 are exposed to form the first sidewall 111.

[0052] Since the first sidewall 111 is formed on the sidewall surface of the initial mandrel structure 110 by self-alignment, a smaller first sidewall 111 can be formed without being limited by etching process, thereby reducing the feature size of the device structure and expanding the process window.

[0053] In this embodiment, the size of the first sidewall 111 ranges from 10 nanometers to 20 nanometers.

[0054] The dimension of the first sidewall 111 refers to the width of the first sidewall 111 in the direction parallel to the substrate surface.

[0055] In this embodiment, the material of the first sidewall 111 includes silicon nitride or titanium oxide.

[0056] The deposition process of the first sidewall material layer includes atomic layer deposition.

[0057] Please refer to Figure 4 After the first sidewall 111 is formed, the initial mandrel structure 110 is removed.

[0058] The first sidewall 111 is subsequently used as a mask for etching the first mask material layer 103 and the first pattern material layer 102, thereby transferring the pattern of the first sidewall 111 downward.

[0059] In this embodiment, the process of removing the initial mandrel structure 110 includes a wet etching process.

[0060] After removing the initial mandrel structure 110, the first mask material layer 103 is etched using the first sidewall 111 as a mask to form the first mask structure 112.

[0061] Please refer to Figure 5 A sacrificial structure 120 is formed on the first graphic material layer 102, the size of which is larger than the size of the first sidewall 111.

[0062] The dimension refers to the width of the sacrificial structure 120 and the first sidewall 111 in a direction parallel to the substrate surface.

[0063] The purpose of the sacrificial structure 120 being larger than the first sidewall 111 is that, during the subsequent implantation of dopant ions into the first patterned material layer 102, the sacrificial structure 120 and the first sidewall 111 have different blocking capabilities for dopant ions. The larger size of the sacrificial structure 120 reduces the number of dopant ions implanted into the first patterned material layer 102 beneath it. In contrast, the smaller size of the first sidewall 111 limits its blocking effect on the dopant ions implanted into the first patterned material layer 102. As a result, after dopant ion implantation, the dopant ion concentration in the first patterned material layer 102 at the bottom of the first sidewall 111 is greater than that at the bottom of the first patterned material layer 102 at the bottom of the sacrificial structure 120. This creates a difference in the materials of the first patterned material layers 102 at the bottom of the first sidewall 111 and the bottom of the sacrificial structure 120, facilitating targeted pattern removal through selective etching processes.

[0064] Furthermore, in subsequent processes, the sacrificial structure 120 will be used as a mask to transfer the pattern to the first pattern material layer 102, thereby achieving the patterning of the first pattern material layer 102. Therefore, the size of the sacrificial structure 120 and the distance between the sacrificial structure 120 and the first sidewall 111 also determine the structure of the pattern formed after the first pattern material layer 102 is patterned.

[0065] Specifically, in this embodiment, the sacrificial structure 120 is located on both sides of the first sidewall 111.

[0066] In this embodiment, the size of the sacrificial structure 120 ranges from 30 nanometers to 50 nanometers.

[0067] The distance between the sacrificial structure 120 and the nearest first sidewall 111 ranges from 50 nanometers to 60 nanometers.

[0068] The materials of the sacrificial structure 120 include photoresist, amorphous silicon, or amorphous carbon.

[0069] Please refer to Figure 6 Using the sacrificial structure 120 and the first sidewall 111 as a mask, doped ions are implanted into the first patterned material layer 102 to form a first doped region 131 and a second doped region 132 within the first patterned material layer 102. The first doped region 131 is located at the bottom of the first sidewall 111, and the second doped region 132 is located at the bottom of the sacrificial structure 120. The doped ion concentration in the first doped region 131 is greater than the doped ion concentration in the second doped region 132.

[0070] During the implantation of doped ions into the first patterned material layer 102, the sacrificial structure 120, being relatively large, acts as a mask to block and reduce the doped ions implanted into the first patterned material layer 102 beneath it. The first sidewall 111, being smaller, has limited blocking effect on the implanted doped ions. Therefore, after doped ion implantation, the doped ion concentration in the first doped region 131 at the bottom of the first sidewall 111 is greater than the doped ion concentration in the second doped region 132 at the bottom of the sacrificial structure 120. Consequently, after subsequent etching of the first patterned material layer 102, the patterned materials formed by the first doped region 131 and the second doped region 132 are different, facilitating targeted pattern removal via selective etching processes.

[0071] Specifically, the process parameters for implanting doped ions into the first patterned material layer 102 include: the doped ions include boron ions; and the energy of the doped ion implantation is 8keV to 20keV.

[0072] The ion concentration of the first doped region 131 is 10. 15 cm -3 ~10 20 cm -3 The ion concentration of the second doped region 132 is 0–10. 5 cm -3 The difference in ion concentration between the first doped region 131 and the second doped region 132 results in a significant difference in their materials. Therefore, by selecting an appropriate etching process, the patterns formed by the first doped region 131 and the second doped region 132 can be selectively removed.

[0073] In this embodiment, in the first patterned material layer 102, except for the portion blocked by the sacrificial structure 120, the concentration of doped ions implanted in other portions is relatively high. Therefore, in addition to the area covered by the second doped region 132, the first doped region 131 is also formed in other portions of the first patterned material layer 102.

[0074] Please refer to Figure 7 After implanting doped ions into the first patterned material layer 102, the thickness of the sacrificial structure 120 is reduced.

[0075] In this embodiment, after the thickness of the sacrificial structure 120 is reduced, the size of the sacrificial structure 120 is the same as the size of the first sidewall 111.

[0076] Since the size of the sacrificial structure 120 determines the size of the pattern formed after the first patterning material layer 102 is patterned, the sacrificial structure 120, which acts as a mask, needs to have a smaller size in order to form a small-sized pattern. In this embodiment, by first forming a larger sacrificial structure 120 and then thinning the thickness of the sacrificial structure 120, a smaller sacrificial structure 120 can be reliably obtained, thereby improving the process window and meeting the needs of small-sized pattern transfer.

[0077] In this embodiment, the process for thinning the thickness of the sacrificial structure 120 includes anisotropic dry etching.

[0078] In this embodiment, after the thickness of the sacrificial structure 120 is reduced, the size range of the sacrificial structure 120 is 10 nanometers to 20 nanometers.

[0079] Please refer to Figure 8 Using the sacrificial structure 120, the first sidewall 111, and the first mask structure 112 as masks, the first patterned material layer 102 is etched to form the first core structure 141 in the first doped region 131 and the second doped region 132 to form the second core structure 142; a second sidewall 152 and a third sidewall 153 are formed on the sidewall of the first core structure 141 and the sidewall of the second core structure 142, respectively.

[0080] The sacrificial structure 120 and the first sidewall 111 act as a mask to transfer the pattern into the first pattern material layer 102. The first mandrel structure 141 has the same dimensions as the first sidewall 111, and the second mandrel structure 142 has the same dimensions as the thinned sacrificial structure 120.

[0081] Furthermore, since the dopant ion concentration in the first doped region 131 is greater than that in the second doped region 132, while achieving pattern transfer, the materials of the first mandrel structure 141 and the second mandrel structure 142 are also different, which is beneficial to form patterns of different sizes through subsequent selective etching processes.

[0082] Since the second sidewall 152 and the third sidewall 153 are formed on the sidewall surfaces of the first mandrel structure 141 and the second mandrel structure 142 through self-alignment, small-sized patterns are formed uniformly and reliably, further reducing the feature size of the device structure and improving the process window.

[0083] Furthermore, in the semiconductor structure formation process of this embodiment, the formation of the first sidewall 111 and the second sidewall 152 involves two self-aligned pattern formation processes. That is, the second sidewall 152 is formed through a quadruple self-aligned pattern formation process, while the formation of the third sidewall 153 involves only one self-aligned pattern formation process. That is, the third sidewall 153 is formed through a dual self-aligned pattern formation process. Therefore, the semiconductor structure formation method combines both dual and quadruple self-aligned pattern formation processes, which further improves the flexibility of pattern size while ensuring small-sized patterns.

[0084] In this embodiment, the second sidewall 152 and the third sidewall 153 are formed simultaneously. The formation process of the second sidewall 152 includes atomic layer deposition (ALD); the formation process of the third sidewall 153 also includes ALD.

[0085] The specific methods for forming the second side wall 152 and the third side wall 153 are the same as those for forming the first side wall 111, and will not be described in detail here.

[0086] In this embodiment, the size range of the second sidewall 152 is 10 nanometers to 20 nanometers; the size range of the third sidewall 153 is 10 nanometers to 20 nanometers.

[0087] In this embodiment, the material of the second sidewall 152 includes silicon nitride or titanium oxide; the material of the third sidewall 153 includes silicon nitride or titanium oxide.

[0088] Please refer to Figure 9 After the second sidewall 152 and the third sidewall 153 are formed, the second mandrel structure 142 is removed.

[0089] Since the materials of the first mandrel structure 141 and the second mandrel structure 142 are different, the second mandrel structure 142 can be selectively removed while the first mandrel structure 141 is retained by selecting an appropriate etching process, thereby forming patterns of different sizes.

[0090] After removing the second mandrel structure 142, the first mandrel structure 141 and the second sidewall 152 constitute the first graphic structure (not shown). While retaining the smaller third sidewall 153, the first graphic structure is formed by the first mandrel structure 141 and its sidewall, the second sidewall 152, thereby making the size of the first graphic structure larger than the size of the third sidewall 153. Furthermore, the combination of the first mandrel structure 141 and the second sidewall 152 allows for more possibilities in the size of the first graphic structure.

[0091] Specifically, in this embodiment, the size range of the first pattern structure is 35 nanometers to 50 nanometers.

[0092] Therefore, the semiconductor structure formation method in this embodiment combines a dual self-aligned patterning process and a quadruple self-aligned patterning process to fabricate and transfer patterns, forming the second sidewall 152 and the third sidewall 153. This allows for greater flexibility in pattern size while achieving small-sized pattern fabrication. Furthermore, after completing the dual self-aligned patterning process and the quadruple self-aligned patterning process, the second mandrel structure 142 is selectively removed while the first mandrel structure 141 is retained. This allows for greater dimensional possibilities in the first pattern structure formed by the first mandrel structure 141 and the second sidewall 152. The combination of the first pattern structure and the third sidewall 153 further increases the overall pattern flexibility and improves process compatibility.

[0093] In this embodiment, the process of removing the second mandrel structure 142 includes a wet etching process.

[0094] Specifically, the etching solution used in the wet etching process includes ammonia, potassium hydroxide, or tetramethylammonium hydroxide.

[0095] Please refer to Figure 10 After removing the second mandrel structure 142, the initial bottom mask layer 101 is etched using the first mandrel structure 141, the second sidewall 152, and the third sidewall 153 as masks to form a bottom mask layer 163. The initial first dielectric layer 100 is etched using the bottom mask layer 163 as a mask to form a first isolation structure 161 located at the bottom of the first mandrel structure 141 and the second sidewall 152, and a second isolation structure 162 located at the bottom of the third sidewall 153. There are several isolation gaps (not shown) between the first isolation structure 161 and the second isolation structure 162.

[0096] The first mandrel structure 141 and the second sidewall 152 constitute a first graphic structure (not shown). Since the size of the first graphic structure is larger than the size of the third sidewall 153, the size of the first isolation structure 161 is larger than the size of the second isolation structure 162.

[0097] In this embodiment, the size range of the first isolation structure 161 is 35 nanometers to 50 nanometers; the size range of the second isolation structure 162 is 10 nanometers to 20 nanometers.

[0098] After forming the first isolation structure 161 and the second isolation structure 162, the first pattern structure, the third sidewall 153 and the bottom mask layer 163 are removed to expose the top surfaces of the first isolation structure 161 and the second isolation structure 162.

[0099] For ease of understanding, in Figure 10 The bottom mask layer 163 is still retained.

[0100] Please refer to Figure 11 and Figure 12 , Figure 11 for Figure 12 A schematic diagram of the cross-sectional structure along the AA' direction. Figure 12 for Figure 11 A top view along the P direction shows several electrical interconnect structures 170 formed within each isolation gap, with each electrical interconnect structure 170 having the same or different dimensions.

[0101] Specifically, the size range of the electrical interconnect structure 170 is 10 nanometers to 35 nanometers.

[0102] In the semiconductor structure formation method of this embodiment, the pattern is formed and transferred by combining a dual self-aligned patterning process and a quadruple self-aligned patterning process. On this basis, by selectively removing part of the core structure, it is possible to overcome the limitations of extreme ultraviolet lithography technology and use traditional immersion lithography process to break through the limit of feature size and realize the fabrication of small-sized electrical interconnect structure 170, first isolation structure 161, and second isolation structure 162 below 38 nanometers. At the same time, it increases the flexibility of the overall pattern of electrical interconnect structure 170, first isolation structure 161, and second isolation structure 162 and improves process compatibility.

[0103] The semiconductor structure formation method in this embodiment is applicable to the fabrication processes of static random-access memory (SRAM), fin field-effect transistor devices, and gate-all-around transistor devices.

[0104] Accordingly, another embodiment of the present invention also provides a method for forming an SRAM memory.

[0105] The method for forming the SRAM memory includes: providing a substrate; forming an initial first dielectric layer and a first patterned material layer on the substrate; forming a first sidewall on the first patterned material layer; forming a sacrificial structure on the first patterned material layer, the sacrificial structure having a size larger than the first sidewall; using the sacrificial structure and the first sidewall as a mask, implanting dopant ions into the first patterned material layer to form a first doped region and a second doped region within the first patterned material layer, the first doped region being located at the bottom of the first sidewall, the second doped region being located at the bottom of the sacrificial structure, and the dopant ion concentration in the first doped region being greater than the dopant ion concentration in the second doped region ... to implant dopant ions into the first patterned material layer to form a first doped region and a second doped region within the first patterned material layer; and using the sacrificial structure and the first sidewall as a mask to implant dopant ions into the first patterned material layer to form a first doped region and a second doped region within the first patterned material layer. Using the first sidewall as a mask, the first patterned material layer is etched to form a first core structure in the first doped region and a second core structure in the second doped region. A second sidewall and a third sidewall are formed on the sidewall of the first core structure. After forming the second and third sidewalls, the second core structure is removed. Using the first core structure, the second sidewall, and the third sidewall as masks, the initial first dielectric layer is etched to form a first isolation structure at the bottom of the first core structure and the second sidewall, and a second isolation structure at the bottom of the third sidewall. A plurality of isolation gaps exist between the first and second isolation structures. A plurality of electrical interconnect structures are formed within each isolation gap.

[0106] The specific steps for forming the SRAM memory in this embodiment are as follows: Figures 1 to 12 The specific steps in forming the semiconductor structure shown are the same, and will not be repeated here.

[0107] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; A first patterned material layer is formed on the substrate; A first sidewall is formed on the first graphic material layer; A sacrificial structure is formed on the first graphic material layer, the size of which is larger than the size of the first sidewall; Using the sacrificial structure and the first sidewall as a mask, doped ions are implanted into the first patterned material layer to form a first doped region and a second doped region within the first patterned material layer. The first doped region is located at the bottom of the first sidewall, and the second doped region is located at the bottom of the sacrificial structure. The doped ion concentration in the first doped region is greater than that in the second doped region. Using the sacrificial structure and the first sidewall as a mask, the first patterned material layer is etched to form a first core structure in the first doped region and a second core structure in the second doped region. A second sidewall is formed on the sidewall of the first mandrel structure, and a third sidewall is formed on the sidewall of the second mandrel structure; After the second and third sidewalls are formed, the second mandrel structure is removed.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first patterned material layer includes amorphous silicon.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming the first sidewall includes: forming an initial mandrel structure on the first patterned material layer; depositing an initial first sidewall material layer on the sidewalls and top surface of the initial mandrel structure; etching back the initial first sidewall material layer until the top surface of the initial mandrel structure is exposed; and removing the initial mandrel structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The size of the first sidewall ranges from 10 nanometers to 20 nanometers; the size of the sacrificial structure ranges from 30 nanometers to 50 nanometers.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for implanting doped ions into the first patterned material layer include: the doped ions include boron ions; the energy of the doped ion implantation is 8keV to 20keV.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The ion concentration of the first doped region is 10 15 cm -3 ~10 20 cm -3 The ion concentration in the second doped region is 0–10. 5 cm -3 .

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, After implanting doped ions into the first patterned material layer and before etching the first patterned material layer, the method further includes: thinning the thickness of the sacrificial structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, After the thickness of the sacrificial structure is reduced, the dimensions of the sacrificial structure are the same as those of the first sidewall.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second sidewall and the third sidewall are formed simultaneously; the formation process of the second sidewall includes atomic layer deposition; the formation process of the third sidewall includes atomic layer deposition.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the second mandrel structure includes a wet etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the first patterned material layer, the method further includes forming an initial first dielectric layer located on the substrate.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, After removing the second mandrel structure, the first mandrel structure and the second sidewall form a first graphic structure, the size of which is larger than the size of the third sidewall.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, After removing the second mandrel structure, the method further includes: using the first mandrel structure, the second sidewall, and the third sidewall as masks, etching the initial first dielectric layer to form a first isolation structure located at the bottom of the first mandrel structure and the second sidewall, and a second isolation structure located at the bottom of the third sidewall, wherein there are several isolation gaps between the first isolation structure and the second isolation structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After forming the first isolation structure and the second isolation structure, the method further includes: removing the first mandrel structure, the second sidewall, and the third sidewall.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, Also includes: Several electrical interconnect structures are formed within each isolation gap, and the dimensions of each electrical interconnect structure may be the same or different.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The size range of the electrical interconnect structure is 10 nanometers to 35 nanometers.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first mandrel structure and the second sidewall constitute the first pattern structure; the size range of the first pattern structure is 35 nanometers to 50 nanometers.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the sacrificial structure include photoresist, amorphous silicon, or amorphous carbon.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first sidewall includes silicon nitride or titanium oxide; the material of the second sidewall includes silicon nitride or titanium oxide; and the material of the third sidewall includes silicon nitride or titanium oxide.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, The size range of the second sidewall is 10 nanometers to 20 nanometers; the size range of the third sidewall is 10 nanometers to 20 nanometers.

21. A method for forming an SRAM memory, characterized in that, include: Provide substrate; An initial first dielectric layer and a first patterned material layer located on the initial first dielectric layer are formed on the substrate; A first sidewall is formed on the first graphic material layer; A sacrificial structure is formed on the first graphic material layer, the size of which is larger than the size of the first sidewall; Using the sacrificial structure and the first sidewall as a mask, doped ions are implanted into the first patterned material layer to form a first doped region and a second doped region within the first patterned material layer. The first doped region is located at the bottom of the first sidewall, and the second doped region is located at the bottom of the sacrificial structure. The doped ion concentration in the first doped region is greater than that in the second doped region. Using the sacrificial structure and the first sidewall as a mask, the first patterned material layer is etched to form a first core structure in the first doped region and a second core structure in the second doped region. A second sidewall is formed on the sidewall of the first mandrel structure, and a third sidewall is formed on the sidewall of the second mandrel structure; After the second and third sidewalls are formed, the second mandrel structure is removed; Using the first mandrel structure, the second sidewall, and the third sidewall as masks, the initial first dielectric layer is etched to form a first isolation structure located at the bottom of the first mandrel structure and the second sidewall, and a second isolation structure located at the bottom of the third sidewall, with a plurality of isolation gaps between the first isolation structure and the second isolation structure. Several electrical interconnect structures are formed within each isolation gap.

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