A chip layout method and apparatus

Abstract

The application discloses a chip layout method and device, and relates to the technical field of integrated circuit design. The method comprises the following steps: determining a first layout planning scheme of a plurality of target objects according to first information; wherein the first information comprises information for describing the plurality of target objects and the connection relationship between the target objects, and the first layout planning scheme is used for describing the initial layout position of the plurality of target objects in a chip; adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the closeness of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout position of the plurality of target objects in the chip; and outputting the corresponding partition information of at least one group to which the plurality of target objects belong on the chip according to the second layout planning scheme, wherein the corresponding partition information of each group on the chip is used for deploying the target objects belonging to the group on the chip. The scheme is helpful for automatically realizing the top layer layout planning and the macro module layout planning in VLSI physical design.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a chip layout method and apparatus. Background Technology

[0002] In very large scale integrated circuit (VLSI) design, physical design is a crucial step. Typically, VLSI chips use a netlist hierarchy to describe the circuit structure: a circuit structure consists of input / output ports, several sub-modules, macromodules, and standard cells, along with their interconnections. A sub-module is also a circuit structure (i.e., a sub-module may contain other sub-modules), a macromodule is a physically implemented sub-module, and a standard cell is a minimal, physically implemented circuit structure of comparable size. Physical design, given the shape and the locations of the input / output ports, assigns positions and interconnections to the macromodules and standard cells in the netlist.

[0003] In physical design, floor plan and macro placement play an irreplaceable role. Floor plan involves defining the shape, position, and port locations of submodules; macro placement, given the possible shapes and port locations, determines the positions of macromodules. The quality of floor plan and macro placement directly affects the chip's power consumption and power performance area (PPA) metrics.

[0004] As design and manufacturing processes continue to evolve, the scale of integrated circuits continues to increase, and the hierarchical complexity of designs continues to rise, increasing the complexity of top-level layout planning and macro-module placement. For hierarchical chip designs, it is generally required that standard cells and macro-modules at the same logic level be closely clustered in the same connected region. For modules that are closely connected, they are placed in adjacent regions to achieve better area utilization and performance.

[0005] In current VLSI physical design, top-level layout planning and macro-module placement mainly rely on manual placement by engineers: top-level layout planning is done by experienced back-end engineers who manually divide the entire chip area into several sub-regions according to modules, based on the data flow guidance provided by the front-end and the chip area requirements; back-end engineers designing the modules then plan the internal layout of the modules according to the shape of the top-level layout plan. This is highly dependent on the engineers' experience and understanding of physical design, resulting in high labor costs. Summary of the Invention

[0006] This application provides a chip layout method and apparatus, which helps to automate the top-level layout planning and macro-module layout planning in VLSI physical design.

[0007] In a first aspect, embodiments of this application provide a chip layout method, comprising: determining a first layout planning scheme for a plurality of target objects based on first information; wherein the first information includes information for describing the plurality of target objects and the connection relationships between the target objects, and the first layout planning scheme is used to describe the initial layout positions of the plurality of target objects in the chip; adjusting the first layout planning scheme based on at least one parameter to obtain a second layout planning scheme for the plurality of target objects, wherein the at least one parameter is used to characterize the density of the plurality of target objects in the chip, and the second layout planning scheme is used to describe the target layout positions of the plurality of target objects in the chip; and outputting corresponding partition information on the chip for at least one group to which the plurality of target objects belong, based on the second layout planning scheme, wherein the corresponding partition information on the chip for each group is used to deploy target objects belonging to the group on the chip.

[0008] Through the above scheme, multiple target objects may include macro modules and / or standard cells and / or other objects that need to be set on the chip. By using at least one parameter, the initial layout positions of multiple target objects are adjusted so as to automatically obtain the target layout positions of multiple target objects on the chip, thereby automatically realizing the top-level layout planning and macro module layout planning in VLSI physical design.

[0009] In one possible design, adjusting the first layout planning scheme based on at least one parameter to obtain a second layout planning scheme for the plurality of target objects includes: iteratively adjusting the first layout planning scheme using gradient descent based on a target model to obtain the second layout planning scheme; wherein, in each iteration, the layout planning scheme under the current gradient and the value of the at least one parameter are input into the target model to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used to characterize the correspondence between the layout planning schemes under two adjacent gradients and the at least one parameter; when a set adjustment termination condition is reached, the layout planning scheme obtained in the last iteration is determined as the second layout planning scheme, wherein the adjustment termination condition includes: the candidate parameter value of the target parameter among the at least one parameter is less than or equal to the corresponding parameter threshold. Optionally, the at least one parameter includes one or more of the following: line length, cell distribution density, and cohesion density.

[0010] The above approach, based on the target requirements of chip physical design, uses the target model to iteratively optimize the current layout positions of multiple target objects in order to obtain a layout planning scheme that meets the corresponding target requirements as much as possible. This reduces labor costs while achieving better layout quality.

[0011] In one possible design, the target model is represented as:

[0012] f = WL r +λ v *WL v +λ d *D+λ g *G

[0013] Among them, WL r WL represents the sum of the actual connection lengths between the multiple target objects in each layout planning scheme; v λ represents the sum of the line lengths of the virtual connection lines between the multiple target objects in each layout planning scheme; D represents the unit distribution density; G represents the cohesion density of target objects belonging to the same group; v , λ d , λ g The WL v The weights corresponding to D and G.

[0014] The above scheme uses the line length of the actual connection line, the line length of the virtual connection line, the cell distribution density, and the cohesion of the group as optimization parameters for iterative optimization. This allows for obtaining a superior layout planning scheme in terms of line length, density, and connectivity within the group from multiple candidate layout planning schemes for the multiple target objects. This enables the automation of chip physical design to reduce labor costs while ensuring the quality of the layout.

[0015] In one possible design, when iteratively adjusting the first layout planning scheme using gradient descent, the method further includes adjusting the weights in the target model according to the Lagrange relaxation method. Thus, by employing the Lagrange relaxation method, the optimization difficulty is reduced as much as possible, and the optimization process is accelerated.

[0016] In one possible design, the first information includes feature values ​​for describing at least one attribute feature of each target object; determining a first layout planning scheme for multiple target objects based on the first information includes: grouping the multiple target objects according to the target features in the at least one attribute feature based on the first information to obtain the at least one group; performing position initialization based on the at least one group to determine the first layout planning scheme for multiple target objects.

[0017] The above scheme involves grouping multiple target objects according to their target characteristics. After global layout, partition information corresponding to each group can be obtained based on at least one group, such as the position and shape of each group. This allows for the deployment of target objects belonging to each group on the chip based on the partition information.

[0018] In one possible design, the multiple target objects belong to multiple levels, and the first information further includes information describing the hierarchical relationship between the multiple levels; based on the first information, the multiple target objects are grouped according to the target feature in the at least one attribute feature, including: logically dividing the target objects under each level into corresponding groups according to the hierarchical relationship of the multiple levels and based on at least one target feature value threshold. Optionally, the target feature is area.

[0019] By using the above approach, in hierarchical chip physical design, grouping the target objects of each level according to the size and logic depth requirements of each level helps to obtain more refined layout planning results.

[0020] In one possible design, the plurality of target objects include macro modules; the method further includes: according to the target utilization rate, splitting each macro module to be set on the chip into at least one corresponding equivalent sub-unit, wherein the area of ​​each equivalent sub-unit is the same as the area of ​​a preset standard unit used as a splitting reference, or the difference between the area of ​​each equivalent sub-unit and the area of ​​the standard unit is within a set error range.

[0021] The above scheme involves logically dividing macro-modules with areas larger than or far larger than standard units to obtain several equivalent sub-units with areas equivalent to standard units. This allows for more uniform optimization of layout positions at a smaller standard unit granularity, further improving the optimization effect of the layout planning scheme.

[0022] It should be noted that in this application, the standard cells to be set on the chip are the minimum circuit structures that have already been physically designed. Therefore, when the relevant design documents have already specified several standard cells to be set on the chip, the dimensions of these standard cells are known. "Standard cell size equivalent" means that the size of the standard cells is not strictly limited, but rather that the dimensions of different standard cells are within a predetermined standard cell size range. When logically decomposing a macro module, the predetermined standard cell size can be used as a reference size so that after logically decomposing the macro module based on this standard cell size, several equivalent sub-cells with sizes close to the standard cell size can be obtained. Logical decomposition is different from actual decomposition; that is, no actual decomposition operation is performed. It is only used to logically decompose the entire macro module into equivalent sub-cells with sizes close to the standard cell size. This allows for subsequent iterative optimization, where virtual connection lines can be added to different equivalent sub-cells / standard cells based on the granularity of the standard cell size, to further optimize the connectivity and aggregation of cells within the macro module or group.

[0023] In one possible design, the plurality of target objects includes standard units that need to be set on the chip, and the method further includes: adding virtual connection lines to the target units among the plurality of target objects, wherein the target unit includes at least one equivalent sub-unit belonging to the same macro module, and / or, standard units and / or equivalent sub-units belonging to the same group.

[0024] The above scheme, based on the granularity of standard unit size, further optimizes the connectivity and aggregation of units within a macro module or group by adding virtual connection lines to target units belonging to the same macro module or the same group.

[0025] Secondly, embodiments of this application provide a chip placement apparatus, comprising: a processing unit, configured to determine a first placement planning scheme for a plurality of target objects based on first information; wherein the first information includes information describing the plurality of target objects and the connection relationships between them, and the first placement planning scheme describes the initial placement positions of the plurality of target objects in the chip; and to adjust the first placement planning scheme according to at least one parameter to obtain a second placement planning scheme for the plurality of target objects, wherein the at least one parameter characterizes the density of the plurality of target objects in the chip, and the second placement planning scheme describes the target placement positions of the plurality of target objects in the chip; and a communication unit, configured to output corresponding partition information on the chip for at least one group to which the plurality of target objects belong, based on the second placement planning scheme, wherein the corresponding partition information for each group on the chip is used to deploy target objects belonging to the group on the chip.

[0026] In one possible design, the processing unit is used to: iteratively adjust the first layout planning scheme using gradient descent according to the target model to obtain the second layout planning scheme; wherein, in each iteration, the layout planning scheme under the current gradient and the value of the at least one parameter are input into the target model to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used to characterize the correspondence between the layout planning schemes under two adjacent gradients and the at least one parameter; when a set adjustment termination condition is reached, the layout planning scheme obtained in the last iteration is determined as the second layout planning scheme, wherein the adjustment termination condition includes: the candidate parameter value of the target parameter among the at least one parameter is less than or equal to the corresponding parameter threshold.

[0027] In one possible design, the at least one parameter includes one or more of the following: line length, cell distribution density, and cohesion.

[0028] In one possible design, the target model is represented as:

[0029] f = WL r +λ v *WL v +λ d *D+λ g *G

[0030] Among them, WL r WL represents the sum of the actual connection lengths between the multiple target objects in each layout planning scheme; vλ represents the sum of the line lengths of the virtual connection lines between the multiple target objects in each layout planning scheme; D represents the unit distribution density; G represents the cohesion density of target objects belonging to the same group; v , λ d , λ g The WL v The weights corresponding to D and G.

[0031] In one possible design, when the processing unit iteratively adjusts the first layout planning scheme using the gradient descent method, it is also used to: adjust the weights in the target model according to the Lagrange relaxation method.

[0032] In one possible design, the first information includes feature values ​​for describing at least one attribute feature of each target object; the processing unit is configured to: group the plurality of target objects according to the first information and the target features in the at least one attribute feature to obtain at least one group; perform position initialization based on the at least one group to determine the first layout position of the target object in each group on the chip.

[0033] In one possible design, the multiple target objects belong to multiple levels, and the first information also includes information describing the hierarchical relationship between the multiple levels; the processing unit is used to: logically divide the target objects under each level into corresponding groups according to the hierarchical relationship of the multiple levels and based on at least one feature value threshold.

[0034] In one possible design, the target feature is area.

[0035] In one possible design, the plurality of target objects include macro modules; the processing unit is further configured to: according to the target utilization rate, split each macro module to be set on the chip into at least one corresponding equivalent sub-unit, the area of ​​each equivalent sub-unit being the same as the area of ​​the preset standard unit used as a splitting reference, or the difference between the area of ​​each equivalent sub-unit and the area of ​​the standard unit being within a set error range.

[0036] In one possible design, the plurality of target objects includes standard units that need to be set on the chip, and the processing unit is further configured to: add virtual connection lines to the target units among the plurality of target objects, wherein the target unit includes at least one equivalent sub-unit belonging to the same macro module, and / or, standard units and / or equivalent sub-units belonging to the same group.

[0037] Thirdly, embodiments of this application provide a computer-readable medium storing a computer program that, when run on a computer, causes the computer to perform the method described in any of the first aspects above.

[0038] Fourthly, embodiments of this application provide a computer program product that, when run on a computer, causes the computer to perform the method described in any of the first aspects above.

[0039] Based on the implementations provided in the above aspects, this application can be further combined to provide more implementations. Attached Figure Description

[0040] Figure 1 A schematic flowchart of a chip layout method according to an embodiment of this application is shown;

[0041] Figure 2a A circuit structure block diagram of an embodiment of this application is shown;

[0042] Figure 2b A schematic flowchart of a chip layout method according to an embodiment of this application is shown;

[0043] Figure 3 A schematic diagram of the grouping of embodiments of this application is shown;

[0044] Figure 4 This paper illustrates a schematic diagram of the macro module logic decomposition according to an embodiment of this application;

[0045] Figures 5a-5b This illustration shows a schematic diagram of adding virtual connection lines to the equivalent subunits of the same macro module according to an embodiment of this application;

[0046] Figure 6 This illustration shows a schematic diagram of adding virtual connection lines to submodules according to an embodiment of this application;

[0047] Figure 7 This application shows a schematic diagram of position initialization;

[0048] Figures 8a-8b A schematic diagram illustrating the cohesive density G of an embodiment of this application is shown;

[0049] Figure 9 A schematic diagram of the physical partitioning of an embodiment of this application is shown;

[0050] Figure 10 A schematic diagram of a chip layout apparatus according to an embodiment of this application is shown;

[0051] Figure 11 A schematic diagram of the communication device of this application is shown. Detailed Implementation

[0052] In current chip physical design, top-level layout planning and macro module placement mainly rely on manual placement by engineers, which is highly dependent on the engineers' experience and understanding of physical design, resulting in high labor costs.

[0053] This application provides a chip layout method and apparatus, which helps to automate the top-level layout planning and macro-module layout planning in VLSI physical design, reducing labor costs and improving the quality of layout. The method and apparatus are based on the same technical concept. Since the principles by which the method and apparatus solve problems are similar, the implementation of the apparatus and method can be mutually referred to, and repeated details will not be elaborated further.

[0054] For ease of understanding, the chip layout scheme of this application will be described below with reference to the accompanying drawings and embodiments.

[0055] Figure 1 A schematic flowchart of a chip placement method according to an embodiment of this application is shown. This method can be implemented by a chip placement apparatus, which can be a terminal device or a server, or a component or module for implementing the method. This application does not limit the specific implementation of this chip placement apparatus.

[0056] See Figure 1 As shown, the chip layout method may include the following steps:

[0057] S110: The chip layout device determines a first layout planning scheme for multiple target objects based on the first information.

[0058] In this application, the first information can be used to describe the plurality of target objects and the connection relationship between each target object, and the first layout planning scheme can be used to describe the first layout position of the plurality of target objects in the chip, which may be, for example, the initial layout position.

[0059] In this application, the target object can be multiple, including but not limited to input / output ports, submodules, macromodules, and standard units that need to participate in the chip physical design. Input / output ports, also known as pins, can be used to connect peripheral circuits. A submodule can be a circuit structure, meaning a submodule can also contain other submodules. A macromodule is a submodule that has already implemented its physical design. A standard unit is a minimal circuit structure of comparable size that has already implemented its physical design. It is understood that the target object described in this application can also include all submodules under a submodule, or all subunits under the same macromodule, i.e., hardware modules or hardware units that have not yet implemented their physical design, or subunits within modules that have already implemented their physical design, can all be considered target objects in this application, and will not be elaborated further here.

[0060] The information included in the first information to describe each target object may include, but is not limited to, product identification information, equipment information (e.g., size, manufacturer, model, category, other attributes, etc.), functional information (e.g., storage function, communication function, processing function, display function, etc.), and other hardware / software attribute-related information for each target object. This application does not limit this information. It is understood that in this application, the types of information included in the first information to describe different target objects may be the same or different, depending on the actual situation of the target object. This application does not limit this information. Furthermore, the information included in the first information to describe each target object may be in any form, such as images, text, numbers, or symbols, depending on the description or understanding requirements. It may use natural language that humans can understand or formal language that machines or programs can understand, and this information may be organized into a corresponding information format. This application does not limit this information.

[0061] The connection relationships between the target objects can include the connection relationships between any two target objects, such as the connection relationships between input / output ports and submodules, macromodules, and standard units, or the connection relationships between submodules and macromodules and standard units, or the connection relationships between macromodules and standard units. Optionally, the connection relationships between the target objects can also include the position of the connecting lines between any two target objects. It should be noted that the above are merely illustrative examples of target objects in this application and not any limitation. In other embodiments or in the future development of VISI, target objects designed into the chip may have other names or other descriptive methods, and this application does not limit them. The connection relationships between any two target objects or between units within the same target object can be physical connections or non-physical connections, such as virtual connections, and this application does not limit them.

[0062] Optionally, during implementation S110, the chip placement device can read a design file, and further, the chip placement device can obtain the first information from the design file. The design file can be created by a front-end engineer or through automated tools. The design file may contain relevant information required for chip physical design, which can describe multiple target objects that need to be placed on the chip and the connection relationships between these target objects. Specifically, during implementation S110, a back-end engineer can import the design file into the chip placement device, and the chip placement device can parse the design file to obtain the first information. Alternatively, the chip placement device can obtain the design file from a device storing the design file (which may also be in the cloud) via a network or physical connection device, and parse the design file to obtain the first information. This application does not limit the method of obtaining this first information.

[0063] In one possible implementation, the relevant information in the design file can be described, verified, and simulated using a hardware description language or other specialized languages. For example, the design file may include one or more of the following:

[0064] (1) Netlists can be used to describe circuit structures in a hierarchical manner. A circuit structure consists of input and output ports, several sub-modules, macro modules, several standard units, and the connection relationships between them.

[0065] It should be understood that in this application, the netlist can be used to describe circuit structures at multiple levels. Based on the logic depth of the circuit structure described by the netlist, the target objects (or design modules) that need to be placed on the chip can be hierarchically divided. Following the direction from the smallest granularity (i.e., the lowest level) to the largest granularity (i.e., the highest level), the levels to which each target object belongs are gradually obtained. Any level can also be called a hierarchy. Each hierarchy and its adjacent levels can have a parent-child relationship. A parent hierarchy can contain all target objects under its child hierarchy, and all target objects under that child hierarchy can be considered as a single target object under its parent hierarchy.

[0066] For example, see Figure 2aAs shown, based on the hierarchical circuit structure described in the network diagram, the levels to which multiple target objects belong can be obtained. For example, the display module, sensor module, memory module, and audio module shown in the dashed box belong to level 1. The display module, including the display screen, display interface, front camera, main camera interface, rear camera, and rear camera interface, belongs to level 2; any subordinate module (if any) included in any of these modules belongs to level 3, and so on. Similarly, the sensor module, including the touchscreen signal circuit, touchscreen interface circuit, coprocessor, and sensor interface, belongs to level 2; any subordinate module (if any) included in any of these modules belongs to level 3, and so on. Likewise, the memory module, including the hard disk and chip, belongs to level 2; any subordinate module (if any) included in any of these modules belongs to level 3, and so on. The audio module, including audio codec interfaces, audio amplifiers, and sensor interfaces, belongs to level 2. Any lower-level modules (if any) within these modules belong to level 3, and so on. Level 1 is the parent level of level 2, level 2 is the child level of level 1, level 2 is the parent level of level 3, and level 3 is a child level of level 2.

[0067] And, as Figure 2a As shown, based on the hierarchical circuit structure described in the network diagram, the connection relationships between various target objects can also be obtained, such as the connection relationships between any target object and the corresponding pins of the target object and the other target object. It should be understood that... Figure 2a This is merely a schematic block diagram of the hierarchical circuit structure based on netlist description in this application, and does not constitute any limitation on the target objects, connection relationships, etc., described in the netlist. Furthermore, the arrowed line segments shown in the figure only indicate that the corresponding target object can have a connection relationship with other target objects, and the solid box is only used to indicate that the target objects are connectable, and does not limit the specific implementation of the connection relationship, which will not be elaborated here.

[0068] It should be noted that in this application, the logic depth described by different circuit structures can be different. Generally, the hierarchy is determined from the smallest granularity to the largest granularity based on the target object described in the circuit structure. For example, Figure 2aThe display module can include a total of 4 levels, the sensor module can include a total of 3 levels, the memory module can include a total of 2 levels, and the audio module can include a total of 3 levels. In this application, for ease of description, the circuit structures based on different logic depths described by the netlist can be named from top to bottom, with each level involved in the netlist being designated as Level 1, Level 2, Level 3, etc. It should be understood that in this application, the level numbers are only for distinguishing different levels and do not limit the functionality of the target objects at different levels.

[0069] (2) A library for describing the shapes of macro modules, sub-modules and standard units that need to be set on the chip, and the relative positions of the ports of the macro modules and / or sub-modules and / or standard units on their own shapes.

[0070] (3) Target shape information, used to describe the target shape and the area of ​​the target shape after the layout design of the chip is completed.

[0071] (4) Chip port location information.

[0072] The chip placement apparatus can parse the aforementioned netlists, libraries, target shape information, and chip port location information to obtain primary information for automated chip physical design. It should be understood that, in specific implementations, the design file may include other descriptive information, and this application does not limit this.

[0073] Optionally, during S110, the chip placement apparatus can process the obtained first information to determine the first placement positions of the plurality of target objects on the chip. The first information obtained by the chip placement apparatus in S110 varies depending on the different descriptive information contained in the design document, and the processing performed differs accordingly. For example, see [link to example]. Figure 2b As shown, S110 may include the following steps:

[0074] S111: The chip layout device acquires the first information.

[0075] In this application, the first information may include feature values ​​for describing at least one attribute feature of each target object. For example, the at least one attribute feature may include shape, area, quantity, etc., and the feature value of the at least one attribute feature may be a value corresponding to the respective attribute feature. For example, the attribute feature "area" corresponds to XX square centimeters. It is understood that "square centimeters" is merely an example of a unit of area and not a limitation; other units of area may be used in specific implementations, which will not be elaborated here.

[0076] In one example, since the circuit structure is typically described hierarchically using netlists in the chip hierarchical physical design, the multiple target objects that need to be placed on the chip can belong to multiple levels. The chip placement device can parse the netlist, etc., to obtain the hierarchical relationship between the levels to which the multiple target objects belong. The first information may also include information that can be used to describe the hierarchical relationship between the multiple levels.

[0077] S112: The chip layout device groups the plurality of target objects according to the first information and the target feature in the at least one attribute feature, to obtain at least one group.

[0078] In this application, to effectively improve the efficiency of automated chip layout design and to allow designers more freedom to optimize performance, area, power consumption, and cost, a target feature can be selected from at least one attribute feature to group multiple target objects, thereby obtaining a better layout plan based on the grouping results. It should be noted that the selection of target features can be pre-set by the designer based on experience or simulation experiments, or it can be selected based on automated tools; this application does not limit the method of determining target features.

[0079] For example, the target feature can be any one of the at least one attribute feature, such as area, number of pins, etc. Alternatively, the target feature can be a combination of two or more of the at least one attribute feature, such as a combination of area and number of pins. Where there are two or more target features, different target features can be combined in an "and" or "or" manner. That is, in the "and" case, a target object needs to be grouped into one group when the corresponding grouping rules of different target features are simultaneously satisfied; while in the "or" case, only the corresponding grouping rule of one of the target features needs to be satisfied. In practical implementation, the corresponding target features can be determined according to the actual design requirements and the actual situation of each target object, so as to automate the top-level layout planning and macro-module layout planning in VLSI physical design. This reduces labor costs while also achieving better layout quality, which will not be elaborated further here.

[0080] Because the module size and logic depth differ at each level in hierarchical physical design, the precision required for the chip layout device to group target objects based on at least one attribute feature can vary. For example, S112 may include: logically dividing the target objects at each level into corresponding groups according to the hierarchical relationship of the multiple levels, for example, from the highest level to the lowest level, based on a target feature value threshold corresponding to at least one target feature.

[0081] by Figure 2a Taking the block diagram shown as an example, assuming that the circuit structure described by the netlist includes three levels, level 1 is the highest level, level 2 is the middle level, and level 3 is the lowest level, when grouping, the target objects under level 1 can be grouped first, then the target objects under level 2 can be grouped, and finally the target objects under level 3 can be grouped.

[0082] For example, the at least one target feature can be one, and the at least one target feature can have two target feature value thresholds, including: a first target feature value threshold and a second target feature value threshold, wherein the first target feature value threshold is greater than the second target feature value threshold; when logically dividing the target objects under each level into corresponding groups in sequence, if the target feature value of a certain target object is less than or equal to the second target feature value threshold, then the target object and its parent level belong to the same group; if the target feature value of a certain target object is greater than the second target feature value threshold and less than or equal to the first target feature value threshold, then the target object is grouped separately; if the target feature value of a certain target object is greater than or equal to the first target feature value threshold, then the grouping continues for the next level.

[0083] To facilitate understanding, the specific implementation process of S112 will be described below using area as the target feature as an example. Here, the target feature value threshold is an area threshold. Thus, taking the first target feature value threshold as the first area threshold A1 and the second target feature value threshold as the second area threshold A2 as an example, based on the top-down approach of each level described by the netlist, the area A of each target object at each level is used. h Logically group the two area thresholds, A2 and A1:

[0084] (1) If the area A of the target object h Satisfy: A h If A2 is less than or equal to A2, then the target object is in the same group as its parent level.

[0085] (2) If the area A of the target object h Satisfy: A2≤A h If A1 ≤ A1, then the target object is grouped separately;

[0086] (3) If the area A of the target object h Satisfy: A h If the result is ≥A1, continue grouping the next level.

[0087] See Figure 3 As shown, with the circuit structure described by the netlist involving 4 levels, A1=15, A2=9, from top to bottom, in level 1, for A... h In the case where 24 ≥ A1, the A hThe target object with a value of 24 can be grouped into a group, denoted as G1; and in level 1, there exists a group that satisfies A2 ≤ A h When the target object is ≤A1, it needs to be grouped separately, i.e., assigned to a group different from G1, which can be represented as G3. If there are no other ungrouped target objects in level 1, the target objects under the sub-levels of level 1 (i.e., level 2) continue to be grouped. It should be understood that since the parent level usually contains all target objects under the child level, without loss of generality, the higher the level, the larger the area of ​​the target objects it contains.

[0088] In level 2, for A h In the cases where 6 and 8 ≤ A2, and their parent level A h =24 can be assigned to the same group, belonging to group G1, for A2≤A h In the case where 10 ≤ A1, A h =10 target objects are assigned to a different group than their parent level, denoted as G2. G2 is a different group from G1. If there are no other ungrouped target objects in level 2, the sub-levels of level 2 (i.e., level 3) are grouped.

[0089] In level 3, for A h =5, 3≤A2, and its parent level A h =8 in the same group, assigned to group G1; for A h =5, 5≤A2, and its parent level A h =10 in the same group, assigned to group G2; if there are no other ungrouped target objects in level 3, continue grouping the sub-levels of level 3 (i.e., level 4); in level 4, for A h =5, 3≤A2, and its parent level A h =5 are in the same group, and are assigned to group G2.

[0090] Ultimately, the netlist logic, comprising four levels, is divided into two groups, G1 and G2. It should be understood that this is merely an illustrative example of grouping and not a limitation. In other embodiments, based on the specific circuit structure described by the netlist and the grouping rules, at least one group can be obtained, which will not be elaborated upon here.

[0091] In order to obtain a better layout planning scheme in terms of line length, density, connectivity and aggregation within groups from multiple candidate layout planning schemes, after grouping in S112, the target objects in each group can be processed so as to improve the connectivity and aggregation of the target objects within the group during subsequent iterative optimization.

[0092] In one example, S112 may be followed by S113: the chip layout device, according to the target utilization, splits each macro module (e.g., kernel (intellectual property, IP) module, input-output (IO) module, or memory module, etc.) logic that needs to be set on the chip into at least one equivalent sub-unit.

[0093] It should be noted that in this application, "logical splitting" differs from actual splitting. No actual splitting operation is performed; it is merely used to logically split large macro modules into equivalent sub-units with sizes similar to the preset standard unit size used as a splitting reference. This allows for the addition of virtual connection lines to different equivalent sub-units / standard units based on the granularity of the standard unit size during optimization adjustments, further optimizing the connectivity and aggregation of units within the macro module or group. In this application, each equivalent sub-unit can be considered a standard unit.

[0094] It should be noted that in this application, the standard unit is a minimum circuit structure of comparable size that has already undergone physical design, and the macro module is a sub-module that has already undergone physical design. The size of the macro module is larger than or much larger than the size of the standard unit. For example, the area of ​​each equivalent sub-unit is the same as the area of ​​the standard unit, or the difference between the area of ​​each equivalent sub-unit and the area of ​​the standard unit is within a set error range. Furthermore, under the target utilization rate, the area occupied by the equivalent sub-unit (A...) i The sum of ) and the area of ​​the original macromodule (A) macro )equal.

[0095] For example, the area of ​​n sub-units satisfies the following expression (1):

[0096]

[0097] Where i = 1, 2, 3, ..., n, and n is an integer greater than or equal to 1.

[0098] For example, the target utilization rate ρ satisfies the following expression (2):

[0099]

[0100] It should be understood that in this application, the target utilization rate ρ can be determined by the engineer based on experience or the needs of chip physical design, and the above expression (2) is only an example and not a limitation.

[0101] For example, with A macro For example, with a value of 10*10 and ρ=0.64, please refer to [reference needed]. Figure 4As shown, in S123, the original macro module can be divided into 10*5 equivalent sub-units, and the area of ​​each equivalent sub-unit is A. i =1.6*0.8.

[0102] Typically, chip placement requires that cells at the same logic level be placed in the same area as much as possible to achieve better PPA (Power-to-Average Performance). Optionally, after S113, S114 may be included: the chip placement device adds virtual connection lines to the target cells among the plurality of target objects, wherein the target cells include at least one equivalent sub-cell belonging to the same macromodule, and / or, standard cells and / or equivalent sub-cells belonging to the same group.

[0103] It should be noted that in this application, additional virtual connection lines are added to all units belonging to the same macromodule or group. The purpose is to enable interconnection between each unit in the macromodule or group, thereby maintaining high cohesion within the macromodule or group and improving the optimization effect of the subsequent target model. In specific implementation, the method of adding virtual connection lines between units is not limited; they can be added randomly or according to a set pattern, such as sequentially or in a mesh pattern, which will not be elaborated further here.

[0104] For example, see Figure 5a As shown, for a macromodule, the chip placement device can randomly assign virtual connection lines to n equivalent sub-units belonging to the same macromodule. Alternatively, as... Figure 5b As shown, the chip layout device can use a grid allocation method to assign virtual connection lines to n equivalent sub-units belonging to the same macro module.

[0105] Alternatively, a group can be called a submodule, and a submodule can contain submodules. See [link / reference] Figure 6As shown, for different submodules, the chip placement device can randomly assign virtual connection lines to all cells belonging to the same submodule. For example, for four submodules A, B, C-c1, and C-c2 (C-c1 and C-c2 are submodules contained in submodule C), the chip placement device can randomly add virtual connection lines to all cells in each submodule. In submodule A, cell a1 is connected to cell a2, and cell a2 is also connected to cell a3; in submodule B, cell b1 is connected to cell b2, and cell b2 is also connected to cells b3 and b4 respectively, and cell b3 is also connected to cell b4; in submodule C-c1... Unit c11 is connected to units c12, c13, and c14 respectively, and unit c12 is also connected to unit c13; within submodule C-c2, unit c21 is connected to units c22 and c24 respectively, and unit c22 is also connected to unit c23, and unit c23 is also connected to unit c24; within submodule C, unit c11 is also connected to unit c24, unit c12 is also connected to units c21 and c24, unit c13 is also connected to unit c23, and unit c13 is also connected to unit c23.

[0106] S115: The chip layout device can perform position initialization based on the at least one group processed by S113-S114 above, and determine a first layout planning scheme for multiple target objects.

[0107] For example, the first layout planning scheme can be used to describe the first layout position of the plurality of target objects in the chip, which may be, for example, an initial layout position. When implementing S115, the chip layout device can treat target objects belonging to the same group as a whole and set the initial layout position for each group. In this case, all units (including standard units and / or equivalent sub-units) within a group have the same initial layout position, which can achieve better intra-group connectivity and deterministic positional relationships between groups compared to indiscriminate random initialization.

[0108] For example, a chip placement apparatus may use a predetermined model, such as a quadratic WL model, to determine the initial placement position of each group on the chip.

[0109] As an example, the squared distance line length model can be described by the following expression (3):

[0110]

[0111] Where m is the number of groups, w j,k Let x be the weight of the connection line between group j and group k. j y j) represents the position of group j, (x k y k ) represents the position of group k.

[0112] See Figure 7 As shown, for three groups with unknown locations: group 1 (x1, y1), group 2 (x2, y2), and group 3 (x3, y3), given that the locations of the three chip ports are known (e.g., (0,1), (1,3), (3,2)), the weights of the connecting lines between the groups (e.g., 0, 2, 5) and between the groups and the chip ports (e.g., 1), the weights of the connecting lines and the chip port location information can be substituted into the above expression (3) to obtain:

[0113] WL = 1 * [(x1-1)] 2 +(y1-3) 2 ]+2*[(x1-x2) 2 +(y1-y2) 2 ]+5*[(x2-x3) 2 +(y2-y3) 2 ]+1*[(x2-3) 2 +(y2-2) 2 ]+1*[(x3-0) 2 +(y3-1) 2 (4)

[0114] The WL model obtains a set of equations by taking the partial derivatives of the positions of each group in expression (4). By solving the set of equations, the positions of each group can be obtained, thus yielding the initial layout positions of each group. In each group, all elements (including standard elements and / or equivalent sub-elements) have the same initial layout positions as that group.

[0115] It should be noted that the WL model mentioned in the above expression (3) can also be used in the following process to solve for the candidate positions of all units in each group in the chip at the unit level, until a layout planning scheme that meets the target requirements is obtained. This will be detailed below and will not be repeated here.

[0116] S120: The chip placement device adjusts the first placement planning scheme according to at least one parameter to obtain a second placement planning scheme for the plurality of target objects. The second placement planning scheme describes the target placement positions of the plurality of target objects within the chip.

[0117] For example, the at least one parameter includes one or more of the following: line length, cell distribution density, and cohesion. In implementation, the chip placement device can, for example, use the first placement planning scheme as a basis, and iteratively optimize it using line length, cell distribution density, and the connectivity and aggregation within each group as optimization parameters, until the second placement position of each cell is finally determined, resulting in a second placement planning scheme. This ensures that the obtained global placement result achieves effects such as short line length, uniform density, and high connectivity and aggregation within groups as much as possible.

[0118] For example, in S120, the chip placement device can iteratively adjust the first placement planning scheme using gradient descent based on the target model to obtain the second placement planning scheme. Specifically, in each iteration, the placement planning scheme under the current gradient and the value of at least one parameter are input into the target model to obtain the placement planning scheme under the next gradient and the value of at least one parameter; the target model is used to characterize the correspondence between the placement planning schemes and the at least one parameter under two adjacent gradients.

[0119] As an example, the target model is represented by the following expression (5):

[0120] f = WL r +λ v↓ *WL v +λ d *D+λ g *G (5)

[0121] Among them, WL r WL represents the sum of the lengths of the physical connection lines between multiple target objects in a layout plan; v λ represents the sum of the line lengths of the virtual connection lines between multiple target objects and / or between units within each target object in a layout planning scheme; D represents the unit distribution density; G represents the cohesion density of target objects belonging to the same group; v , λ d , λ g The WL v The weights are D and G, and the arrows indicate the direction of adjustment for the corresponding weights.

[0122] Optionally, when adjusting the first layout planning scheme using gradient descent, the chip placement device can adjust the weights in the target model according to the Lagrange multiplication method. For example, λ v↓ , λ d↑ , λ g↓ .

[0123] See Figure 2b As shown, in implementation, S120 may include the following steps:

[0124] S121: The chip placement device performs gradient calculation based on the current placement planning scheme and the current value of the at least one parameter, according to the target model.

[0125] S122: The chip placement device calculates the new placement position of each standard cell (including equivalent sub-cells) based on the current gradient and the current placement planning scheme, and obtains a new placement planning scheme. The new placement planning scheme includes a new set of candidate positions and a new value of the at least one parameter.

[0126] S123: The chip layout device determines whether the layout plan obtained in the most recent iteration meets the standard. If yes, that is, the layout plan obtained in this iteration meets the standard, then proceed to step S130; if no, that is, the layout plan obtained in this iteration does not meet the standard, then return to steps S121-S123, and continue to iteratively adjust the current layout position of the multiple target objects using the gradient descent method.

[0127] In each iteration, the weights of each parameter are adjusted using the Lagrange relaxation method. The gradient of the standard cell in the target model is calculated during each iteration, and the layout position of the standard cell is updated based on the current gradient, resulting in a new set of candidate positions. This process continues until a termination condition is met. For example, if the candidate parameter value of the target parameter in at least one of the parameters is less than or equal to the corresponding parameter threshold, the iterative adjustment stops, and the layout planning scheme obtained in the last iteration is determined as the second layout planning scheme. For instance, the target parameter can be the cell distribution density D. During the iterative adjustment process, when the value of the cell distribution density D obtained based on the updated layout planning scheme is less than or equal to the set target density threshold, the termination condition is met.

[0128] It should be noted that this application uses cell distribution density as an example of adjustment termination condition and is not a limitation. In specific implementations, one or more other parameters can be set as target parameters, which will not be elaborated here.

[0129] In this application, for example, during each iteration adjustment, the chip layout apparatus can describe the cohesion G of each group in a variety of optional ways.

[0130] Example 1: Describe G using the area of ​​the perimeter of the fence and the bounding rectangle of the group:

[0131] See Figure 8a As shown, using the fence force, G is described by the following expression (6):

[0132]

[0133] in, Represents the area of ​​the bounding rectangle of each Group; max(x g ) represents the maximum x-coordinate of the cells contained in the Group, min(x) g ) represents the minimum x-coordinate of the cells contained in the Group, max(y) g ) represents the maximum ordinate of the cells contained in the Group, min(y g ) represents the minimum ordinate of the unit contained in the Group. Figure 8a In the diagram, different groups are outlined with different dashed lines, and standard units (including equivalent sub-units) in different groups are represented by hollow circles and solid circles.

[0134] Example 2: Describing G using the distance from the center of gravity:

[0135] See Figure 8b As shown, the distance between the centers of gravity is described by the following expression (7):

[0136] G=∑((x i -x g ) 2 +(y i -y g ) 2 (7)

[0137] Among them, (x i y i (x) represents the position of the standard unit i (including equivalent sub-units) in each Group, (x) g y g ) represents the center of gravity of the Group. Figure 8b In the diagram, hollow circles and solid circles represent standard units (including equivalent sub-units) in different groups. An arrow corresponding to each group points to the centroid of that group. This is for easy differentiation. Figure 8a The center of gravity of the corresponding group is indicated by the larger hollow and solid circles.

[0138] After completing global layout optimization, the chip layout device will obtain a cell distribution result with uniform density and clustering within the group.

[0139] S130: The chip placement device outputs the corresponding partition information on the chip for at least one group to which the plurality of target objects belong, according to the second placement planning scheme. The corresponding partition information of each group on the chip is used to deploy the target objects belonging to the group on the chip.

[0140] In this application, the corresponding partition information of the at least one group on the chip may include, for example, the partition shape corresponding to each of the at least one group, and the position of each of the at least one group on the chip. In implementation, the chip placement device can physically partition the placement positions of the at least one group on the chip based on the obtained global placement results (including the second placement position of each standard cell and / or macro module), and process the placement area corresponding to each group into a right-angled polygon, obtaining the shape of the corresponding partition of each group on the chip and the deployment position of that group area on the chip. Furthermore, based on the obtained relatively standardized physical partitions, it is convenient to perform the next level of layered design or for the placement of macro modules.

[0141] For example, see Figure 9 As shown, after global layout optimization, we can obtain... Figure 9 The left side shows seven grouped regions, each corresponding to one of the aforementioned groups. Initially, each group is irregularly shaped. After right-angled processing of these seven grouped regions, we can obtain... Figure 9 The right side shows seven right-angled polygonal regions. The information for each region can be used as output for next-level hierarchical design or for the layout and placement of macro modules.

[0142] Optionally, the target objects and their layout positions contained in each group can also be output as output, so that when designing the next level of layered design or when laying out macro modules, the relevant design modules can be set up on the chip directly based on the output information.

[0143] Therefore, the chip layout method described above, through iterative global layout optimization, helps to automatically solve the top-level design layout planning problem and the macro-module layout location planning problem. It can make up for the high dependence on the engineer's experience and design understanding in manual layout planning, which is conducive to reducing labor costs and ensuring the quality of layout.

[0144] Based on the same technical concept, embodiments of this application also provide a chip placement apparatus, such as... Figure 10As shown, the chip placement device 1000 may include a processing unit 1010 and a communication unit 1020. The processing unit 1010 is configured to determine a first placement planning scheme for a plurality of target objects based on first information; wherein the first information includes information describing the plurality of target objects and the connection relationships between them, and the first placement planning scheme describes the initial placement positions of the plurality of target objects in the chip; and adjust the first placement planning scheme according to at least one parameter to obtain a second placement planning scheme for the plurality of target objects, wherein the at least one parameter characterizes the density of the plurality of target objects in the chip, and the second placement planning scheme describes the target placement positions of the plurality of target objects in the chip; the communication unit 1020 is configured to output, according to the second placement planning scheme, corresponding partition information on the chip for at least one group to which the plurality of target objects belong, and the corresponding partition information on the chip for each group is used to deploy target objects belonging to that group on the chip.

[0145] In one possible design, the processing unit 1010 is used to: iteratively adjust the first layout planning scheme using gradient descent according to the target model to obtain the second layout planning scheme; wherein, in each iteration, the layout planning scheme under the current gradient and the value of the at least one parameter are input into the target model to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used to characterize the correspondence between the layout planning schemes under two adjacent gradients and the at least one parameter; when a set adjustment termination condition is reached, the layout planning scheme obtained in the last iteration is determined as the second layout planning scheme, wherein the adjustment termination condition includes: the candidate parameter value of the target parameter among the at least one parameter is less than or equal to the corresponding parameter threshold.

[0146] In one possible design, the at least one parameter includes one or more of the following: line length, cell distribution density, and cohesion.

[0147] In one possible design, the target model is represented as:

[0148] f = WL r +λ v *WL v +λ d *D+λ g *G

[0149] Among them, WL r WL represents the sum of the actual connection lengths between the multiple target objects in each layout planning scheme; vλ represents the sum of the line lengths of the virtual connection lines between the multiple target objects in each layout planning scheme; D represents the unit distribution density; G represents the cohesion density of target objects belonging to the same group; v , λ d , λ g The WL v The weights corresponding to D and G.

[0150] In one possible design, when the processing unit 1010 iteratively adjusts the first layout planning scheme using the gradient descent method, it is also used to: adjust the weights in the target model according to the Lagrange relaxation method.

[0151] In one possible design, the first information includes feature values ​​for describing at least one attribute feature of each target object; the processing unit 1010 is configured to: group the plurality of target objects according to the first information and the target features in the at least one attribute feature to obtain the at least one group; perform position initialization based on the at least one group to determine a first layout planning scheme for the plurality of target objects.

[0152] In one possible design, the multiple target objects belong to multiple levels, and the first information also includes information for describing the hierarchical relationship between the multiple levels; the processing unit 1010 is used to: logically divide the target objects under each level into corresponding groups according to the hierarchical relationship of the multiple levels and based on at least one target feature value threshold.

[0153] In one possible design, the target feature is area.

[0154] In one possible design, the plurality of target objects include macro modules; the processing unit 1010 is further configured to: according to the target utilization rate, split each macro module to be set on the chip into at least one corresponding equivalent sub-unit, the area of ​​each equivalent sub-unit being the same as the area of ​​a preset standard unit used as a splitting reference, or the difference between the area of ​​each equivalent sub-unit and the area of ​​the standard unit being within a set error range.

[0155] In one possible design, the plurality of target objects includes standard units that need to be set on the chip, and the processing unit 1010 is further configured to: add virtual connection lines to the target units among the plurality of target objects, wherein the target unit includes at least one equivalent sub-unit belonging to the same macro module, and / or standard units and / or equivalent sub-units belonging to the same group.

[0156] like Figure 11 The diagram shown is a schematic representation of a communication device according to an embodiment of this application. The structure of the communication device is as follows: Figure 11 As shown, the device includes a processor 1101 and a memory 1102. The memory stores one or more computer programs, which include instructions. When the processor invokes the instructions, the communication device executes the methods provided in the above embodiments. The functions of each unit component of the communication device are described below.

[0157] The processor 1101 and the memory 1102 are interconnected via a bus 1103. The bus 1103 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 11 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0158] The memory 1102 stores one or more computer programs, which include instructions. The memory 1102 may include random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The processor 1101 executes the program instructions in the memory 1102 and uses the data stored in the memory 1102 to implement the above-described functions, thereby implementing the method provided in the above embodiments.

[0159] It is understood that this application Figure 11The memory 1102 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0160] It should be noted that the module division in the above embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical entities, or have two or more units integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0161] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0162] Based on the above embodiments, this application also provides a computer program that, when run on a computer, causes the computer to execute the methods provided in the above embodiments.

[0163] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a computer, causes the computer to perform the methods provided in the above embodiments.

[0164] The storage medium can be any available medium that a computer can access. For example, but not limited to, a computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

[0165] Based on the above embodiments, this application also provides a chip coupled to a memory, which is used to read a computer program stored in the memory to implement the method provided in the above embodiments.

[0166] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0167] The various illustrative logic units and circuits described in the embodiments of this application can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can also be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0168] The steps of the methods or algorithms described in the embodiments of this application can be directly embedded in hardware, software units executed by a processor, or a combination of both. The software units can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC, which can be housed in a terminal device. Optionally, the processor and storage medium can also be housed in different components within the terminal device.

[0169] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0170] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A chip layout method, characterized in that, include: Based on the first information, a first layout planning scheme for multiple target objects is determined; wherein, the first information includes information for describing the multiple target objects and the connection relationships between each target object, and the first layout planning scheme is used to describe the initial layout positions of the multiple target objects in the chip; Based on the target model and at least one parameter, the first layout planning scheme is iteratively adjusted using gradient descent to obtain a second layout planning scheme for the plurality of target objects. The at least one parameter characterizes the density of the plurality of target objects within the chip and includes one or more of the following: line length, cell distribution density, and cohesion density. The target model characterizes the correspondence between the layout planning schemes under two adjacent gradients and the at least one parameter. The second layout planning scheme describes the target layout position of the plurality of target objects within the chip. In each iteration, the layout planning scheme under the current gradient and the value of the at least one parameter are input into the target model to obtain the layout planning scheme under the next gradient and the value of the at least one parameter. When a set adjustment termination condition is met, the layout planning scheme obtained in the last iteration is determined as the second layout planning scheme. The adjustment termination condition includes: the candidate parameter value of the target parameter among the at least one parameter is less than or equal to the corresponding parameter threshold. According to the second layout planning scheme, the corresponding partition information of at least one group to which the plurality of target objects belong is output on the chip, and the corresponding partition information of each group on the chip is used to deploy the target objects belonging to the group on the chip.

2. The method according to claim 1, characterized in that, The target model is represented as follows: in, This represents the sum of the actual connection lengths between the multiple target objects in each layout planning scheme; The sum of the line lengths of the virtual connection lines between the multiple target objects in each layout planning scheme; D represents the unit distribution density; G represents the cohesion density of target objects belonging to the same group; , , The respective , , The corresponding weights.

3. The method according to claim 1 or 2, characterized in that, The first information includes feature values ​​that describe at least one attribute feature of each target object; Based on the initial information, determine the first layout plan for multiple target objects, including: Based on the first information, the plurality of target objects are grouped according to the target features in the at least one attribute feature to obtain the at least one group; Based on the at least one group, position initialization is performed to determine a first layout planning scheme for multiple target objects.

4. The method according to claim 3, characterized in that, The multiple target objects belong to multiple levels, and the first information also includes information for describing the hierarchical relationship between the multiple levels; Based on the first information, the plurality of target objects are grouped according to the target features among the at least one attribute feature, including: Based on the hierarchical relationship of the multiple levels, and based on at least one target feature value threshold, the target objects under each level are logically divided into corresponding groups in sequence.

5. The method according to claim 3, characterized in that, The target feature is area.

6. The method according to claim 1 or 2, characterized in that, The plurality of target objects includes macro modules, and the method further includes: According to the target utilization rate, each macro module that needs to be set on the chip is divided into at least one corresponding equivalent sub-unit. The area of ​​each equivalent sub-unit is the same as the area of ​​a preset standard unit used as a reference for division, or the difference between the area of ​​each equivalent sub-unit and the area of ​​the standard unit is within a set error range.

7. The method according to claim 6, characterized in that, The plurality of target objects includes standard units that need to be set on the chip, and the method further includes: Virtual connection lines are added to the target units among the plurality of target objects, wherein the target unit includes at least one equivalent sub-unit belonging to the same macro module, and / or standard units and / or equivalent sub-units belonging to the same group.

8. A chip placement apparatus, characterized in that, include: A processing unit is configured to: determine a first layout planning scheme for multiple target objects based on first information; wherein the first information includes information describing the multiple target objects and the connection relationships between them, and the first layout planning scheme describes the initial layout positions of the multiple target objects in the chip; iteratively adjust the first layout planning scheme using gradient descent based on a target model and at least one parameter to obtain a second layout planning scheme for the multiple target objects, wherein the at least one parameter characterizes the density of the multiple target objects in the chip, including one or more of the following: line length, cell distribution density, and cohesion density; the target model characterizes the correspondence between the layout planning schemes under two adjacent gradients and the at least one parameter; the second layout planning scheme describes the target layout positions of the multiple target objects in the chip; during each iteration, input the layout planning scheme under the current gradient and the value of the at least one parameter into the target model to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; and when a set adjustment termination condition is reached, determine the layout planning scheme obtained in the last iteration as the second layout planning scheme, wherein the adjustment termination condition includes: the candidate parameter value of the target parameter among the at least one parameter is less than or equal to the corresponding parameter threshold; The communication unit is used to output the corresponding partition information of at least one group to which the plurality of target objects belong on the chip according to the second layout planning scheme. The corresponding partition information of each group on the chip is used to deploy the target objects belonging to the group on the chip.

9. The apparatus according to claim 8, characterized in that, The target model is represented as follows: in, This represents the sum of the actual connection lengths between the multiple target objects in each layout planning scheme; The sum of the line lengths of the virtual connection lines between the multiple target objects in each layout planning scheme; D represents the unit distribution density; G represents the cohesion density of target objects belonging to the same group; , , The respective , , The corresponding weights.

10. The apparatus according to claim 8 or 9, characterized in that, The first information includes feature values ​​describing at least one attribute feature of each target object; the processing unit is used to: Based on the first information, the plurality of target objects are grouped according to the target features in the at least one attribute feature to obtain the at least one group; Position initialization is performed based on the at least one group, and the target object in each group is determined to be in the first layout position on the chip.

11. The apparatus according to claim 10, characterized in that, The multiple target objects belong to multiple levels, and the first information also includes information describing the hierarchical relationship between the multiple levels; the processing unit is used for: Based on the hierarchical relationship of the multiple levels, and based on at least one target feature value threshold, the target objects under each level are logically divided into corresponding groups in sequence.

12. The apparatus according to claim 10, characterized in that, The target feature is area.

13. The apparatus according to claim 8 or 9, characterized in that, The plurality of target objects includes macro modules; the processing unit is further configured to: According to the target utilization rate, each macro module that needs to be set on the chip is divided into at least one corresponding equivalent sub-unit. The area of ​​each equivalent sub-unit is the same as the area of ​​a preset standard unit used as a reference for division, or the difference between the area of ​​each equivalent sub-unit and the area of ​​the standard unit is within a set error range.

14. The apparatus according to claim 13, characterized in that, The plurality of target objects includes standard units that need to be set on the chip, and the processing unit is further configured to: Virtual connection lines are added to the target units among the plurality of target objects, wherein the target unit includes at least one equivalent sub-unit belonging to the same macro module, and / or, standard units and / or equivalent sub-units belonging to the same group.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when run on a computer, causes the computer to perform the method described in any one of claims 1-7.

16. A computer program product, characterized in that, When the computer program product is run on a computer, it causes the computer to perform the method according to any one of claims 1-7.

Images