Congestion prediction model training method, image processing method and device

Abstract

A congestion prediction model training method, an image processing method and device. The training method comprises: dividing a plurality of metal layers into at least two prediction layers; wherein the plurality of metal layers are metal layers contained in each semiconductor chip of K semiconductor chips, and K is a positive integer; determining M first feature maps corresponding to each prediction layer; wherein the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer; adding the M first feature maps corresponding to each prediction layer in the K semiconductor chips to a data set, and training a congestion prediction model using the data set. By using the method, the accuracy of semiconductor chip congestion prediction can be improved while reducing the time consumption of congestion prediction.

Description

Technical Field

[0001] This application relates to the field of electronic design automation (EDA) technology, and in particular to a congestion prediction model training method, image processing method and apparatus. Background Technology

[0002] Congestion prediction, a crucial step in the physical design phase of Electronic Design Automation (EDA) for chips, is integral to the entire design flow. The congestion level of the placement scheme directly determines chip performance metrics such as latency and thermal power consumption. The goal of congestion prediction is to estimate the degree of routing congestion during Global Placement (GP) based on the current cell placement position. This provides an optimization basis for the global placement, enabling the placer to disperse cells in severely congested areas, reducing congestion in those areas and thus lowering overall chip congestion. Essentially, it involves predicting the difference between the routing track demand and the given routing track capacity for each grid on the gridded chip.

[0003] Due to the large size and complex structure of chips, existing congestion prediction methods have the following limitations: low congestion prediction accuracy, long computation time for congestion calculation, and difficulty in simultaneously achieving both accuracy and time-consuming congestion prediction. Summary of the Invention

[0004] This application discloses a congestion prediction model training method, an image processing method, and an apparatus. This congestion prediction method can improve the accuracy of congestion prediction for semiconductor chips while reducing the time consumption of congestion prediction.

[0005] In a first aspect, embodiments of this application disclose a congestion prediction model training method, the method comprising: dividing a plurality of metal layers into at least two prediction layers; wherein the plurality of metal layers are metal layers contained in each of K semiconductor chips, and K is a positive integer; determining M first feature maps corresponding to each prediction layer; wherein the M first feature maps are respectively used to describe M chip features of each prediction layer, and M is a positive integer; adding the M first feature maps corresponding to each prediction layer in the K semiconductor chips to a dataset, and using the dataset to train a congestion prediction model.

[0006] It should be understood that the embodiments of this application can divide the metal layer in each semiconductor chip into at least two prediction layers in different ways, so that some or all of the feature data of different metal layers in the same prediction layer after division show strong correlation and consistency; wherein, each prediction layer contains at least one metal layer.

[0007] As can be seen, in this embodiment, by grouping the metal layers in the semiconductor chip, each semiconductor chip is divided into at least two prediction layers. Since the feature data (i.e., feature maps) corresponding to the metal layers in each prediction layer exhibit strong correlation and consistency, this avoids the mutual interference caused by the lack of layering in existing technologies when training with significantly different feature data corresponding to different metal layers. Furthermore, when training the congestion prediction model using feature data from different prediction layers, the different trends exhibited by the feature data in different prediction layers allow the resulting model to effectively identify feature data with different trends and make corresponding predictions based on the identified features. In other words, the model possesses refined identification and prediction capabilities. In summary, the training method in this embodiment can effectively improve the model's prediction accuracy and generalization ability.

[0008] In one feasible implementation, the method further includes: performing global routing on the K semiconductor chips, obtaining a true congestion map corresponding to each prediction layer based on the globally routed K semiconductor chips; and adding the true congestion map corresponding to each prediction layer in the K semiconductor chips to the dataset.

[0009] As can be seen in this embodiment, the actual congestion map of each prediction layer is calculated based on the K semiconductor chips after global winding, so that the actual congestion map can be compared with the predicted congestion map of each prediction layer to adjust the congestion prediction model parameters and thus obtain the optimal congestion prediction model.

[0010] In one feasible implementation, the above-described division of the plurality of metal layers into at least two prediction layers includes: dividing the plurality of metal layers into at least two prediction layers according to the manufacturing process or functional module distribution of the metal layers in each semiconductor chip.

[0011] As can be seen, in the embodiments of this application, multiple metal layers in each semiconductor chip can be divided into at least two prediction layers based on the manufacturing process of each metal layer and / or the distribution of functional modules on each metal layer. For example, the metal layers in each semiconductor chip can be divided into two prediction layers based on whether there are macrocells, with one prediction layer containing both macrocells and standard cells, and the other prediction layer containing only standard cells; or multiple metal layers can be divided into at least two prediction layers based on the difference in the amount of winding resources in each metal layer, with the amount of winding resources in each metal layer within each prediction layer being roughly equivalent. Dividing multiple metal layers into different prediction layers based on the above methods results in a high degree of consistency in the feature data of metal layers within the same prediction layer, while the feature data corresponding to different prediction layers have significant differences. Therefore, after training the congestion prediction model using the feature data corresponding to each of the different prediction layers, the resulting model can effectively identify feature data with different trends and make corresponding predictions based on the identified features, i.e., the model has refined identification and prediction capabilities.

[0012] In one feasible implementation, determining the M first feature maps corresponding to each prediction layer includes: obtaining M second feature maps corresponding to each metal layer in each prediction layer; wherein the M second feature maps are used to describe the M chip features of each metal layer; generating M first feature maps corresponding to each prediction layer based on the M second feature maps of each metal layer; wherein the first feature map in the M first feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing that any chip feature.

[0013] It should be understood that the above-mentioned method of obtaining the first feature map describing any chip feature based on the second feature map describing any chip feature in each metal layer may include: taking a weighted average, taking the maximum or minimum value, etc., on the corresponding pixels on each second feature map describing the same chip feature in each metal layer to obtain the pixel value of the corresponding pixel on the first feature map describing the same chip feature.

[0014] As can be seen, in this embodiment, each metal layer corresponds to M second feature maps, which are used to describe M chip features of each metal layer respectively. Based on the above layering method, in each prediction layer, for the same chip feature, since the second feature maps corresponding to each metal layer have strong correlation and consistency, the first feature map describing the same chip feature obtained by taking the average, maximum or minimum value can accurately characterize the same chip feature of each metal layer. That is, the first feature map describing the same chip feature has good correlation and consistency with the second feature map describing the same chip feature in each metal layer; this avoids the situation where the first feature map describing the same chip feature in each metal layer in the same prediction layer has large differences, resulting in a large difference between the final first feature map describing the same chip feature and the second feature map describing the same chip feature in each metal layer. In summary, for the same chip feature, the first feature map that accurately reflects the same chip feature on each metal layer in each prediction layer can be obtained through the above-mentioned layering method and the determination method of the first feature map. Therefore, after training the congestion prediction model using the first feature maps corresponding to different prediction layers, the obtained model can effectively identify feature data with different trends and make corresponding predictions based on the identified features. That is, the model trained using the embodiments of this application has refined identification and prediction capabilities.

[0015] In one feasible implementation, the true congestion map corresponding to each prediction layer includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each prediction layer includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each prediction layer, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each prediction layer.

[0016] It should be understood that the method of obtaining the first level true congestion map corresponding to the prediction layer based on the second level true congestion map corresponding to each metal layer in each prediction layer may include: taking the mean, weighted average, or maximum value of the second level true congestion maps corresponding to each metal layer to obtain the first level true congestion map corresponding to the prediction layer; in addition, those skilled in the art may also use other methods to obtain the first level true congestion map corresponding to the prediction layer based on the second level true congestion maps corresponding to each metal layer, and this application does not limit this. Similarly, the method of obtaining the first vertical true congestion map corresponding to the prediction layer is the same as the method of obtaining the first level true congestion map, and will not be described again here.

[0017] As can be seen in this embodiment, based on the above-mentioned layering method, in each prediction layer, since the real congestion maps corresponding to each metal layer have strong correlation and consistency, the real congestion map of each prediction layer obtained by the above-mentioned method of determining the real congestion map (i.e., real congestion map) of each prediction layer has good consistency with the real congestion maps of each metal layer in the prediction layer. That is, a real congestion map that accurately reflects the congestion degree of each prediction layer can be obtained, thereby ensuring the prediction accuracy of the congestion prediction model trained using the real congestion map of each prediction layer.

[0018] In one feasible implementation, the above-mentioned addition of M first feature maps corresponding to each prediction layer in the K semiconductor chips to the dataset and training the congestion prediction model using the dataset includes: iteratively training the congestion prediction model using the dataset; wherein, each iteration includes: inputting the M first feature maps corresponding to any prediction layer in the dataset into the congestion prediction model to obtain a predicted congestion map corresponding to any prediction layer; and updating the congestion prediction model based on the predicted congestion map and the actual congestion map corresponding to any prediction layer.

[0019] As can be seen, in the embodiments of this application, the congestion prediction model can be obtained through multiple training iterations. In each iteration of training, the model input data is the feature data (M first feature maps) of each prediction layer. Since the feature data of each prediction layer can accurately reflect the corresponding features of each metal layer in the prediction layer, and the feature data corresponding to different prediction layers have significant differences, the prediction model can perform congestion prediction in a refined manner based on the feature data of different prediction layers, and obtain a predicted congestion map that can accurately reflect the congestion level of each prediction layer. Then, the model parameters are updated based on the predicted congestion map and the actual congestion map of each prediction layer, so that the trained model has a high prediction accuracy and a strong generalization ability.

[0020] In one feasible implementation, each of the aforementioned semiconductor chips includes a prediction layer comprising a macrocell layer and a non-macrocell layer, and the congestion prediction model includes a first congestion prediction model and a second congestion prediction model. The step of adding M first feature maps corresponding to each prediction layer in the K semiconductor chips to a dataset and training the congestion prediction model using the dataset includes: training the first congestion prediction model using the first feature maps corresponding to the macrocell layers in the dataset and the corresponding real congestion maps; and training the second congestion prediction model using the first feature maps corresponding to the non-macrocell layers in the dataset and the corresponding real congestion maps.

[0021] As can be seen in the embodiments of this application, when multiple metal layers in each semiconductor chip are divided into macrocell layers and non-macrocell layers (i.e., divided into two prediction layers), since the feature data corresponding to the macrocell layers and non-macrocell layers are quite different, the feature data corresponding to the macrocell layers can be used to train the first congestion prediction model, and the feature data corresponding to the non-macrocell layers can be used to train the second congestion prediction model. In this way, a prediction model that makes accurate predictions based on the feature data of the macrocell layers and a prediction model that makes accurate predictions based on the features of the non-macrocell layers can be obtained, thereby improving the model prediction accuracy. In addition, using two models to make predictions on different prediction layers of the same semiconductor chip at the same time can improve the speed of congestion prediction for the same semiconductor chip.

[0022] In one feasible implementation, the aforementioned M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0023] It should be understood that the M chip features corresponding to each metal layer and prediction layer may also include other chip features besides the four types of chip features mentioned above, and this application does not limit this.

[0024] As can be seen, in this embodiment, the aforementioned M chip features may include one or more of the following: pin density, network connection density, module mask, or winding resource quantity, reflecting chip function and on-chip device characteristics. By obtaining the first feature map of the chip features corresponding to each prediction layer, and training the prediction model based on the M first feature maps that accurately reflect the chip function and on-chip device characteristics, the prediction accuracy of the trained prediction model is improved.

[0025] Secondly, embodiments of this application disclose an image processing method, which includes: determining M first feature maps corresponding to each prediction layer in a semiconductor chip to be predicted; wherein the semiconductor chip to be predicted includes at least two prediction layers, and M is a positive integer; processing the M first feature maps corresponding to each prediction layer using a congestion prediction model to obtain a predicted congestion map corresponding to each prediction layer; wherein the congestion prediction model is obtained by training a dataset, the dataset including training data corresponding to the training prediction layers contained in each of a plurality of training semiconductor chips, the training data corresponding to each training prediction layer including M first training feature maps and a real congestion map, the M first training feature maps being used to describe M chip features of each training prediction layer, the real congestion map being used to describe the real congestion degree of each training prediction layer, each training semiconductor chip including at least two training prediction layers, and each training prediction layer including at least one metal layer.

[0026] It should be understood that the method for determining the M first feature maps corresponding to each prediction layer is the same as the method for determining the M first training feature maps of each training prediction layer, and will not be repeated here.

[0027] As can be seen in the embodiments of this application, in the process of using the congestion prediction model trained by the model training method in the first aspect above to perform congestion prediction, since the trained model has good prediction accuracy and generalization ability, a more accurate prediction congestion map corresponding to each prediction layer in the semiconductor chip to be predicted can be obtained, that is, the accuracy of the prediction congestion map is improved, which makes it easier to use the accurate prediction congestion map of each prediction layer to optimize the chip layout in the chip production process.

[0028] In one feasible implementation, the method further includes: aggregating the prediction congestion maps corresponding to all prediction layers in the semiconductor chip to be predicted to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0029] As can be seen in this embodiment, since the prediction congestion map corresponding to each prediction layer has high accuracy, the prediction congestion map describing the congestion level of the chip to be predicted obtained after aggregation based on the prediction congestion map corresponding to each prediction layer also has high accuracy. This makes it easier to optimize the chip layout by using the prediction congestion map of the chip to be predicted during the chip manufacturing process.

[0030] In one feasible implementation, the prediction congestion map corresponding to each prediction layer includes a vertical prediction congestion map and a horizontal prediction congestion map. Aggregating the prediction congestion maps corresponding to each prediction layer to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted includes: aggregating the vertical prediction congestion maps corresponding to each prediction layer using a hierarchical aggregation operator to obtain a reference vertical prediction congestion map; aggregating the horizontal prediction congestion maps corresponding to each prediction layer using the hierarchical aggregation operator to obtain a reference horizontal prediction congestion map; aggregating the reference vertical prediction congestion map and the reference horizontal prediction congestion map using a directional aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted; or aggregating the vertical and horizontal prediction congestion maps corresponding to each prediction layer using the directional aggregation operator to obtain a reference prediction congestion map corresponding to each prediction layer; and aggregating the reference prediction congestion map corresponding to each prediction layer using the hierarchical aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0031] As can be seen in this embodiment, for the chip to be predicted, hierarchical aggregation operators and directional aggregation operators can be used to aggregate the predicted congestion graphs corresponding to each prediction layer to obtain the predicted congestion graph of the chip to be predicted. The operations of the hierarchical aggregation operators and directional aggregation operators include, but are not limited to, weighted averaging, taking the maximum or minimum value of the predicted congestion graph. Since the predicted congestion graphs corresponding to each prediction layer obtained based on the prediction model have high accuracy, the predicted congestion graph of the chip to be predicted obtained based on the aggregation operators, after subsequent specific operations of the hierarchical aggregation operators and directional aggregation operators determined according to the specific scenario, also has high accuracy.

[0032] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers is obtained based on the K training semiconductor chips after global routing.

[0033] In one feasible implementation, the training prediction layer included in each of the training semiconductor chips is obtained based on the manufacturing process of the metal layers in each training semiconductor chip or the functional module distribution.

[0034] In one feasible implementation, the M first training feature maps corresponding to each training prediction layer are obtained based on the M second feature maps corresponding to each metal layer in each training prediction layer; wherein, the first training feature map in the M first training feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the feature of that chip.

[0035] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each of the training prediction layers includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each of the training prediction layers, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each of the training prediction layers.

[0036] In one feasible implementation, during each iteration of the congestion prediction model training, the congestion prediction model is updated using the predicted congestion map corresponding to any training prediction layer in the dataset and the actual congestion map corresponding to that training prediction layer; the predicted congestion map corresponding to any training prediction layer is obtained by inputting M first training feature maps corresponding to that training prediction layer into the congestion prediction model.

[0037] In one feasible implementation, the plurality of training prediction layers are divided into macrocell layers and non-macrocell layers, and the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; the first congestion prediction model is trained using a first training feature map corresponding to the macrocell layer in the dataset and a corresponding real congestion map; the second congestion prediction model is trained using a first training feature map corresponding to the non-macrocell layer in the dataset and a corresponding real congestion map.

[0038] In one feasible implementation, the M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0039] It should be understood that the beneficial effects of the various embodiments describing the congestion prediction model training process described above can be referred to in relation to the effective effects of the corresponding training methods in the first aspect, and will not be repeated here.

[0040] Thirdly, this application discloses a training apparatus for a congestion prediction model. The apparatus includes: a layering unit for dividing multiple metal layers into at least two prediction layers; wherein the multiple metal layers are metal layers contained in each of K semiconductor chips, and K is a positive integer; a determination unit for determining M first feature maps corresponding to each prediction layer; wherein the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer; and a training unit for using the M first feature maps corresponding to the prediction layers contained in each of the K semiconductor chips and the real congestion map as a dataset, and using the dataset to train a congestion prediction model; wherein the real congestion map corresponding to each prediction layer is used to describe the real congestion degree of each prediction layer.

[0041] In one feasible implementation, the training unit is further configured to: obtain the real congestion map corresponding to each prediction layer based on the K semiconductor chips after global routing; and add the real congestion map corresponding to each prediction layer in the K semiconductor chips to the dataset.

[0042] In one feasible implementation, the layering unit is specifically used to divide the plurality of metal layers into at least two prediction layers according to the manufacturing process or functional module distribution of the metal layers in each semiconductor chip.

[0043] In one feasible implementation, the determining unit is specifically used to: obtain M second feature maps corresponding to each metal layer in each prediction layer; wherein the M second feature maps are used to describe the M chip features of each metal layer; and generate M first feature maps corresponding to each prediction layer based on the M second feature maps of each metal layer; wherein the first feature map in the M first feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the any chip feature.

[0044] In one feasible implementation, the true congestion map corresponding to each prediction layer includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each prediction layer includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each prediction layer, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each prediction layer.

[0045] In one feasible implementation, regarding the aspect of training the congestion prediction model using the dataset, the training unit is specifically used to: iteratively train the congestion prediction model using the dataset; wherein, each iteration includes: processing M first feature maps corresponding to any prediction layer in the dataset using the congestion prediction model to obtain a predicted congestion map corresponding to the predicted layer; and updating the congestion prediction model based on the predicted congestion map and the actual congestion map corresponding to the predicted layer.

[0046] In one feasible implementation, each of the semiconductor chips includes a prediction layer that is a macrocell layer and a non-macrocell layer, respectively; in terms of training the congestion prediction model using the dataset, the training unit is specifically used to: train the first congestion prediction model using the first feature map corresponding to the macrocell layer in the dataset and the corresponding real congestion map; and train the second congestion prediction model using the first feature map corresponding to the non-macrocell layer in the dataset and the corresponding real congestion map.

[0047] In one feasible implementation, the aforementioned M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0048] Fourthly, this application discloses an image processing apparatus, comprising: a determining unit, configured to determine M first feature maps corresponding to each prediction layer in a semiconductor chip to be predicted; wherein the semiconductor chip to be predicted includes at least two prediction layers, and M is a positive integer; and a processing unit, configured to process the M first feature maps corresponding to each prediction layer using a congestion prediction model to obtain a predicted congestion map corresponding to each prediction layer; wherein the congestion prediction model is obtained by training a dataset, the dataset including training data corresponding to the training prediction layers contained in each of K training semiconductor chips, the training data corresponding to each training prediction layer including M first training feature maps and a real congestion map, the M first training feature maps respectively describing M chip features of each training prediction layer, the real congestion map describing the real congestion degree of each training prediction layer, each training semiconductor chip including at least two training prediction layers, and each training prediction layer including at least one metal layer.

[0049] In one feasible implementation, the above apparatus further includes: an aggregation unit, configured to aggregate the prediction congestion maps corresponding to all prediction layers in the semiconductor chip to be predicted, to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0050] In one feasible implementation, the prediction congestion map corresponding to each prediction layer includes a vertical prediction congestion map and a horizontal prediction congestion map; the aggregation unit is specifically used to: aggregate the vertical prediction congestion map corresponding to each prediction layer using a hierarchical aggregation operator to obtain a reference vertical prediction congestion map; aggregate the horizontal prediction congestion map corresponding to each prediction layer using the hierarchical aggregation operator to obtain a reference horizontal prediction congestion map; aggregate the reference vertical prediction congestion map and the reference horizontal prediction congestion map using a directional aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted; or, aggregate the vertical prediction congestion map and the horizontal prediction congestion map corresponding to each prediction layer using the directional aggregation operator to obtain a reference prediction congestion map corresponding to each prediction layer; aggregate the reference prediction congestion map corresponding to each prediction layer using the hierarchical aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0051] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers is obtained based on the K training semiconductor chips after global routing.

[0052] In one feasible implementation, the training prediction layer included in each of the training semiconductor chips is obtained based on the manufacturing process of the metal layers in each training semiconductor chip or the functional module distribution.

[0053] In one feasible implementation, the M first training feature maps corresponding to each training prediction layer are obtained based on the M second feature maps corresponding to each metal layer in each training prediction layer; wherein, the first training feature map in the M first training feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the feature of that chip.

[0054] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each of the training prediction layers includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each of the training prediction layers, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each of the training prediction layers.

[0055] In one feasible implementation, during each iteration of the congestion prediction model training, the congestion prediction model is updated using the predicted congestion map corresponding to any training prediction layer in the dataset and the actual congestion map corresponding to that training prediction layer; the predicted congestion map corresponding to any training prediction layer is obtained by inputting M first training feature maps corresponding to that training prediction layer into the congestion prediction model.

[0056] In one feasible implementation, the plurality of training prediction layers are divided into macrocell layers and non-macrocell layers, and the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; the first congestion prediction model is trained using a first training feature map corresponding to the macrocell layer in the dataset and a corresponding real congestion map; the second congestion prediction model is trained using a first training feature map corresponding to the non-macrocell layer in the dataset and a corresponding real congestion map.

[0057] In one feasible implementation, the M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0058] Fifthly, this application discloses a chip system, characterized in that the chip system includes at least one processor, a memory, and an interface circuit, wherein the memory, the interface circuit, and the at least one processor are interconnected via circuits, and the at least one memory stores instructions; when the instructions are executed by the processor, the method described in any one of the first and / or second aspects is implemented.

[0059] In a sixth aspect, this application discloses a terminal device, characterized in that the terminal device includes a chip system as described in the third aspect above, and discrete devices coupled to the chip system.

[0060] In a seventh aspect, this application discloses a computer-readable storage medium, characterized in that the computer-readable storage medium stores program instructions that, when executed on a processor, implement any of the methods described in the first aspect and / or the second aspect.

[0061] Eighthly, this application discloses a computer program product, characterized in that, when the computer program product is run on a terminal, any of the methods described in the first aspect and / or the second aspect above are implemented. Attached Figure Description

[0062] The accompanying drawings used in the embodiments of this application are described below.

[0063] Figure 1 This is a schematic diagram of a system architecture provided in an embodiment of this application;

[0064] Figure 2 This is a schematic diagram of the structure of a network model provided in an embodiment of this application;

[0065] Figure 3 This is a schematic diagram of a chip hardware structure provided in an embodiment of this application;

[0066] Figure 4 This is a schematic diagram of another system architecture provided in an embodiment of this application;

[0067] Figure 5 This is a schematic flowchart illustrating a training method for a congestion prediction model provided in an embodiment of this application.

[0068] Figure 6 This is a schematic diagram of the layer division of a semiconductor chip provided in an embodiment of this application;

[0069] Figure 7 This is a schematic flowchart of an image processing method provided in an embodiment of this application;

[0070] Figure 8 This is a schematic diagram of the spatial relationship between a first feature map and a fourth feature map provided in an embodiment of this application;

[0071] Figure 9 This is a schematic diagram of a congestion prediction process provided in an embodiment of this application;

[0072] Figure 10 This is a schematic diagram of the structure of a model training device provided in an embodiment of this application;

[0073] Figure 11 This is a schematic diagram of the structure of an image processing device provided in an embodiment of this application;

[0074] Figure 12 This is a schematic diagram of the hardware structure of a model training device according to an embodiment of this application;

[0075] Figure 13 This is a schematic diagram of the hardware structure of the image processing device provided in the embodiments of this application. Detailed Implementation

[0076] The embodiments of this application are described below with reference to the accompanying drawings.

[0077] The embodiments of this application can be applied to image processing tasks, such as congestion prediction in the physical design stage of Electronic Design Automation (EDA). That is, based on the feature map (feature data) of the semiconductor chip, the congestion level of the chip is predicted, thereby providing an optimization basis for global layout. This allows the placer to push away the cells in the severely congested area, reducing the layout congestion level in that area, thereby reducing the overall congestion of the chip.

[0078] It should be understood that the images in the embodiments of this application can be static images (or static pictures) or moving images (or moving pictures). For example, the images in this application can be videos or animated pictures, or they can be static pictures or photographs. For ease of description, in the following embodiments, static images or moving images will be uniformly referred to as images.

[0079] Furthermore, the congestion prediction described above is merely a specific scenario in which the method of this application embodiment is applied. The method of this application embodiment is not limited to the above scenario and can be applied to any scenario requiring image processing. Alternatively, the method of this application embodiment can also be similarly applied to other fields, such as speech recognition and natural language processing, and this application embodiment is not limited in this regard.

[0080] The method provided in this application is described below from the perspectives of model training and model application:

[0081] The congestion prediction model training method provided in this application involves computer vision processing, specifically applicable to data processing methods such as data training, machine learning, and deep learning. It performs symbolic and formal intelligent information modeling, extraction, preprocessing, and training on training data (such as the first feature map in this application) to ultimately obtain a trained congestion prediction model. Furthermore, the image processing method provided in this application can utilize the trained congestion prediction model, inputting input data (such as the feature map in this application) into the trained congestion prediction model to obtain output data (such as the predicted congestion map of the chip to be predicted in this application). It should be noted that the congestion prediction model training method and the image processing method provided in this application are inventions based on the same concept, and can also be understood as two parts of a system, or two stages of an overall process: such as the model training stage and the model application stage.

[0082] This application involves a large number of applications related to neural networks. In order to better understand the solutions of this application, the relevant terms and concepts in the fields of neural networks and computer vision that may be involved in this application will be introduced below.

[0083] (1) Neural Network

[0084] Neural networks can be composed of neural units, which can refer to units represented by x. s The arithmetic unit that takes an intercept of 1 as input can output the following:

[0085]

[0086] Where s = 1, 2, ..., n, n is a natural number greater than 1, W s For x s The weights are denoted by b, where b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input to the next convolutional layer. The activation function can be the sigmoid function. A neural network is a network formed by connecting many of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0087] (2) Deep Neural Networks

[0088] Deep neural networks (DNNs), also known as multilayer neural networks, can be understood as neural networks with many hidden layers, though there's no specific metric for "many." DNNs can be categorized into three layers based on their position: input layers, hidden layers, and output layers. Generally, the first layer is the input layer, the last layer is the output layer, and the layers in between are hidden layers. All layers are fully connected, meaning that any neuron in the i-th layer is connected to any neuron in the (i+1)-th layer. Although DNNs appear complex, the operation of each layer is actually quite simple, resembling a linear relationship as follows: in, It is the input vector. It is the output vector. α is the offset vector, W is the weight matrix (also called coefficients), and α() is the activation function. Each layer is simply an adjustment of the input vector. The output vector is obtained through such a simple operation. Because DNNs have many layers, the coefficients W and the offset vector... The number of these parameters is therefore quite large. The definitions of these parameters in a DNN are as follows: Taking the coefficient W as an example: Assuming a three-layer DNN, the linear coefficient from the 4th neuron in the second layer to the 2nd neuron in the third layer is defined as... The superscript 3 represents the layer number where coefficient W resides, while the subscript corresponds to the output third layer index 2 and the input second layer index 4. In summary, the coefficients from the k-th neuron in layer L-1 to the j-th neuron in layer L are defined as follows: It's important to note that the input layer does not have a W parameter. In deep neural networks, more hidden layers allow the network to better represent complex real-world situations. Theoretically, the more parameters a model has, the higher its complexity and "capacity," meaning it can perform more complex learning tasks. Training a deep neural network is essentially the process of learning the weight matrix, with the ultimate goal of obtaining the weight matrix of all layers in the trained deep neural network (a weight matrix formed by the vectors W from many layers).

[0089] (3) Convolutional Neural Network

[0090] A Convolutional Neural Network (CNN) is a deep neural network with a convolutional structure. A CNN contains a feature extractor consisting of convolutional layers and subsampling layers. This feature extractor can be viewed as a filter, and the convolution process can be seen as using a trainable filter to convolve with an input image or a convolutional feature map. A convolutional layer is a layer of neurons in a CNN that performs convolution processing on the input signal. In a convolutional layer of a CNN, a neuron may only be connected to some of its neighboring neurons. A convolutional layer typically contains several feature maps, each composed of rectangularly arranged neural units. Neural units on the same feature map share weights, which are the convolutional kernel. Shared weights can be understood as the way image information is extracted regardless of location. The underlying principle is that the statistical information of one part of the image is the same as that of other parts. This means that image information learned in one part can also be used in another part. Therefore, the same learned image information can be used for all locations in the image. In the same convolutional layer, multiple convolutional kernels can be used to extract different image information. Generally, the more convolutional kernels there are, the richer the image information reflected by the convolution operation.

[0091] Convolutional kernels can be initialized as matrices of random size, and during the training of a convolutional neural network, they can learn appropriate weights. Furthermore, sharing weights directly reduces the number of connections between layers in the convolutional neural network, while also lowering the risk of overfitting.

[0092] (4) Loss Function

[0093] In training a deep neural network, to ensure the output closely approximates the desired predicted value, we compare the network's prediction with the target value. Based on the difference, we update the weight vector of each layer (usually pre-configuring parameters before the initial update). For example, if the prediction is too high, the weight vector is adjusted to predict a lower value. This adjustment continues until the deep neural network predicts the target value or a value very close to it. Therefore, we need to predefine "how to compare the difference between the predicted and target values," which is the loss function or objective function. These are important equations used to measure the difference between the predicted and target values. Taking the loss function as an example, a higher output value (loss) indicates a greater difference, and training the deep neural network becomes a process of minimizing this loss.

[0094] (5) Backpropagation algorithm

[0095] Convolutional neural networks can employ backpropagation (BP) to correct the parameters in the initial super-resolution model during training, thereby reducing the reconstruction error loss. Specifically, forward propagation of the input signal to the output generates an error loss; this error loss information is then propagated back to update the parameters in the initial super-resolution model, leading to convergence of the error loss. The backpropagation algorithm is an error-loss-driven backpropagation process aimed at obtaining the optimal parameters of the super-resolution model, such as the weight matrix.

[0096] (6) Pixel value s

[0097] A pixel value in an image can be a red-green-blue (RGB) color value, which can be a long integer representing the color. For example, a pixel value of 256*Red+100*Green+76Blue, where Blue represents the blue component, Green represents the green component, and Red represents the red component. Within each color component, the smaller the value, the lower the brightness; the larger the value, the higher the brightness. For grayscale images, the pixel value can be a grayscale value.

[0098] The system architecture provided in the embodiments of this application is described below.

[0099] See appendix Figure 1 , Figure 1This is a schematic diagram of a system architecture 100 provided in an embodiment of this application. As shown in the system architecture 100, the data acquisition device 160 is used to collect training data. In this embodiment of the application, the training data includes the first feature map and the real congestion map corresponding to all prediction layers.

[0100] After collecting the training data, the data acquisition device 160 stores the training data in the database 130, and the training device 120 trains the target model 101 (i.e., the congestion prediction model in this embodiment) based on the training data maintained in the database 130.

[0101] The following describes in more detail, using Embodiment 1, how the training device 120 obtains the target model 101 based on training data. This target model 101 can be used to implement the image processing method provided in this application embodiment. Specifically, after preprocessing the M first feature maps corresponding to each prediction layer of the chip to be predicted, the model 101 is input to obtain the predicted congestion map corresponding to each prediction layer. In this application embodiment, the target model 101 can specifically be a congestion prediction model. In the embodiments provided in this application, this congestion prediction model is obtained through at least one training iteration. It should be noted that in practical applications, the training data maintained in the database 130 may not all come from the data acquisition device 160; it may also be received from other devices. Furthermore, it should be noted that the training device 120 may not necessarily train the target model 101 entirely based on the training data maintained in the database 130; it may also obtain training data from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0102] The target model 101 trained using training device 120 can be applied to different systems or devices, such as... Figure 1 The execution device 110 shown can be a terminal, such as a tablet computer, laptop computer, mobile phone terminal, vehicle terminal, etc., or it can be a server or cloud platform, etc. (See attached...) Figure 1 In the process, the execution device 110 is configured with an input / output (I / O) interface 112 for data interaction with external devices. Users can input data to the I / O interface 112 through the client device 140. The input data in this embodiment may include the first feature map corresponding to each prediction layer of the chip to be predicted.

[0103] During the preprocessing of input data by the execution device 110, or during the calculation module 111 of the execution device 110 performing calculations and other related processes, the execution device 110 can call data, code, etc. in the data storage system 150 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 150.

[0104] Finally, I / O interface 112 returns the processing results, such as the predicted congestion map of each prediction layer of the chip to be predicted (or the predicted congestion map corresponding to the chip to be predicted) obtained above, to client device 140, thereby providing it to the user.

[0105] It is worth noting that the training device 120 can generate corresponding target models 101 based on different training data for different objectives or tasks. The corresponding target models 101 can be used to achieve the above objectives or complete the above tasks, thereby providing the user with the required results.

[0106] In the appendix Figure 1 In the scenario shown, the user can manually provide input data, which can be done through the interface provided by I / O interface 112. Alternatively, the client device 140 can automatically send input data to I / O interface 112. If user authorization is required for the client device 140 to automatically send input data, the user can set the corresponding permissions in the client device 140. The user can view the output results of the execution device 110 on the client device 140, which can be presented in various forms such as display, sound, or animation. The client device 140 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 112 as new sample data and storing them in the database 130. Alternatively, data can be collected directly from the I / O interface 112 without going through the client device 140, using the input data and output results of the input I / O interface 112 as new sample data and storing them in the database 130.

[0107] It is worth noting that, attached Figure 1 This is merely a schematic diagram of a system architecture provided by an embodiment of the present invention. The positional relationships between the devices, components, modules, etc. shown in the diagram do not constitute any limitation. For example, in the attached diagram... Figure 1 In this context, the data storage system 150 is an external memory relative to the execution device 110. In other cases, the data storage system 150 may also be placed within the execution device 110.

[0108] like Figure 1 As shown, the target model 101 is trained by the training device 120. In this embodiment of the application, the target model 101 can be trained based on the training method of the congestion prediction model of this embodiment of the application. Specifically, the congestion prediction model provided in this embodiment of the application can be a convolutional neural network, a generative adversarial neural network, a variational autoencoder, or a semantic segmentation neural network, etc. This solution does not make specific limitations on this.

[0109] As introduced in the basic concepts above, a Convolutional Neural Network (CNN) is a deep neural network with a convolutional structure. It is a deep learning (DL) architecture, which refers to learning at multiple levels of abstraction using machine learning algorithms. As a deep learning architecture, a CNN is a feed-forward artificial neural network, where each neuron can respond to the input image.

[0110] like Figure 2 As shown, the convolutional neural network (CNN) 200 may include an input layer 210, a convolutional / pooling layer 220 (where the pooling layer is optional), and a neural network layer 230.

[0111] Convolutional / pooling layer 220:

[0112] Convolutional layers:

[0113] like Figure 2 The convolutional / pooling layer 220 shown may include layers as in Examples 221-226. For instance, in one implementation, layer 221 is a convolutional layer, layer 222 is a pooling layer, layer 223 is a convolutional layer, layer 224 is a pooling layer, layer 225 is a convolutional layer, and layer 226 is a pooling layer; in another implementation, layers 221 and 222 are convolutional layers, layer 223 is a pooling layer, layers 224 and 225 are convolutional layers, and layer 226 is a pooling layer. That is, the output of the convolutional layer can be used as the input to a subsequent pooling layer, or as the input to another convolutional layer to continue the convolution operation.

[0114] The following section will use convolutional layer 221 as an example to introduce the internal working principle of a convolutional layer.

[0115] Convolutional layer 221 can include multiple convolution operators, also known as kernels. In image processing, a convolution operator acts as a filter to extract specific information from the input image matrix. Essentially, a convolution operator can be a weight matrix, which is usually predefined. During the convolution operation, the weight matrix typically processes the input image pixel by pixel (or two pixels by two pixels, depending on the stride) along the horizontal direction, thus extracting specific features from the image. The size of the weight matrix should be related to the image size. It's important to note that the depth dimension of the weight matrix is ​​the same as the depth dimension of the input image; during convolution, the weight matrix extends to the entire depth of the input image. Therefore, convolution with a single weight matrix produces a single-depth convolutional output. However, in most cases, a single weight matrix is ​​not used; instead, multiple weight matrices of the same size (rows × columns) are applied—multiple identical matrices. The outputs of each weight matrix are stacked to form the depth dimension of the convolutional image; this dimension can be understood as being determined by the "multiple" mentioned above. Different weight matrices can be used to extract different features from an image. For example, one weight matrix can be used to extract image edge information, another weight matrix can be used to extract specific colors of the image, and yet another weight matrix can be used to blur unwanted noise in the image. These multiple weight matrices have the same size (rows × columns), and the feature maps extracted by these multiple weight matrices of the same size also have the same size. The extracted feature maps of the same size are then merged to form the output of the convolution operation.

[0116] The weight values ​​in these weight matrices need to be obtained through extensive training in practical applications. The weight matrices formed by the weight values ​​obtained through training can be used to extract information from the input image, thereby enabling the convolutional neural network 200 to make correct predictions.

[0117] When a convolutional neural network 200 has multiple convolutional layers, the initial convolutional layers (e.g., 221) tend to extract more general features, which can also be called low-level features. As the depth of the convolutional neural network 200 increases, the features extracted by later convolutional layers (e.g., 226) become more and more complex, such as high-level semantic features. Features with higher semantic levels are more suitable for the problem to be solved.

[0118] Pooling layer:

[0119] Because it is often necessary to reduce the number of training parameters, pooling layers are often introduced periodically after convolutional layers, such as... Figure 2Layers 221-226, as exemplified in convolutional / pooling layers 220, can be one convolutional layer followed by one pooling layer, or multiple convolutional layers followed by one or more pooling layers. In image processing, the sole purpose of pooling layers is to reduce the spatial size of the image. Pooling layers can include average pooling operators and / or max pooling operators to sample the input image to obtain a smaller image size. The average pooling operator calculates the average value of pixel values ​​within a specific range as the result of average pooling. The max pooling operator takes the pixel with the largest value within a specific range as the result of max pooling. Furthermore, just as the size of the weight matrix in a convolutional layer should be related to the image size, the operators in a pooling layer should also be related to the image size. The size of the output image after processing by the pooling layer can be smaller than the size of the input image of the pooling layer. Each pixel in the output image of the pooling layer represents the average or maximum value of the corresponding sub-region of the input image of the pooling layer.

[0120] Neural network layer 230:

[0121] After processing by the convolutional / pooling layers 220, the convolutional neural network 200 is still insufficient to output the required information. As mentioned earlier, the convolutional / pooling layers 220 only extract features and reduce the parameters introduced by the input image. However, to generate the final output information (the required class information or other relevant information), the convolutional neural network 200 needs to utilize neural network layers 230 to generate one or more outputs representing the required number of classes. Therefore, neural network layers 230 can include multiple hidden layers (such as...). Figure 2 As shown in layers 231, 232 to 23n) and output layer 240, the parameters contained in these multi-layer hidden layers can be pre-trained based on relevant training data for specific task types.

[0122] After the multiple hidden layers in neural network layer 230, the final layer of the entire convolutional neural network 200 is the output layer 240. This output layer 240 has a loss function similar to classification cross-entropy, specifically used to calculate the prediction error. Once the entire convolutional neural network 200 has undergone forward propagation (e.g., ...), the loss function is applied. Figure 2 Propagation from 210 to 240 degrees is considered forward propagation, while backward propagation (e.g.) is completed. Figure 2 The propagation from 240 to 210 (backpropagation) will begin to update the weight values ​​and biases of the layers mentioned above, in order to reduce the loss of the convolutional neural network 200 and the error between the output of the convolutional neural network 200 through the output layer and the ideal result.

[0123] It should be noted that, as Figure 2The convolutional neural network 200 shown is only an example of a convolutional neural network. In specific applications, convolutional neural networks can also exist in the form of other network models.

[0124] The following describes a chip hardware structure provided by an embodiment of this application.

[0125] Figure 3 A chip hardware structure provided in this embodiment of the invention includes a neural network processor 50. This chip can be configured as follows: Figure 1 The execution device 110 shown is used to perform the calculations of the calculation module 111. This chip can also be located in, for example... Figure 1 The training device 120 shown is used to complete the training work of the training device 120 and output the target model 101. For example... Figure 2 The algorithms for each layer in the convolutional neural network shown can all be implemented in, for example... Figure 3 This is achieved in the chip shown.

[0126] The Neural Processing Unit (NPU) 50 is mounted as a coprocessor on the host CPU, which allocates tasks to it. The core of the NPU is the arithmetic circuit 503, which is controlled by the controller 504 to retrieve data from the memory (weight memory or input memory) and perform calculations.

[0127] In some implementations, the arithmetic circuit 503 internally includes multiple process engines (PEs). In some implementations, the arithmetic circuit 503 is a two-dimensional pulsating array. The arithmetic circuit 503 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 503 is a general-purpose matrix processor.

[0128] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 502 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 501 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 508.

[0129] The vector computation unit 507 can further process the output of the arithmetic circuit, such as vector multiplication, vector addition, exponentiation, logarithmic operations, size comparisons, etc. For example, the vector computation unit 507 can be used for network computation in non-convolutional / non-FC layers of neural networks, such as pooling, batch normalization, and local response normalization.

[0130] In some implementations, vector computation unit 507 can store the processed output vector in unified memory 506. For example, vector computation unit 507 can apply a nonlinear function to the output of arithmetic circuit 503, such as a vector of accumulated values, to generate activation values. In some implementations, vector computation unit 507 generates normalized values, merged values, or both. In some implementations, the processed output vector can be used as activation input to arithmetic circuit 503, for example, for use in subsequent layers of a neural network.

[0131] The unified memory 506 is used to store input data and output data.

[0132] The weight data is directly transferred from the external memory to the input memory 501 and / or the unified memory 506 through the direct memory access controller 505 (DMAC), the weight data in the external memory is stored in the weight memory 502, and the data in the unified memory 506 is stored in the external memory.

[0133] The bus interface unit (BIU) 510 is used to enable interaction between the main CPU, DMAC and instruction fetch memory 509 via a bus.

[0134] The instruction fetch buffer 509, which is connected to the controller 504, is used to store the instructions used by the controller 504.

[0135] The controller 504 is used to call the instructions cached in the instruction fetch memory 509 to control the operation of the computing accelerator.

[0136] Generally, the unified memory 506, input memory 501, weighted memory 502, and instruction fetch memory 509 are all on-chip memories, while the external memory is memory outside the NPU. This external memory can be double data rate synchronous dynamic random access memory (DDR SDRAM), high bandwidth memory (HBM), or other readable and writable memory.

[0137] in, Figure 2 The operations of each layer in the convolutional neural network shown can be performed by the operation circuit 503 or the vector calculation unit 507.

[0138] The above-mentioned Figure 1 The training device 120 in the embodiment of this application is capable of executing each step of the congestion prediction model training method. Figure 1 The execution device 110 in the present application is capable of executing each step of the image processing method according to the embodiments of the present application. Figure 2 The neural network model shown and Figure 3 The chip shown can also be used to perform various steps of the image processing method according to the embodiments of this application. Figure 3 The chip shown can also be used to perform the various steps of the congestion prediction model training method in the embodiments of this application.

[0139] like Figure 4 As shown, Figure 4 This application provides a schematic diagram of a system architecture 300. The system architecture includes a local device 301, a local device 302, an execution device 210, and a data storage system 250; wherein, the local devices 301 and 302 are connected to the execution device 210 through a communication network.

[0140] The execution device 210 can be implemented by one or more servers. Optionally, the execution device 210 can be used in conjunction with other computing devices, such as data storage devices, routers, load balancers, etc. The execution device 210 can be deployed on a single physical site or distributed across multiple physical sites. The execution device 210 can use data in the data storage system 250 or call program code in the data storage system 250 to implement the congestion prediction model training method or image processing method of the embodiments of this application.

[0141] Specifically, the execution device 210 can perform the following processes:

[0142] Multiple metal layers are divided into at least two prediction layers; wherein, the multiple metal layers are the metal layers contained in each of K semiconductor chips, N is an integer greater than 1, and K is a positive integer; M first feature maps corresponding to each prediction layer are determined; wherein, the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer; the M first feature maps corresponding to each prediction layer in the K semiconductor chips are added to the dataset, and the congestion prediction model is trained using the dataset.

[0143] The congestion prediction model can be trained by the aforementioned execution device 210. This congestion prediction model can be used for image processing, speech processing, and natural language processing. For example, the congestion prediction model can be used to implement the congestion prediction method in the embodiments of this application.

[0144] Alternatively, the above-described process execution device 210 can be configured into an image processing apparatus, which can be used for image processing (e.g., it can be used to implement congestion prediction of semiconductor chips in the embodiments of this application).

[0145] Users can interact with execution device 210 by operating their respective user devices (e.g., local device 301 and local device 302). Each local device can represent multiple computing devices, such as personal computers, computer workstations, smartphones, tablets, etc.

[0146] Each user's local device can interact with the execution device 210 through a communication network of any communication mechanism / standard. The communication network can be a wide area network, a local area network, a point-to-point connection, or any combination thereof.

[0147] In one implementation, local devices 301 and 302 obtain relevant parameters of the congestion prediction model from execution device 210, deploy the congestion prediction model on local devices 301 and 302, and use the congestion prediction model to perform congestion prediction on the chip to be predicted, thereby obtaining the predicted congestion map of the chip to be predicted.

[0148] In another implementation, a pre-trained congestion prediction model can be directly deployed on the execution device 210. The execution device 210 obtains the feature data of the chip to be predicted from the local devices 301 and 302, and uses the pre-trained congestion prediction model to predict the congestion of the chip to be predicted, thereby obtaining the predicted congestion map of the chip to be predicted.

[0149] In one implementation, local devices 301 and 302 obtain relevant parameters of the image processing device from execution device 210, deploy the image processing device on local devices 301 and 302, and use the image processing device to perform congestion prediction on the chip to be predicted, thereby obtaining a predicted congestion map of the chip to be predicted.

[0150] In another implementation, an image processing device can be directly deployed on the execution device 210. The execution device 210 obtains feature data of the chip to be predicted from local devices 301 and 302, and uses the image processing device to perform congestion prediction on the chip to be predicted, thereby obtaining a predicted congestion map of the chip to be predicted.

[0151] In other words, the execution device 210 can also be a cloud device, in which case the execution device 210 can be deployed in the cloud; or, the execution device 210 can also be a terminal device, in which case the execution device 210 can be deployed on the user terminal side. This application embodiment does not limit this.

[0152] The training method and image processing method (e.g., congestion prediction method in EDA) of the congestion prediction model of this application embodiment will be described in detail below with reference to the accompanying drawings.

[0153] Please see Figure 5 , Figure 5 This is a flowchart illustrating a congestion prediction model training method 500 provided in an embodiment of this application. The method includes, but is not limited to, the following steps:

[0154] Step S510: Divide the multiple metal layers into at least two prediction layers; wherein the multiple metal layers are the metal layers contained in each of the K semiconductor chips, and K is a positive integer.

[0155] Specifically, the metal layers contained in each semiconductor chip are divided into at least two prediction layers; wherein each prediction layer contains at least one metal layer. See also... Figure 6 , Figure 6 This is a schematic diagram illustrating the layer division of a semiconductor chip as provided in an embodiment of this application. Figure 6 As shown, a semiconductor chip may contain multiple metal layers (from top to bottom, metal layer 1-1... metal layer NB). The semiconductor chip may be divided into at least two prediction layers (from top to bottom, prediction layer 1... prediction layer N). Each prediction layer contains at least one metal layer. For example, prediction layer 1 may contain metal layers 1-1... metal layer 1-A, and prediction layer N may contain metal layers N-1... metal layer NB. Wherein, A and B are positive integers, and N is an integer greater than or equal to 2.

[0156] In one feasible implementation, the above-described division of multiple metal layers into at least two prediction layers includes: dividing the multiple metal layers into at least two prediction layers according to the manufacturing process or functional module distribution of the metal layers in each semiconductor chip.

[0157] Specifically, the prediction layers are grouped based on the manufacturing process of the metal layers or whether the metal layers contain the same functional modules. That is, on the same semiconductor chip, metal layers with similar manufacturing processes can be grouped into the same prediction layer, or metal layers containing the same functional modules can be grouped into the same prediction layer. The manufacturing process of each metal layer can be characterized by its routing track capacity, which is specifically the number of routing tracks on each metal layer. The more advanced the manufacturing process of a metal layer, the larger its routing track capacity; for example, the routing track capacity of a 7nm manufacturing process metal layer is greater than that of a 14nm manufacturing process metal layer. Functional modules refer to hardware structures within the metal layers, such as macrocell layers or registers.

[0158] For example, when dividing multiple metal layers in the same semiconductor chip into at least two prediction layers based on the differences in the amount of wire resources in each metal layer, metal layers with differences in wire resources less than or equal to a preset threshold can be assigned to the same prediction layer. This preset threshold can be determined based on the specific application scenario. Assume a semiconductor chip contains six metal layers with wire resources of 15, 15, 14, 10, 10, and 2 respectively, and a preset threshold of 2. In this case, the six metal layers can be divided into three prediction layers; where the unit for the amount of wire resources is "strips". Specifically, the three metal layers with wire resources of 15, 15, and 14 can be assigned to the same prediction layer; the two metal layers with a wire resource of 10 can be assigned to the same prediction layer; and the metal layer with a wire resource of 2 can be assigned to the same prediction layer.

[0159] For example, when dividing multiple metal layers in the same semiconductor chip into at least two prediction layers based on the functional modules contained in each metal layer, the division can be based on whether the semiconductor chip contains a macrocell layer or a register. For instance, metal layers containing macrocell layers can be assigned to the same prediction layer, and metal layers containing non-macrocell layers can be assigned to the same prediction layer; or metal layers containing registers can be assigned to the same prediction layer, and metal layers not containing registers can be assigned to the same prediction layer.

[0160] As can be seen, dividing multiple metal layers into different prediction layers based on the above division method makes the feature data of metal layers in the same prediction layer highly consistent, while the feature data corresponding to different prediction layers have large differences. Therefore, after training the congestion prediction model with the feature data corresponding to each of the different prediction layers, the obtained model can effectively identify feature data of different trends and make corresponding predictions based on the identified features. That is, the model has refined identification and prediction capabilities.

[0161] Step S520: Determine M first feature maps corresponding to each prediction layer; wherein the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer.

[0162] Specifically, M chip features used for congestion prediction can be determined based on the specific application scenario. Chip-related data is acquired, including netlists, macromodule locations, transistor locations, transistor pin locations, and winding resource quantities. Based on this chip-related data, M first feature maps corresponding to the M chip features of each prediction layer are calculated. Each chip feature in the prediction layer corresponds to a first feature map describing that chip feature.

[0163] In one feasible implementation, the above M chip features may include one or more of pin density, network connection density, module mask, or amount of wiring resources.

[0164] It should be understood that the above-described chip features are merely a few specific examples listed in the embodiments of this application, and those skilled in the art can also use other chip features to describe the prediction layer accordingly. Furthermore, after layering using the above-described prediction layer layering criteria, each metal layer in each prediction layer has similar chip features; for example, in the same prediction layer, the pin density of one metal layer is similar to the pin density of another metal layer.

[0165] In one feasible implementation, determining the M first feature maps corresponding to each prediction layer includes: obtaining M second feature maps corresponding to each metal layer in each prediction layer; wherein the M second feature maps are used to describe the M chip features of each metal layer; generating M first feature maps corresponding to each prediction layer based on the M second feature maps of each metal layer; wherein the first feature map in the M first feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the any chip feature.

[0166] Specifically, each metal layer of each semiconductor chip corresponds to the aforementioned M chip features. That is, the chip features of each metal layer may include one or more of the following: pin density, network connection density, module mask, or wiring resource quantity. Among these, pin density and module mask are non-directional; wiring resource quantity and network connection density are directional. Within the same metal layer, wiring resource quantity and network connection density are either horizontal or vertical.

[0167] The winding resource quantity specifically refers to the number of routing tracks on each metal layer. Since the routing tracks on each metal layer are directional (horizontal or vertical), the winding resource quantity also has a corresponding directionality. Network connectivity density refers to the number of windings per unit area. The windings are wound around the aforementioned routing tracks, therefore the network connectivity density also has a directionality, i.e., it is horizontal or vertical. It should be understood that for directional chip features, the first feature map describing the chip feature also has a corresponding directionality; for example, when the winding resource quantity is horizontal, the first feature map describing the winding resource quantity is also horizontal.

[0168] Further, the acquisition of M second feature maps corresponding to each metal layer in each prediction layer includes: performing feature extraction based on the wiring data of each metal layer in each prediction layer to obtain M second feature maps corresponding to each metal layer. The generation of M first feature maps corresponding to each prediction layer based on the M second feature maps of each metal layer includes: for the same chip feature, obtaining a first feature map describing the same chip feature based on the second feature maps describing the same chip feature on each metal layer; this first feature map is one of the M first feature maps corresponding to each prediction layer. Specifically, a weighted average, maximum, or minimum value is taken from the corresponding pixels on each of the second feature maps describing the same chip feature on each metal layer in the same prediction layer to obtain the pixel value of the corresponding pixel on the first feature map corresponding to the same chip feature. Performing the above operation on each pixel on each of the second feature maps yields the pixel value of each pixel on the first feature map corresponding to the same chip feature, thus obtaining the first feature map describing the same chip feature.

[0169] It should be understood that, in addition to using the weighted average, taking the maximum or minimum value as described above, those skilled in the art may also use other methods to process each second feature map describing the same chip feature on each metal layer to obtain a first feature map describing the same chip feature. This application does not limit this.

[0170] For example, when a prediction layer contains four metal layers and M chip features include pin density, the first feature map corresponding to the pin density of the prediction layer is determined as follows: First, based on the wiring data of each of the four metal layers, four second feature maps describing the pin density of each of the four metal layers are obtained. The pixel values ​​at the same position in these four second feature maps are processed using methods such as weighted averaging, taking the maximum or minimum value, to obtain the pixel values ​​at the same position in the first feature map describing the pin density of the prediction layer. Each pixel in the four second feature maps is processed using the above method to obtain the first feature map corresponding to the pin density of the prediction layer.

[0171] It should be noted that when a metal layer lacks the first chip feature among the aforementioned M chip features, i.e., when the metal layer lacks a true second feature map describing the first chip feature, a preset operation can be used to obtain a second feature map describing the first chip feature of the metal layer. This preset operation can be: first, determining the prediction layer in which the metal layer is located; and then, based on the second feature maps describing the first chip features on other metal layers in the prediction layer, determining the second feature map describing the first chip feature on the metal layer. For example, a weighted average, maximum or minimum value, or other processing method can be applied to the corresponding pixels in the second feature maps describing the first chip features on other metal layers to obtain the second feature map describing the first chip feature of the metal layer.

[0172] As can be seen, in this embodiment, each metal layer corresponds to M second feature maps, which are used to describe M chip features of each metal layer respectively. Based on the above layering method, in each prediction layer, for the same chip feature, since the second feature maps corresponding to each metal layer have strong correlation and consistency, the first feature map describing the same chip feature obtained by taking the average, maximum or minimum value can accurately characterize the same chip feature of each metal layer. That is, the first feature map describing the same chip feature has good correlation and consistency with the second feature map describing the same chip feature in each metal layer; this avoids the situation where the first feature map describing the same chip feature in each metal layer in the same prediction layer has large differences, resulting in a large difference between the final first feature map describing the same chip feature and the second feature map describing the same chip feature in each metal layer. In summary, for the same chip feature, the first feature map that accurately reflects the same chip feature on each metal layer in each prediction layer can be obtained through the above-mentioned layering method and the determination method of the first feature map. Therefore, after training the congestion prediction model using the first feature maps corresponding to different prediction layers, the obtained model can effectively identify feature data with different trends and make corresponding predictions based on the identified features. That is, the model trained using the embodiments of this application has refined identification and prediction capabilities.

[0173] Step S530: Determine a dataset based on the M first feature maps and the real congestion map corresponding to the prediction layer contained in each of the K semiconductor chips, and train a congestion prediction model using the dataset; wherein, the real congestion map corresponding to each prediction layer is used to describe the real congestion degree of each prediction layer.

[0174] Congestion level refers to the difference between the required number of wires and the available wire resources. The available wire resources refer to the number of wire tracks. The required number of wires is the number of wires needed to connect all network tables; these wires are wound around the wire tracks. Therefore, the difference between the required number of wires and the available wire resources is the congestion level. For example, if the required number of wires is 10, 10 wires are needed to connect all network tables. If the available number of wires is 8, meaning there are 8 wire tracks, then two wires will be wrapped around the same track with the other wires, resulting in a congestion level of 2.

[0175] In one feasible implementation, the method further includes: performing global routing on the K semiconductor chips, obtaining a true congestion map corresponding to each prediction layer based on the globally routed K semiconductor chips; and adding the true congestion map corresponding to each prediction layer in the K semiconductor chips to the dataset.

[0176] Chip design can be divided into two stages: chip placement and global routing. The chip placement stage mainly determines the netlist, macro module locations, transistor locations, transistor pin locations, and routing resource amounts for each metal layer on the chip. The global routing stage mainly winds the metal wires into the routing tracks corresponding to the routing resource amounts.

[0177] Specifically, the above-mentioned method of obtaining the true congestion map corresponding to each prediction layer based on the K semiconductor chips after global routing includes: after global routing of the semiconductor chips, the number of routings on the chip can be determined, i.e., routing track demand; and then the true congestion map of each prediction layer is calculated based on the routing track demand and the amount of routing resources.

[0178] The image processing method (also known as the congestion prediction method) in this application embodiment is mainly used in the chip layout stage. When global routing is not performed, the congestion process of the chip is predicted based on this method, and the chip layout is adjusted accordingly.

[0179] In one feasible implementation, the true congestion map corresponding to each prediction layer includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each prediction layer includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each prediction layer, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each prediction layer.

[0180] Specifically, the actual congestion map corresponding to each metal layer in each semiconductor chip is obtained. The actual congestion map for each metal layer includes a second horizontal actual congestion map and a second vertical actual congestion map. The second horizontal actual congestion map describes the congestion level of the metal layer in the horizontal direction, and the second vertical actual congestion map describes the congestion level of the metal layer in the vertical direction. The actual congestion map for each metal layer is calculated based on the winding resource requirements and winding resource quantity of each metal layer after global routing.

[0181] Optionally, the specific process of obtaining the first horizontal true congestion map corresponding to the prediction layer based on the second horizontal true congestion map corresponding to each metal layer in the prediction layer can be referred to in the above-described process of determining the first feature map corresponding to the prediction layer. That is, the specific process of obtaining the first feature map describing the same chip feature using the second feature map corresponding to the same chip feature on each metal layer will not be repeated here. Similarly, the specific process of determining the first vertical true congestion map corresponding to the prediction layer is the same as the process of determining the first horizontal true congestion map, and will not be repeated here.

[0182] It should be understood that the M first feature maps corresponding to each prediction layer have the same size as the actual congestion map.

[0183] As can be seen in this embodiment, based on the above-mentioned layering method, in each prediction layer, since the real congestion maps corresponding to each metal layer have strong correlation and consistency, the real congestion map of each prediction layer obtained based on the method in this embodiment has good consistency with the real congestion maps of each metal layer in the prediction layer. That is, a real congestion map that accurately reflects the congestion degree of each prediction layer can be obtained, thereby ensuring the prediction accuracy of the congestion prediction model trained using the real congestion map of each prediction layer.

[0184] In one feasible implementation, the above-mentioned addition of M first feature maps corresponding to each prediction layer in the K semiconductor chips to a dataset and training a congestion prediction model using the dataset includes: iteratively training the congestion prediction model using the dataset; wherein, each iteration includes: processing the M first feature maps corresponding to any prediction layer in the dataset using the congestion prediction model to obtain a predicted congestion map corresponding to any prediction layer; and updating the congestion prediction model based on the predicted congestion map and the actual congestion map corresponding to any prediction layer.

[0185] Specifically, each iteration of training includes: determining single-iteration training samples from M first feature maps and 2 real congestion maps corresponding to any prediction layer. Each single-iteration training sample contains M third feature maps and 2 target real congestion maps. The M third feature maps are input into the congestion prediction model to obtain the predicted congestion map output by the model; the prediction error is determined based on the predicted congestion map and the 2 target real congestion maps. Based on the prediction error, the model parameters in the congestion prediction model are updated using gradient descent or other backpropagation algorithms. Finally, it is determined whether the training process has met a preset condition. When the preset condition is met, the training process of the congestion prediction model ends; when the preset condition is not met, the next iteration of training begins. The preset condition can be a training iteration greater than or equal to a preset number of iterations, a prediction error less than or equal to a preset error, or other feasible conditions, which are not limited in this application. The congestion prediction model can be a generative adversarial neural network, a variational autoencoder, a semantic segmentation neural network, etc., which are not limited in this application.

[0186] The process of determining the training samples for a single iteration is as follows:

[0187] M third feature maps are selected from any identical regions on the M first feature maps corresponding to the prediction layer. Two target real congestion maps are selected from these identical regions on the two real congestion maps corresponding to the prediction layer. The size of the M third feature maps and the two target real congestion maps is equal to the target size. These M third feature maps and the two target real congestion maps are used as training samples for a single iteration. The target size is the size of the input image allowed by the congestion prediction model, and the target size can be less than or equal to the size of the first feature maps.

[0188] Furthermore, when the target size is equal to the size of the M first feature maps corresponding to the prediction layer, the M first feature maps are respectively used as the aforementioned M third feature maps, and the two real congestion maps corresponding to the prediction layer are respectively used as the aforementioned two target real congestion maps. That is, at this time, the training samples in a single iteration include M first feature maps and 2 real congestion maps.

[0189] In one feasible implementation, each semiconductor chip includes prediction layers that are macrocell layers and non-macrocell layers, and the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; the step of adding M first feature maps corresponding to each prediction layer in the K semiconductor chips to the dataset and training the congestion prediction model using the dataset includes: training the first congestion prediction model using the first feature maps corresponding to the macrocell layers in the dataset and the corresponding real congestion maps; and training the second congestion prediction model using the first feature maps corresponding to the non-macrocell layers in the dataset and the corresponding real congestion maps.

[0190] Optionally, the multiple metal layers in each semiconductor chip are divided into two prediction layers: a macrocell layer and a non-macrocell layer. The first congestion prediction model and the second congestion prediction model have identical model structures, and their initial model parameters can be the same or different.

[0191] Specifically, the above-mentioned training of the first congestion prediction model using the first feature map corresponding to the macrounit layer in the dataset and the corresponding real congestion map includes: determining single-iteration training samples from the M first feature maps and the real congestion map corresponding to any macrounit layer, and then training the first congestion prediction model using the single-iteration training samples. The process of determining the single-iteration training samples used to train the first congestion prediction model can refer to the aforementioned process of determining single-iteration training samples for the congestion prediction model, and will not be repeated here; the specific training process of the first congestion prediction model can correspond to the same training process of the congestion prediction model in the above embodiments, and will not be repeated here.

[0192] Similarly, the training process of the second congestion prediction model is the same as that of the first congestion prediction model, and will not be repeated here.

[0193] Please see Figure 7 , Figure 7 This is a flowchart illustrating an image processing method 700 provided in an embodiment of this application. The method includes, but is not limited to, the following steps:

[0194] Step S710: Determine M first feature maps corresponding to each prediction layer in the semiconductor chip to be predicted; wherein the semiconductor chip to be predicted includes at least two prediction layers, and M is a positive integer;

[0195] Specifically, the method for determining the M first feature maps corresponding to each prediction layer can be referred to Figure 5 The specific description of the illustrated embodiment will not be repeated here.

[0196] Step S720: Process the M first feature maps corresponding to each prediction layer using the congestion prediction model to obtain the prediction congestion map corresponding to each prediction layer;

[0197] The congestion prediction model is obtained by training a dataset, which includes training data corresponding to the training prediction layers of each of the K training semiconductor chips. The training data corresponding to each training prediction layer includes M first training feature maps and a real congestion map. The M first training feature maps are used to describe the M chip features of each training prediction layer, and the real congestion map is used to describe the real congestion level of each training prediction layer. Each training semiconductor chip includes at least two training prediction layers, and each training prediction layer includes at least one metal layer. K is a positive integer.

[0198] Optionally, when the size of the first feature map is larger than the target size of the input image of the congestion prediction model, a sliding window approach can be used to obtain M fourth feature maps for a single prediction from the M first feature maps. The size of each fourth feature map is the target size, such as... Figure 8 As shown, the length and width of the target size can be E and F, respectively, where E and F are positive integers and their units can be pixels.

[0199] Specifically, the following will refer to Figure 8 Describe the composition of the model input data used by the congestion prediction model for a single prediction:

[0200] Figure 8 The first feature map shown is any one of the M first feature maps corresponding to the prediction layer. For example... Figure 8 As shown, the first feature map can contain D fourth feature maps, and the width of the overlap between any two adjacent fourth feature maps is G, where G is an integer greater than or equal to zero, and the unit can be pixels. That is, each of the M first feature maps contains D fourth feature maps. The M fourth feature maps in the same region on the M first feature maps are used as input data for a single prediction by the model. In summary, the M first feature maps corresponding to each prediction layer contain a total of D sets of input data for congestion prediction. Each set of input data corresponds to a specific region on the first feature map, and also to a specific region on the prediction layer, where D is a positive integer.

[0201] Optionally, the above-mentioned processing of the M first feature maps corresponding to each prediction layer using the congestion prediction model to obtain the predicted congestion map corresponding to each prediction layer includes: sequentially inputting D sets of input data corresponding to each prediction layer into one or more congestion prediction models to obtain the predicted congestion map corresponding to each set of input data, for a total of D sets of predicted congestion maps. Each set of predicted congestion maps includes a horizontal predicted congestion map and a vertical predicted congestion map. The horizontal predicted congestion maps in the D sets of predicted congestion maps are concatenated to obtain the horizontal predicted congestion map corresponding to each prediction layer; the vertical predicted congestion maps in the D sets of predicted congestion maps are concatenated to obtain the vertical congestion map corresponding to each prediction layer. It should be noted that during the concatenation of the two predicted congestion maps, in the overlapping part of the two predicted congestion maps, each pixel point in the overlapping part corresponds to two pixel values ​​in the two predicted congestion maps. The pixel value of each pixel point after concatenation can be determined by weighted averaging or taking the maximum value, etc., of the two pixel values ​​corresponding to each pixel point.

[0202] Further, optionally, the above-mentioned inputting the D sets of input data corresponding to each prediction layer into one or more congestion prediction models sequentially includes: inputting the above-mentioned D sets of input data sequentially into a congestion prediction model trained to obtain a predicted congestion map corresponding to each set of input data; or inputting each set of input data in the D sets of input data into one of the multiple congestion prediction models to perform parallel prediction and obtain a predicted congestion map corresponding to each set of input data; wherein, the model structure and parameters of each of the multiple congestion prediction models are the same as those of the trained congestion prediction model.

[0203] As can be seen, the parallel prediction method adopted in this embodiment can greatly save the time of congestion prediction and improve efficiency.

[0204] Optionally, the above-mentioned inputting the D sets of input data corresponding to each prediction layer into one or more congestion prediction models includes: when the semiconductor chip to be predicted is divided into two prediction layers, namely a macrocell layer and a non-macrocell layer, inputting the D sets of input data corresponding to the macrocell layer into one or more first congestion prediction models to obtain the predicted congestion map corresponding to the macrocell layer. Inputting the D sets of input data corresponding to the non-macrocell layer into one or more second congestion prediction models to obtain the predicted congestion map corresponding to the non-macrocell layer.

[0205] Specifically, the training process for the aforementioned congestion prediction model can be found in [link to relevant documentation]. Figure 5 The embodiments described herein will not be repeated here.

[0206] In one feasible implementation, the method further includes: aggregating the prediction congestion maps corresponding to all prediction layers in the semiconductor chip to be predicted to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0207] Specifically, the vertical and horizontal prediction congestion maps corresponding to each prediction layer in the semiconductor chip to be predicted are aggregated to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0208] In one feasible implementation, the prediction congestion map corresponding to each prediction layer includes a vertical prediction congestion map and a horizontal prediction congestion map. Aggregating the prediction congestion maps corresponding to each prediction layer to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted includes: aggregating the vertical prediction congestion maps corresponding to each prediction layer using a hierarchical aggregation operator to obtain a reference vertical prediction congestion map; aggregating the horizontal prediction congestion maps corresponding to each prediction layer using the hierarchical aggregation operator to obtain a reference horizontal prediction congestion map; aggregating the reference vertical prediction congestion map and the reference horizontal prediction congestion map using a directional aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted; or aggregating the vertical and horizontal prediction congestion maps corresponding to each prediction layer using the directional aggregation operator to obtain a reference prediction congestion map corresponding to each prediction layer; and aggregating the reference prediction congestion map corresponding to each prediction layer using the hierarchical aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0209] Optionally, the hierarchical aggregation operator described above can be an operation such as averaging or maximizing. Specifically, the corresponding pixels on any two predicted congestion maps undergoing hierarchical aggregation are averaged or maximized to obtain the pixel value of the corresponding pixel on the aggregated predicted congestion map. Similarly, the directional aggregation operator described above can also be an operation such as averaging or maximizing, and this application does not limit this. Furthermore, the specific operation process of the directional aggregation operator can be found in the operation process corresponding to the hierarchical aggregation operator, and will not be repeated here.

[0210] In summary, the semiconductor chip to be predicted contains at least two prediction layers. First, directional aggregation operators can be used to aggregate the horizontal and vertical prediction congestion maps corresponding to each prediction layer to obtain a reference prediction congestion map for each prediction layer. Then, hierarchical aggregation operators can be used to aggregate the reference prediction congestion maps for each prediction layer to obtain the prediction congestion map for the semiconductor chip to be predicted. Alternatively, hierarchical aggregation operators can be used to aggregate the horizontal prediction congestion maps corresponding to each prediction layer separately to obtain a reference horizontal prediction congestion map. Hierarchical aggregation operators can then be used to aggregate the vertical prediction congestion maps corresponding to each prediction layer separately to obtain a reference vertical prediction congestion map. Finally, directional aggregation operators can be used to aggregate the reference horizontal and reference vertical prediction congestion maps to obtain the prediction congestion map for the semiconductor chip to be predicted. Alternatively, other aggregation orders can be used, employing hierarchical and directional aggregation operators to aggregate the prediction congestion maps corresponding to each prediction layer to obtain the prediction congestion map for the semiconductor chip to be predicted. This application does not limit this approach.

[0211] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers is obtained based on the K training semiconductor chips after global routing.

[0212] In one feasible implementation, the training prediction layer included in each of the training semiconductor chips is obtained based on the manufacturing process of the metal layers in each training semiconductor chip or the functional module distribution.

[0213] In one feasible implementation, the M first training feature maps corresponding to each training prediction layer are obtained based on the M second feature maps corresponding to each metal layer in each training prediction layer; wherein, the first training feature map in the M first training feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the feature of that chip.

[0214] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each of the training prediction layers includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each of the training prediction layers, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each of the training prediction layers.

[0215] In one feasible implementation, during each iteration of the congestion prediction model training, the congestion prediction model is updated using the predicted congestion map corresponding to any training prediction layer in the dataset and the actual congestion map corresponding to that training prediction layer; the predicted congestion map corresponding to any training prediction layer is obtained by inputting M first training feature maps corresponding to that training prediction layer into the congestion prediction model.

[0216] In one feasible implementation, the plurality of training prediction layers are divided into macrocell layers and non-macrocell layers, and the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; the first congestion prediction model is trained using a first training feature map corresponding to the macrocell layer in the dataset and a corresponding real congestion map; the second congestion prediction model is trained using a first training feature map corresponding to the non-macrocell layer in the dataset and a corresponding real congestion map.

[0217] In one feasible implementation, the M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0218] Specifically, the detailed process of training the congestion prediction model using a training semiconductor chip can be found in [reference needed]. Figure 5 The specific description of the embodiments shown will not be repeated here.

[0219] Please see Figure 9 , Figure 9 This is a schematic diagram illustrating a congestion prediction process provided in an embodiment of this application. Figure 9 As shown, the congestion prediction process for a semiconductor chip is as follows: The semiconductor chip to be predicted is divided into two prediction layers: a macrocell layer and a non-macrocell layer. M first feature maps corresponding to the macrocell layer and the non-macrocell layer are determined according to the method described in the previous embodiment. The first congestion prediction model is used to process the M first feature maps corresponding to the macrocell layer to obtain the horizontal and vertical predicted congestion maps corresponding to the macrocell layer. The second congestion prediction model is used to process the M first feature maps corresponding to the non-macrocell layer to obtain the horizontal and vertical predicted congestion maps corresponding to the non-macrocell layer. Finally, hierarchical aggregation operators and directional aggregation operators are used to aggregate the horizontal and vertical predicted congestion maps corresponding to the macrocell layer, the horizontal and vertical predicted congestion maps corresponding to the non-macrocell layer, and the vertical predicted congestion maps corresponding to the non-macrocell layer to obtain the predicted congestion map corresponding to the semiconductor chip to be predicted.

[0220] Specifically, the detailed process for predicting congestion in the aforementioned semiconductor chips can be found in the aforementioned [reference needed]. Figure 5 and Figure 7 The corresponding processes in the embodiments will not be repeated here.

[0221] The methods of the embodiments of this application have been described in detail above, and the apparatus of the embodiments of this application is provided below.

[0222] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of a model training device 1000 provided in an embodiment of this application. The device 1000 may include a layering unit 1010, a determination unit 1020 and a training unit 1030, wherein each unit is described in detail below.

[0223] A layering unit 1010 is used to divide multiple metal layers into at least two prediction layers; wherein the multiple metal layers are metal layers contained in each of K semiconductor chips, and K is a positive integer; a determination unit 1020 is used to determine M first feature maps corresponding to each prediction layer; wherein the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer; a training unit 1030 is used to add the M first feature maps corresponding to each prediction layer in the K semiconductor chips to the dataset, and use the dataset to train a congestion prediction model.

[0224] In one feasible implementation, the training unit is further configured to: obtain the real congestion map corresponding to each prediction layer based on the K semiconductor chips after global routing; and add the real congestion map corresponding to each prediction layer in the K semiconductor chips to the dataset.

[0225] In one feasible implementation, the layering unit is specifically used to divide the plurality of metal layers into at least two prediction layers according to the manufacturing process or functional module distribution of the metal layers in each semiconductor chip.

[0226] In one feasible implementation, the determining unit is specifically used to: obtain M second feature maps corresponding to each metal layer in each prediction layer; wherein the M second feature maps are used to describe the M chip features of each metal layer; and generate M first feature maps corresponding to each prediction layer based on the M second feature maps of each metal layer; wherein the first feature map in the M first feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the any chip feature.

[0227] In one feasible implementation, the true congestion map corresponding to each prediction layer includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each prediction layer includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each prediction layer, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each prediction layer.

[0228] In one feasible implementation, regarding the aspect of training the congestion prediction model using the dataset, the training unit is specifically used to: iteratively train the congestion prediction model using the dataset; wherein, each iteration includes: processing M first feature maps corresponding to any prediction layer in the dataset using the congestion prediction model to obtain a predicted congestion map corresponding to the predicted layer; and updating the congestion prediction model based on the predicted congestion map and the actual congestion map corresponding to the predicted layer.

[0229] In one feasible implementation, each of the semiconductor chips includes a prediction layer that is a macrocell layer and a non-macrocell layer, respectively; in terms of training the congestion prediction model using the dataset, the training unit is specifically used to: train the first congestion prediction model using the first feature map corresponding to the macrocell layer in the dataset and the corresponding real congestion map; and train the second congestion prediction model using the first feature map corresponding to the non-macrocell layer in the dataset and the corresponding real congestion map.

[0230] In one feasible implementation, the aforementioned M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0231] It should be noted that the implementation of each unit can also be referenced accordingly. Figure 5 and Figure 7 The corresponding description of the method embodiments shown.

[0232] Please see Figure 11 , Figure 11 This is a schematic diagram of the structure of an image processing apparatus 1100 provided in an embodiment of this application. The apparatus 1100 includes a determining unit 1110 and a processing unit 1120.

[0233] The determining unit 1110 is used to determine M first feature maps corresponding to each prediction layer in the semiconductor chip to be predicted; wherein the semiconductor chip to be predicted includes at least two prediction layers, and M is a positive integer; the processing unit 1120 is used to process the M first feature maps corresponding to each prediction layer using a congestion prediction model to obtain a predicted congestion map corresponding to each prediction layer; wherein the congestion prediction model is obtained by training on a dataset, the dataset includes training data corresponding to the training prediction layers contained in each of K training semiconductor chips, the training data corresponding to each training prediction layer includes M first training feature maps and a real congestion map, the M first training feature maps are used to describe the M chip features of each training prediction layer, the real congestion map is used to describe the real congestion degree of each training prediction layer, each training semiconductor chip includes at least two training prediction layers, and each training prediction layer includes at least one metal layer.

[0234] In one feasible implementation, the above apparatus further includes: an aggregation unit, configured to aggregate the prediction congestion maps corresponding to all prediction layers in the semiconductor chip to be predicted, to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0235] In one feasible implementation, the prediction congestion map corresponding to each prediction layer includes a vertical prediction congestion map and a horizontal prediction congestion map; the aggregation unit is specifically used to: aggregate the vertical prediction congestion map corresponding to each prediction layer using a hierarchical aggregation operator to obtain a reference vertical prediction congestion map; aggregate the horizontal prediction congestion map corresponding to each prediction layer using the hierarchical aggregation operator to obtain a reference horizontal prediction congestion map; aggregate the reference vertical prediction congestion map and the reference horizontal prediction congestion map using a directional aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted; or, aggregate the vertical prediction congestion map and the horizontal prediction congestion map corresponding to each prediction layer using the directional aggregation operator to obtain a reference prediction congestion map corresponding to each prediction layer; aggregate the reference prediction congestion map corresponding to each prediction layer using the hierarchical aggregation operator to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

[0236] In one feasible implementation, the training prediction layer included in each of the training semiconductor chips is obtained based on the manufacturing process of the metal layers in each training semiconductor chip or the functional module distribution.

[0237] In one feasible implementation, the M first training feature maps corresponding to each training prediction layer are obtained based on the M second feature maps corresponding to each metal layer in each training prediction layer; wherein, the first training feature map in the M first training feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the feature of that chip.

[0238] In one feasible implementation, the true congestion map corresponding to each of the training prediction layers includes a first horizontal true congestion map and a first vertical true congestion map, and the true congestion map corresponding to each metal layer in each of the training prediction layers includes a second horizontal true congestion map and a second vertical true congestion map; the first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each of the training prediction layers, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each of the training prediction layers.

[0239] In one feasible implementation, during each iteration of the congestion prediction model training, the congestion prediction model is updated using the predicted congestion map corresponding to any training prediction layer in the dataset and the actual congestion map corresponding to that training prediction layer; the predicted congestion map corresponding to any training prediction layer is obtained by inputting M first training feature maps corresponding to that training prediction layer into the congestion prediction model.

[0240] In one feasible implementation, the plurality of training prediction layers are divided into macrocell layers and non-macrocell layers, and the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; the first congestion prediction model is trained using a first training feature map corresponding to the macrocell layer in the dataset and a corresponding real congestion map; the second congestion prediction model is trained using a first training feature map corresponding to the non-macrocell layer in the dataset and a corresponding real congestion map.

[0241] In one feasible implementation, the M chip features include one or more of pin density, network connectivity density, module mask, or amount of wiring resources.

[0242] Specifically, the image processing device 1100 can be used to process... Figure 7 The corresponding steps of the image processing method 700 described herein will not be repeated here.

[0243] Please see Figure 12 , Figure 12 This is a schematic diagram of the hardware structure of a model training device 1200 provided in an embodiment of this application. Figure 12The model training device 1200 shown (which can specifically be a computer device) includes a memory 1201, a processor 1202, a communication interface 1203, and a bus 1204. The memory 1201, processor 1202, and communication interface 1203 are interconnected via the bus 1204.

[0244] The memory 1201 may be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1201 may store a program. When the program stored in the memory 1201 is executed by the processor 1202, the processor 1202 and the communication interface 1203 are used to execute the various steps of the training method of the congestion prediction model of the embodiments of this application.

[0245] The processor 1202 may be a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), graphics processing unit (GPU), or one or more integrated circuits, used to execute relevant programs to achieve the functions required by the units in the training device for the congestion prediction model in the embodiments of this application, or to execute the congestion prediction model training method in the method embodiments of this application.

[0246] The processor 1202 can also be an integrated circuit chip with signal processing capabilities. During implementation, each step of the training method for the congestion prediction model of this application can be completed by the integrated logic circuits in the hardware of the processor 1202 or by instructions in software form. The aforementioned processor 1202 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory 1201. The processor 1202 reads the information in the memory 1201 and, in conjunction with its hardware, performs the functions required by the units included in the training device of the congestion prediction model of this application embodiment, or executes the training method of the congestion prediction model of this application embodiment.

[0247] The communication interface 1203 uses a transceiver device, such as, but not limited to, a transceiver, to enable communication between the device 1200 and other devices or communication networks. For example, training data can be acquired through the communication interface 1203.

[0248] Bus 1204 may include a pathway for transmitting information between various components of device 1200 (e.g., memory 1201, processor 1202, communication interface 1203).

[0249] Please see Figure 13 , Figure 13 This is a schematic diagram of the hardware structure of the image processing device 1300 provided in an embodiment of this application. The image processing device 1300 may be a computer, mobile phone, tablet computer, or other possible terminal device; this application does not limit this to any particular type. Figure 13 The image processing device 1300 shown (which may specifically be a computer device) includes a memory 1301, a processor 1302, a communication interface 1303, and a bus 1304. The memory 1301, the processor 1302, and the communication interface 1303 are interconnected via the bus 1304.

[0250] The memory 1301 may be a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1301 may store a program. When the program stored in the memory 1301 is executed by the processor 1302, the processor 1302 and the communication interface 1303 are used to execute the various steps of the image processing method of the embodiments of this application.

[0251] The processor 1302 may be a general-purpose central processing unit (CPU), microprocessor, application-specific integrated circuit (ASIC), graphics processing unit (GPU), or one or more integrated circuits, used to execute relevant programs to achieve the functions required by the units in the image processing apparatus of this application embodiment, or to execute the image processing method of this application method embodiment.

[0252] The processor 1302 can also be an integrated circuit chip with signal processing capabilities. In implementation, each step of the image processing method of this application can be completed by the integrated logic circuits in the hardware of the processor 1302 or by instructions in software form. The processor 1302 described above can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory 1301. The processor 1302 reads the information in the memory 1301 and, in conjunction with its hardware, performs the functions required by the units included in the image processing apparatus of this application embodiment, or executes the image processing method of the method embodiment of this application.

[0253] The communication interface 1303 uses a transceiver device, such as, but not limited to, a transceiver, to enable communication between the device 1300 and other devices or communication networks. For example, training data can be acquired through the communication interface 1303.

[0254] Bus 1304 may include a pathway for transmitting information between various components of device 1300 (e.g., memory 1301, processor 1302, communication interface 1303).

[0255] It should be noted that, although Figure 12 and Figure 13 The illustrated devices 1200 and 1300 only show the memory, processor, and communication interface. However, those skilled in the art should understand that in specific implementations, devices 1200 and 1300 may also include other devices necessary for normal operation. Furthermore, depending on specific needs, those skilled in the art should understand that devices 1200 and 1300 may also include hardware devices for implementing other additional functions. Moreover, those skilled in the art should understand that devices 1200 and 1300 may only include the devices necessary for implementing the embodiments of this application, and may not necessarily include... Figure 12 or Figure 13 All the devices shown.

[0256] It can be understood that the aforementioned device 1200 is equivalent to Figure 1 The training equipment 120 and device 1300 are equivalent to Figure 1 The execution device 110 is described herein. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0257] This application embodiment also provides a chip system, the chip system including at least one processor, a memory, and an interface circuit, the memory, the interface circuit, and the at least one processor being interconnected via circuits, the at least one memory storing instructions; when the instructions are executed by the processor, the above... Figure 5 and / or Figure 7 The method was thus implemented.

[0258] This application also provides a computer-readable storage medium storing instructions that, when executed on a network device. Figure 5 / or Figure 7 The method and flow shown are thus implemented.

[0259] This application also provides a computer program product, which, when run on a terminal, provides a solution for... Figure 5 / or Figure 7 The method and flow shown are thus implemented.

[0260] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0261] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0262] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0263] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0264] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0265] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A training method for a congestion prediction model, characterized in that, The method includes: Multiple metal layers are divided into at least two prediction layers; wherein, the multiple metal layers are the metal layers contained in each of K semiconductor chips, and K is a positive integer; M first feature maps are determined for each prediction layer; wherein the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer; The M first feature maps corresponding to each prediction layer in the K semiconductor chips are added to the dataset, and the congestion prediction model is trained using the dataset.

2. The method according to claim 1, characterized in that, The method further includes: Global routing is performed on the K semiconductor chips, and the actual congestion map corresponding to each prediction layer is obtained based on the K semiconductor chips after global routing. The actual congestion map corresponding to each prediction layer in the K semiconductor chips is added to the dataset.

3. The method according to claim 1 or 2, characterized in that, The process of dividing multiple metal layers into at least two prediction layers includes: The plurality of metal layers are divided into at least two prediction layers based on the manufacturing process or functional module distribution of the metal layers in each of the semiconductor chips.

4. The method according to claim 1, characterized in that, The determination of the M first feature maps corresponding to each prediction layer includes: Obtain M second feature maps corresponding to each metal layer in each prediction layer; wherein the M second feature maps are used to describe the M chip features of each metal layer respectively; Based on the M second feature maps of each metal layer, M first feature maps corresponding to each prediction layer are generated; wherein, the first feature map in the M first feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the chip feature.

5. The method according to claim 2, characterized in that, The true congestion map corresponding to each prediction layer includes a first horizontal true congestion map and a first vertical true congestion map. The true congestion map corresponding to each metal layer in each prediction layer includes a second horizontal true congestion map and a second vertical true congestion map. The first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each prediction layer, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each prediction layer.

6. The method according to claim 2, characterized in that, The step of adding the M first feature maps corresponding to each prediction layer in the K semiconductor chips to the dataset and training the congestion prediction model using the dataset includes: The congestion prediction model is iteratively trained using the dataset; wherein each iteration includes: The congestion prediction model is used to process the M first feature maps corresponding to any prediction layer in the dataset to obtain the predicted congestion map corresponding to any prediction layer. The congestion prediction model is updated based on the predicted congestion graph and the actual congestion graph corresponding to any prediction layer.

7. The method according to claim 2, characterized in that, Each semiconductor chip includes prediction layers that are either macrocell layers or non-macrocell layers; the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; the step of adding the M first feature maps corresponding to each prediction layer in the K semiconductor chips to the dataset and training the congestion prediction model using the dataset includes: The first congestion prediction model is trained using the first feature map corresponding to the macro-unit layer in the dataset and the corresponding real congestion map; The second congestion prediction model is trained using the first feature map corresponding to the non-macrocell layer in the dataset and the corresponding real congestion map.

8. The method according to claim 1, characterized in that, The M chip features include one or more of the following: pin density, network connection density, module mask, or amount of winding resources.

9. An image processing method, characterized in that, The method includes: M first feature maps corresponding to each prediction layer in the semiconductor chip to be predicted are determined; wherein, the semiconductor chip to be predicted includes at least two prediction layers, and M is a positive integer; The congestion prediction model is used to process the M first feature maps corresponding to each prediction layer to obtain the prediction congestion map corresponding to each prediction layer. The congestion prediction model is obtained by training a dataset, which includes training data corresponding to each training prediction layer in K training semiconductor chips. The training data corresponding to each training prediction layer includes M first training feature maps and a real congestion map. The M first training feature maps are used to describe the M chip features of each training prediction layer, and the real congestion map is used to describe the real congestion degree of each training prediction layer. Each training semiconductor chip includes at least two training prediction layers, and each training prediction layer includes at least one metal layer.

10. The method according to claim 9, characterized in that, The method further includes: The prediction congestion maps corresponding to all prediction layers in the semiconductor chip to be predicted are aggregated to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

11. The method according to claim 10, characterized in that, Each prediction layer corresponds to a prediction congestion graph, which includes a vertical prediction congestion graph and a horizontal prediction congestion graph. The prediction congestion graphs corresponding to each prediction layer are aggregated to obtain the prediction congestion graph corresponding to the semiconductor chip to be predicted, including: The hierarchical aggregation operator is used to aggregate the vertical prediction congestion map corresponding to each prediction layer to obtain a reference vertical prediction congestion map; the hierarchical aggregation operator is used to aggregate the horizontal prediction congestion map corresponding to each prediction layer to obtain a reference horizontal prediction congestion map; the directional aggregation operator is used to aggregate the reference vertical prediction congestion map and the reference horizontal prediction congestion map to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted. or The directional aggregation operator is used to aggregate the vertical and horizontal prediction congestion maps corresponding to each prediction layer to obtain a reference prediction congestion map corresponding to each prediction layer; the hierarchical aggregation operator is used to aggregate the reference prediction congestion maps corresponding to each prediction layer to obtain a prediction congestion map corresponding to the semiconductor chip to be predicted.

12. The method according to any one of claims 9-11, characterized in that, The true congestion graph corresponding to each of the training prediction layers is obtained based on the K training semiconductor chips after global routing.

13. The method according to claim 9, characterized in that, The training prediction layer contained in each of the training semiconductor chips is determined based on the manufacturing process of the metal layers or the distribution of functional modules in each training semiconductor chip.

14. The method according to claim 9, characterized in that, The M first training feature maps corresponding to each training prediction layer are obtained based on the M second feature maps corresponding to each metal layer in each training prediction layer; wherein, the first training feature map in the M first training feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the feature of that chip.

15. The method according to claim 9, characterized in that, The true congestion map corresponding to each of the training prediction layers includes a first horizontal true congestion map and a first vertical true congestion map. The true congestion map corresponding to each metal layer in each of the training prediction layers includes a second horizontal true congestion map and a second vertical true congestion map. The first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each of the training prediction layers, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each of the training prediction layers.

16. The method according to claim 9, characterized in that, During each iteration of the congestion prediction model training, the congestion prediction model is updated using the predicted congestion map corresponding to any training prediction layer in the dataset and the actual congestion map corresponding to that training prediction layer. The predicted congestion map corresponding to any training prediction layer is obtained by inputting the M first training feature maps corresponding to that training prediction layer into the congestion prediction model.

17. The method according to claim 9, characterized in that, The training prediction layers are divided into macro-unit layers and non-macro-unit layers. The congestion prediction model includes a first congestion prediction model and a second congestion prediction model. The first congestion prediction model is trained using the first training feature map corresponding to the macro-unit layer in the dataset and the corresponding real congestion map. The second congestion prediction model is trained using the first training feature map corresponding to the non-macro-unit layer in the dataset and the corresponding real congestion map.

18. The method according to claim 9, characterized in that, The M chip features include one or more of the following: pin density, network connection density, module mask, or amount of winding resources.

19. A training device for a congestion prediction model, characterized in that, The device includes: A layering unit is used to divide multiple metal layers into at least two prediction layers; wherein the multiple metal layers are metal layers contained in each of K semiconductor chips, and K is a positive integer; A determining unit is configured to determine M first feature maps corresponding to each prediction layer; wherein the M first feature maps are used to describe M chip features of each prediction layer, and M is a positive integer; The training unit is used to add the M first feature maps corresponding to each prediction layer in the K semiconductor chips to the dataset, and use the dataset to train the congestion prediction model.

20. The apparatus according to claim 19, characterized in that, The training unit is also used for: Based on the K semiconductor chips after global routing, the true congestion map corresponding to each prediction layer is obtained; The actual congestion map corresponding to each prediction layer in the K semiconductor chips is added to the dataset.

21. The apparatus according to claim 19 or 20, characterized in that, The hierarchical unit is specifically used for: The plurality of metal layers are divided into at least two prediction layers based on the manufacturing process or functional module distribution of the metal layers in each of the semiconductor chips.

22. The apparatus according to claim 19, characterized in that, The determining unit is specifically used for: Obtain M second feature maps corresponding to each metal layer in each prediction layer; wherein the M second feature maps are used to describe the M chip features of each metal layer respectively; Based on the M second feature maps of each metal layer, M first feature maps corresponding to each prediction layer are generated; wherein, the first feature map in the M first feature maps used to describe any chip feature is obtained based on the second feature map in each metal layer describing the chip feature.

23. The apparatus according to claim 20, characterized in that, The true congestion map corresponding to each prediction layer includes a first horizontal true congestion map and a first vertical true congestion map. The true congestion map corresponding to each metal layer in each prediction layer includes a second horizontal true congestion map and a second vertical true congestion map. The first horizontal true congestion map is obtained based on the second horizontal true congestion map corresponding to each metal layer in each prediction layer, and the first vertical true congestion map is obtained based on the second vertical true congestion map corresponding to each metal layer in each prediction layer.

24. The apparatus according to claim 20, characterized in that, In the aspect of training the congestion prediction model using the dataset, the training unit is specifically used for: The congestion prediction model is iteratively trained using the dataset; wherein each iteration includes: The congestion prediction model is used to process the M first feature maps corresponding to any prediction layer in the dataset to obtain the predicted congestion map corresponding to any prediction layer. The congestion prediction model is updated based on the predicted congestion graph and the actual congestion graph corresponding to any prediction layer.

25. The apparatus according to claim 20, characterized in that, Each semiconductor chip includes prediction layers that are macrocell layers and non-macrocell layers; the congestion prediction model includes a first congestion prediction model and a second congestion prediction model; in terms of training the congestion prediction model using the dataset, the training unit is specifically used for: The first congestion prediction model is trained using the first feature map corresponding to the macro-unit layer in the dataset and the corresponding real congestion map; The second congestion prediction model is trained using the first feature map corresponding to the non-macrocell layer in the dataset and the corresponding real congestion map.

26. The apparatus according to claim 19, characterized in that, The M chip features include one or more of the following: pin density, network connection density, module mask, or amount of winding resources.

27. An image processing apparatus, characterized in that, The device includes: A determining unit is configured to determine M first feature maps corresponding to each prediction layer in the semiconductor chip to be predicted; wherein the semiconductor chip to be predicted includes at least two prediction layers, and M is a positive integer; The processing unit is used to process the M first feature maps corresponding to each prediction layer using the congestion prediction model to obtain the prediction congestion map corresponding to each prediction layer. The congestion prediction model is obtained by training a dataset, which includes training data corresponding to the training prediction layers of each of the K training semiconductor chips. The training data corresponding to each training prediction layer includes M first training feature maps and a real congestion map. The M first training feature maps are used to describe the M chip features of each training prediction layer, and the real congestion map is used to describe the real congestion level of each training prediction layer. Each training semiconductor chip includes at least two training prediction layers, and each training prediction layer includes at least one metal layer.

28. The apparatus according to claim 27, characterized in that, The device further includes: The aggregation unit is used to aggregate the prediction congestion maps corresponding to all prediction layers in the semiconductor chip to be predicted, so as to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted.

29. The apparatus according to claim 28, characterized in that, Each prediction layer corresponds to a prediction congestion graph that includes a vertical prediction congestion graph and a horizontal prediction congestion graph; the aggregation unit is specifically used for: The hierarchical aggregation operator is used to aggregate the vertical prediction congestion map corresponding to each prediction layer to obtain a reference vertical prediction congestion map; the hierarchical aggregation operator is used to aggregate the horizontal prediction congestion map corresponding to each prediction layer to obtain a reference horizontal prediction congestion map; the directional aggregation operator is used to aggregate the reference vertical prediction congestion map and the reference horizontal prediction congestion map to obtain the prediction congestion map corresponding to the semiconductor chip to be predicted. or, The directional aggregation operator is used to aggregate the vertical and horizontal prediction congestion maps corresponding to each prediction layer to obtain a reference prediction congestion map corresponding to each prediction layer; the hierarchical aggregation operator is used to aggregate the reference prediction congestion maps corresponding to each prediction layer to obtain a prediction congestion map corresponding to the semiconductor chip to be predicted.

30. A chip system, characterized in that, The chip system includes at least one processor, a memory, and an interface circuit. The memory, the interface circuit, and the at least one processor are interconnected via lines. The at least one memory stores instructions. When the instructions are executed by the processor, the method described in any one of claims 1-18 is implemented.

31. A terminal device, characterized in that, The terminal device includes the chip system as described in claim 30, and discrete devices coupled to the chip system.

32. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program instructions that, when executed on a processor, implement the method described in any one of claims 1-18.

33. A computer program product, characterized in that, When the computer program product is run on a terminal, the method described in any one of claims 1-18 is implemented.

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