Driving method of display panel and display device

Abstract

The application discloses a driving method of a display panel (100) and a display device. The driving method comprises the following steps: when a display mode switching on instruction is received, entering a non-counting state, driving the display panel (100) to display a first setting picture, and switching a current display mode to a target display mode (S10); and when a data mode switching completion instruction is received, entering a counting state (S20).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a driving method and display device for a display panel. Background Technology

[0002] Display panels such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED) typically include multiple pixel units. Each pixel unit may include a red subpixel, a green subpixel, and a blue subpixel. By controlling the brightness of each subpixel, the desired colors are mixed to display a color image. Summary of the Invention

[0003] The display panel driving method provided in this disclosure includes:

[0004] Upon receiving a command to enable display mode switching, the system enters a non-counting state, drives the display panel to display the first set screen, and switches the current display mode to the target display mode.

[0005] Upon receiving the data mode switching completion instruction, it enters the counting state.

[0006] In some examples, after entering the counting state, the following is also included:

[0007] Receive display data;

[0008] Count the first number of the set targets corresponding to the displayed data;

[0009] After determining that the first number is the same as the set number corresponding to the target display mode, the display panel is driven to display the corresponding screen based on the target display mode and the received display data.

[0010] In some examples, after counting the first number of the set target in the display data, and after determining that the first number is the same as the set number corresponding to the target display mode, before driving the display panel to display the corresponding screen based on the target display mode and the received display data, the method further includes:

[0011] When it is determined that the first number is the same as the set number, the display panel is driven to display the second set screen in at least one display frame based on the target display mode.

[0012] In some examples, the number of display frames for displaying the second set screen is determined using the following formula;

[0013] SM = TM / AM;

[0014] Wherein, SM represents the number of display frames for displaying the second set screen, TM represents the set time, and AM represents the reciprocal of the refresh rate corresponding to the target display mode.

[0015] In some examples, at least one of the first setting screen and the second setting screen includes at least one of a solid color screen and a grayscale screen.

[0016] In some examples, the non-counting state includes one of the following: a zero-counting state, an disabled state, and a power-off state.

[0017] In some examples, the display panel includes a first display mode; wherein the first display mode includes: in the first display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous odd-numbered row of display sub-pixels are driven and the gate lines connected to the next odd-numbered row of display sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data lines corresponding to the next even-numbered row of display sub-pixels; and in the second display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous even-numbered row of display sub-pixels are driven and the gate lines connected to the next even-numbered row of display sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data lines corresponding to the next even-numbered row of display sub-pixels.

[0018] In some examples, the display panel includes a second display mode; wherein the second display mode includes: driving the gate lines line by line in each display frame, and when the previous row of gate lines has been driven and the next row of gate lines is being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the next row of gate lines.

[0019] In some examples, the display panel includes a third display mode; wherein the third display mode includes: in each display frame, taking at least two adjacent rows of gate lines as a gate line group, receiving display data corresponding to a row of sub-pixels in each gate line group, simultaneously driving the gate lines in the same gate line group according to the received display data, and driving the gate line groups one by one, when the gate lines in the previous gate line group have been driven and the gate lines in the next gate line group are being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group.

[0020] In some examples, the current display mode is one of the first display mode, the second display mode, and the third display mode;

[0021] The target display mode is one of the first display mode, the second display mode, and the third display mode, excluding the current display mode.

[0022] In some examples, the target setting includes sub-pixel rows of the display panel;

[0023] The display panel includes display sub-pixel rows and virtual sub-pixel rows;

[0024] When the target display mode is the first display mode, the set number includes the total number of all virtual sub-pixel rows and half of the total number of display sub-pixel rows;

[0025] When the target display mode is the second display mode, the set number includes the total number of all virtual subpixel rows and the total number of all display subpixel rows.

[0026] In some examples, the set target includes the grid lines of the display panel;

[0027] When the target display mode is the third display mode, the set number includes the total number of grid line groups.

[0028] The display device provided in this disclosure includes:

[0029] Display panel;

[0030] The timing controller is configured as follows:

[0031] Upon receiving a command to enable display mode switching, the system enters a non-counting state, drives the display panel to display the first set screen, and switches the current display mode to the target display mode.

[0032] Upon receiving the data mode switching completion instruction, it enters the counting state.

[0033] In some examples, the display device further includes:

[0034] The system circuit is configured as follows:

[0035] When it is determined to switch between different display modes, a display mode switching enable command is sent to the timing controller, and the data transmission mode corresponding to the current display mode is switched to the data transmission mode corresponding to the target display mode;

[0036] After switching the data transmission mode corresponding to the current display mode to the data transmission mode corresponding to the target display mode, a data mode switching completion command is sent to the timing controller.

[0037] In some examples, the display device further includes a counting unit;

[0038] The counting unit is configured to count the first number of the set target corresponding to the displayed data, and output a counting pass command when it is determined that the first number is the same as the set number corresponding to the target display mode;

[0039] The timing controller is further configured to control the counting unit to enter the non-counting state when it receives the display mode switching enable command; and to control the counting unit to enter the counting state when it receives the data mode switching complete command.

[0040] In some examples, the counting unit is integrated within the timing controller. Attached Figure Description

[0041] Figure 1 Some structural schematic diagrams of the display device provided in the embodiments of this disclosure;

[0042] Figure 2 Some structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0043] Figure 3 These are some other structural schematic diagrams of the display panel provided in the embodiments of this disclosure;

[0044] Figure 4 Some signal timing diagrams provided for embodiments of this disclosure;

[0045] Figure 5 Other signal timing diagrams provided for embodiments of this disclosure;

[0046] Figure 6 Further signal timing diagrams provided for embodiments of this disclosure;

[0047] Figure 7 Some flowcharts of the driving method provided in the embodiments of this disclosure;

[0048] Figure 8 Other structural schematic diagrams of the display device provided in the embodiments of this disclosure;

[0049] Figure 9 Further signal timing diagrams are provided for embodiments of this disclosure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0052] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0053] See Figure 1 and Figure 2 The display device may include a display panel 100, a timing controller 200, and a system circuit 300. The display panel 100 may include multiple pixel units arranged in an array, multiple gate lines GA (e.g., GA1, GA2, GA3, GA4), multiple data lines DA (e.g., DA1, DA2, DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, respectively, and the source driving circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. Exemplarily, each pixel unit includes multiple sub-pixels SPX. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing of red, green, and blue to achieve color display. Alternatively, a pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, allowing for color mixing of red, green, blue, and white to achieve color display. Of course, in practical applications, the emission color of the sub-pixels in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0054] For example, there can be two source drive circuits 120, with one source drive circuit 120 connected to half of the data lines and the other source drive circuit 120 connected to the other half of the data lines. Of course, there can also be three, four, or more source drive circuits 120, which can be designed and determined according to the actual application requirements, and are not limited here.

[0055] See Figure 2 As shown, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. One row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. The gate of transistor 01 is electrically connected to the corresponding gate line, the source of transistor 01 is electrically connected to the corresponding data line, and the drain of transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure of this disclosure can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels. This arrangement can reduce the number of data lines by half; that is, some adjacent columns of sub-pixels contain data lines, while others do not. The specific sub-pixel arrangement structure and the arrangement of data lines and scan lines are not limited.

[0056] It should be noted that the display panel 100 in this embodiment can be a liquid crystal display panel 100, an OLED display panel 100, etc., and is not limited thereto.

[0057] To improve the display quality, dummy subpixels can be set in the non-display area of ​​the display panel 100. Exemplarily, in this embodiment, the dummy subpixels are located in the peripheral area of ​​the display subpixels. That is, the area where the display subpixels are located is the display area, and the area on the substrate other than the display area can be a non-display area. The gate driving circuit 110 and the source driving circuit 120 can be disposed in the non-display area, and the dummy subpixels can be located in the dummy area of ​​the non-display area. For example, as... Figure 3 As shown, display subpixels R11 to B62 are illustrated. Virtual subpixels can be set around the periphery of display subpixels R11 to B62. For example, virtual subpixels can be set above display subpixels R11 to B12. Alternatively, virtual subpixels can be set below display subpixels R61 to B62; this is not limited here. Optionally, the structure in the virtual subpixels can be substantially the same as the structure in the display subpixels. Alternatively, pixel electrodes can be set only in the virtual subpixels without transistors. Of course, in practical applications, the number of virtual subpixels can be set according to the needs of the application; this is not limited here.

[0058] Different display application scenarios require different display effects. For example, in static image display, low power consumption is preferred over a high refresh rate. In game mode, a higher refresh rate is needed for smoother display. The display panel 100 provided in this embodiment can be applied to a variety of different display modes. For example, in conjunction with... Figure 1 and Figure 2 The system circuit 300 can acquire the original display data of the image to be displayed (the original display data includes a digital signal form of data voltage carrying the corresponding grayscale value for each sub-pixel (including display sub-pixels and virtual sub-pixels) in the display panel 100), process the original display data accordingly to obtain the display data corresponding to the current display mode, and send the obtained display data to the timing controller 200. The timing controller 200, based on the obtained display data and the current display mode, inputs a corresponding control signal to the gate driving circuit 110 in the display panel 100, controlling the gate driving circuit 110 to drive the gate lines GA (e.g., GA1, GA2, GA3, GA4) in the display panel 100, thereby controlling the transistors in the sub-pixels to turn on. Furthermore, the timing controller 200 sends the received display data to the source driving circuit, which loads data voltage onto the data lines DA (e.g., DA1, DA2, DA3) in the display panel 100 according to the received display data. When the transistors in the sub-pixels are turned on, the sub-pixels are charged, thus charging each sub-pixel with data voltage and realizing the image display function.

[0059] The following explanation uses an example where a pixel unit includes red, green, and blue sub-pixels. Figure 3As shown, red sub-pixels R11, green sub-pixels G11, and blue sub-pixels B11 form a pixel unit; red sub-pixels R12, green sub-pixels G12, and blue sub-pixels B12 form a pixel unit; red sub-pixels R21, green sub-pixels G21, and blue sub-pixels B21 form a pixel unit; red sub-pixels R22, green sub-pixels G22, and blue sub-pixels B22 form a pixel unit; red sub-pixels R31, green sub-pixels G31, and blue sub-pixels B31 form a pixel unit; red sub-pixels R32, green sub-pixels G32, and blue sub-pixels B32 form a pixel unit; red sub-pixels R41, green sub-pixels G41, and blue sub-pixels B41 form a pixel unit; red sub-pixels R42, green sub-pixels G42, and blue sub-pixels B42 form a pixel unit. Red subpixel R51, green subpixel G51, with blue subpixel B51 as one pixel unit; red subpixel R52, green subpixel G52, with blue subpixel B52 as one pixel unit; red subpixel R61, green subpixel G61, with blue subpixel B61 as one pixel unit; red subpixel R62, green subpixel G62, with blue subpixel B62 as one pixel unit.

[0060] The display panel 100 in this embodiment may include multiple different display modes, and can switch between any two display modes. In some examples, one of the multiple display modes may be a second display mode. The second display mode may include: in each display frame, the system circuit 300 executes a data transmission mode corresponding to the second display mode: sending the received raw display data (including a digital signal form of a data voltage carrying the corresponding grayscale value for each display sub-pixel and each virtual sub-pixel) to the timing controller 200. Based on the received display data, the timing controller 200 controls the gate driving circuit to drive the gate lines row by row and sends the display data to the source driving circuit. The source driving circuit, based on the received display data, inputs the corresponding display data voltage to the data line corresponding to the sub-pixel connected to the next row of gate lines while the previous row of gate lines is driven and the next row of gate lines is being driven.

[0061] For example, combining Figure 3 and Figure 4As shown, ga1 represents the signal loaded on gate line GA1, ga2 represents the signal loaded on gate line GA2, ga3 represents the signal loaded on gate line GA3, ga4 represents the signal loaded on gate line GA4, ga5 represents the signal loaded on gate line GA5, and ga6 represents the signal loaded on gate line GA6. Vda1 represents the data voltage loaded on data line DA1. Furthermore, the high level of signals ga1 to ga6 can be used as a gate enable signal to control the transistor in the sub-pixel to conduct. When the display panel 100 is driven in the second display mode, gate enable signals can be sequentially loaded onto gate lines GA1 to GA6. Taking a display frame F03, data line DA1, and the red sub-pixel connected to data line DA1 as an example, when signal ga1 on gate line GA1 outputs a high-level gate enable signal, the transistor in the red sub-pixel R11 conducts. And during the T31 time period corresponding to the high level of signal ga1, the data voltage Vr11 corresponding to the display data is loaded onto data line DA1 connected to the red sub-pixel R11, so that the red sub-pixel R11 inputs the data voltage Vr11. Furthermore, during time period T31, the signal ga2 on gate line GA2 outputs a high-level gate-on signal, turning on the transistor in the red sub-pixel R21. Simultaneously, the data voltage Vr11 is input to the red sub-pixel R21 to pre-charge it.

[0062] Furthermore, during the T32 time period corresponding to the high level of signal ga2, a data voltage Vr21 corresponding to the displayed data is applied to the data line DA1 connected to the red sub-pixel R21, so that the red sub-pixel R21 is charged with the data voltage Vr21. Also, during the T32 time period, signal ga3 on gate line GA3 outputs a high-level gate-on signal, turning on the transistor in the red sub-pixel R31. Simultaneously, the data voltage Vr21 is input to the red sub-pixel R31 to pre-charge it.

[0063] Furthermore, during the T33 time period corresponding to the high level of signal ga3, a data voltage Vr31 corresponding to the displayed data is applied to the data line DA1 connected to the red sub-pixel R31, so that the red sub-pixel R31 is charged with the data voltage Vr31. Also, during the T33 time period, signal ga4 on gate line GA4 outputs a high-level gate-on signal, turning on the transistor in the red sub-pixel R41. Simultaneously, the data voltage Vr31 is input to the red sub-pixel R41 to pre-charge it.

[0064] Furthermore, during the T34 time period corresponding to the high level of signal ga4, a data voltage Vr41 corresponding to the displayed data is applied to the data line DA1 connected to the red sub-pixel R41, so that the red sub-pixel R41 is charged with the data voltage Vr41. Also, during the T34 time period, signal ga5 on gate line GA5 outputs a high-level gate-on signal, turning on the transistor in the red sub-pixel R51. Simultaneously, the data voltage Vr41 is input to the red sub-pixel R51 to pre-charge it.

[0065] Furthermore, during the T35 time period corresponding to the high level of signal ga5, a data voltage Vr51 corresponding to the displayed data is applied to the data line DA1 connected to the red sub-pixel R51, so that the red sub-pixel R51 is charged with the data voltage Vr51. Also, during the T35 time period, signal ga6 on gate line GA6 outputs a high-level gate-on signal, turning on the transistor in the red sub-pixel R61. Simultaneously, the data voltage Vr51 is input to the red sub-pixel R51 to pre-charge it.

[0066] Furthermore, during the T36 time period corresponding to the high level of signal ga6, the data line DA1 connected to the red sub-pixel R61 is loaded with the corresponding display data voltage Vr61, so that the red sub-pixel R61 is charged with the data voltage Vr61. This also pre-charges the next red sub-pixel.

[0067] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel 100 are charged with data voltage, which will not be described in detail here.

[0068] It should be noted that when the display panel 100 is driven by the second display mode, the working process of each display frame is basically the same as that of the display frame F03 described above, and will not be repeated here.

[0069] In other examples, one of the multiple display modes can be a first display mode. The first display mode includes: in the first display frame of two adjacent display frames, the system circuit 300 executes a data transmission mode corresponding to the first display mode: after deleting the original display data corresponding to the display sub-pixels from the received original display data, display data corresponding to the odd-numbered rows of display sub-pixels is obtained; the obtained display data including the display data corresponding to the odd-numbered rows of display sub-pixels and the display data corresponding to each virtual sub-pixel is sent to the timing controller 200. It should be noted that, in this embodiment, optionally, the display panel includes virtual sub-pixels, and data voltages are sent to the virtual sub-pixels. Optionally, the display panel may also only include display sub-pixels; this is not limited here. The timing controller 200 sends a control signal corresponding to the first display mode to the gate driving circuit according to the received display data, so as to control the gate driving circuit to drive the gate lines in the display panel 100 line by line, and sends the display data corresponding to the odd-numbered row display sub-pixels and the display data corresponding to each virtual sub-pixel to the source driving circuit. According to the received display data (e.g., the display data of the odd-numbered row display sub-pixels), when the gate line connected to the previous virtual sub-pixel row is driven and the gate line connected to the next virtual sub-pixel row is driven, the source driving circuit inputs the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next virtual sub-pixel row, and when the gate line connected to the previous odd-numbered row display sub-pixel is driven and the gate line connected to the next odd-numbered row display sub-pixel is driven, the source driving circuit inputs the data voltage corresponding to the display data to the data line corresponding to the next odd-numbered row display sub-pixel. Furthermore, in the second display frame of two adjacent display frames, the system circuit 300 executes the data transmission mode corresponding to the first display mode: after deleting the original display data corresponding to the display sub-pixel in the received original display data, the display data corresponding to the even-numbered row display sub-pixel is obtained, and the obtained display data including the even-numbered row display sub-pixel and the display data corresponding to each virtual sub-pixel is sent to the timing controller 200.The timing controller 200 sends a control signal corresponding to the first display mode to the gate driving circuit according to the received display data, so as to control the gate driving circuit to drive the gate lines in the display panel 100 line by line, and sends the display data corresponding to the even-numbered row display sub-pixels and the display data corresponding to each virtual sub-pixel to the source driving circuit. According to the received display data (e.g., the display data of the even-numbered row display sub-pixels), when the gate line connected to the previous virtual sub-pixel row is driven and the gate line connected to the next virtual sub-pixel row is driven, the source driving circuit inputs the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next virtual sub-pixel row, and when the gate line connected to the previous even-numbered row display sub-pixel is driven and the gate line connected to the next even-numbered row display sub-pixel is driven, the source driving circuit inputs the data voltage corresponding to the display data to the data line corresponding to the next even-numbered row display sub-pixel.

[0070] For example, combining Figure 3 and Figure 5 The following describes the operation of the display panel 100 when driven in the first display mode. Here, ga1 represents the signal loaded on gate line GA1, ga2 represents the signal loaded on gate line GA2, ga3 represents the signal loaded on gate line GA3, ga4 represents the signal loaded on gate line GA4, ga5 represents the signal loaded on gate line GA5, and ga6 represents the signal loaded on gate line GA6. Vda1 represents the data voltage loaded on data line DA1. Furthermore, the high level of signals ga1 to ga6 can be used as a gate enable signal to control the transistor in the sub-pixel to conduct. When controlling the display panel to be driven in the third display mode, gate enable signals can be sequentially loaded onto gate lines GA1 to GA6. Taking two adjacent display frames F01 and F02, data line DA1, and the red sub-pixel connected to data line DA1 as an example...

[0071] In display frame F01, when signal ga1 on gate line GA1 outputs a high-level gate-on signal, the transistor in red sub-pixel R11 is turned on. During time period T11 corresponding to the high level of signal ga1, a data voltage Vr11 corresponding to the display data of red sub-pixel R11 is applied to data line DA1 connected to red sub-pixel R11, causing red sub-pixel R11 to input the data voltage Vr11. Also during time period T11, signal ga2 on gate line GA2 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R21. The data voltage Vr11 is simultaneously input to red sub-pixel R21 to pre-charge it. Also during time period T11, signal ga3 on gate line GA3 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R31. The data voltage Vr11 is simultaneously input to red sub-pixel R31 to pre-charge it. Furthermore, during time period T11, signal ga4 on gate line GA4 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R41. Data voltage Vr11 is simultaneously input to red sub-pixel R41 to pre-charge it. Also during time period T11, signal ga5 on gate line GA5 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R51. Data voltage Vr11 is simultaneously input to red sub-pixel R51 to pre-charge it. Finally, during time period T11, signal ga6 on gate line GA6 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R61. Data voltage Vr11 is simultaneously input to red sub-pixel R61 to pre-charge it.

[0072] Furthermore, during time period T12, signal ga1 goes low and signal ga3 goes high. A data voltage Vr31 corresponding to the display data of red sub-pixel R31 is applied to data line DA1 connected to red sub-pixel R31, charging red sub-pixel R31 with the data voltage Vr31. Also, when signal ga2 goes high, the data voltage Vr31 is simultaneously input to red sub-pixel R21 to charge it. Similarly, when signal ga4 goes high, the data voltage Vr31 is simultaneously input to red sub-pixel R41 to pre-charge it. And when signal ga5 goes high, the data voltage Vr31 is simultaneously input to red sub-pixel R51 to pre-charge it. Finally, when signal ga6 goes high, the data voltage Vr31 is simultaneously input to red sub-pixel R61 to pre-charge it.

[0073] Furthermore, during time period T13, signal ga3 goes low and signal ga5 goes high. A data voltage Vr51 corresponding to the display data of red sub-pixel R51 is applied to data line DA1 connected to red sub-pixel R51, thus charging red sub-pixel R51 with the data voltage Vr51. Also, when signal ga4 goes high, the data voltage Vr51 is simultaneously input to red sub-pixel R41 to charge it. And when signal ga6 goes high, the data voltage Vr51 is simultaneously input to red sub-pixel R61 to pre-charge it.

[0074] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel are charged with data voltage, which will not be elaborated here.

[0075] In display frame F02, when signal ga2 on gate line GA2 outputs a high-level gate-on signal, the transistor in red sub-pixel R21 is turned on. During time period T21 corresponding to the high level of signal ga2, a data voltage Vr21 corresponding to the display data of red sub-pixel R21 is applied to data line DA1 connected to red sub-pixel R21, causing red sub-pixel R21 to input the data voltage Vr21. Also, during time period T21, signal ga1 on gate line GA1 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R11. The data voltage Vr21 is simultaneously input to red sub-pixel R11 to charge it. Furthermore, during time period T21, signal ga3 on gate line GA3 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R31. The data voltage Vr21 is simultaneously input to red sub-pixel R31 to pre-charge it. During time period T21, signal ga4 on gate line GA4 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R41. Data voltage Vr21 is simultaneously input to red sub-pixel R41 to pre-charge it. Also during time period T21, signal ga5 on gate line GA5 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R51. Data voltage Vr21 is simultaneously input to red sub-pixel R51 to pre-charge it. Finally, during time period T21, signal ga6 on gate line GA6 outputs a high-level gate-on signal, turning on the transistor in red sub-pixel R61. Data voltage Vr21 is simultaneously input to red sub-pixel R61 to pre-charge it.

[0076] Furthermore, during time period T22, signal ga2 goes low and signal ga4 goes high. A data voltage Vr41 corresponding to the display data of red sub-pixel R41 is applied to data line DA1 connected to red sub-pixel R41, charging red sub-pixel R41 with the data voltage Vr41. Also, when signal ga3 goes high, the data voltage Vr41 is simultaneously input to red sub-pixel R31 to charge it. And when signal ga5 goes high, the data voltage Vr41 is simultaneously input to red sub-pixel R51 to pre-charge it. And when signal ga6 goes high, the data voltage Vr41 is simultaneously input to red sub-pixel R61 to pre-charge it.

[0077] Furthermore, during time period T23, signal ga4 goes low and signal ga6 goes high. A data voltage Vr61 corresponding to the display data of red sub-pixel R61 is applied to data line DA1 connected to red sub-pixel R61, charging red sub-pixel R61 with the data voltage Vr61. Simultaneously, with signal ga5 at a high level, the data voltage Vr61 is input to red sub-pixel R51 to charge it. Additionally, other red sub-pixels are pre-charged.

[0078] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel are charged with data voltage, which will not be elaborated here.

[0079] It should be noted that when the display panel 100 is driven by the first display mode, the working process of the other display frames can be basically the same as the working process of the above display frames F01 and F02. That is, the display panel 100 can work in the HSR display mode, which can achieve a high refresh rate while improving the charging rate of sub-pixels.

[0080] Furthermore, it should be noted that when the display panel 100 is driven in the first display mode, in display frame F01, even-numbered row sub-pixels can be charged by the data voltage of adjacent odd-numbered row sub-pixels, thereby realizing the display function of even-numbered row sub-pixels. For example, the voltage charged into red sub-pixel R21 can be related to the data voltage corresponding to red sub-pixel R11 and red sub-pixel R31 (approximately the average of the data voltages corresponding to red sub-pixels R11 and R31), and the voltage charged into red sub-pixel R41 can be related to the data voltages corresponding to red sub-pixels R31 and R51 (approximately the average of the data voltages corresponding to red sub-pixels R31 and R51).

[0081] Furthermore, in display frame F02, odd-numbered row subpixels can be charged by the data voltage of adjacent even-numbered row subpixels, thereby achieving the display function of odd-numbered row subpixels. For example, the voltage charged to red subpixel R11 can be related to the data voltage corresponding to red subpixel R21 (approximately the data voltage corresponding to red subpixel R21), and the voltage charged to red subpixel R31 can be related to the data voltages corresponding to red subpixel R21 and red subpixel R41 (approximately the average of the data voltages corresponding to red subpixel R21 and red subpixel R41). The voltage charged to red subpixel R51 can be related to the data voltages corresponding to red subpixel R41 and red subpixel R61 (approximately the average of the data voltages corresponding to red subpixel R41 and red subpixel R61).

[0082] In other examples, one of the multiple display modes can be a third display mode. The third display mode includes: in each display frame, with at least two adjacent rows of gate lines forming a gate line group, the system circuit 300 executes a data transmission mode corresponding to the third display mode: after reducing the received original display data, display data corresponding to the sub-pixel electrically connected to one gate line in each gate line group is obtained, and the obtained display data is sent to the timing controller 200. Based on the received display data, the timing controller 200 sends a control signal corresponding to the third display mode to the gate driving circuit to control the gate driving circuit to simultaneously drive the gate lines in the same gate line group, and drive the gate line groups one by one. It also sends the display data to the source driving circuit so that, based on the received display data, when the gate lines in the previous gate line group are driven and the gate lines in the next gate line group are being driven, the source driving circuit inputs the corresponding display data voltage to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group. For example, two adjacent rows of grid lines can be considered as a grid line group; or, three adjacent rows of grid lines can be considered as a grid line group; or, adjacent rows of grid lines can be considered as a grid line group; or, more adjacent rows of grid lines can be considered as a grid line group, without limitation.

[0083] For example, combining Figure 3 and Figure 6The following describes the operation of the display panel 100 when driven in the third display mode. Here, two adjacent rows of grid lines are considered as one grid line group. For example, grid lines GA1 and GA2 form one grid line group, grid lines GA3 and GA4 form another, and grid lines GA5 and GA6 form yet another. After the system circuit 300 performs a reduction process, it obtains the display data corresponding to each sub-pixel connected to grid line GA1, the display data corresponding to each sub-pixel connected to grid line GA3, and the display data corresponding to each sub-pixel connected to grid line GA5, and sends this display data to the timing controller 200. Alternatively, after the system circuit 300 performs the reduction process, it could also obtain the display data corresponding to each sub-pixel connected to grid line GA2, the display data corresponding to each sub-pixel connected to grid line GA4, and send this display data to the timing controller 200; this is not limited to this method.

[0084] Wherein, ga1 represents the signal loaded on gate line GA1, ga2 represents the signal loaded on gate line GA2, ga3 represents the signal loaded on gate line GA3, ga4 represents the signal loaded on gate line GA4, ga5 represents the signal loaded on gate line GA5, and ga6 represents the signal loaded on gate line GA6. Vda1 represents the data voltage loaded on data line DA1. Furthermore, the high level of signals ga1 to ga6 can be used as a gate enable signal to control the transistor in the sub-pixel to conduct. When the display panel 100 is driven in the first display mode, taking a display frame F04, data line DA1, and the red sub-pixel connected to data line DA1 as an example, the signal ga1 on gate line GA1 and the signal ga2 on gate line GA2 simultaneously output a high-level gate enable signal, and the transistors in the red sub-pixels R11 and R21 conduct simultaneously. Furthermore, during the T41 time period corresponding to the high levels of signals ga1 and ga2, a data voltage Vr11 corresponding to the displayed data is input to the data line DA1 connected to the red sub-pixels R11 and R21, so that the red sub-pixels R11 and R21 are charged with the data voltage Vr11. Also, during the T41 time period, signals ga3 on gate line GA3 and ga4 on gate line GA4 simultaneously output high-level gate-on signals, and the transistors in the red sub-pixels R31 and R41 are simultaneously turned on. The data voltage Vr11 is simultaneously input to the red sub-pixels R31 and R41 to pre-charge them.

[0085] Furthermore, during the T42 time period corresponding to the high levels of signals ga3 and ga4, a data voltage Vr31 corresponding to the displayed data is applied to the data line DA1 connected to the red sub-pixels R31 and R41, so that the red sub-pixels R31 and R41 are charged with the data voltage Vr31. Also, during the T42 time period, signals ga5 on gate line GA5 and ga6 on gate line GA6 simultaneously output high-level gate-on signals, turning on the transistors in the red sub-pixels R51 and R61. The data voltage Vr31 is simultaneously input to the red sub-pixels R51 and R61 to pre-charge them.

[0086] Furthermore, during the T43 time period corresponding to the high levels of signals ga5 and ga6, the data voltage Vr51 corresponding to the displayed data is applied to the data line DA1 connected to the red sub-pixels R51 and R61, so that the red sub-pixels R51 and R61 are charged with the data voltage Vr51. This also pre-charges the next red sub-pixel.

[0087] The implementation methods for the remaining sub-pixels are similar, until all sub-pixels in the entire display panel 100 are charged with data voltage, which will not be described in detail here.

[0088] It should be noted that when the display panel 100 is driven by the third display mode, the working process of each display frame can be basically the same as the working process of the aforementioned display frame F04. That is, the display panel 100 can work in DLG display mode, which will not be elaborated here.

[0089] In this embodiment, the refresh rate of the second display mode can be lower than the refresh rates of the first and third display modes. For example, the refresh rate of the display panel 100 may include 30Hz, 48Hz, 60Hz, 90Hz, 96Hz, 120Hz, 144Hz, 240Hz, etc. The refresh rates of the first, second, and third display modes can be selected from the refresh rates supported by the display panel 100. For example, the refresh rate of the second display mode may be 60Hz, the refresh rate of the first display mode may be 120Hz, and the refresh rate of the third display mode may be 120Hz. Of course, in practical applications, the refresh rates of the first, second, and third display modes can be determined according to the needs of the actual application, and are not limited here.

[0090] In this embodiment, since the display panel includes multiple display modes, the display modes can be switched in different application scenarios. However, the discloser has discovered that when the system circuit determines to switch between different display modes, it also begins a data transmission mode switching process. For example, when the system circuit determines to switch from the second display mode to the first display mode, it also begins a process of switching from the data transmission mode corresponding to the second display mode to the data transmission mode corresponding to the first display mode. Simultaneously, it sends a mode switching signal to the timing controller. After receiving the mode switching signal, the timing controller switches the second display mode to the first display mode. However, since the system circuit can send display data to the timing controller while switching data transmission modes, the data transmission mode switching speed of the system circuit is slower than the display mode switching speed of the timing controller. After the timing controller finishes switching from the second display mode to the first display mode, the system circuit usually has not yet finished switching. At this time, the system circuit still uses the data transmission mode corresponding to the second display mode to send the original display data Vdata1 corresponding to all sub-pixels to the timing controller. After receiving the raw display data Vdata1, the timing controller's counting unit counts the total number of corresponding sub-pixel rows in Vdata1. However, since the timing controller has switched to the first display mode, the count set by the counting unit in the first display mode differs from the count obtained from the raw display data Vdata1. This causes the counting unit to fail to automatically reset to zero, resulting in a stuck count. The counting unit then returns an error command to the timing controller, which in turn enters the warning mode that controls the display panel to show a warning image, leading to a display anomaly.

[0091] To address the aforementioned issues, this disclosure provides a method for driving a display panel. Upon receiving a display mode switching enable command, the method drives the display panel to display a first preset screen and switches the current display mode to the target display mode, thus achieving the mode switching process. Furthermore, upon receiving the display mode switching enable command, the method enters a non-counting state, placing the counting unit in a non-counting working state. This prevents the timing controller from counting any received display data even after receiving display data from the system circuit. Upon receiving a data mode switching completion command, the non-counting state is released, and the method enters a counting state, placing the counting unit in a counting working state, thereby enabling the counting of any received display data. By starting the counting operation only after the system circuit has completed the mode switching, the method avoids the problem of the counting unit getting stuck due to its inability to automatically reset to zero.

[0092] Combination Figure 7 As shown, the display panel driving method provided in this embodiment may include the following steps:

[0093] S10. Upon receiving a command to enable display mode switching, the system enters a non-counting state, drives the display panel to display the first set screen, and switches the current display mode to the target display mode.

[0094] The driving method provided in this disclosure can switch between different display modes according to the actual application scenario of the display panel. For example, game displays require a high refresh rate; however, a high refresh rate compresses the charging time of sub-pixels on the display panel, resulting in insufficient charging of the sub-pixels. In this disclosure, when switching from a low refresh rate display mode to a high refresh rate display mode, the charging rate of the sub-pixels can be improved while maintaining a high refresh rate.

[0095] For example, the system circuit 300 determines to switch between different display modes based on the application scenario. For instance, the current application scenario for the display panel 100 might be a regular video playback interface, driven by a second display mode. When the user wants to open a game, the system circuit 300 recognizes that the next application scenario is a game interface. Since game interfaces require a high refresh rate, the system circuit 300 determines that a different display mode switch is needed and sends a display mode switching enable command to the timing controller 200. Upon receiving the display mode switching enable command, the timing controller 200 executes step S10. When sending the display mode switching enable command, the system circuit 300 also switches its data transmission mode corresponding to the current display mode to the data transmission mode of the target display mode.

[0096] For example, such as Figure 8As shown, the display device may further include a connector 400. A first end 410 of the connector 400 is connected to the system circuit 300, and a second end 420 of the connector 400 is connected to the timing controller 200. The first end 410 of the connector 400 may include a first IIC pin angle 411 and a first switching command transmission pin angle 412, and the second end 420 of the connector 400 may include a second IIC pin angle 421 and a second switching command transmission pin angle 422. For example, the system circuit 300 outputs a handshake signal through the first IIC pin angle 410, and the timing controller 200 receives the handshake signal through the second IIC pin angle 421. After receiving the handshake signal, the timing controller 200 performs a handshake with the system circuit 300. After the handshake is completed, it indicates that the system circuit 300 and the timing controller 200 are connected and signal transmission can begin. For example, system circuit 300 can output a display mode switching enable command via first switching command transmission pin 412 (e.g., by pulling the level of first switching command transmission pin 412 high). Timing controller 200 can receive the display mode switching enable command output by system circuit 300 via second switching command transmission pin 422 (e.g., since the level of first switching command transmission pin 412 is pulled high, the level of second switching command transmission pin 422 is also pulled high). When display mode switching is not required, and when system circuit 300 determines that display mode switching is not required, it pulls the level of first switching command transmission pin 412 low to output a display mode switching stop command. Then, second switching command transmission pin 422 is also pulled low to receive the display mode switching stop command, and timing controller 200 does not perform display mode switching. Alternatively, the system circuit 300 can output a display mode switching enable command in digital signal form via the first IIC pin 411 (e.g., the display mode switching enable command has Byte0 to Byte1. For example, Byte0 is 0xC2, Byte1 is 0xF26F, Byte2 is 0x01, and Byte3 is 0xAA). The timing controller 200 receives the display mode switching enable command via the second IIC pin 421 and performs the display mode switching process according to the display mode switching enable command. Furthermore, when the system circuit 300 determines that display mode switching is not required, the system circuit 300 can output a display mode switching stop command in digital signal form via the first IIC pin 411 (e.g., the display mode switching stop command has Byte0 to Byte1. For example, Byte0 is 0xC2, Byte1 is 0xF26F, Byte2 is 0x01, and Byte3 is 0x55). The timing controller 200 receives the display mode switching stop command via the second IIC pin 421, and the timing controller 200 does not perform display mode switching.

[0097] In the embodiments disclosed herein, such as Figure 8 As shown, the first end 410 of connector 400 may further include a first data transmission pin angle 413; the second end 420 of connector 400 may further include a second data transmission pin angle 423. The system circuit 300 can output display data through the first data transmission pin angle 413, and the timing controller 200 can receive display data through the second data transmission pin angle 423.

[0098] In the embodiments disclosed herein, such as Figure 8 As shown, the display device further includes a counting unit 500. The counting unit 500 is configured to count a first number corresponding to a set target in the displayed data, and output a count pass command when it is determined that the first number is the same as the set number corresponding to the target display mode. The timing controller 200 is configured to control the counting unit 500 to enter a non-counting state when a display mode switching start command is received; and to control the counting unit 500 to enter a counting state when a data mode switching completion command is received. Exemplarily, the counting unit 500 can be integrated into the timing controller 200 to improve integration and shorten the length of the data transmission line between the timing controller 200 and the counting unit 500. In some examples, the counting unit 500 may include, but is not limited to, a counter circuit.

[0099] For example, such as Figure 8 As shown, when the timing controller 200 receives a display mode switching on command, it controls the counting unit 500 to be in a zeroed state, preventing the counting unit 500 from performing a counting operation and maintaining the zeroed state to enter a non-counting state. Alternatively, when the timing controller 200 receives a display mode switching on command, it controls the counting unit 500 to be in an disabled state, i.e., the counting unit 500 is not enabled, so the counting unit 500 does not perform a counting operation to enter a non-counting state. Or, when the timing controller 200 receives a display mode switching on command, it does not supply power to the counting unit 500, controlling the counting unit 500 to be in a power-off state, so the counting unit 500 does not perform a counting operation to enter a non-counting state. Because the counting unit 500 does not perform a counting operation, even if the system circuit 300 sends display data, it will not count the set target in the display data, thus avoiding the problem of freezing.

[0100] For example, the circuit board housing the timing controller 200 is equipped with flash memory, which stores display data corresponding to the first set screen (this display data includes digital voltage forms of data voltage corresponding to each sub-pixel). For example, when the timing controller 200 switches from the second display mode to the first display mode, since the timing controller 200 starts the switching process between different display modes upon receiving the display mode switching enable command, the timing controller 200 still drives the display panel 100 to display the screen in the second display mode until the display mode switching is completed. Specifically, when the timing controller 200 receives the display mode switching enable command, it retrieves the pre-stored display data corresponding to the first set screen from the flash memory and outputs the retrieved display data corresponding to the first set screen to the source drive circuit 120. The source drive circuit 120 can receive the display data corresponding to the first set screen and, based on the display data corresponding to the first set screen, load the corresponding data voltage onto the data line. Furthermore, the timing controller 200 inputs a control signal to the gate driving circuit, which drives the gate lines line by line, following the same driving process as described above when the display panel 100 is in the second display mode, thereby driving the display panel 100 to display the first set screen. After the display mode switching is completed, the timing controller 200 can drive the display panel 100 to display the screen according to the first display mode. Specifically, the timing controller 200 retrieves the display data corresponding to the pre-stored first set screen from the flash memory, and after deleting the display data of the corresponding display sub-pixels from the retrieved display data corresponding to the first set screen, outputs the display data of the corresponding virtual sub-pixels and the remaining display data of the corresponding display sub-pixels to the source driving circuit 120. The source driving circuit 120 can receive this display data and, based on this display data, apply the corresponding data voltage to the data lines. Furthermore, the timing controller 200 inputs a control signal to the gate driving circuit, which drives the gate lines line by line, following the same driving process as described above when the display panel 100 is in the second display mode, thereby driving the display panel 100 to display the first set screen.

[0101] In some examples, the current display mode can be the second display mode, and the target display mode can be the first display mode. This allows the display panel 100 to switch from the second display mode to the first display mode, which serves as the HSR (High Refresh Rate) display mode. For example, game displays require a high refresh rate. Therefore, when the display panel 100 is displaying game content, the first display mode, which serves as the HSR display mode, can be used. This achieves a high refresh rate while improving the charging rate of subpixels. For instance, the second display mode corresponding to 120Hz 4K 2K can be switched to the first display mode corresponding to 240Hz 4K 1K.

[0102] In some other examples, the current display mode can be the second display mode, and the target display mode can be the third display mode. This allows the display panel 100 to switch from the second display mode to the third display mode, which serves as the DLG display mode. For example, game displays require a high refresh rate. Therefore, when the display panel 100 is displaying game content, the third display mode, which serves as the DLG display mode, can be used. This achieves a high refresh rate while also increasing the charging rate of subpixels.

[0103] In some other examples, the current display mode can be the third display mode, and the target display mode can be the first display mode. This allows the display panel 100 to switch from the third display mode (DLG display mode) to the first display mode (HSR display mode). While the resolution of the image displayed by the display panel 100 in the third display mode (DLG display mode) will also decrease, the voltage input to adjacent rows of sub-pixels in the same column will not be exactly the same in the first display mode (HSR display mode). Therefore, the image displayed by the display panel 100 in the first display mode (HSR display mode) will be more detailed. Thus, when the display panel 100 is displaying game content, using the first display mode (HSR display mode) can further improve the display quality.

[0104] In some other examples, the current display mode can be a first display mode, and the target display mode can be a third display mode. This allows the display panel 100 to switch from the first display mode, which is the HSR display mode, to the third display mode, which is the DLG display mode. This allows the display panel 100 to use the third display mode as the DLG display mode when displaying game-related content, further improving the charging rate of subpixels.

[0105] In some other examples, the current display mode can be the third display mode, and the target display mode can be the second display mode. This allows the display panel 100 to switch from the third display mode, which is the DLG display mode, to the second display mode. For example, static images do not require a high refresh rate but rather low power consumption. Therefore, when the display panel 100 needs to display static images, it can use the second display mode, which is the normal display mode, thus reducing power consumption.

[0106] In some other examples, the current display mode can be a first display mode, and the target display mode can be a second display mode. This allows the display panel 100 to switch from the first display mode, which is the HSR display mode, to the second display mode. For example, static images do not require a high refresh rate but rather low power consumption. Therefore, when the display panel 100 needs to display static images, it can use the second display mode, which is the normal display mode, thus reducing power consumption. For example, the first display mode corresponding to 240Hz 4K 1K can be switched to the second display mode corresponding to 120Hz 4K 2K.

[0107] Grayscale, in general, divides the brightness variation between the darkest and brightest points into several parts to facilitate screen brightness control. For example, a displayed image may consist of three colors: red, green, and blue. Each color can be displayed at different brightness levels, and combinations of different brightness levels of red, green, and blue can form different colors. For instance, if the grayscale bit depth of an LCD panel 100 is 6 bits, then red, green, and blue each have 64 (i.e., 2^34) grayscale values. 6 There are 64 gray levels, with gray values ​​ranging from 0 to 63. The LCD panel 100 has an 8-bit grayscale, meaning that red, green, and blue each have 256 (i.e., 2^6) grayscale values. 8 The LCD panel 100 has 256 gray levels, with gray values ​​ranging from 0 to 255. The LCD panel 100 has a 10-bit gray level, meaning that red, green, and blue each have 1024 (i.e., 2^35) gray levels. 10 There are 1024 gray levels, with gray values ​​ranging from 0 to 1023. The LCD panel 100 has a 12-bit grayscale, meaning that red, green, and blue each have 4096 (i.e., 2^3) grayscale values. 12 There are 4096 gray levels, with gray values ​​ranging from 0 to 4093.

[0108] In this embodiment of the disclosure, the first setting screen may include a solid color screen. For example, the first setting screen may include a red solid color screen, a green solid color screen, and a blue solid color screen. For example, taking a display panel 100 having grayscale values ​​of 0 to 255 as an example, when the display panel 100 displays a red solid color screen, the red sub-pixels in the display panel 100 input data voltages corresponding to the display data of the same grayscale value (e.g., grayscale value 127, grayscale value 255, etc.), while the green and blue sub-pixels input data voltages corresponding to the display data of 0 grayscale value. When the display panel 100 displays a green solid color screen, the green sub-pixels in the display panel 100 input data voltages corresponding to the display data of the same grayscale value (e.g., grayscale value 127, grayscale value 255, etc.), while the red and blue sub-pixels input data voltages corresponding to the display data of 0 grayscale value. When the display panel 100 displays a pure blue image, the blue sub-pixel in the display panel 100 inputs the data voltage of the display data corresponding to the same gray level value (e.g., gray level 127, gray level 255, etc.), and the green and red sub-pixels input the data voltage of the display data corresponding to the 0 gray level value.

[0109] In this embodiment, the first set screen may also include a grayscale screen. This grayscale screen can be a screen where all sub-pixels of various colors have the same grayscale value. For example, taking a display panel 100 with grayscale values ​​from 0 to 255 as an example, a screen where all sub-pixels of various colors have a grayscale value of 0 (i.e., a black screen); a screen where all sub-pixels of various colors have a grayscale value of 127; a screen where all sub-pixels of various colors have a grayscale value of 100; a screen where all sub-pixels of various colors have a grayscale value of 200; or a screen where all sub-pixels of various colors have a grayscale value of 255.

[0110] S20. Upon receiving the data mode switching completion instruction, enter the counting state.

[0111] In this embodiment, the system circuit 300 can send a data mode switching completion command to the timing controller 200 after switching the data transmission mode corresponding to the current display mode to the data transmission mode corresponding to the target display mode. Since the switching speed of the system circuit 300 is slower than that of the timing controller 200, the timing controller 200 has already completed its switching after the system circuit 300 has finished switching. Therefore, when the system circuit 300 sends the data mode switching completion command to the timing controller 200, the timing controller 200 can determine that the system circuit 300 has completed the switching and, upon receiving the data mode switching completion command, controls the counting unit 500 to enter a counting state. Exemplarily, the timing controller 200 can enable the counter circuit in the counting unit 500, allowing the counter circuit to perform counting operations. For example, the system circuit 300 can also output a data mode switching completion instruction in digital signal form (e.g., a display mode switching enable instruction has Byte0 to Byte1. For example, Byte0 is 0xC2, Byte1 is 0xF26F, Byte2 is 0x01, and Byte3 is 0x66) through the first IIC pin 411. The timing controller 200 receives the data mode switching completion instruction through the second IIC pin 421 and controls the counter circuit to start the counting operation function according to the data mode switching completion instruction.

[0112] In this embodiment of the present disclosure, after entering the counting state, the process may further include: receiving display data; counting the first number of the corresponding set target in the display data; and, after determining that the first number is the same as the set number corresponding to the target display mode, driving the display panel 100 to display the corresponding image based on the target display mode and the received display data. For example, the system circuit 300 may adopt a data transmission mode corresponding to the target display mode to process the received raw display data into display data corresponding to the target display mode. The processed display data is then output to the timing controller 200. After receiving the display data, the timing controller 200 controls the counting unit 500 to count the corresponding set target in the display data to obtain the first number. When the counting unit 500 determines that the first count is the same as the set count corresponding to the target display mode, it can automatically clear the count and send a pass command to the timing controller 200. When the timing controller 200 receives the pass command, it can determine that the display data output by the system circuit 300 corresponds to the display data required by the target display mode. Therefore, the timing controller 200 can drive the display panel 100 to display the corresponding screen based on the target display mode and the received display data.

[0113] In this embodiment of the disclosure, the display panel 100 includes a plurality of subpixel rows, wherein these subpixel rows may have display subpixel rows (e.g., Figure 3 The first to sixth rows of subpixels shown are shown, along with virtual subpixel rows. The target setting can include the subpixel rows of the display panel 100. When the target display mode is the first display mode, the set number can include the total number of all virtual subpixel rows and half the total number of displayed subpixel rows. For example, the counting unit 500 can count the number of corresponding subpixel rows in the display data received by the timing controller 200 to determine the total number of these subpixel rows, which is used as the first number. After the timing controller 200 switches to the first display mode, the set number can be half the total number of all virtual subpixel rows and half the total number of displayed subpixel rows.

[0114] In this embodiment of the disclosure, the display panel 100 includes a plurality of subpixel rows, wherein these subpixel rows may have display subpixel rows (e.g., Figure 3 The first to sixth rows of subpixels shown are shown) and virtual subpixel rows. The target setting can include the subpixel rows of the display panel 100. When the target display mode is the second display mode, the set number can include the total number of all virtual subpixel rows and the total number of all display subpixel rows. For example, the counting unit 500 can count the number of corresponding subpixel rows in the display data received by the timing controller 200 to calculate the total number of these subpixel rows, which is used as the first number. After the timing controller 200 switches to the second display mode, the set number can be the total number of all virtual subpixel rows and the total number of all display subpixel rows. For example, when switching from the second display mode to the first display mode, if the display data in the second display mode is 4K2K display data, the set number corresponding to the second display mode can be 2177 (including 2160 display subpixel rows and 17 virtual subpixel rows), and the set number corresponding to the first display mode can be 1097 (including 1080 display subpixel rows (i.e., half the total number of display subpixel rows) and 17 virtual subpixel rows).

[0115] In this embodiment of the disclosure, the display panel 100 includes a plurality of subpixel rows, wherein these subpixel rows may have display subpixel rows (e.g., Figure 3The first to sixth rows of subpixels shown are shown, along with virtual subpixel rows. In the third display mode, these multiple subpixel rows are divided into multiple grid groups, so the target setting can include the grid groups of the display panel 100. Furthermore, when the target display mode is the third display mode, the set number includes the total number of grid groups. For example, the counting unit 500 can count the number of corresponding grid groups in the display data received by the timing controller 200 to calculate the total number of these grid groups, which is used as a first number. After the timing controller 200 switches to the third display mode, the set number can be the total number of all grid groups.

[0116] In practical implementation, upon receiving the pass command, the timing controller 200 can directly drive the display panel 100 to display the corresponding image based on the target display mode and the received display data. However, since the system circuit 300 may experience instability after switching, to further improve display stability, after counting the first number of corresponding set targets in the display data, and confirming that the first number matches the set number, the display panel 100 is driven to display the second set image in at least one display frame based on the target display mode. Then, based on the target display mode and the received display data, the display panel 100 is driven to display the corresponding image. For example, the system circuit 300 can use a data transmission mode corresponding to the target display mode to process the received raw display data into display data corresponding to the target display mode. The processed display data is then output to the timing controller 200. After receiving the display data, the timing controller 200 controls the counting unit 500 to count the corresponding set targets in the display data to obtain the first number. When the counting unit 500 determines that the first count is the same as the set count corresponding to the target display mode, it can send a pass command to the timing controller 200. Upon receiving the pass command, the timing controller 200 can drive the display panel 100 to display the second set screen in one or more display frames based on the target display mode. Subsequently, based on the target display mode and the received display data, it drives the display panel 100 to display the corresponding screen.

[0117] In this embodiment, the number of display frames for displaying the second set screen is determined using the formula SM = TM / AM; where SM represents the number of display frames for displaying the second set screen, TM represents the set time, and AM represents the reciprocal of the refresh rate corresponding to the target display mode. For example, the set time can be determined based on the time consumed by the system circuit 300 during switching to improve stability. Alternatively, the set time can be determined based on the interval between the timing controller 200 receiving the display mode switching start command and the data mode switching completion command to further improve stability.

[0118] For example, when determining the setting time based on the time consumed by switching the system circuit 300, if the time consumed by switching the system circuit 300 is approximately 83ms, the refresh rate corresponding to the target display mode is 240Hz, and the time of one display frame at 240Hz is approximately 4.16ms, then the number of display frames SM for displaying the second setting screen can be 20. If the time consumed by switching the system circuit 300 is 83ms, the refresh rate corresponding to the target display mode is 120Hz, and the time of one display frame at 120Hz is approximately 8.33ms, then the number of display frames SM for displaying the second setting screen can be 10.

[0119] In this embodiment, the second setting screen may include a solid color screen. For example, the second setting screen may include a red solid color screen, a green solid color screen, and a blue solid color screen. For example, taking a display panel 100 having grayscale values ​​from 0 to 255 as an example, when the display panel 100 displays a red solid color screen, the red sub-pixels in the display panel 100 input data voltages corresponding to the same grayscale value (e.g., grayscale value 127, grayscale value 255, etc.), while the green and blue sub-pixels input data voltages corresponding to display data with a grayscale value of 0. When the display panel 100 displays a green solid color screen, the green sub-pixels in the display panel 100 input data voltages corresponding to the same grayscale value (e.g., grayscale value 127, grayscale value 255, etc.), while the red and blue sub-pixels input data voltages corresponding to display data with a grayscale value of 0. When the display panel 100 displays a pure blue image, the blue sub-pixel in the display panel 100 inputs the data voltage of the display data corresponding to the same gray level value (e.g., gray level 127, gray level 255, etc.), and the green and red sub-pixels input the data voltage of the display data corresponding to the 0 gray level value.

[0120] In this embodiment, the second setting screen may also include a grayscale screen. This grayscale screen can be a screen where all sub-pixels of various colors have the same grayscale value. For example, taking a display panel 100 with grayscale values ​​from 0 to 255 as an example, a screen where all sub-pixels of various colors have a grayscale value of 0 (i.e., a black screen); a screen where all sub-pixels of various colors have a grayscale value of 127; a screen where all sub-pixels of various colors have a grayscale value of 100; a screen where all sub-pixels of various colors have a grayscale value of 200; or a screen where all sub-pixels of various colors have a grayscale value of 255.

[0121] In this embodiment of the disclosure, the display data of the second setting screen can also be stored in the flash memory. For example, the first setting screen and the second setting screen can be identical, thus requiring only the display data of either the first or second setting screen to be stored in the flash memory, reducing the required storage space. Of course, in practical applications, the first setting screen and the second setting screen can also be different, and this is not limited here.

[0122] In this embodiment of the disclosure, the system circuit 300 may include a system on a chip (SOC). Of course, the system circuit 300 may be implemented in other ways, which are not limited here.

[0123] The following is combined with Figure 8 and Figure 9 The driving method described above, as provided in the embodiments of this disclosure, will be further described.

[0124] When the display device is powered on, the system circuit 300 is powered on. The system circuit 300 provides a power supply voltage VIN1 (e.g., 3.3V) to the timing controller 200 through the first power supply pin of connector 400, pulling the first power supply pin high from 0V to 3.3V. The system circuit 300 provides a power supply voltage VIN2 (e.g., 1.1V) to the timing controller 200 through the second power supply pin of connector 400, pulling the second power supply pin high from 0V to 1.1V. The system circuit 300 provides a power supply voltage VIN3 (e.g., 1.8V) to the timing controller 200 through the third power supply pin of connector 400, pulling the third power supply pin high from 0V to 1.8V. Finally, the system circuit 300 provides an initialization voltage RES (e.g., 1.15V) to the timing controller 200 through the initialization pin of connector 400, pulling the initialization pin high from 0V to 1.15V. Where t1 represents the delay time from when the first power supply pin is pulled high from 0V to 2.8V until the second power supply pin is pulled high from 0V to 0.8V; t2 represents the delay time from when the second power supply pin is pulled high from 0V to 0.8V until the third power supply pin is pulled high from 0V to 1.5V; and t3 represents the delay time from when the third power supply pin is pulled high from 0V to 1.5V until the initialization pin is pulled high from 0V to 0.8V. The timing controller 200 can activate the desired function after the power supply voltages VIN1 to VIN3 stabilize. After the initialization voltage is pulled high to 1.15V, in stage t4, the timing controller 200 performs an initialization operation to determine the current display mode as the second display mode. That is, when the timing controller 200 is powered on again, it will default to the second display mode. Then, in stage t5, the system circuit does not determine that a display mode switch is needed, so the second display mode continues to drive the display panel 100 to display the 4K2K data. Then, in stage t6, the system circuit determines that a switching process is needed to switch the second display mode (e.g., 4K2K display data) to the first display mode (e.g., 4K1K display data). System circuit 300 pulls the level of the first switching command transmission pin 412 high to output a display mode switching enable command via the first switching command transmission pin 412. It then initiates the switching process from the data transmission mode corresponding to the second display mode to the data transmission mode corresponding to the first display mode.

[0125] Since the level of the first switching command transmission pin 412 is pulled high, the level of the second switching command transmission pin 422 is also pulled high. The timing controller 200 receives the display mode switching enable command output by the system circuit 300 through the second switching command transmission pin 422, controlling the counter circuit in the counting unit 500 to be in a cleared state, so that the counter circuit in the counting unit 500 does not perform counting operations and remains in a cleared state, thus entering a non-counting state. Furthermore, the timing controller 200 retrieves the pre-stored display data corresponding to the black screen from the flash memory. Since it also takes time for the timing controller 200 to switch its own second display mode to the first display mode, before the display mode switching is complete, the timing controller 200 still inputs control signals to the gate drive circuit in the second display mode, controlling the gate drive circuit to drive the gate lines line by line. The timing controller 200 also outputs the retrieved display data corresponding to the black screen (e.g., 4K2K data) to the source drive circuit 120 in the second display mode. The source drive circuit 120 can receive display data corresponding to the black screen and, based on this data, apply a corresponding data voltage to the data line to drive the display panel 100 to display the black screen. During the data transmission mode switching process, the system circuit 300 can simultaneously switch modes and send display data to the timing controller 200. While the timing controller 200 is switching display modes, it can receive display data sent by the system circuit 300 and can either buffer or not store the received display data. Furthermore, since the counter circuit in the control counting unit 500 is in a cleared state, it will not count any received display data.

[0126] Because the data transmission mode switching speed of system circuit 300 is slower than the display mode switching speed of timing controller 200, system circuit 300 is usually not yet fully switched after timing controller 200 has switched from the second display mode to the first display mode. Timing controller 200 then inputs a control signal to the gate drive circuit in the first display mode, controlling the gate drive circuit to drive the gate lines line by line. Timing controller 200 also outputs the acquired display data corresponding to the black screen (e.g., 4K1K display data) to source drive circuit 120 in the first display mode. Source drive circuit 120 can receive the display data corresponding to the black screen and, based on the display data, apply the corresponding data voltage to the data lines to drive display panel 100 to display the black screen. During the data transmission mode switching process, system circuit 300 can simultaneously switch and send display data to timing controller 200. After timing controller 200 has finished switching, it can receive the display data sent by system circuit 300 and can either buffer or not store the received display data. Furthermore, since the control counting unit 500 is in a zeroed state, the counting unit 500 will not count any received display data.

[0127] After switching the data transmission mode corresponding to the second display mode to the data transmission mode corresponding to the first display mode, the system circuit 300 outputs a data mode switching completion command in digital signal form through the first IIC pin 411. The timing controller 200 receives the data mode switching completion command through the second IIC pin 421 and controls the counter circuit in the counting unit 500 to release the non-counting state and start the counting operation function according to the data mode switching completion command. The system circuit 300 sends display data using the data transmission mode corresponding to the second display mode. The timing controller 200 receives the display data and controls the counter circuit in the counting unit 500 to count the corresponding sub-pixel rows in the display data to obtain the first count. When the counter circuit in the counting unit 500 determines that the first count is the same as the set number (e.g., 1097) corresponding to the first display mode, it can automatically clear the count and send a pass command to the timing controller 200. When the timing controller 200 receives the pass command, it can determine that the display data output by the system circuit 300 corresponds to the display data required by the first display mode. Therefore, the timing controller 200 can drive the display panel 100 to display the corresponding image based on the first display mode and the received display data (e.g., 4K1K display data).

[0128] When the counter circuit in the counting unit 500 determines that the first count and the set count (e.g., 1097) corresponding to the first display mode are different, it cannot automatically reset to zero and sends an abnormal readback command (e.g., 32448) to the timing controller 200. Upon receiving this abnormal readback command, the timing controller 200 can determine that the display data output by the system circuit 300 does not correspond to the display data required by the first display mode. Therefore, the timing controller 200 retrieves the display data of the warning screen from the flash memory and drives the display panel 100 to display the warning screen (e.g., looping red, green, and blue solid colors). It should be noted that the warning screen is different from the first and second set screens, so the corresponding prompt information can be obtained through the difference in the display screen.

[0129] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0130] Furthermore, the driving method and display device provided in this disclosure can switch between different display modes according to the actual application scenario of the display panel 100. For example, game displays require a high refresh rate; however, a high refresh rate compresses the charging time of the sub-pixels of the display panel 100, resulting in insufficient charging of the sub-pixels. In this disclosure, when switching from a low refresh rate display mode to a high refresh rate display mode, a high refresh rate can be achieved while simultaneously increasing the charging rate of the sub-pixels.

[0131] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0133] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0134] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0135] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0136] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A method for driving a display panel, comprising: Upon receiving a command to enable display mode switching, the system enters a non-counting state, drives the display panel to display the first set screen, and switches the current display mode to the target display mode. Upon receiving the data mode switching completion instruction, it enters the counting state; After entering the counting state, the process further includes: Receive display data; Count the first number of the set targets corresponding to the displayed data; After determining that the first number is the same as the set number corresponding to the target display mode, based on the target display mode and according to the received display data, the display panel is driven to display the corresponding screen; The display panel includes a first display mode; wherein the first display mode includes: in the first display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous odd-numbered row of display sub-pixels are driven and the gate lines connected to the next odd-numbered row of display sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next odd-numbered row of display sub-pixels; and in the second display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous even-numbered row of display sub-pixels are driven and the gate lines connected to the next even-numbered row of display sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next even-numbered row of display sub-pixels; The display panel includes a second display mode; wherein, the second display mode includes: driving the gate lines line by line in each display frame, and when the previous row of gate lines has been driven and the next row of gate lines is being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the next row of gate lines; The display panel includes a third display mode; wherein, the third display mode includes: in each display frame, taking at least two adjacent rows of gate lines as a gate line group, receiving display data corresponding to a row of sub-pixels in each gate line group, simultaneously driving the gate lines in the same gate line group according to the received display data, and driving the gate line groups one by one, when the gate lines in the previous gate line group have been driven and the gate lines in the next gate line group are being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group; The current display mode is one of the first display mode, the second display mode, and the third display mode; The target display mode is one of the first display mode, the second display mode, and the third display mode, excluding the current display mode. The set target includes the sub-pixel rows of the display panel; The display panel includes display sub-pixel rows and virtual sub-pixel rows; When the target display mode is the first display mode, the set number includes the total number of all virtual sub-pixel rows and half of the total number of display sub-pixel rows; When the target display mode is the second display mode, the set number includes the total number of all virtual subpixel rows and the total number of all display subpixel rows.

2. The driving method for the display panel as described in claim 1, wherein, After counting the first number of the set target in the display data, and after determining that the first number is the same as the set number corresponding to the target display mode, before driving the display panel to display the corresponding screen based on the target display mode and the received display data, the method further includes: When it is determined that the first number is the same as the set number, the display panel is driven to display the second set screen in at least one display frame based on the target display mode.

3. The driving method for the display panel as described in claim 2, wherein, The number of display frames for displaying the second set screen is determined using the following formula; SM = TM / AM; Wherein, SM represents the number of display frames for displaying the second set screen, TM represents the set time, and AM represents the reciprocal of the refresh rate corresponding to the target display mode.

4. The driving method for the display panel as described in claim 2 or 3, wherein, At least one of the first setting screen and the second setting screen includes at least one of a solid color screen and a grayscale screen.

5. The driving method for a display panel as described in any one of claims 1-3, wherein, The non-counting state includes one of the following: zeroing state, disabled state, and power-off state.

6. The driving method for a display panel as described in any one of claims 1-3, wherein, The set target includes the grid line group of the display panel; When the target display mode is the third display mode, the set number includes the total number of grid line groups.

7. A display device, comprising: Display panel; The timing controller is configured as follows: Upon receiving a command to enable display mode switching, the system enters a non-counting state, drives the display panel to display the first set screen, and switches the current display mode to the target display mode. Upon receiving the data mode switching completion instruction, it enters the counting state; After entering the counting state, the process further includes: Receive display data; Count the first number of the set targets corresponding to the displayed data; After determining that the first number is the same as the set number corresponding to the target display mode, based on the target display mode and according to the received display data, the display panel is driven to display the corresponding screen; The display panel includes a first display mode; wherein the first display mode includes: in the first display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous odd-numbered row of display sub-pixels are driven and the gate lines connected to the next odd-numbered row of display sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next odd-numbered row of display sub-pixels; and in the second display frame of two adjacent display frames, driving the gate lines in the display panel line by line, and when the gate lines connected to the previous even-numbered row of display sub-pixels are driven and the gate lines connected to the next even-numbered row of display sub-pixels are being driven, inputting a data voltage corresponding to the display data to the data line corresponding to the next even-numbered row of display sub-pixels; The display panel includes a second display mode; wherein, the second display mode includes: driving the gate lines line by line in each display frame, and when the previous row of gate lines has been driven and the next row of gate lines is being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the next row of gate lines; The display panel includes a third display mode; wherein, the third display mode includes: in each display frame, taking at least two adjacent rows of gate lines as a gate line group, receiving display data corresponding to a row of sub-pixels in each gate line group, simultaneously driving the gate lines in the same gate line group according to the received display data, and driving the gate line groups one by one, when the gate lines in the previous gate line group have been driven and the gate lines in the next gate line group are being driven, inputting the data voltage corresponding to the display data to the data line corresponding to the sub-pixel connected to the gate line of the next gate line group; The current display mode is one of the first display mode, the second display mode, and the third display mode; The target display mode is one of the first display mode, the second display mode, and the third display mode, excluding the current display mode. The set target includes the sub-pixel rows of the display panel; The display panel includes display sub-pixel rows and virtual sub-pixel rows; When the target display mode is the first display mode, the set number includes the total number of all virtual sub-pixel rows and half of the total number of display sub-pixel rows; When the target display mode is the second display mode, the set number includes the total number of all virtual subpixel rows and the total number of all display subpixel rows.

8. The display device as claimed in claim 7, wherein, The display device further includes: The system circuit is configured as follows: When it is determined to switch between different display modes, a display mode switching enable command is sent to the timing controller, and the data transmission mode corresponding to the current display mode is switched to the data transmission mode corresponding to the target display mode; After switching the data transmission mode corresponding to the current display mode to the data transmission mode corresponding to the target display mode, a data mode switching completion command is sent to the timing controller.

9. The display device as claimed in claim 7, wherein, The display device further includes: a counting unit; The counting unit is configured to count the first number of the set target corresponding to the displayed data, and output a counting pass command when it is determined that the first number is the same as the set number corresponding to the target display mode; The timing controller is further configured to control the counting unit to enter the non-counting state when it receives the display mode switching enable command; and to control the counting unit to enter the counting state when it receives the data mode switching complete command.

10. The display device as claimed in claim 9, wherein, The counting unit is integrated within the timing controller.

Images