Method, apparatus and device for measuring potential defects of soi cmos device
By detecting various current parameters of SOI CMOS devices, potentially damaged devices are screened out, solving the problem of device failure under high temperature conditions and improving the reliability and durability of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHINA ELECTRONICS RELIABILITY AND ENVIRONMENTAL TESTING INSTITUTE ((THE FIFTH INSTITUTE OF ELECTRONICS MINISTRY OF INDUSTRY AND INFORMATION TECHNOLOGY) (CHINA SAIBAO LABORATORY)
- Filing Date
- 2023-12-01
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies struggle to detect potential defects in SOI CMOS devices under high-temperature conditions, leading to device malfunctions after a period of operation and resulting in significant losses.
By acquiring parameters such as saturated drain current, off-state drain current, on-state substrate current, and off-state substrate current of SOI CMOS devices, and performing multiple comparisons and correlation analyses, devices with potential damage were screened out.
This improves the reliability of SOI CMOS devices at high temperatures and avoids failures and losses caused by potential defects.
Smart Images
Figure CN117572190B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor device measurement technology, and in particular to a method, apparatus and equipment for measuring potential defects in SOI CMOS devices. Background Technology
[0002] With the development of electronic automatic control systems in high-temperature environments such as aerospace, automotive electronics, deep well exploration, and nuclear reactors, the demand for high-temperature resistant components is constantly increasing. High-temperature resistant components typically refer to silicon-on-insulator (SOICMOS) devices. Compared to bulk silicon devices isolated by PN junctions, SOI CMOS devices lack well regions and possess excellent oxide isolation structures. The buried SiO2 layer eliminates the coupling between the device and the substrate, and the single-crystal silicon layer can be partially or fully depleted under gate voltage. The presence of buried oxide forms the unique front and back gate structures of SOI devices, allowing conductive channels to be formed both above and below the single-crystal silicon layer under gate voltage or substrate bias.
[0003] However, potential defects in SOI CMOS devices threaten their normal function. Under normal operating conditions, these defects do not manifest immediately but rather after a period of time. If these defects are exposed, they will cause the circuit to malfunction, leading to task failure and significant losses. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, and device for measuring potential defects in SOI CMOS devices to address the problems mentioned in the background art. This method can at least detect potential defects in SOI CMOS devices, thereby screening out qualified SOI CMOS devices, improving the reliability of SOI CMOS devices at high temperatures, and avoiding huge losses caused by failures.
[0005] To achieve the above and other objectives, according to various embodiments of the present disclosure, a first aspect of the present disclosure provides a method for measuring potential defects in SOI CMOS devices, including:
[0006] Obtain the saturated drain current and off-state drain current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on the first comparison result of the saturated drain current and the off-state drain current.
[0007] Obtain the on-state substrate current and off-state substrate current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on the second comparison result of the on-state substrate current and the off-state substrate current.
[0008] At a preset temperature, the off-state drain current of at least one SOI CMOS device is obtained, and the correlation between the off-state drain current and the corresponding temperature is obtained. Based on the correlation, it is determined whether there is potential damage to the drain of the SOI CMOS device, and SOI CMOS devices with potential damage are screened.
[0009] The method for measuring potential defects in SOI CMOS devices in the above embodiments first acquires the saturated drain current and off-state drain current of at least one SOI CMOS device. Based on a first comparison result of the saturated drain current and the off-state drain current, it determines whether there is potential damage to the drain of the SOI CMOS device, making a preliminary judgment on whether the drain is potentially damaged. Then, it acquires the on-state substrate current and off-state substrate current of at least one SOI CMOS device. Based on a second comparison result of the on-state substrate current and the off-state substrate current, it determines whether there is potential damage to the drain of the SOI CMOS device. It verifies whether there is potential damage to the drain by checking whether a leakage channel from the drain to the substrate is generated. Then, it acquires the off-state drain current of at least one SOI CMOS device at a preset temperature, obtains the correlation between the off-state drain current and the corresponding temperature, and determines whether there is potential damage to the drain of the SOI CMOS device based on the correlation. SOI CMOS devices with potential damage are screened to ensure that qualified SOI CMOS devices can work normally at high temperatures and avoid failures. Current methods for measuring defects in SOI CMOS devices primarily detect obvious defects that occur during the manufacturing process, such as defects at the silicon wafer bonding interface. These methods do not consider the impact of potential defects within the SOI CMOS device. After a period of operation, these potential defects may surface, causing circuit malfunction and even significant losses. Furthermore, conventional measurements of the saturation drain current, threshold voltage, and current-voltage curve of a single SOI CMOS device cannot detect potential damage to the drain. The SOI CMOS device potential defect measurement method in this disclosure simultaneously measures the off-state drain current of multiple SOI CMOS devices to determine the presence of potential defects in the drain. It also verifies the potential damage and extent of damage to the drain by measuring the off-state drain current versus temperature of multiple SOI CMOS devices. This allows for the selection of qualified SOI CMOS devices, reducing heat loss during operation, improving reliability at high temperatures, and preventing significant losses due to malfunctions.
[0010] In some embodiments, determining whether there is potential damage to the drain of the SOICMOS device based on a first comparison result of the saturated drain current and the off-state drain current includes:
[0011] Determine whether the saturated drain current is within a preset first threshold range; and / or determine whether the off-state drain current is within a preset second threshold range;
[0012] If at least one of the saturation drain current and the off-state drain current of an SOI CMOS device is outside the corresponding preset threshold range, the drain of the SOI CMOS device is considered to have potential damage. By simultaneously measuring the off-state drain current of multiple devices, the potential damage to the drain of the SOI CMOS device can be detected, reducing the measurement difficulty.
[0013] In some embodiments, determining whether there is potential damage to the drain of the SOICMOS device based on a second comparison result of the on-state substrate current and the off-state substrate current includes:
[0014] Determine whether the substrate current in the on state is within a preset third threshold range; and / or determine whether the substrate current in the off state is within a preset fourth threshold range;
[0015] If at least one of the on-state substrate current and off-state substrate current of an SOI CMOS device is outside the corresponding preset threshold range, it is determined that the drain of the SOI CMOS device has potential damage. By simultaneously measuring the substrate current of multiple SOI CMOS devices, the types of potential defects are analyzed, the potential damage to the drain of the SOI CMOS device is detected, and whether a leakage path from the drain to the substrate has been formed.
[0016] In some embodiments, determining whether there is potential damage to the drain of the SOI CMOS device based on the correlation includes:
[0017] The slope of the off-state drain current as a function of temperature is obtained. If the slope is greater than a preset value, the drain of the SOI CMOS device is considered to have potential damage. By simultaneously obtaining the slope of the off-state drain current as a function of temperature for multiple SOI CMOS devices, the potential damage to the drain of the SOI CMOS devices is detected, and the degree of damage is determined based on the magnitude of the slope, thus screening out qualified SOI CMOS devices.
[0018] In some embodiments, before determining whether there is potential damage to the drain in the SOI CMOS device, the method further includes:
[0019] Obtain the drain current and gate voltage of at least one SOI CMOS device, obtain the transfer characteristic relationship between drain current and gate voltage, and determine whether the SOI CMOS device is damaged based on the transfer characteristic relationship.
[0020] The on-state and off-state gate currents of at least one SOI CMOS device are obtained. Based on a third comparison of the on-state and off-state gate currents, it is determined whether the gate of the SOI CMOS device is damaged. By first determining whether the SOI CMOS device and its gate are damaged, normal SOI CMOS devices are screened out, and then the drain is checked for potential damage.
[0021] In some embodiments, determining whether an SOI CMOS device is damaged based on transfer characteristic relationships includes:
[0022] Based on the transfer characteristics, if the drain current is within a preset fifth threshold range during the preset initial portion of the gate voltage, the SOI CMOS device is considered normal. Further measurements can then be performed.
[0023] In some embodiments, determining whether the gate of the SOI CMOS device is damaged based on a third comparison result of the on-state gate current and the off-state gate current includes:
[0024] Determine whether the on-state gate current is within a preset sixth threshold range; and / or determine whether the off-state gate current is within a preset seventh threshold range;
[0025] If both the on-state and off-state gate currents of the SOI CMOS device are within the corresponding preset threshold ranges, the gate of the SOI CMOS device is considered normal. Then, the drain of the SOI CMOS device can be measured to determine if there are any potential defects in the drain.
[0026] The second aspect of this disclosure provides a potential defect measurement device for SOI CMOS devices, including a drain current measurement module, a substrate current measurement module, and a preset temperature judgment module. The drain current measurement module is used to acquire the saturated drain current and off-state drain current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on a first comparison result of the saturated drain current and the off-state drain current. The substrate current measurement module is used to acquire the on-state substrate current and off-state substrate current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on a second comparison result of the on-state substrate current and the off-state substrate current. The preset temperature judgment module is used to acquire the off-state drain current of at least one SOI CMOS device at a preset temperature, acquire the correlation between the off-state drain current and the corresponding temperature, and determine whether there is potential damage to the drain of the SOI CMOS device based on the correlation, and screen out SOI CMOS devices with potential damage.
[0027] The SOI CMOS device potential defect measurement device in the above embodiments acquires the saturated drain current and off-state drain current of at least one SOI CMOS device through a drain current measurement module. Based on a first comparison result of the saturated drain current and the off-state drain current, it determines whether there is potential damage to the drain of the SOI CMOS device, and makes a preliminary judgment on whether the drain is potentially damaged. It acquires the on-state substrate current and off-state substrate current of at least one SOI CMOS device through a substrate current measurement module. Based on a second comparison result of the on-state substrate current and the off-state substrate current, it determines whether there is potential damage to the drain of the SOI CMOS device, and verifies whether there is potential damage to the drain based on whether a leakage channel from the drain to the substrate is generated. It acquires the off-state drain current of at least one SOI CMOS device at a preset temperature through a preset temperature judgment module, obtains the correlation between the off-state drain current and the corresponding temperature, and determines whether there is potential damage to the drain of the SOI CMOS device based on the correlation. It screens out SOI CMOS devices with potential damage, ensuring that qualified SOI CMOS devices can work normally at high temperatures and avoiding failures. Current SOI CMOS device defect measurement devices primarily detect obvious defects that occur during the manufacturing process, such as defects in the insulating layer of SOI CMOS devices. However, they do not consider the impact of potential defects within the SOI CMOS device. After a period of operation, these potential defects may surface, causing circuit malfunction or even significant losses. The SOI CMOS device potential defect measurement device in this embodiment, by incorporating a drain current measurement module, a substrate current measurement module, and a preset temperature judgment module, simultaneously measures the off-state drain current, substrate current, and the change in off-state drain current with temperature for multiple SOI CMOS devices. This determines whether potential defects exist in the drain of the SOI CMOS device, understands the degree of damage, and thus screens out qualified SOI CMOS devices. This reduces heat loss during SOI CMOS device operation, improves the reliability of SOI CMOS devices at high temperatures, and avoids significant losses due to malfunctions.
[0028] In some embodiments, the aforementioned SOI CMOS device potential defect measurement device further includes a transfer characteristic measurement module and a gate current measurement module. The transfer characteristic measurement module is used to acquire the drain current and gate voltage of at least one SOI CMOS device, acquire the transfer characteristic relationship between the drain current and gate voltage, and determine whether the SOI CMOS device is damaged based on the transfer characteristic relationship. The gate current measurement module is used to acquire the on-state gate current and off-state gate current of at least one SOI CMOS device, and determine whether the gate of the SOI CMOS device is damaged based on a third comparison result of the on-state gate current and off-state gate current. By measuring the SOI CMOS device and the gate in the SOI CMOS device through the transfer characteristic measurement module and the gate current measurement module, it is determined whether the SOI CMOS device has obvious damage, and SOI CMOS devices without obvious damage are selected for measurement to determine whether the SOI CMOS device has potential damage.
[0029] A third aspect of this disclosure provides an apparatus for measuring latent defects in an SOI CMOS device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the SOI CMOS device latent defect measurement method described above. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This diagram illustrates the application environment of the SOI CMOS device potential defect measurement method provided in one embodiment of this disclosure.
[0032] Figure 2 This is a flowchart illustrating a method for measuring potential defects in an SOI CMOS device according to an embodiment of this disclosure.
[0033] Figure 3 This is a flowchart illustrating a method for measuring potential defects in an SOI CMOS device provided in another embodiment of this disclosure.
[0034] Figure 4 This is a flowchart illustrating a method for measuring potential defects in an SOI CMOS device provided in another embodiment of the present disclosure.
[0035] Figure 5This is a schematic diagram of the transfer characteristic measurement of an SOI CMOS device provided in one embodiment of the present disclosure;
[0036] Figure 6 This is a schematic diagram of gate current measurement of an SOI CMOS device provided in one embodiment of the present disclosure;
[0037] Figure 7 This is a schematic diagram of drain current measurement of an SOI CMOS device provided in one embodiment of the present disclosure;
[0038] Figure 8 This is a schematic diagram of substrate current measurement of an SOI CMOS device provided in one embodiment of the present disclosure;
[0039] Figure 9 This is a schematic diagram showing the change of drain current as a function of temperature in an SOI CMOS device provided in one embodiment of this disclosure;
[0040] Figure 10 This is a schematic block diagram of a potential defect measurement device for SOI CMOS devices provided in one embodiment of the present disclosure;
[0041] Figure 11 This is a schematic block diagram of a potential defect measurement device for SOI CMOS devices provided in another embodiment of this disclosure;
[0042] Figure 12 This is a schematic diagram of the internal structure of a computer device provided in one embodiment of the present disclosure.
[0043] Explanation of reference numerals in the attached figures:
[0044] 100. SOI CMOS device potential defect measurement device; 111. Transfer characteristic measurement module; 112. Gate current measurement module; 120. Drain current measurement module; 130. Substrate current measurement module; 140. Preset temperature judgment module. Detailed Implementation
[0045] To facilitate understanding of this disclosure, a more complete description will be given below with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure.
[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0048] When using the terms "comprising," "having," and "including" as described herein, another component may be added unless explicitly qualifying terms such as "only," "consisting of," etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one. Those skilled in the art will understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0049] The method for measuring potential defects in SOI CMOS devices provided in this disclosure can be applied to, for example... Figure 1 In the application environment shown, terminal 104 communicates with server 102 via a network. Server 102 is connected to the server receiving end, and terminal 104 can also be directly connected to the server receiving end. The communication connection can be wired or wireless.
[0050] For example, the method for measuring potential defects in SOI CMOS devices is applied to terminal 104. Terminal 104 obtains the saturated drain current, off-state drain current, substrate current, and preset temperature of at least one SOI CMOS device from the server receiver. Terminal 104 determines whether there is potential damage to the drain of the SOI CMOS device based on a first comparison result and a second comparison result. Terminal 104 also obtains the correlation between the off-state drain current and the corresponding temperature, and determines whether there is potential damage to the drain of the SOI CMOS device based on the correlation, and sends the determination result of whether there is potential damage to the drain to server 102 for storage. Terminal 104 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc. Server 102 can be implemented using a standalone server or a server cluster composed of multiple servers. Terminal 104 and server 102 can be directly or indirectly connected via wired or wireless communication, such as through a network connection.
[0051] For example, the method for measuring potential defects in SOI CMOS devices is applied to server 102. Server 102 acquires the saturated drain current, off-state drain current, substrate current, and preset temperature of at least one SOI CMOS device from a server receiving end. Terminal 104 determines whether there is potential damage to the drain of the SOI CMOS device based on a first comparison result and a second comparison result. Server 102 also acquires the correlation between the off-state drain current and the corresponding temperature from the server receiving end. Terminal 104 determines whether there is potential damage to the drain of the SOI CMOS device based on the correlation. After determining whether there is potential damage to the drain of the SOI CMOS device, server 102 stores the determination result.
[0052] Potential defects in SOI CMOS devices threaten their normal function. Under normal operating conditions, these defects do not manifest immediately but rather over time, leading to significant losses. Potential defects are generally susceptible to temperature effects. At room temperature, their impact on the device is relatively small, and the device functions normally. However, as the temperature rises to a certain level, the electrical characteristics of the defects change, increasing leakage current and thus amplifying their impact on the device, potentially causing complete failure.
[0053] Currently, at high temperatures, the failure modes and failure stimuli of SOI CMOS devices mainly include saturation drain current failure, off-state drain current failure, and threshold voltage failure. Among them, saturation drain current failure is related to the failure of threshold voltage and gate oxide capacitance, and temperature changes can also cause saturation drain current failure. Off-state drain current failure is related to gate oxide quality, channel surface contamination, drain damage, etc. When the drain is damaged, although the channel is in the off state, current will still flow from the drain to the substrate, thus generating leakage current. Threshold voltage failure is related to gate oxide quality, channel injection, etc.
[0054] When the saturation drain current, threshold voltage, and off-state drain current measurements are normal, it doesn't mean the device is problem-free. A certain parameter might be too high because the drain terminal of the device has suffered minor damage. After the device has been operating for a period of time, the damage will increase, causing changes in the saturation drain current and threshold voltage, leading to device failure. This, in turn, will affect the functionality of the entire device and system, resulting in irreversible damage.
[0055] Based on this, please refer to Figure 2 This disclosure provides a method for measuring potential defects in SOI CMOS devices, which can at least detect potential defects in SOI CMOS devices, thereby screening out qualified SOI CMOS devices, improving the reliability of SOI CMOS devices at high temperatures, and avoiding huge losses caused by failures. The method includes the following steps:
[0056] Step S12: Obtain the saturated drain current and off-state drain current of at least one SOI CMOS device. Based on the first comparison result of the saturated drain current and the off-state drain current, determine whether there is potential damage to the drain of the SOI CMOS device.
[0057] Step S14: Obtain the on-state substrate current and off-state substrate current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on the second comparison result of the on-state substrate current and the off-state substrate current.
[0058] Step S16: Obtain the off-state drain current of at least one SOI CMOS device at a preset temperature, obtain the correlation between the off-state drain current and the corresponding temperature, and determine whether there is potential damage to the drain of the SOI CMOS device based on the correlation, and screen out SOI CMOS devices with potential damage.
[0059] As an example, please continue to refer to Figure 2First, by acquiring the saturated drain current and off-state drain current of at least one SOI CMOS device, and based on the first comparison result of the saturated drain current and off-state drain current, it is determined whether there is potential damage to the drain of the SOI CMOS device, and a preliminary judgment is made on whether the drain is potentially damaged. Then, by acquiring the on-state substrate current and off-state substrate current of at least one SOI CMOS device, and based on the second comparison result of the on-state substrate current and off-state substrate current, it is determined whether there is potential damage to the drain of the SOI CMOS device, and the presence of a drain-to-substrate leakage channel is verified to verify whether there is potential damage to the drain. Then, at a preset temperature, the off-state drain current of at least one SOI CMOS device is acquired, and the correlation between the off-state drain current and the corresponding temperature is obtained. Based on the correlation, it is determined whether there is potential damage to the drain of the SOI CMOS device, and SOI CMOS devices with potential damage are screened to ensure that qualified SOI CMOS devices can work normally at high temperatures and avoid failures. Current methods for measuring defects in SOI CMOS devices primarily detect obvious defects that occur during the manufacturing process, such as defects at the silicon wafer bonding interface. These methods do not consider the impact of potential defects within the SOI CMOS device. After a period of operation, these potential defects may surface, causing circuit malfunction and even significant losses. Furthermore, conventional measurements of the saturation drain current, threshold voltage, and current-voltage curve of a single SOI CMOS device cannot detect potential damage to the drain. The SOI CMOS device potential defect measurement method in this disclosure simultaneously measures the off-state drain current of multiple SOI CMOS devices to determine the presence of potential defects in the drain. It also verifies the potential damage and extent of damage to the drain by measuring the off-state drain current of multiple SOI CMOS devices with temperature. This allows for the selection of qualified SOI CMOS devices, reducing heat loss during operation, improving the reliability of SOI CMOS devices at high temperatures, and preventing significant losses due to malfunctions.
[0060] It should be noted that the preset temperatures include 298 Kelvin (K) to 473 Kelvin (K), such as 300K, 323K, 360K, 400K, 450K, or 473K, etc.
[0061] For example, please refer to Figure 3 Before determining whether there is potential damage to the drain in an SOI CMOS device, the following steps are also taken:
[0062] Step S111: Obtain the drain current and gate voltage of at least one SOI CMOS device, obtain the transfer characteristic relationship between the drain current and gate voltage, and determine whether the SOI CMOS device is damaged based on the transfer characteristic relationship.
[0063] Step S112: Obtain the on-state gate current and off-state gate current of at least one SOI CMOS device, and determine whether the gate of the SOI CMOS device is damaged based on the third comparison result of the on-state gate current and the off-state gate current.
[0064] As an example, please continue to refer to Figure 3 By first determining whether the SOI CMOS device and its gate are damaged, normal SOI CMOS devices are screened out. Then, the drain is checked for potential damage to determine the types of defects in the SOI CMOS device and improve the yield of SOI CMOS devices.
[0065] For example, please refer to Figure 4 In step S111, based on the transfer characteristic relationship, it is determined whether the SOI CMOS device is damaged, including:
[0066] Step S1111: Based on the transfer characteristic relationship, if the drain current is within the preset fifth threshold range in the preset initial part of the gate voltage, then the SOI CMOS device is judged to be normal.
[0067] As an example, please continue to refer to Figure 4 In step S112, based on the third comparison result of the on-state gate current and the off-state gate current, it is determined whether the gate of the SOI CMOS device is damaged, including:
[0068] Step S1121: Determine whether the on-state gate current is within the preset sixth threshold range; and / or determine whether the off-state gate current is within the preset seventh threshold range;
[0069] Step S1122: If the on-state gate current and off-state gate current of the SOI CMOS device are both within the corresponding preset threshold range, then the gate of the SOI CMOS device is determined to be normal.
[0070] As an example, please continue to refer to Figure 4 In step S12, based on the first comparison result of the saturated drain current and the off-state drain current, it is determined whether there is potential damage to the drain of the SOI CMOS device, including:
[0071] Step S121: Determine whether the saturated drain current is within a preset first threshold range; and / or determine whether the off-state drain current is within a preset second threshold range;
[0072] Step S122: If at least one of the saturation drain current and the off-state drain current of the SOI CMOS device is outside the corresponding preset threshold range, it is determined that there is potential damage to the drain of the SOI CMOS device.
[0073] As an example, please continue to refer to Figure 4 In step S14, based on the second comparison result of the on-state substrate current and the off-state substrate current, it is determined whether there is potential damage to the drain of the SOI CMOS device, including:
[0074] Step S141: Determine whether the on-state substrate current is within a preset third threshold range; and / or determine whether the off-state substrate current is within a preset fourth threshold range;
[0075] Step S142: If at least one of the on-state substrate current and the off-state substrate current of the SOI CMOS device is outside the corresponding preset threshold range, it is determined that there is potential damage to the drain of the SOI CMOS device.
[0076] As an example, please continue to refer to Figure 4 In step S16, based on the correlation, it is determined whether there is potential damage to the drain of the SOI CMOS device, including:
[0077] Step S161: Obtain the slope of the off-state drain current as a function of the corresponding temperature. If the slope is greater than a preset value, it is determined that there is potential damage to the drain of the SOI CMOS device.
[0078] For example, please refer to Figure 5 Simultaneously, the transfer characteristics of eight SOI CMOS devices were measured to determine whether the SOI CMOS devices had been damaged, resulting in leakage current, such as... Figure 5 As shown, in the preset initial part of the gate voltage, these 8 SOI CMOS devices did not exhibit large drain currents. The drain currents were all within the preset fifth threshold range, indicating that the 8 SOI CMOS devices were normal and had no obvious damage, and defects could be further measured.
[0079] For example, please refer to Figure 6 Simultaneously, the gate currents of eight SOI CMOS devices were measured to determine whether the gates were damaged. Figure 5 As shown, there is no significant difference between the on-state and off-state gate currents of these eight SOI CMOS devices, and they are all within the corresponding preset threshold range. This indicates that the gates of the eight SOI CMOS devices are not significantly damaged. Subsequently, the drain of the SOI CMOS devices can be measured to determine whether there are potential defects in the drain of the SOI CMOS devices.
[0080] For example, please refer to Figure 7Simultaneously, the saturated drain current and off-state drain current of eight SOI CMOS devices were measured. It was found that the saturated drain current of these eight SOI CMOS devices did not differ significantly and remained within the preset first threshold range. However, observing the off-state drain current of these eight SOI CMOS devices revealed that the off-state drain currents of SOI CMOS devices No. 3 and No. 4 were significantly larger than those of the other SOI CMOS devices, falling outside the preset second threshold range. Furthermore, the off-state drain current of SOI CMOS device No. 4 was greater than that of SOI CMOS device No. 3, indicating potential damage to the drains of SOI CMOS devices No. 3 and No. 4. By simultaneously measuring the off-state drain current of multiple devices, the potential damage to the drains of SOI CMOS devices can be detected, reducing the measurement difficulty.
[0081] For example, please refer to Figure 8 Simultaneously, the substrate currents of eight SOI CMOS devices were measured. It was found that the on-state substrate currents of these eight SOI CMOS devices did not differ significantly and were within the preset third threshold range. However, observing the off-state substrate currents of these eight SOI CMOS devices revealed that the off-state drain currents of SOI CMOS devices No. 3 and No. 4 were significantly larger than those of the other SOI CMOS devices, falling outside the preset fourth threshold range. Furthermore, the off-state substrate current of SOI CMOS device No. 4 was greater than that of SOI CMOS device No. 3, indicating potential damage to the drains of SOI CMOS devices No. 3 and No. 4, resulting in a leakage path from the drain to the substrate. By simultaneously measuring the substrate currents of multiple SOI CMOS devices, the types of potential defects were analyzed, potential damage to the drains of SOI CMOS devices was detected, and whether a leakage path from the drain to the substrate had been formed.
[0082] For example, please refer to Figure 9 Within the range of 300K-475K, the off-state drain current of eight SOI CMOS devices was measured simultaneously, and the relationship between the off-state drain current of these eight SOI CMOS devices and temperature was established. Figure 8As shown, the off-state drain current of SOI CMOS device No. 4 increases significantly with increasing temperature, and its slope is outside the preset value, indicating that SOI CMOS device No. 4 has a potential defect and poses a serious threat to the device's reliability. Although the off-state drain current of SOI CMOS device No. 3 also increases with increasing temperature, its slope is within the preset value, indicating that SOI CMOS device No. 3 has a potential defect, but the threat to the device's reliability is relatively small. By simultaneously obtaining the slope of the off-state drain current of multiple SOI CMOS devices as a function of temperature, the potential damage to the drain of SOI CMOS devices can be detected, and the degree of damage can be judged based on the magnitude of the slope, thus screening qualified SOI CMOS devices.
[0083] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0084] Based on the same inventive concept, this disclosure also provides a measuring apparatus for implementing the aforementioned method for measuring potential defects in SOI CMOS devices. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, specific limitations in one or more measuring apparatus embodiments provided below can be found in the above-described limitations regarding the method for measuring potential defects in SOI CMOS devices, and will not be repeated here.
[0085] For example, please refer to Figure 10This disclosure also provides a potential defect measurement device 100 for SOI CMOS devices, including a drain current measurement module 120, a substrate current measurement module 130, and a preset temperature judgment module 140. The drain current measurement module 120 is used to acquire the saturated drain current and off-state drain current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on a first comparison result of the saturated drain current and the off-state drain current. The substrate current measurement module 130 is used to acquire the on-state substrate current and off-state substrate current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on a second comparison result of the on-state substrate current and the off-state substrate current. The preset temperature judgment module 140 is used to acquire the off-state drain current of at least one SOI CMOS device at a preset temperature, acquire the correlation between the off-state drain current and the corresponding temperature, and determine whether there is potential damage to the drain of the SOI CMOS device based on the correlation, and screen out SOI CMOS devices with potential damage.
[0086] As an example, please continue to refer to Figure 11The SOI CMOS device potential defect measurement device 100 acquires the saturated drain current and off-state drain current of at least one SOI CMOS device through the drain current measurement module 120. Based on the first comparison result of the saturated drain current and the off-state drain current, it determines whether there is potential damage to the drain of the SOI CMOS device and makes a preliminary judgment on whether the drain is potentially damaged. The substrate current measurement module 130 acquires the on-state substrate current and off-state substrate current of at least one SOI CMOS device. Based on the second comparison result of the on-state substrate current and the off-state substrate current, it determines whether there is potential damage to the drain of the SOI CMOS device. It verifies whether there is potential damage to the drain by checking whether a leakage channel from the drain to the substrate is generated. The preset temperature judgment module 130 acquires the off-state drain current of at least one SOI CMOS device at a preset temperature, obtains the correlation between the off-state drain current and the corresponding temperature, and determines whether there is potential damage to the drain of the SOI CMOS device based on the correlation. It screens out SOI CMOS devices with potential damage to ensure that qualified SOI CMOS devices can work normally at high temperatures and avoid failures. Current SOI CMOS device defect measurement devices mainly detect obvious defects that occur during the manufacturing process, such as defects in the insulating layer of SOI CMOS devices. They do not consider the impact of potential defects within the SOI CMOS device. After a period of operation, these potential defects become apparent, causing circuit malfunction. The SOI CMOS device potential defect measurement device 100 in this embodiment, by setting up a drain current measurement module 120, a substrate current measurement module 130, and a preset temperature judgment module 140, simultaneously measures the off-state drain current, substrate current, and the change of off-state drain current with temperature for multiple SOI CMOS devices. This determines whether potential defects exist in the drain of the SOI CMOS device, understands the degree of damage to the SOI CMOS device, and thus screens out qualified SOI CMOS devices, reducing heat loss during SOI CMOS device operation, improving the reliability of SOI CMOS devices at high temperatures, and avoiding significant losses due to malfunctions.
[0087] For example, please refer to Figure 11The aforementioned SOI CMOS device potential defect measurement device 100 further includes a transfer characteristic measurement module 111 and a gate current measurement module 112. The transfer characteristic measurement module 111 acquires the drain current and gate voltage of at least one SOI CMOS device, obtains the transfer characteristic relationship between the drain current and gate voltage, and determines whether the SOI CMOS device is damaged based on the transfer characteristic relationship. The gate current measurement module 112 acquires the on-state gate current and off-state gate current of at least one SOI CMOS device, and determines whether the gate of the SOI CMOS device is damaged based on a third comparison result of the on-state gate current and off-state gate current. By measuring the SOI CMOS device and its gate through the transfer characteristic measurement module 111 and the gate current measurement module 112, it determines whether the SOI CMOS device has obvious damage, selects SOI CMOS devices without obvious damage for measurement, and determines whether the SOI CMOS device has potential damage.
[0088] Each module in the aforementioned SOI CMOS device latent defect measurement device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.
[0089] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 12 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a method for measuring potential defects in SOI CMOS devices. The display screen can be an LCD screen or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device casing, or an external keyboard, touchpad, or mouse.
[0090] Those skilled in the art will understand that Figure 12The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. A specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0091] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, databases, or other media used in the embodiments provided in this disclosure can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetically resistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be dynamic random access memory (DRAM). The processors involved in the various embodiments provided in this disclosure may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited thereto.
[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0093] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent disclosure. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the appended claims.
Claims
1. A method of measuring potential defects in SOI CMOS devices, comprising: include: Obtain the saturated drain current and off-state drain current of at least one SOI CMOS device, and determine whether there is potential damage to the drain of the SOI CMOS device based on the first comparison result of the saturated drain current and the off-state drain current. The on-state substrate current and off-state substrate current of the at least one SOI CMOS device are obtained, and based on the second comparison result of the on-state substrate current and the off-state substrate current, it is determined whether there is potential damage to the drain of the SOI CMOS device. At a preset temperature, the off-state drain current of the at least one SOI CMOS device is obtained, and the correlation between the off-state drain current and the corresponding temperature is obtained. Based on the correlation, it is determined whether there is potential damage to the drain of the SOI CMOS device, and SOI CMOS devices with potential damage are screened.
2. The SOI CMOS device potential defect measurement method of claim 1, wherein, Based on the first comparison result of the saturated drain current and the off-state drain current, determine whether there is potential damage to the drain of the SOI CMOS device, including: Determine whether the saturated drain current is within a preset first threshold range; and / or Determine whether the off-state drain current is within a preset second threshold range; If at least one of the saturated drain current and the off-state drain current of the SOI CMOS device is outside the corresponding preset threshold range, it is determined that the drain of the SOI CMOS device has potential damage.
3. The SOI CMOS device potential defect measurement method of claim 1, wherein, Based on the second comparison result of the on-state substrate current and the off-state substrate current, determine whether there is potential damage to the drain of the SOI CMOS device, including: Determine whether the on-state substrate current is within a preset third threshold range; and / or Determine whether the off-state substrate current is within a preset fourth threshold range; If at least one of the on-state substrate current and the off-state substrate current of the SOI CMOS device is outside the corresponding preset threshold range, it is determined that there is potential damage to the drain of the SOI CMOS device.
4. The method for measuring potential defects in an SOI CMOS device according to claim 1, wherein determining whether there is potential damage to the drain of the SOI CMOS device based on the correlation includes: Obtain the slope of the off-state drain current as a function of the corresponding temperature. If the slope is greater than a preset value, it is determined that there is potential damage to the drain of the SOI CMOS device.
5. The device potential defect measurement method according to any one of claims 1 to 4, wherein Before determining whether there is potential damage to the drain in the SOI CMOS device, the following steps are also included: Obtain the drain current and gate voltage of the at least one SOI CMOS device, obtain the transfer characteristic relationship between the drain current and gate voltage, and determine whether the SOI CMOS device is damaged based on the transfer characteristic relationship. The on-state gate current and off-state gate current of the at least one SOI CMOS device are obtained, and based on a third comparison result of the on-state gate current and the off-state gate current, it is determined whether the gate of the SOI CMOS device is damaged.
6. The SOI CMOS device potential defect measurement method of claim 5, wherein, Based on the aforementioned transfer characteristic relationship, determining whether the SOI CMOS device is damaged includes: According to the transfer characteristic relationship, if the drain current is within a preset fifth threshold range during the preset initial portion of the gate voltage, then the SOI CMOS device is determined to be normal.
7. The SOI CMOS device potential defect measurement method of claim 5, wherein, Based on the third comparison result of the on-state gate current and the off-state gate current, it is determined whether the gate of the SOI CMOS device is damaged, including: Determine whether the on-state gate current is within a preset sixth threshold range; and / or Determine whether the off-state gate current is within a preset seventh threshold range; If both the on-state gate current and the off-state gate current of the SOI CMOS device are within the corresponding preset threshold range, then the gate of the SOI CMOS device is determined to be normal.
8. An SOI CMOS device potential defect measurement apparatus, characterized by, include: A drain current measurement module is used to acquire the saturated drain current and off-state drain current of at least one SOI CMOS device, and to determine whether there is potential damage to the drain of the SOI CMOS device based on a first comparison result of the saturated drain current and the off-state drain current. A substrate current measurement module is used to acquire the on-state substrate current and the off-state substrate current of the at least one SOI CMOS device, and to determine whether there is potential damage to the drain of the SOI CMOS device based on a second comparison result of the on-state substrate current and the off-state substrate current. A preset temperature judgment module is used to obtain the off-state drain current of the at least one SOI CMOS device at a preset temperature, obtain the correlation between the off-state drain current and the corresponding temperature, and determine whether there is potential damage to the drain of the SOI CMOS device based on the correlation, and screen out SOI CMOS devices with potential damage.
9. The SOI CMOS device potential defect measurement apparatus of claim 8, wherein, Also includes: The transfer characteristic measurement module is used to acquire the drain current and gate voltage of the at least one SOI CMOS device, acquire the transfer characteristic relationship between the drain current and gate voltage, and determine whether the SOI CMOS device is damaged based on the transfer characteristic relationship. A gate current measurement module is used to acquire the on-state gate current and off-state gate current of the at least one SOI CMOS device, and to determine whether the gate of the SOI CMOS device is damaged based on a third comparison result of the on-state gate current and the off-state gate current.
10. An SOI CMOS device potential defect measurement apparatus comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1-7.