A solid state disk write delay processing method and device, a solid state disk and a medium

Abstract

This invention discloses a method, apparatus, solid-state drive (SSD), and medium for handling write latency in solid-state drives (SSDs), relating to the field of storage technology. The method uses a preset Long Short-Term Memory (LSTM) network model to predict the remaining quantity in the command queue and the remaining quantity in the data buffer. If the remaining quantity is determined to be greater than a target remaining quantity, the rate at which the host issues write commands or the rate at which the SSD receives write commands is reduced. This ensures that commands in the command queue and data in the data buffer can be processed, minimizing the risk of the command queue and data buffer becoming clogged. This allows for continued processing of write commands sent by the host, reducing peak write latency. Furthermore, reducing the rate at which the host issues write commands or the rate at which the SSD receives write commands keeps the number of commands in the command queue and the amount of data in the data buffer as close as possible to the target remaining quantity, ensuring consistency in write latency and stability of the SSD's performance.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a method, apparatus, solid-state drive and medium for processing write latency of solid-state drives. Background Technology

[0002] With the rapid development of internet technology, the amount of data is growing exponentially, requiring the support of storage technologies. Solid State Drives (SSDs) are one of the commonly used data storage devices. When a host writes data to an SSD, it first issues a write command to the Submission Queue (SQ), then saves the corresponding data to be written in the host's memory. When a write request arrives at the SSD, it executes it immediately, first transferring the write command and the corresponding data from the host memory to the SSD's command queue and data buffer, respectively. Then, it processes the write command in the command queue and writes the corresponding data to the storage.

[0003] During the data storage process, the speed at which the host issues write commands is much faster than the speed at which the SSD processes write commands. This can lead to a situation where the SSD's command queue is full of write commands and its data buffer is full of data, making it unable to continue processing write commands sent by the host. This results in peak write latency, which in turn reduces the consistency of SSD write latency and reduces performance stability.

[0004] Therefore, minimizing peak write latency and improving the consistency and performance stability of solid-state drive write latency are technical problems that urgently need to be solved by those in this field. Summary of the Invention

[0005] The purpose of this invention is to provide a method, apparatus, solid-state drive (SSD), and medium for handling write latency in solid-state drives (SSDs), in order to solve the technical problem that when an SSD's command queue is filled with write commands and its data buffer is filled with data during the data storage process, it is unable to continue processing write commands sent by the host, resulting in write latency peaks and reduced consistency and performance stability of the SSD's write latency.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for processing solid-state drive write latency, comprising:

[0007] Obtain the first current rate at which the host issues the write command and / or the second current rate at which the solid-state drive receives the write command;

[0008] The method utilizes a preset Long Short-Term Memory (LSTM) network model to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive (SSD). Determining the output of the preset LSM network model includes: inputting the first historical remaining quantity of the command queue and / or the second historical remaining quantity of the data buffer, collected over multiple historical periods, into a forward LSM network model in chronological order to obtain a first output; and inputting the first historical remaining quantity and / or the second historical remaining quantity into a reverse LSM network model in chronological order to obtain a second output; and combining the first output and the second output according to a first preset weight to obtain the final output of the preset LSM network model.

[0009] If the first remaining quantity is detected to be greater than the first target remaining quantity and / or the second remaining quantity is detected to be greater than the second target remaining quantity, the first current rate is reduced to the first target rate value and / or the second current rate is reduced to the second target rate value.

[0010] On the one hand, obtaining the first historical remaining quantity of the command queue collected within multiple historical time periods includes:

[0011] Establish a test platform for testing the solid-state drive, and simulate preset services on the test platform;

[0012] During the simulation of the preset service, monitoring is conducted through the firmware operation logs of the solid-state drive;

[0013] The log information is used to obtain the first historical remaining quantity of the command queue of the solid-state drive within multiple historical time periods; wherein, the feature data corresponding to the first historical remaining quantity of the command queue includes: the time period in which the first historical remaining quantity of the command queue was sampled, the mode of the host issuing commands, the size of the data block, and the size of the data read or written; the mode of the host issuing commands includes read commands and write commands;

[0014] After obtaining the first historical remaining quantity of the command queue collected within the multiple historical time periods, the method further includes:

[0015] The first remaining historical quantity is divided into a training set, a validation set, and a test set according to a second preset weight; wherein the weight corresponding to the training set is greater than the weight of the validation set and the weight of the test set.

[0016] The preset long short-term memory network model is trained using the training set, and the current number of training iterations is obtained.

[0017] Determine whether the current training count is greater than or equal to the preset training count;

[0018] If so, output the training results of the preset long short-term memory network model;

[0019] If not, then obtain the preset error precision;

[0020] If the error accuracy is found to meet the first preset requirement, the step of returning the training result of the preset long short-term memory network model is performed.

[0021] If the error accuracy is found to be not in line with the first preset requirement, the process returns to the step of determining whether the current number of training iterations is greater than or equal to the preset number of training iterations.

[0022] After outputting the training results of the preset long short-term memory network model, the method further includes:

[0023] The prediction ability of the determined preset long short-term memory network model is tested using the validation set, and the prediction ability test results are obtained.

[0024] If the prediction ability detection result meets the second preset requirement, the prediction result of the determined preset long short-term memory network model is verified using the test set.

[0025] If the prediction capability detection result does not meet the second preset requirement, the process returns to the step of establishing a test platform for testing the solid-state drive and simulating a preset service on the test platform.

[0026] On the other hand, determining the remaining quantity of the first target and / or the remaining quantity of the second target includes:

[0027] If the host is detected to issue the write command at different rates, and / or if the solid-state drive is detected to receive the write command at different rates, the first historical remaining quantity and / or the second historical remaining quantity at each issuance rate are obtained; wherein, the first historical remaining quantity is determined based on the difference between the bits at the head of the command queue and the bits at the tail of the command queue; the second historical remaining quantity is determined based on the difference between the preset data storage amount of the data buffer and the data storage amount at a historical time.

[0028] Write latency data at various download speeds was obtained using a test tool for testing the write latency of the solid-state drive.

[0029] Obtain the minimum write latency data from all the write latency data;

[0030] Obtain the first historical remaining quantity and / or the second historical remaining quantity corresponding to the minimum write latency data as the first target remaining quantity and / or the second target remaining quantity.

[0031] On the other hand, after reducing the first current rate to the first target rate value and reducing the second current rate to the second target rate value, the method further includes:

[0032] The data corresponding to the write command sent by the host according to the first target rate value is stored in the data storage area of ​​the host;

[0033] The host controller uses the value of the doorbell register to indicate to the solid-state drive that a new write command exists and stores it in the host's command submission queue.

[0034] The write command retrieved from the command submission queue according to the second target rate value is stored in the command queue, and the data corresponding to the write command is stored from the data storage area to the data buffer; wherein, the command queue and the data buffer are both located in the solid-state drive;

[0035] Parse the write command in the command queue;

[0036] According to the parsed write command, the data corresponding to the write command is stored from the data buffer into the non-volatile memory.

[0037] On the other hand, the non-volatile memory includes multiple flash memory modules; each flash memory module contains multiple channels; the step of storing the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command includes:

[0038] According to the parsed write command, the data corresponding to the write command in the data buffer is stored in the multiple flash memory corresponding to the non-volatile memory;

[0039] The command submission queue is multiple, and the step of retrieving the write command from the command submission queue according to the second target rate value and storing the write command into the command queue, and storing the data corresponding to the write command from the data storage area to the data buffer includes:

[0040] According to the second target rate value, the same number of write commands are sequentially retrieved from each of the command submission queues and stored in the command queue, and the data corresponding to the write commands is stored from the data storage area to the data buffer.

[0041] On the other hand, after storing the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command, the method further includes:

[0042] Obtain prompt information indicating that the write data corresponding to the write command is stored in the non-volatile memory;

[0043] The prompt message is sent to the completion queue in the host;

[0044] The host is notified that the write command has been processed based on the prompt information in the completion queue.

[0045] On the other hand, predicting the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive using a preset long short-term memory network model includes:

[0046] Monitor the process of the host processing the write command and / or monitor the process of the solid-state drive processing the write command;

[0047] If it is detected that the process of the host processing the write command is to store the write command to the command submission queue, and / or if it is detected that the process of the solid-state drive processing the write command is to write the write command to the command queue, the first remaining quantity of the command queue of the solid-state drive and / or the second remaining quantity of the data buffer are predicted by the preset long short-term memory network model.

[0048] Before comparing the first remaining quantity with the first target remaining quantity, and / or before comparing the second remaining quantity with the second target remaining quantity, the method further includes:

[0049] The first remaining quantity of the command queue of the solid-state drive and / or the second remaining quantity of the data buffer are low-pass filtered by a low-pass filter.

[0050] To address the aforementioned technical problems, the present invention also provides a solid-state drive write latency processing device, comprising:

[0051] The acquisition module is used to acquire the first current rate at which the host issues a write command and / or the second current rate at which the solid-state drive receives the write command;

[0052] The prediction module is used to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive using a preset long short-term memory network model. Determining the output of the preset long short-term memory network model includes: inputting the first historical remaining quantity of the command queue and / or the second historical remaining quantity of the data buffer collected over multiple historical periods into a forward long short-term memory network model in chronological order to obtain a first output; and inputting the first historical remaining quantity and / or the second historical remaining quantity into a reverse long short-term memory network model in chronological order to obtain a second output; and combining the first output and the second output according to a first preset weight to obtain the final output of the preset long short-term memory network model.

[0053] The reduction module is configured to reduce the first current rate to a first target rate value and / or reduce the second current rate to a second target rate value when the first remaining quantity is detected to be greater than the first target remaining quantity and / or the second remaining quantity is detected to be greater than the second target remaining quantity.

[0054] To address the aforementioned technical problems, the present invention also provides a solid-state drive, comprising:

[0055] Memory, used to store computer programs;

[0056] The processor is used to implement the steps of the above-described solid-state drive write latency processing method when executing the computer program.

[0057] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described solid-state drive write latency processing method.

[0058] The solid-state drive (SSD) write latency processing method provided by the present invention includes: obtaining a first current rate at which the host issues a write command and / or a second current rate at which the SSD receives a write command; predicting a first remaining quantity in the command queue and / or a second remaining quantity in the data buffer of the SSD using a preset long short-term memory (LSTM) network model; and reducing the first current rate to a first target rate value and / or the second current rate to a second target rate value when the first remaining quantity is detected to be greater than a first target remaining quantity and / or when the second remaining quantity is detected to be greater than a second target remaining quantity.

[0059] The beneficial effects of this invention are as follows: First, the method uses a preset long short-term memory network model to predict the remaining quantity in the command queue and the remaining quantity in the data buffer. Then, when it is determined that the remaining quantity is greater than the target remaining quantity, the rate at which the host issues write commands or the rate at which the solid-state drive (SSD) receives write commands is reduced. This allows commands in the command queue and data in the data buffer to be processed, minimizing the risk of the command queue and data buffer becoming full. This allows for continued processing of write commands sent by the host, reducing peak write latency. Furthermore, by reducing the rate at which the host issues write commands or the rate at which the SSD receives write commands, the number of commands in the command queue and the amount of data in the data buffer are kept as close as possible to the target remaining quantity, improving the consistency of write latency and the stability of performance of the SSD. Second, compared to obtaining the actual remaining quantity... The method provided by this invention, which adjusts the write command issuance / reception rate after the quantity is measured, uses a preset Long Short-Term Memory (LSTM) network model to predict the remaining quantity in advance. Based on the remaining quantity, the rate at which the host issues write commands or the rate at which the solid-state drive receives write commands is adjusted, ensuring that the adjustment of the write command rate is lag-free and greatly improving the processing efficiency of write latency peaks. Furthermore, when predicting the remaining quantity, the preset LSM network model is trained by inputting a forward input sequence into a forward LSM network model and a reverse input sequence into a reverse LSM network model, i.e., bidirectional learning. This strengthens and highlights the overall characteristics of the remaining quantity in the LSM network command queue, greatly improving the accuracy of the remaining quantity prediction. Thus, based on the more accurate remaining quantity, the write command rate can be adjusted more accurately.

[0060] In addition, after obtaining the first historical remaining quantity, the historical remaining quantity is divided into training set, validation set and test set and input into the long short-term memory network model respectively. The number of training times and training accuracy are also set, which greatly improves the accuracy of the determined preset long short-term memory network model.

[0061] When determining the remaining quantity of the first target and the remaining quantity of the second target, the historical remaining quantity and write data delay data corresponding to the write commands issued / received at different rates are obtained, and the historical remaining quantity corresponding to the minimum write delay data is used as the target remaining quantity, so that the determined target remaining quantity value is more accurate.

[0062] After the host stores the data corresponding to the write command in the data storage, it notifies the solid-state drive (SSD) of the existence of the write command through the doorbell register, enabling the SSD to understand the status of the write command in a timely manner and process it promptly. After parsing the write command in the command queue, the SSD stores the data corresponding to the write command in non-volatile storage, ensuring that the data will not be lost due to power failure and achieving persistent data preservation.

[0063] Setting up multiple flash drives in the solid-state drive, multiple channels in each flash drive, and multiple command submission queues in the host facilitates access and improves data throughput.

[0064] After storing the data in non-volatile memory, the system notifies the host that the write command has been completed, thus ensuring that the data has been written to the non-volatile memory of the solid-state drive in the manner that the host was notified. The system also sends a completion message to the completion queue in the host, allowing the user to understand the progress of the data writing process.

[0065] Upon detecting that a write command is being placed in the command submission queue, and / or upon detecting that the SSD is writing a write command to the command queue, the remaining quantity is predicted, enabling timely adjustment of the write command rate and improving the stability of SSD performance. Before comparing the remaining quantity with the target remaining quantity, the information is processed by a low-pass filter to ensure a smooth signal input to the SSD controller, minimizing spikes or rapid changes in the SSD controller's response to the command queue or data buffer.

[0066] In addition, the present invention also provides a solid-state drive write latency processing device and a solid-state drive, which have the same or corresponding technical features as the solid-state drive write latency processing method mentioned above, and have the same effect. Attached Figure Description

[0067] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 A structural diagram of an apparatus for reducing write latency peak based on adjusting the rate of sending / receiving write commands, provided in an embodiment of the present invention;

[0069] Figure 2 A flowchart illustrating a method for a host computer and a solid-state drive to process write commands, provided in an embodiment of the present invention;

[0070] Figure 3 A flowchart illustrating a method for handling solid-state drive write latency provided in an embodiment of the present invention;

[0071] Figure 4 A flowchart illustrating a method for predicting the remaining number of SSD command queues based on a long short-term memory network, provided in an embodiment of the present invention;

[0072] Figure 5A structural diagram of a solid-state drive write latency processing device provided in an embodiment of the present invention;

[0073] Figure 6 A structural diagram of a solid-state drive provided in another embodiment of the present invention. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0075] The core of this invention is to provide a method, apparatus, solid-state drive (SSD), and medium for handling solid-state drive (SSD) write latency, in order to solve the technical problem that when the SSD's command queue is full of write commands and the data buffer is full of data during the data storage process, it is unable to continue processing write commands sent by the host, resulting in write latency peaks, which leads to reduced consistency of SSD write latency and reduced performance stability.

[0076] With the rapid development of internet technology, data volume is exponentially increasing, making storage technology increasingly crucial for big data. Various big data applications pose greater challenges to the performance and reliability of storage systems. Solid-state drives (SSDs) based on Not-AND (NAND) flash memory have become a hot topic in the storage field due to their higher reliability, better performance, and lower power consumption. SSDs are data storage devices that use integrated circuit components. Compared to traditional hard disk drives (HDDs), SSDs offer higher input / output (I / O) performance. Conventional SSD designs primarily focus on achieving high throughput or high input / output operations per second (IOPS), which is achieved through parallelism in their architecture, where the SSD executes write requests immediately. However, the host typically submits write commands to the SSD at a faster rate than the SSD can execute write commands.

[0077] When the host writes data to the SSD, it first issues a write command to the command commit queue. Then, it stores the data to be written corresponding to the write command in the host's data memory. When the SSD is ready to process the write command and related data, the SSD memory controller transfers the write command and the corresponding data from the host memory to the SSD's command queue and write data buffer, respectively. A mismatch in the processing speed between the host issuing write commands and the SSD processing them can cause the SSD controller to receive too many write commands from the host, exceeding the SSD's processing speed and the speed at which it writes the related data to the semiconductor flash memory. This can lead to the SSD's command queue becoming full of write commands and the write data buffer becoming full of data, causing the SSD to be unable to accept new write commands and related data, resulting in peak write latency. Furthermore, the SSD cannot handle urgent write commands from the host.

[0078] Therefore, this invention provides a method to predict the remaining quantity of the solid-state drive (SSD) command queue and data buffer using a preset long short-term memory (LSTM) network model. Based on these remaining quantities and a target remaining quantity, the rate at which the SSD receives host commands or the rate at which the host issues write commands is adjusted to minimize write latency peaks. Furthermore, compared to traditional control algorithms (such as Proportional-Integral-Differential (PID) control), which exhibit significant performance fluctuations under different hardware configurations and are prone to disturbances during transitions that propagate to the stable phase, affecting write latency consistency, and whose disturbance levels may vary across hardware configurations, requiring meticulous calibration by developers, resulting in high time and manpower costs, the method provided by this invention, applied to SSDs, allows for automatic adjustment of the write command issuance / reception rate via the SSD controller, eliminating the need for manual adjustment. This method is suitable for various complex scenarios and enables more precise adaptive parameter optimization, leading to higher SSD stability.

[0079] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0080] Figure 1 A structural diagram of a device for reducing write latency peaks based on adjusting the write command sending / receiving rate, as provided in an embodiment of the present invention, is shown below. Figure 1As shown, the device includes: a host 1 and a solid-state drive 2. The host memory of host 1 includes a command submission queue and a data storage area. The command submission queue can be a circular buffer with a fixed size. When it is full, a new entry is written to the beginning of the buffer, overwriting the first entry placed in the circular buffer. Solid-state drive 2 includes a solid-state drive controller, dynamic random access memory (DRAM), and non-volatile memory. Specifically, the solid-state drive controller includes a flash memory control module, a control module, a prediction module, a host interface, and direct memory access (DMA); the DRAM includes a command queue and a data buffer; and the non-volatile memory contains multiple flash memory modules. Solid-state drive 2 is connected to host 1 via a host interface. Currently, the mainstream host interface for solid-state drive 2 uses either a Serial Advanced Technology Attachment (SATA) interface or a Peripheral Component Interconnect Express (PCIe) interface.

[0081] When host 1 needs to write data to solid-state drive 2, it adds a new command to the command commit queue. Host 1 places the write command at the end of the command commit queue. Furthermore, host 1 stores the corresponding write data in the write data storage area.

[0082] Host 1 can notify the SSD controller by updating the doorbell register, indicating that the SSD host has added a new command to the command submission queue. To process the write command and ultimately store the relevant data in non-volatile memory, the SSD controller retrieves the write command from the head of the command submission queue. The SSD controller parses the write command and includes it as part of the command queue to be executed, identifying the start position and length of the write data within the data storage area. This start position and length are written to the direct memory access (DMI) module within the SSD controller. Subsequently, the DMI controller retrieves the write data from the data storage area and writes it to the write data buffer. The flash memory control module processes the write command in the command queue and writes the corresponding data to the SSD's non-volatile memory. Write data can be written to multiple flash memory modules, which can be partitioned into channels to facilitate access and improve data throughput.

[0083] If the rate at which the SSD controller retrieves write commands from the command commit queue and the rate at which it retrieves the corresponding write data from the data storage area is not controlled, the rate at which write commands and write data are transferred to the command queue and data buffer can exceed the rate at which the SSD executes write commands in the command queue to store the write data in non-volatile memory. This can lead to one or both of the command queue and data buffer becoming full. If the command queue or data buffer is full, write latency will spike or increase relative to the time spent storing data in non-volatile memory. This is because when the host continues to submit write commands without knowing the command queue and data buffer, the write commands are backed up in the command commit queue.

[0084] To avoid or minimize increased write latency, the solid-state drive (SSD) controller can limit the rate at which write commands enter, i.e., the rate at which write commands are queued in the command queue. This is done dynamically, i.e., during the operation of SSD 2, the remaining quantity of the write command queue or the remaining quantity of the data buffer is dynamically predicted by a prediction module, and the queuing rate is dynamically adjusted by an adaptive controller based on this prediction. In other words, SSD 2 controls and adjusts the rate at which it processes new write commands from the command submission queue to avoid the command queue and / or write data buffer becoming full. Increasing or decreasing the ingress throttling rate allows the SSD controller to retrieve and process write commands from the command submission queue for placement in the command queue, and to retrieve corresponding write data from the write data storage area for placement in the data buffer, thereby maintaining the command queue and data buffer at a rate close to or at the desired capacity. In this embodiment, the control module is used to calculate the appropriate ingress throttling rate. The adaptive controller provides a method for adjusting the ingress throttling rate so that the available capacity of the command queue and write data buffer is kept as close as possible to the desired or optimal value, and the system can respond promptly to fluctuations in the I / O command submission pattern of host 1 without overshooting or over-shooting.

[0085] Figure 2 A flowchart illustrating a method for processing write commands between a host and a solid-state drive, as provided in an embodiment of the present invention, is shown below. Figure 2 As shown, the method includes:

[0086] S10: The host prepares to write data and commands, and prompts the solid-state drive to start processing the write command;

[0087] S11: Predicted remaining quantity of command queue and data buffer for solid-state drives;

[0088] S12: The solid-state drive adjusts the current rate at which it receives write commands based on the remaining quantity;

[0089] S13: The solid-state drive acquires and parses write commands according to the adjusted rate for receiving write commands;

[0090] S14: Solid-state drive write command processing;

[0091] S15: After executing the write command, the solid-state drive sends back information to the host indicating that the write command has been processed.

[0092] When the host determines that data needs to be stored on the solid-state drive (SSD), it submits a write command to the command submission queue and stores the corresponding write data in the data storage area. The host updates a doorbell register to indicate the new tail position of the submission queue and notifies the SSD controller that a new write command has been submitted to the submission queue.

[0093] It should be noted that, Figure 2 The prediction of the remaining quantity is performed after the host prompts the SSD to start processing a write command. In practice, the prediction can also be performed after the SSD receives the write command sent by the host, so as to receive the next write command at the predicted rate. Therefore, predicting the first remaining quantity in the SSD's command queue and / or the second remaining quantity in the data buffer using a preset Long Short-Term Memory (LSTM) network model includes:

[0094] Monitor the host's process of processing write commands and / or monitor the solid-state drive's process of processing write commands;

[0095] If it is detected that the host process is storing the write command to the command submission queue, and / or if it is detected that the solid-state drive process is writing the write command to the command queue, the process proceeds to the step of predicting the first remaining quantity of the solid-state drive's command queue and / or the second remaining quantity of the data buffer using a preset long short-term memory network model.

[0096] The SSD controller retrieves write commands from the head of the command submission queue. To prevent the command queue or data buffer from becoming full, the SSD controller retrieves commands from the command submission queue at a limited rate (i.e., at a limited rate based on the write command entry point). Based on the retrieved host-issued commands, the prediction module predicts the remaining number of commands in the SSD's command queue, and the control module dynamically adjusts the rate at which the SSD controller retrieves write commands from the command submission queue. The SSD controller parses the retrieved write commands and identifies the start position of the corresponding write data in the data buffer and the total length of the write data.

[0097] The solid-state drive controller places the parsed write commands into free slots in the command queue. Additionally, the data transfer controller retrieves write data from the data storage area and writes it to the data buffer.

[0098] The flash translation layer of the solid-state drive (SSD) processes the parsed write commands from the command queue, translating any logical address into a physical address in non-volatile memory (NDM). The data transfer controller stores the address and length of the corresponding write data in the data buffer, as well as the physical address of the destination in NDM. The data transfer controller then retrieves the write data from the data buffer and writes it to the SSD's NDM, thus permanently storing the written data on the SSD.

[0099] Additionally, the SSD controller places an entry in the completion queue stored on the host and notifies the host. Both an entry in the completion queue and the notification alert the host that the written data has been written to the SSD's non-volatile memory, ensuring that the written data has been written to the SSD's non-volatile memory in the same manner as the host was notified.

[0100] Figure 3 A flowchart of a solid-state drive write latency processing method provided in an embodiment of the present invention is shown below. Figure 3 As shown, the method includes:

[0101] S16: Obtain the first current rate at which the host issues write commands and / or the second current rate at which the solid-state drive receives write commands;

[0102] S17: Predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive using a pre-defined long short-term memory network model;

[0103] S18: If a first remaining quantity is detected to be greater than a first target remaining quantity and / or a second remaining quantity is detected to be greater than a second target remaining quantity, the first current rate is reduced to a first target rate value and / or the second current rate is reduced to a second target rate value.

[0104] It should be noted that, in order to reduce the occurrence of write latency peaks in the embodiments of the present invention, the method of reducing the rate at which the host issues write commands can be adopted, the method of reducing the rate at which the solid-state drive receives write commands can be adopted, or both the method of reducing the rate at which the host issues write commands can be adopted and the method of reducing the rate at which the solid-state drive receives write commands can be adopted. There is no limitation on this, and the choice can be flexible.

[0105] To determine whether the rate of issuing or receiving write commands needs to be adjusted, the remaining quantity in the command queue and the remaining quantity in the data buffer are first predicted. In this embodiment of the invention, a preset Long Short-Term Memory (LSTM) network model is used to predict the remaining quantity.

[0106] The output of the preset long short-term memory network model is determined by: inputting the first historical remaining quantity of command queues and / or the second historical remaining quantity of data buffers collected in multiple historical time periods into the forward long short-term memory network model in chronological order to obtain the first output result; and inputting the first historical remaining quantity and / or the second historical remaining quantity into the reverse long short-term memory network model in chronological order to obtain the second output result; and combining the first output result and the second output result according to the first preset weight to obtain the final output result of the preset long short-term memory network model.

[0107] In addition, obtaining the first historical remaining quantity of command queues collected over multiple historical periods includes:

[0108] Establish a test platform for testing solid-state drives, and simulate preset business operations on the test platform;

[0109] During the simulation of preset business processes, monitoring is conducted through the firmware operation logs of the solid-state drive;

[0110] The log information is used to obtain the first historical remaining quantity of the command queue of the solid-state drive over multiple historical periods. The characteristic data corresponding to the first historical remaining quantity of the command queue includes: the time period in which the first historical remaining quantity of the command queue was sampled, the mode of the host issuing commands, the size of the data block, and the size of the data read or written. The mode of the host issuing commands includes read commands and write commands.

[0111] After obtaining the first historical remaining quantity of command queues collected over multiple historical time periods, the following is also included:

[0112] The remaining quantity of the first history is divided into a training set, a validation set, and a test set according to the second preset weight; wherein the weight of the training set is greater than the weight of the validation set and the weight of the test set.

[0113] The pre-defined long short-term memory network model is trained using the training set, and the current number of training iterations is obtained.

[0114] Determine whether the current number of training iterations is greater than or equal to the preset number of training iterations;

[0115] If so, output the training results of the preset long short-term memory network model;

[0116] If not, then obtain the preset error precision;

[0117] The step of returning the training result of the preset long short-term memory network model after detecting that the error accuracy meets the first preset requirement;

[0118] If the error accuracy is found to be less than the first preset requirement, return to the step of determining whether the current number of training iterations is greater than or equal to the preset number of training iterations.

[0119] After outputting the training results of the preset Long Short-Term Memory network model, it also includes:

[0120] The prediction ability of the predetermined long short-term memory network model is tested using the validation set, and the prediction ability test results are obtained.

[0121] If the prediction ability test result meets the second preset requirement, the prediction result of the determined preset long short-term memory network model is verified using the test set.

[0122] If the prediction capability test result does not meet the second preset requirement, return to the steps of establishing a test platform for testing solid-state drives and simulating preset business operations on the test platform.

[0123] The values ​​of the first preset weight, the second preset weight, the historical time obtained, the preset number of training sessions, the first preset requirement, and the second preset requirement mentioned in the above text regarding the establishment of a preset long short-term memory network model are not limited and can be determined according to the actual situation.

[0124] Figure 4 A flowchart illustrating a method for predicting the remaining quantity of an SSD command queue based on a Long Short-Term Memory (LSTM) network, as provided in this embodiment of the invention, is shown below. Figure 4 As shown, the method includes:

[0125] S19: Obtain historical data on the remaining number of commands in the SSD command queue through the SSD operation log, and then cut, organize, and classify the data to obtain the training set, validation set, and test set;

[0126] S20: Design an improved long short-term memory network model;

[0127] S21: Train the improved long short-term memory network model using the training set to obtain the trained long short-term memory network model;

[0128] S22: Obtain the remaining number of command queues for the solid-state drive using an improved long short-term memory network model.

[0129] A solid-state drive (SSD) testing platform was established to simulate real-world SSD operations. The remaining command queue count of the SSD exhibited strong periodicity and self-similarity over a given period. Utilizing this characteristic, the remaining command queue count of the SSD within a week was selected for learning, and the remaining command queue count for the 8th day was predicted. The SSD was run under real-world workload conditions, and the remaining command queue count was recorded hourly. Specifically, the SSD firmware operation logs were monitored, and the relevant data on the remaining command queue count of the SSD each hour was updated and statistically analyzed to obtain historical data on the remaining command queue count for 7 days. After obtaining the above remaining command queue count data, a four-dimensional array [time, rw, bs, size] was formed, with each element representing a single remaining command queue count. Table 1 shows the relevant feature data of the remaining command queue count of the SSD.

[0130] Table 1. Relevant characteristic data of the remaining number of command queues for solid-state drives.

[0131] time The time period for sampling the remaining number of commands in the solid-state drive's command queue rw The command modes issued by the host are divided into read and write. bs Data block size size Scale of reads or writes

[0132] After obtaining the above operational data, the raw network traffic data is first processed using a sliding window technique, such as cleaning outliers to reduce abnormal disturbances and normalizing sample features. After data normalization, the data is divided, for example, 80% of the dataset is used as the training set to train and optimize the model, another 10% as the validation set to evaluate the predictive ability of the trained model, and 10% as the test set to verify the prediction results. In other words, the data is divided into an 80% training set, a 10% validation set, and a 10% test set. Then, the data is quantized without dimensions to ensure that all feature data have a uniform data specification. The normalization transformation function for sample features is shown below:

[0133]

[0134] In the above formula, x′ t It refers to the sample features collected at time t, x′ min It is the minimum value of the features of the collected samples, x′ max It is the maximum value of the features of the collected samples.

[0135] When using an improved Long Short-Term Memory (LSTM) network (i.e., a pre-defined LSTM network model) to predict the remaining number of commands in the command queue, a network model for predicting the remaining number of commands in the command queue of a solid-state drive (SSD) based on an improved LSTM network is constructed. The network model mainly includes an input layer, a hidden layer, and an output layer structure. The hidden layer of the basic LSTM network is only trained in a positive direction, which leads to the problem of early learning of some features and poor memory performance. The hidden layer of the improved LSTM network model is trained in a bidirectional manner, which fully learns the overall features of the remaining number of commands in the SSD's command queue.

[0136] Specifically, an improved long short-term memory (LSTM) neural network is constructed by fusing a forward LSM network and a backward LSM neural network. Two LSM networks, each containing a forward input sequence and a backward input sequence, are used, and their outputs are combined with weights to obtain the final result. The hidden layer of the improved model consists of two parts: a forward cell state and a backward cell state. The flow sequence enters the hidden layer through the input layer and participates in both forward and backward computations. The final output is obtained by fusing the outputs of the forward and backward LSM networks in the output layer with certain weights. While ensuring that the sampled command queue remaining quantity strengths are arranged in chronological order, unknown command queue remaining quantity data is predicted using known command queue remaining quantity data. An improved Long Short-Term Memory (LSTM) network model is trained using the remaining command queue data from the first 7 days in a forward-ordered sequence. Simultaneously, the LTM network model is trained using the remaining command queue data in a reverse-ordered sequence, enabling bidirectional learning to strengthen and highlight the overall characteristics of the remaining command queue data in the LTM network. The training iterations and error precision need to be set. The standard for determining whether the model training is complete is: whether the training count has reached the set number of training iterations. If the training iterations have been reached, the results are output; otherwise, whether the prediction error meets the error requirements set by the training objective is checked. The prediction error is measured using Mean Absolute Error (MAE) and Root Mean Squared Error (RMSE). MAE is the average absolute error between the predicted and observed values, and RMSE is the expected value of the squared difference between the predicted and actual values. The smaller these two error values, the better the model performance. The formulas for calculating MAE and RMSE are shown below:

[0137]

[0138]

[0139] In the formula, P i R represents the predicted value. i represents the true value, and m represents the number of training iterations.

[0140] After predicting the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive using a preset long short-term memory network model, the first remaining quantity is compared with the first target remaining quantity, and the second remaining quantity is compared with the second target remaining quantity.

[0141] To ensure that the information on the first remaining quantity and the second remaining quantity can be smoothly input to the solid-state drive (SSD) controller, and to maximize the SSD controller's responsiveness to spikes or rapid changes in the command queue or data buffer, in some embodiments, before comparing the magnitudes of the first remaining quantity and the first target remaining quantity, and / or before comparing the magnitudes of the second remaining quantity and the second target remaining quantity, the following steps are also included:

[0142] The first remaining quantity in the command queue and / or the second remaining quantity in the data buffer of the solid-state drive are low-pass filtered using a low-pass filter.

[0143] To ensure the accuracy of the determined remaining quantities of the first and second targets, in some embodiments, determining the remaining quantities of the first and / or second targets includes:

[0144] When the host is detected to issue write commands at different rates, and / or when the solid-state drive is detected to receive write commands at different rates, the first historical remaining quantity and / or the second historical remaining quantity at each issuance rate are obtained; wherein, the first historical remaining quantity is determined based on the difference between the bits at the head of the command queue and the bits at the tail of the command queue; and the second historical remaining quantity is determined based on the difference between the preset data storage amount of the data buffer and the data storage amount at the historical moment.

[0145] Write latency data at various download speeds was obtained using a test tool for testing solid-state drives (SSDs).

[0146] Find the minimum write latency data from all write latency data;

[0147] Obtain the first and / or second historical remaining quantities corresponding to the minimum write latency data as the first target remaining quantity and / or second target remaining quantity.

[0148] If the comparison shows that the first remaining quantity is greater than the first target remaining quantity and / or the second remaining quantity is greater than the second target remaining quantity, then the first current rate is reduced to the first target rate value and / or the second current rate is reduced to the second target rate value.

[0149] In the solid-state drive (SSD) write latency processing method provided in this embodiment of the invention, a preset long short-term memory (LSTM) network model is used to predict the remaining quantity in the command queue and the remaining quantity in the data buffer. Then, when it is determined that the remaining quantity is greater than the target remaining quantity, the rate at which the host issues write commands or the rate at which the SSD receives write commands is reduced. This ensures that commands in the command queue and data in the data buffer can be processed, minimizing the risk of the command queue and data buffer becoming full. This allows for continued processing of write commands sent by the host, reducing peak write latency. Furthermore, by reducing the rate at which the host issues write commands or the rate at which the SSD receives write commands, the number of commands in the command queue and the amount of data in the data buffer are kept as close as possible to the target remaining quantity, improving the consistency of SSD write latency and the stability of performance. Secondly, compared to obtaining the actual remaining quantity... The method provided in this embodiment of the invention, which adjusts the write command issuance / reception rate after determining the remaining quantity, uses a preset Long Short-Term Memory (LSTM) network model to predict the remaining quantity in advance. Based on the remaining quantity, it adjusts the rate at which the host issues write commands or reduces the rate at which the solid-state drive (SSD) receives write commands. This ensures that the adjustment of the write command rate is lag-free and greatly improves the processing efficiency of write latency peaks. Furthermore, when predicting the remaining quantity, the preset LSM network model is trained by inputting a forward input sequence into a forward LSM network model and a reverse input sequence into a reverse LSM network model, i.e., it performs bidirectional learning. This strengthens and highlights the overall characteristics of the remaining quantity in the LSM network command queue, greatly improving the accuracy of the remaining quantity prediction. Thus, based on the more accurate remaining quantity, a more accurate adjustment of the write command rate can be achieved.

[0150] Based on the above embodiments, in order to write data to the solid-state drive, in some embodiments, after reducing the first current rate to a first target rate value and the second current rate to a second target rate value, the method further includes:

[0151] The data corresponding to the write command sent by the host according to the first target rate value is stored in the host's data storage area;

[0152] The control host uses the value of the doorbell register to indicate that there is a new write command on the solid-state drive, which is then stored in the host's command submission queue.

[0153] Write commands retrieved from the command submission queue according to the second target rate value are stored in the command queue, and the data corresponding to the write commands is stored from the data storage area to the data buffer; wherein, both the command queue and the data buffer are located in the solid-state drive;

[0154] Parse write commands in the command queue;

[0155] Based on the parsed write command, the data corresponding to the write command is stored in the non-volatile memory from the data buffer.

[0156] In the method provided in this embodiment, the solid-state drive (SSD) processes the write commands sent by the host; and after the host sends the write command, the SSD is notified through the doorbell register that there is a write command in the host's command submission queue, so that the SSD can process the write command in a timely manner.

[0157] To facilitate data access and improve data throughput, in some embodiments, the non-volatile memory includes multiple flash memory modules; each flash memory module contains multiple channels; storing the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command includes:

[0158] Based on the parsed write command, the data corresponding to the write command in the data buffer is stored in multiple flash memory locations corresponding to the non-volatile memory;

[0159] There are multiple command submission queues. The process of retrieving write commands from the command submission queues according to the second target rate value and storing the write commands in the command queues, as well as storing the data corresponding to the write commands from the data storage area to the data buffer, includes:

[0160] According to the second target rate value, the same number of write commands are retrieved sequentially from each command submission queue and stored in the command queue, and the data corresponding to the write commands is stored from the data storage area to the data buffer.

[0161] The number of flash memory modules contained in the non-volatile memory, the number of channels in each flash memory module, and the number of command submission queues in the host are not limited and are determined according to the actual situation. When multiple command submission queues exist, the solid-state drive controller will apply an appropriate write data rate (i.e., ingress throttling rate) to all command submission queues. If the write commands in one command submission queue are processed, the write commands in the remaining command submission queues will have to wait for a long time before they can be processed. Therefore, in this embodiment, commands from the submission queues are processed in a more equitable manner. The solid-state drive controller can process a certain number of commands from each submission queue evenly, or the solid-state drive controller can process a certain number of commands from each submission queue, so that a uniform amount of write data is stored in the data buffer.

[0162] In the method provided in this embodiment, the non-volatile memory includes multiple flash memory modules; each flash memory module contains multiple channels, and the host contains multiple command submission queues, which can greatly improve the data writing rate; in addition, when there are multiple command submission queues, the same number of commands in each command queue are processed, thereby storing a uniform amount of write data in the data buffer.

[0163] To ensure that the written data is written to the non-volatile memory of the solid-state drive in accordance with the notification to the host, in some embodiments, after storing the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command, the method further includes:

[0164] Obtain prompt information indicating that the write data corresponding to the write command is stored in non-volatile memory;

[0165] Send the notification message to the completion queue in the host;

[0166] The host is notified that the write command processing is complete based on the prompt information in the completion queue.

[0167] The notification message can be generated immediately after the write command is processed, or it can be generated some time later. In practice, to ensure that the host can promptly receive notification of the write command's completion, the solid-state drive (SSD) can generate a notification message immediately after processing the write command and send it to the host's completion queue, thus quickly notifying the host that the write command has been completed.

[0168] In the solid-state drive (SSD) write latency handling method described above, an adaptive controller is used to calculate and adjust the appropriate ingress throttling rate for the SSD to receive host write commands. The adaptive controller provides a method for adjusting the ingress throttling rate to keep the available capacity of the command queue and write data buffer as close as possible to the desired or optimal value, and the system can respond promptly to fluctuations in the host I / O command submission pattern without overshooting or over-shooting. The SSD controller receives information about the remaining available capacity in the command queue and the remaining available capacity in the write data buffer. Before receiving this information, a low-pass filter is used to process the information to smooth the signal input to the controller and prevent the controller from responding to spikes or rapid changes in the command queue or write data buffer. The adaptive controller performs these calculations individually and continuously, where the difference between the expected value (the remaining quantity of the first target and the remaining quantity of the second target) and the actual value (the remaining quantity of the command queue and the remaining quantity of the data buffer predicted by a preset long short-term memory network model) is used as the basis for calculations to adjust the entry throttling rate of the solid-state drive receiving host commands in real time, so as to keep the remaining quantity of the command queue at the optimal value as much as possible, eliminate write latency peaks as much as possible, reduce write latency, and maintain the performance stability of the solid-state drive.

[0169] In the above embodiments, the method for handling solid-state drive (SSD) write latency has been described in detail. This invention also provides a method for handling SSD write latency and corresponding embodiments for SSDs. It should be noted that this invention describes the embodiments of the device from two perspectives: one based on functional modules, and the other based on hardware.

[0170] Figure 5 This is a structural diagram of a solid-state drive write latency processing device provided according to an embodiment of the present invention. This embodiment, based on functional modules, includes:

[0171] The acquisition module 10 is used to acquire the first current rate at which the host issues a write command and / or the second current rate at which the solid-state drive receives a write command;

[0172] The prediction module 11 is used to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive using a preset long short-term memory network model. The determination of the output of the preset long short-term memory network model includes: inputting the first historical remaining quantity of the command queue and / or the second historical remaining quantity of the data buffer collected over multiple historical periods into a forward long short-term memory network model in chronological order to obtain a first output; and inputting the first historical remaining quantity and / or the second historical remaining quantity into a reverse long short-term memory network model in chronological order to obtain a second output; and combining the first output and the second output according to a first preset weight to obtain the final output of the preset long short-term memory network model.

[0173] The reduction module 12 is used to reduce the first current rate to the first target rate value and / or the second current rate to the second target rate value when a first remaining quantity is detected to be greater than a first target remaining quantity and / or a second remaining quantity is detected to be greater than a second target remaining quantity.

[0174] The solid-state drive write latency processing device also includes: a first acquisition module, which is used to acquire the first historical remaining quantity of command queues collected over multiple historical time periods;

[0175] The first acquisition module includes:

[0176] The setup and simulation module is used to build a test platform for testing solid-state drives and simulate preset services on the test platform;

[0177] The monitoring module is used to monitor the firmware operation logs of the solid-state drive during the simulation of preset business processes.

[0178] The second acquisition module is used to obtain the first historical remaining quantity of the command queue of the solid-state drive over multiple historical periods using log information; wherein, the characteristic data corresponding to the first historical remaining quantity of the command queue includes: the time period in which the first historical remaining quantity of the command queue was sampled, the mode of the command issued by the host, the size of the data block, and the size of the data read or written; the mode of the command issued by the host includes read commands and write commands;

[0179] The solid-state drive write latency processing device also includes:

[0180] The partitioning module is used to divide the remaining quantity of the first history into a training set, a validation set, and a test set according to a second preset weight; wherein the weight corresponding to the training set is greater than the weight of the validation set and the weight of the test set.

[0181] The training and acquisition module is used to train a preset long short-term memory network model using the training set and to acquire the current number of training iterations.

[0182] The judgment module is used to determine whether the current number of training iterations is greater than or equal to the preset number of training iterations; if yes, the output module is triggered; if no, the third acquisition module is triggered.

[0183] The output module is used to output the training results of the preset long short-term memory network model;

[0184] The third acquisition module is used to acquire the preset error precision;

[0185] The first detection module is used to return to the trigger output module when the detected error accuracy meets the first preset requirement;

[0186] The first detection module is also used to return to the trigger judgment module when the detected error accuracy does not meet the first preset requirement;

[0187] Also includes:

[0188] The detection and acquisition module is used to detect the prediction ability of the determined preset long short-term memory network model using the validation set and to acquire the prediction ability detection results.

[0189] The second detection module is used to verify the prediction results of the determined preset long short-term memory network model using a test set when the prediction ability detection result meets the second preset requirement.

[0190] The second detection module is also used to return to the trigger establishment and simulation module when the detection result of the predictive ability does not meet the second preset requirement.

[0191] The solid-state drive write latency processing device also includes a determination module, which is used to determine the remaining quantity of the first target and / or the remaining quantity of the second target;

[0192] The module specifically includes:

[0193] The fourth acquisition module is used to acquire a first historical remaining quantity and / or a second historical remaining quantity at each sending rate when the host sends write commands at different rates and / or when the solid-state drive receives write commands at different rates; wherein, the first historical remaining quantity is determined based on the difference between the bits at the head of the command queue and the bits at the tail of the command queue; the second historical remaining quantity is determined based on the difference between the preset data storage amount of the data buffer and the data storage amount at the historical moment.

[0194] The fifth acquisition module is used to acquire write latency data at various download speeds using a test tool for testing the write latency of solid-state drives.

[0195] The sixth acquisition module is used to obtain the minimum write latency data from all write latency data;

[0196] The module is used to obtain the first historical remaining quantity and / or the second historical remaining quantity corresponding to the minimum write latency data as the first target remaining quantity and / or the second target remaining quantity.

[0197] Solid-state drive write latency processing devices also include:

[0198] The first storage module is used to store the data corresponding to the write command sent by the host according to the first target rate value in the host's data storage area;

[0199] The first notification module is used to control the host to notify the solid-state drive of a new write command by using the value of the doorbell register, which is then stored in the host's command submission queue.

[0200] The second storage module is used to store write commands retrieved from the command submission queue according to the second target rate value into the command queue, and to store the data corresponding to the write commands from the data storage area into the data buffer; wherein, the command queue and the data buffer are both located in the solid-state drive;

[0201] The parsing module is used to parse write commands in the command queue;

[0202] The third storage module is used to store the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command.

[0203] The non-volatile memory includes multiple flash memory modules; each flash memory module contains multiple channels; the third storage module specifically includes:

[0204] The fourth storage module is used to store the data corresponding to the write command in the data buffer into multiple flash memory corresponding to the non-volatile memory according to the parsed write command;

[0205] There are multiple command submission queues, and the second storage module specifically includes:

[0206] The retrieval and storage module is used to retrieve the same number of write commands from each command submission queue according to the second target rate value and store the write commands into the command queue, and to store the data corresponding to the write commands from the data storage area into the data buffer.

[0207] Solid-state drive write latency processing devices also include:

[0208] The seventh acquisition module is used to acquire prompt information indicating that the write data corresponding to the write command is stored in non-volatile memory;

[0209] The sending module is used to send the prompt message to the completion queue in the host.

[0210] The second prompt module is used to notify the host that the write command processing is complete based on the prompt information in the completion queue.

[0211] The prediction module specifically includes:

[0212] The monitoring module is used to monitor the host's process of processing write commands and / or monitor the solid-state drive's process of processing write commands;

[0213] The first prediction module is used to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive (SSD) when it is detected that the process of the host processing a write command stores the write command to the command submission queue for the host, and / or when it is detected that the process of the solid-state drive (SSD) processing a write command writes the write command to the command queue for the SSD.

[0214] The solid-state drive write latency processing device also includes a filtering module, used to perform low-pass filtering on the first remaining quantity of the solid-state drive's command queue and / or the second remaining quantity of the data buffer through a low-pass filter.

[0215] Since the embodiments of the device part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the device part, which will not be repeated here, and it has the same beneficial effects as the solid-state drive write latency processing method mentioned above.

[0216] Figure 6 This is a structural diagram of a solid-state drive provided in another embodiment of the present invention. This embodiment is based on a hardware perspective, such as... Figure 6 As shown, solid-state drives include:

[0217] Memory 20 is used to store computer programs;

[0218] The processor 21 is used to implement the steps of the solid-state drive write latency processing method mentioned in the above embodiments when executing a computer program.

[0219] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to handle computational operations related to machine learning.

[0220] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the relevant steps of the solid-state drive write latency processing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, and the storage method may be temporary or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the solid-state drive write latency processing method mentioned above.

[0221] In some embodiments, the solid-state drive may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0222] Those skilled in the art will understand that Figure 6 The structure shown is not intended to limit the solid-state drive and may include more or fewer components than illustrated.

[0223] The solid-state drive provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following method: a solid-state drive write latency processing method, with the same effect as above.

[0224] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0225] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0226] The computer-readable storage medium provided by this invention includes the aforementioned method for handling solid-state drive write latency, with the same effect.

[0227] The foregoing has provided a detailed description of a method, apparatus, solid-state drive (SSD), and medium for handling write latency in a solid-state drive (SSD). The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0228] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for handling write latency in a solid-state drive, characterized in that, include: Obtain the first current rate at which the host issues the write command and / or the second current rate at which the solid-state drive receives the write command; The method utilizes a preset Long Short-Term Memory (LSTM) network model to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive (SSD). Determining the output of the preset LSM network model includes: inputting the first historical remaining quantity of the command queue and / or the second historical remaining quantity of the data buffer, collected over multiple historical periods, into a forward LSM network model in chronological order to obtain a first output; and inputting the first historical remaining quantity and / or the second historical remaining quantity into a reverse LSM network model in chronological order to obtain a second output; and combining the first output and the second output according to a first preset weight to obtain the final output of the preset LSM network model. If the first remaining quantity is detected to be greater than the first target remaining quantity and / or the second remaining quantity is detected to be greater than the second target remaining quantity, the first current rate is reduced to the first target rate value and / or the second current rate is reduced to the second target rate value; Determining the remaining quantity of the first target and / or the remaining quantity of the second target includes: If the host is detected to issue the write command at different rates, and / or if the solid-state drive is detected to receive the write command at different rates, the first historical remaining quantity and / or the second historical remaining quantity at each issuance rate are obtained; wherein, the first historical remaining quantity is determined based on the difference between the bits at the head of the command queue and the bits at the tail of the command queue; the second historical remaining quantity is determined based on the difference between the preset data storage amount of the data buffer and the data storage amount at a historical time. Write latency data at various download speeds was obtained using a test tool for testing the write latency of the solid-state drive. Obtain the minimum write latency data from all the write latency data; Obtain the first historical remaining quantity and / or the second historical remaining quantity corresponding to the minimum write latency data as the first target remaining quantity and / or the second target remaining quantity.

2. The solid-state drive write latency processing method according to claim 1, characterized in that, Obtaining the first historical remaining quantity of the command queue collected within multiple historical time periods includes: Establish a test platform for testing the solid-state drive, and simulate preset services on the test platform; During the simulation of the preset service, monitoring is conducted through the firmware operation logs of the solid-state drive; The log information is used to obtain the first historical remaining quantity of the command queue of the solid-state drive within multiple historical time periods; wherein, the feature data corresponding to the first historical remaining quantity of the command queue includes: the time period in which the first historical remaining quantity of the command queue was sampled, the mode of the host issuing commands, the size of the data block, and the size of the data read or written; the mode of the host issuing commands includes read commands and write commands; After obtaining the first historical remaining quantity of the command queue collected within the multiple historical time periods, the method further includes: The first remaining historical quantity is divided into a training set, a validation set, and a test set according to a second preset weight; wherein the weight corresponding to the training set is greater than the weight of the validation set and the weight of the test set. The preset long short-term memory network model is trained using the training set, and the current number of training iterations is obtained. Determine whether the current training count is greater than or equal to the preset training count; If so, output the training results of the preset long short-term memory network model; If not, then obtain the preset error precision; If the error accuracy is found to meet the first preset requirement, the step of returning the training result of the preset long short-term memory network model is performed. If the error accuracy is found to be not in line with the first preset requirement, the process returns to the step of determining whether the current number of training iterations is greater than or equal to the preset number of training iterations. After outputting the training results of the preset long short-term memory network model, the method further includes: The prediction ability of the determined preset long short-term memory network model is tested using the validation set, and the prediction ability test results are obtained. If the prediction ability detection result meets the second preset requirement, the prediction result of the determined preset long short-term memory network model is verified using the test set. If the prediction capability detection result does not meet the second preset requirement, the process returns to the step of establishing a test platform for testing the solid-state drive and simulating a preset service on the test platform.

3. The solid-state drive write latency processing method according to claim 1 or 2, characterized in that, After reducing the first current rate to the first target rate value and the second current rate to the second target rate value, the method further includes: The data corresponding to the write command sent by the host according to the first target rate value is stored in the data storage area of ​​the host; The host controller uses the value of the doorbell register to indicate to the solid-state drive that a new write command exists and stores it in the host's command submission queue. The write command retrieved from the command submission queue according to the second target rate value is stored in the command queue, and the data corresponding to the write command is stored from the data storage area to the data buffer; wherein, the command queue and the data buffer are both located in the solid-state drive; Parse the write command in the command queue; According to the parsed write command, the data corresponding to the write command is stored from the data buffer into the non-volatile memory.

4. The solid-state drive write latency processing method according to claim 3, characterized in that, The non-volatile memory includes multiple flash memory modules; each flash memory module contains multiple channels; the step of storing the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command includes: According to the parsed write command, the data corresponding to the write command in the data buffer is stored in the multiple flash memory corresponding to the non-volatile memory; The command submission queue is multiple, and the step of retrieving the write command from the command submission queue according to the second target rate value and storing the write command into the command queue, and storing the data corresponding to the write command from the data storage area to the data buffer includes: According to the second target rate value, the same number of write commands are sequentially retrieved from each of the command submission queues and stored in the command queue, and the data corresponding to the write commands is stored from the data storage area to the data buffer.

5. The solid-state drive write latency processing method according to claim 3, characterized in that, After storing the data corresponding to the write command from the data buffer to the non-volatile memory according to the parsed write command, the method further includes: Obtain prompt information indicating that the write data corresponding to the write command is stored in the non-volatile memory; The prompt message is sent to the completion queue in the host; The host is notified that the write command has been processed based on the prompt information in the completion queue.

6. The method for handling solid-state drive write latency according to claim 1, characterized in that, The step of using a preset long short-term memory network model to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive includes: Monitor the process of the host processing the write command and / or monitor the process of the solid-state drive processing the write command; If it is detected that the process of the host processing the write command is to store the write command to the command submission queue, and / or if it is detected that the process of the solid-state drive processing the write command is to write the write command to the command queue, the first remaining quantity of the command queue of the solid-state drive and / or the second remaining quantity of the data buffer are predicted by the preset long short-term memory network model. Before comparing the first remaining quantity with the first target remaining quantity, and / or before comparing the second remaining quantity with the second target remaining quantity, the method further includes: The first remaining quantity of the command queue of the solid-state drive and / or the second remaining quantity of the data buffer are low-pass filtered by a low-pass filter.

7. A solid-state drive write latency processing device, characterized in that, include: The acquisition module is used to acquire the first current rate at which the host issues a write command and / or the second current rate at which the solid-state drive receives the write command; The prediction module is used to predict the first remaining quantity of the command queue and / or the second remaining quantity of the data buffer of the solid-state drive using a preset long short-term memory network model. Determining the output of the preset long short-term memory network model includes: inputting the first historical remaining quantity of the command queue and / or the second historical remaining quantity of the data buffer collected over multiple historical periods into a forward long short-term memory network model in chronological order to obtain a first output; and inputting the first historical remaining quantity and / or the second historical remaining quantity into a reverse long short-term memory network model in chronological order to obtain a second output; and combining the first output and the second output according to a first preset weight to obtain the final output of the preset long short-term memory network model. The reduction module is configured to reduce the first current rate to a first target rate value and / or reduce the second current rate to a second target rate value when the first remaining quantity is detected to be greater than the first target remaining quantity and / or the second remaining quantity is detected to be greater than the second target remaining quantity. The solid-state drive write latency processing device also includes a determination module, which is used to determine the remaining quantity of the first target and / or the remaining quantity of the second target; The module specifically includes: The fourth acquisition module is used to acquire a first historical remaining quantity and / or a second historical remaining quantity at each sending rate when the host sends write commands at different rates and / or when the solid-state drive receives write commands at different rates; wherein, the first historical remaining quantity is determined based on the difference between the bits at the head of the command queue and the bits at the tail of the command queue; the second historical remaining quantity is determined based on the difference between the preset data storage amount of the data buffer and the data storage amount at the historical moment. The fifth acquisition module is used to acquire write latency data at various download speeds using a test tool for testing the write latency of solid-state drives. The sixth acquisition module is used to obtain the minimum write latency data from all write latency data; The module is used to obtain the first historical remaining quantity and / or the second historical remaining quantity corresponding to the minimum write latency data as the first target remaining quantity and / or the second target remaining quantity.

8. A solid-state drive, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the solid-state drive write latency processing method as described in any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the solid-state drive write latency processing method as described in any one of claims 1 to 6.

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