Ijtag-based test network and control method, storage medium

Abstract

The application discloses an IJTAG-based test network and a control method and a storage medium, and relates to the technical field of electronics. The control method comprises the following steps: controlling an FSM state machine of a TAP interface to perform DR access jump, wherein the DR access jump comprises sequentially performed path construction jump, TDR access jump and SIB closing jump; the path construction jump controls the execution of step S110: opening at least part of SIBs in an SIB multi-layer network, and enabling the TAP interface to construct a serial path with selected TDR registers through the SIB units; the TDR access jump controls the execution of step S120: enabling the SIB units and the TDR registers in the serial path to control the serial transmission of data in the serial path; and the SIB closing jump controls the execution of step S130: enabling each SIB unit in the serial path to receive setting data for closing the SIB from outside the serial path, and controlling the SIB unit to switch to a closed state. The application can improve the robustness of the test network.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically to IJTAG-based test networks and control methods, and storage media. Background Technology

[0002] As chip integration and complexity increase, the testing method using the TAP (Test Access Port) interface combined with the TDR (Test Data Register) becomes difficult to balance test time and integration complexity requirements. Therefore, the IJTAG (IEEE 1687) standard was proposed. Figure 1 As shown, an IJTAG-based test network typically includes a test controller ( Figure 1 (Not shown), TAP interface 10, SIB (Segment Insertion Bit) unit 20 and TDR register 30, the controller is connected to TDR register 30 in sequence through TAP interface 10 and multiple SIB units 20.

[0003] The controller controls the state transitions of the FSM state machine of TAP interface 10, establishes a serial path, and enables SIB unit 20 and TDR register 30 to control the serial transmission of data in the serial path. Specifically, when it is necessary to shut down SIB unit 20, the controller controls itself to switch to the off state by receiving data for shutting down the SIB from the serially transmitted data in the serial path.

[0004] In a test network with multiple TDR registers 30 and a complex structure, defects in the chip manufacturing process will also appear probabilistically in the SIB unit 20 or TDR register 30, and a large amount of logic in these parts will inevitably appear on the serial path.

[0005] like Figure 1 As shown, Figure 1 The serial path is indicated by a bold solid line with an arrow, where the arrow in the bold solid line indicates the data transmission direction of the serial path. At this time, the TDR register located in the serial path is the first register 30a, and the multiple SIB units 20 located in the serial path are designated as first SIB unit 20a, second SIB unit 20b, third SIB unit 20c, and fourth SIB unit 20d. If the first TDR register 30a malfunctions, causing the first TDR register 30a to form a clamping failure portion, it will be clamped to the first control value used to control the opening of the SIB (where the first control value is in...). Figure 1When the value is 1), after the first control value is sequentially shifted to the third SIB unit 20c, the fourth SIB unit 20d, the second SIB unit 20b, and the first SIB unit 20a through the serial path transmission, the data of all SIB units 20 located after the clamp failure part in the serial path, such as the third SIB unit 20c, the fourth SIB unit 20d, the second SIB unit 20b, and the first SIB unit 20a, are set to the first control value. This causes all subsequent SIB units 20 to be unexpectedly opened and unable to be closed normally, forming an unexpected open part, which in turn affects the subsequent access to other TDR registers 30.

[0006] Therefore, how to avoid the impact of faults in some SIB cells or TDR registers on the subsequent construction of serial paths to access other TDR registers in the IJTAG-based test network, so as to improve the robustness of the test network, is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of this, in order to solve the above-mentioned technical problems, this application provides a test network and control method based on IJTAG, and a storage medium.

[0008] To achieve the above objectives, this application provides a control method for an IJTAG-based test network, the control method comprising:

[0009] The FSM state machine that controls the TAP interface performs DR access transitions, which include sequential path construction transitions, TDR access transitions, and SIB shutdown transitions.

[0010] Path construction jump control execution step S110: Enable at least some of the SIBs in the SIB multilayer network, and allow the TAP interface to construct a serial path with the selected TDR register through the SIB unit;

[0011] TDR access jump control execution step S120: Enable the SIB unit and TDR register in the serial path to control the serial transmission of data in the serial path.

[0012] SIB shutdown jump control execution step S130: Each SIB unit in the serial path receives the set data for shutting down the SIB from outside the serial path, and controls itself to switch to the shutdown state.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide a storage medium that stores a computer program that can be executed by a processor to implement the above-mentioned control method.

[0014] To address the aforementioned technical problems, another technical solution adopted in this application is to provide a test network based on IJTAG. The test network includes a controller, a TAP interface, a SIB multilayer network, and multiple TDR registers. The controller is sequentially connected to the multiple TDR registers through the TAP interface and the SIB multilayer network. The controller is used to control the FSM state machine of the TAP interface to implement the aforementioned control method.

[0015] Beneficial Effects: Unlike existing technologies, in this application, even if some SIB units or TDR registers in the serial path fail, causing the faulty SIB units or TDR registers to be clamped to a first control value for opening the SIB unit, after the first control value is shifted through the serial path, all SIB units in the serial path following the faulty SIB unit or the faulty TDR register are set to the first control value, thus being abnormally opened and unable to be closed normally. At this time, by using the SIB close jump control, the SIB units in the serial path can receive the set data for closing the SIB from outside the serial path, thereby controlling themselves to switch to the closed state. This allows the SIB units in the currently constructed serial path following the faulty SIB unit or the faulty TDR register to be closed, so that the SIB units in the previously constructed serial path following the faulty SIB unit or the faulty TDR register can participate normally in the construction of the serial path when accessing other TDR registers, thereby improving the robustness of the test network. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the circuit principle of the TAP interface, SIB multilayer network and TDR register in the prior art;

[0017] Figure 2 This is a schematic diagram of the IJTAG-based test network of this application;

[0018] Figure 3 This is a schematic diagram of the circuit principle of the TAP interface, SIB multilayer network and TDR register of the IJTAG-based test network of this application.

[0019] Figure 4 This is a schematic diagram of the state transitions of the FSM state machine of the IJTAG-based test network of this application;

[0020] Figure 5 This is a schematic diagram of the circuit principle of the TAP interface of the IJTAG-based test network of this application;

[0021] Figure 6This is a schematic diagram of the circuit principle of the SIB interface of the IJTAG-based test network of this application;

[0022] Figure 7 This is a schematic diagram showing the connection between a TDR register and the circuit under test in the IJTAG-based test network of this application;

[0023] Figure 8 This is a schematic diagram of the write-only register unit of the IJTAG-based test network of this application.

[0024] Figure 9 This is a schematic diagram showing the connection between another TDR register of the IJTAG-based test network and the circuit under test in this application.

[0025] Figure 10 This is a schematic diagram of the read-only register unit of the IJTAG-based test network of this application.

[0026] Figure 11 This is a schematic diagram showing the connection between the TDR register and the circuit under test in the IJTAG-based test network of this application.

[0027] Figure 12 This is a flowchart illustrating an embodiment of the control method for an IJTAG-based test network according to this application;

[0028] Figure 13 This is a flowchart illustrating another embodiment of the control method for the IJTAG-based test network of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100 - Test Network; 110 - Controller; 120 - TAP Interface; 130 - SIB Multilayer Network; 140 - TDR Register; 200 - Circuit Under Test; 300 - Risk Area;

[0031] 131-SIB unit; b0-Preset bit signal terminal; 132-First data selection circuit; 133-First shift register unit; 134-First update register unit; 135-First delay register unit;

[0032] 131a - First SIB unit; 131b - Second SIB unit; 131c - Third SIB unit; 131d - Fourth SIB unit;

[0033] 141 - Register unit; 141a - Write-only register unit; 141b - Read-only register unit; P1 - Second serial transmission terminal; P1.1 - First input terminal; P1.2 - First output terminal; 142a - Second data selection circuit; 143a - Second shift register unit; 144a - Second update register unit; P2 - Third serial transmission terminal; P2.1 - Second input terminal; P2.2 - Second output terminal; 142b - Third data selection circuit; 143b - Third shift register unit;

[0034] 140a - First TDR register; 140b - Second TDR register; 140c - Third TDR register; 140d - Fourth TDR register; 300a - First risk area; 300b - Second risk area; 300c - Third risk area. Detailed Implementation

[0035] To enable those skilled in the art to better understand the technical solutions of this application, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] Please see Figure 2 The IJTAG-based test network 100 of the first embodiment of this application includes a controller 110, a TAP (Test Access Port) 120, a SIB (Segment Insertion Bit) multilayer network 130, and multiple TDR (Test Data Register) registers 140. The controller 110 is sequentially connected to the multiple TDR registers 140 through the TAP interface 120 and the SIB multilayer network 130. The TDR registers 140 are used to connect to the circuit under test 200 to update configuration data or test stimuli to the circuit under test 200 or to capture circuit status or test results from the circuit under test 200.

[0037] Optionally, in one example, different TDR registers 140 can be connected to different circuits under test 200. Alternatively, in another example, different TDR registers 140 can be connected to different interfaces of the same circuit under test 200. The following descriptions all illustrate the example of different TDR registers 140 connected to different circuits under test 200.

[0038] Furthermore, combined Figure 2 See Figure 3The SIB multilayer network 130 includes multiple hierarchically arranged SIB units 131. The initial state of the multiple SIB units 131 in the SIB multilayer network 130 is a closed state. The closed SIB units 131 can be used for serial communication with other adjacent SIB units 131 belonging to the same layer in the SIB multilayer network 130. The SIB units 131 can be opened by the control unit through the TAP interface 120 and become open. The open SIB units 131 can be used for serial communication with other adjacent SIB units 131 belonging to adjacent layers in the SIB multilayer network 130. Thus, the SIB multilayer network 130 can establish a serial path between the TAP interface 120 and the selected TDR register 140 based on the opening of at least some of the SIBs.

[0039] For example, rather than limiting, in one example, such as Figure 3 As shown, the multiple TDR registers 140 include a first TDR register 140a, a second TDR register 140b, a third TDR register 140c, and a fourth TDR register 140d. Figure 3 A bold solid line with an arrowhead indicates a serial path connecting the selected TDR register 140, where the arrow in the bold solid line indicates the direction of data transmission in the serial path. The serial path is used to connect the TAP interface 120 and the selected TDR register 140 for data transmission.

[0040] For example, rather than limiting, in one example, such as Figure 3 As shown, the first TDR register 140a is the selected TDR register 140. The multiple SIB units in the serial path connecting the TAP interface 120 and the first TDR register 140a are the first SIB unit 131a, the second SIB unit 131b, the third SIB unit 131c, and the fourth SIB unit 131d. Specifically, the first SIB unit 131a is in the off state, the second SIB unit 131b is in the on state, the third SIB unit 131c is in the on state, and the fourth SIB unit 131d is in the off state.

[0041] Optionally, in one example, the data transmitted in the serial path includes, but is not limited to, configuration data or test stimuli transmitted by the TAP interface 120 to the TDR register 140 via the serial path. Optionally, in another example, the data transmitted in the serial path includes, but is not limited to, data captured from the circuit under test 200 transmitted by the TDR register 140 to the TAP interface 120 via the serial path.

[0042] The above method achieves two technical effects. First, depending on the selected TDR register 140 each time, the corresponding SIB unit 131 can be opened during the construction of the serial path, so that the serial paths constructed in the previous and subsequent constructions of the SIB multilayer network 130 can be different, and thus the serial paths constructed in the previous and subsequent constructions can connect to different TDR registers 140. Second, each constructed serial path can connect to any one to four TDR registers 140, so as to access any one to four TDR registers 140 through the serial path.

[0043] Furthermore, combined Figures 2-3 See Figure 5 The TAP interface 120 includes interfaces for five standard signals, and the controller 110 is connected to the TAP interface 120 through these five standard signal interfaces.

[0044] Specifically, the five standard signal interfaces of the TAP interface 120 are TCK (Test Clock) interface, TMS (Test Mode Selection) interface, TDI (Test Data Input) interface, TDO (Test Data Output) interface, and TRST (Test Reset) interface.

[0045] The TCK interface of TAP interface 120 provides an independent, basic TCK signal for the operation of TAP interface 120. All operations of TAP interface 120 are driven by this TCK signal. The TMS interface of TAP interface 120 provides a TMS signal to control the state transitions of the FSM state machine of TAP interface 120. The TMS signal controls the transitions between different states of the FSM state machine of TAP interface 120. The TMS signal is valid on the rising edge of the TCK signal. The TDI interface of TAP interface 120 is the test data input interface. All data to be input into TDR register 140 is input serially bit by bit through the TDI interface driven by TCK. The TDO interface is the test data output interface. All data to be output from TDR register 140 is output serially bit by bit through the TDO interface driven by TCK. The TRST interface can be used to reset (initialize) TAP interface 120.

[0046] For a more detailed description of the TCK, TMS, TDI, TDO and TRST interfaces of the TAP interface 120, please refer to the description of the TAP interface 120 in the prior art related to the IEEE 1687-2014 standard, which will not be elaborated here.

[0047] Specifically, in combination Figures 2-3 and Figure 5 See Figure 4 The FSM state machine has 16 states. When the TRST interface is active low, the FSM is in the Test Logic Reset state. Under a valid TCK clock stimulus, if TMS = 1, the state is retained; otherwise, the state switches to the Run-Test / Idle state. Subsequently, under the control of TMS being 0 or 1, it enters either the IR (Instruction Register) access branch or the DR (Data Register) access branch.

[0048] The DR access branches include Select DR-Scan, Capture-DR, Shift-DR, Exit 1-DR, Pause-DR, Exit 2-DR, and Update-DR.

[0049] The IR access branches include Select IR-Scan, Capture-IR, Shift-DR, Exit 1-IR, Pause-IR, Exit 2-IR, and Update-DR.

[0050] The specific functions of the 16 states of the aforementioned FSM state machine can be found in the description of the TAP interface 120 in the prior art related to the IEEE 1687-2014 standard, and will not be elaborated further here.

[0051] Furthermore, combined Figures 2-3 See Figures 5-7The TAP interface 120 includes an FSM decoder, an IR register, an IR decoder, a Reset interface, a CaptureEn interface, a ShiftEn interface, an Update interface, a Select interface, a ScanIn interface, and a ScanOut interface. The SIB unit 131 includes a ScanIn interface, a ToScanIn interface, a FromScanOut interface, a ScanOut interface, a CaptureEn interface, a ShiftEn interface, an Update interface, a Select interface, a ToSelect interface, a Reset interface, and a TCK interface. The TDR register 140 includes a ScanIn interface, a Select interface, a Reset interface, a TCK interface, a CaptureEn interface, a ShiftEn interface, an UpdateEn interface, and a Scanout interface. Here, CaptureEn represents the enable signal for loading the DR state, ShiftEn represents the enable signal for shifting the DR state, and UpdateEn represents the enable signal for updating the DR state.

[0052] If the specific connection methods of the above interfaces are not specifically described below, please refer to the relevant descriptions in the existing technology related to the IEEE 1687-2014 standard, and will not be repeated here.

[0053] The Select and ToSelect interfaces are enable signal interfaces. The Select and ToSelect interfaces connect the upper and lower layer networks. The enable signal is used to enable SIB unit 131 or TDR register 140 to select SIB unit 131 and TDR register 140, thereby constructing a serial path through the selected SIB unit and the selected TDR unit.

[0054] Within the same SIB unit 131, the ScanIn interface is connected to the ToScanIn interface. The TAP interface 120, multiple SIB units 131 in the SIB multilayer network 130, and the TDR register 140 can establish serial connections in a serial path through the ScanIn and ScanOut interfaces of the TAP interface 120, the ScanIn, ScanOut, ToScanIn, and FromScanOut interfaces of the SIB unit 131, and the ScanIn and ScanOut interfaces of the TDR register 140. The ToScanIn, ScanIn, ScanOut, and FromScanOut interfaces provide serial connections for same-layer or upper / lower-layer networks, serving as data transmission interfaces for the serial path. When the TAP interface 120 establishes a serial path with the selected TDR register 140 through the SIB multilayer network 130, data is transmitted in the serial path through the ScanIn, ToScanIn, ScanOut, and FromScanOut interfaces.

[0055] For example, and not as a limitation, two adjacent SIB units 131 located in a serial path and belonging to the same layer in the SIB multilayer network 130 are connected in a serial connection through the ScanOut interface of one SIB unit 131 and the ScanIn interface of the other SIB unit 131.

[0056] For example, and not as a limitation, two adjacent SIB units 131 located in a serial path and belonging to adjacent layers in the SIB multilayer network 130 are serially connected via the ToScanIn and FromScanOut interfaces of one SIB unit 131 to the ScanIn and ScanOut interfaces of the other SIB unit 131. More specifically, the ToScanIn interface of one SIB unit 131 is connected to the ScanIn interface of the other SIB unit 131, and the FromScanOut interface of one SIB unit 131 is connected to the ScanOut interface of the other SIB unit 131.

[0057] Specifically, the closed state of SIB unit 131 is when the ScanIn interface of SIB unit 131 is connected to the ScanOut interface and the ToScanIn interface, while the FromScanOut interface of SIB unit 131 is disconnected from the ScanOut interface. The open state of SIB unit 131 is when the ScanIn interface of SIB unit 131 is disconnected from the ScanOut interface and connected to the ToScanIn interface, while the FromScanOut interface of SIB unit 131 is connected to the ScanOut interface.

[0058] For ease of explanation, the set of ScanIn, ScanOut, ToScanIn and FromScanOut interfaces in SIB unit 131 will be referred to as the first serial transmission end of SIB unit 131.

[0059] Further, see Figure 6 SIB unit 131 includes a preset bit signal terminal b0, a first data selection circuit 132, a first shift register unit 133, a first update register unit 134, and a delay register unit 135. The preset bit signal terminal b0 is used to receive a second signal from outside the serial path. The first serial transmission terminal is used to be connected in series in the serial path.

[0060] The first data selection circuit 132 is configured to respond to the control signal corresponding to the loaded DR state, select the preset bit signal terminal b0 and the first shift register unit 133, and shift the first shift register unit 133 into the second signal to replace the originally registered data.

[0061] The first data selection circuit 132 is also configured to select the first serial transmission terminal and the first shift register 133 in response to the control signal corresponding to the shift DR state, so that the first shift register 133 shifts data from the serial path to replace the originally registered data.

[0062] For example, and not as a limitation, when SIB unit 131 is in the off state, the first data selection circuit 132 selects the ScanIn interface in the first serial transmission terminal and the first shift register unit 133. When SIB unit 131 is in the on state, the first data selection circuit 132 selects the FromScanOut interface in the first serial transmission terminal and the first shift register unit 133.

[0063] The first update register 134 is configured to latch the data registered in the first shift register 133 in response to the control signal corresponding to the update DR state, so as to control the first data selection circuit 132 to set the connection state of the serial transmission terminal, thereby switching the SIB unit 131 to the open state or the closed state. The delay register 135 is configured to latch the data latched by the first update register 134 after a delay of one clock cycle in response to the control signal corresponding to the update DR state, so as to enable the next level of SIB.

[0064] In the above manner, during the SIB shutdown transition, after sequentially transitioning from the loaded DR state to the exit DR state and the update DR state via the loaded DR state, the second signal can be latched in the first update register unit 134, so that the first update register unit 134 sets the connection state of the serial transmission end according to the second signal, and switches the SIB unit 131 to the shutdown state.

[0065] Comparative Reference Figure 7 , Figure 9 and Figure 11 The TDR register 140 includes multiple register units 141 connected in series and used for serial connection to the serial path. The register units 141 are write-only register units 141a or read-only register units 141b.

[0066] The write-only register 141a is configured to capture its own written configuration data or test stimulus in response to the control signal corresponding to the load DR state, replacing the previously registered data. The write-only register 141a is also configured to shift in data through the serial path in response to the control signal corresponding to the shift DR state, replacing the previously registered data and transmitting the previously registered data along the serial path.

[0067] The write-only register 141a is configured to write its own registered data to the circuit under test 200 in response to the control signal corresponding to the update DR state, as updated configuration data or test stimulus.

[0068] Thus, during the SIB shutdown transition, after sequentially transitioning from the loaded DR state to the exited DR state and the updated DR state via the shifted DR state, the configuration data or test stimuli written before and after the write-only register unit 141a can remain unchanged.

[0069] The read-only register 141b is configured to capture circuit status or test results from the circuit under test 200 in response to the control signal corresponding to the loaded DR state.

[0070] The read-only register 141b is configured to, in response to the control signal corresponding to the shift DR state, shift in data through the serial path to replace the previously registered data and transmit the previously registered data along the serial path.

[0071] Optionally, combined Figure 3 See Figure 7 In a single TDR register 140, such as the first TDR register 140a and the third TDR register 140c, there may be only a write-only register 141a. For example, and not as a limitation, the first TDR register 140a and the third TDR register 140c can each store 3 bits of data, and each write-only register 141a is used to store one of the 3 bits, which are Bit[0], Bit[1] and Bit[2].

[0072] Optionally, combined Figure 3 See Figure 9 In a single TDR register 140, such as the second TDR register unit 140b, there may be only read-only register unit 141b. For example, and not limited to, the second TDR register unit 140b can store 3 bits of data, and each read-only register unit 141b is used to store one of the 3 bits, which are Bit[0], Bit[1] and Bit[2].

[0073] Optionally, combined Figure 3 See Figure 11 In a single TDR register 140, such as the fourth TDR register 140d, there may be both write-only register 141a and read-only register 141b. For example, and not as a limitation, the fourth TDR register 140d can store 3 bits of data, with each write-only register 141a storing one bit and each read-only register 141b storing one bit, and the bits of the 3 bits of data being Bit[0], Bit[1] and Bit[2].

[0074] Furthermore, combined Figure 3 , Figure 7 and Figure 11 See Figure 8 The write-only register 141a includes a second serial transmission terminal P1, a set data selection circuit 142a, a second shift register 143a, and a second update register 144a. The TDR register 140, equipped with the write-only register 141a, is configured to write data to the circuit under test 200 via the ToDataIn terminal and read data from the circuit under test 200 via the FromDataOut terminal. The output of the second update register 144a is connected to the ToDataIn terminal. The ToDataIn terminal is connected to the FromDataOut terminal.

[0075] The second serial transmission terminal P1 is used to be connected in series in the serial path. By way of example and not limitation, the second serial transmission terminal P1 includes a first input terminal P1.1 and a first output terminal P1.2. The first input terminal P1.1 is used to receive data from the serial path, and the first output terminal P1.2 is used to output data to the serial path.

[0076] The set data selection circuit 142a is configured to respond to the control signal corresponding to the loaded DR state, select the FromDataOut terminal and the second shift register 143a, so that the second shift register 143a captures the configuration data or test stimulus written to the ToDataIn terminal by the second update register 144a to replace the original registered data.

[0077] The set data selection circuit 142a is also configured to, in response to the control signal corresponding to the shift DR state, select the second serial transmission terminal P1 and the second shift register 143a, so that the second shift register 143a shifts data into the serial path to replace the previously registered data and shifts the previously registered data out along the transmission path. For example, and not as a limitation, the set data selection circuit 142a is configured to, in response to the control signal corresponding to the shift DR state, select the first input terminal P1.1 of the second serial transmission terminal P1 and the second shift register 143a, so that data is shifted into the first input terminal P1.1 to replace the previously registered data; and the previously registered data is shifted out through the first output terminal P1.2.

[0078] The second update register 144a is configured to latch the data registered in the second shift register 143a and write it to the ToDataIn terminal in response to the control signal corresponding to the update DR state, so as to serve as configuration data or test stimulus to update the circuit under test 200.

[0079] Furthermore, combined Figure 3 , Figure 9 and Figure 11 See Figure 10 The read-only register 141b includes a third serial transmission terminal P2, a third data selection circuit 142b, and a third shift register 143b. The TDR register 140, which is equipped with the read-only register 141b, is configured to read data from the circuit under test 200 via the FromDataOut terminal.

[0080] The third serial transmission terminal P2 is used to connect in series in the serial path. For example, and not as a limitation, the third serial transmission terminal P2 includes a second input terminal P2.1 and a second output terminal P2.2. The second input terminal P2.1 is used to receive data from the serial path, and the second output terminal P2.2 is used to output data to the serial path.

[0081] The third data selection circuit 142b is configured to select the FromDataOut terminal and the third shift register unit 143b in response to the control signal corresponding to the loaded DR state, so that the third shift register unit 143b captures the circuit state or test result output by the circuit under test 200 to replace the originally registered data.

[0082] The third data selection circuit 142b is also configured to, in response to the control signal corresponding to the shift DR state, select the third serial transmission terminal P2 and the third shift register 143b, so that the third shift register 143b shifts in data through the serial path to replace the previously registered data and transmits the previously registered data along the serial path. For example, but not as a limitation, the third data selection circuit 142b is configured to, in response to the control signal corresponding to the shift DR state, select the second input terminal P2.1 of the third serial transmission terminal P2 and the third shift register 143b, so that data is shifted in through the second input terminal P2.1 to replace the previously registered data, and the previously registered data is shifted out through the second output terminal P2.2.

[0083] The IJTAG-based test network 100 of the first embodiment of this application is used to implement the control method of the IJTAG-based test network 100 in the following embodiments.

[0084] See Figure 12 As shown, the control method for an IJTAG-based test network in the first embodiment of this application includes controlling the FSM state machine of the TAP interface to perform DR access transitions. The DR access transitions include path construction transitions, TDR access transitions, and SIB shutdown transitions performed sequentially. Specifically, the path construction transition control execution step S110, the TDR access transition control execution step S120, and the SIB shutdown transition control execution step S130.

[0085] Step S110: Enable at least some of the SIB cells in the SIB multilayer network, allowing the TAP interface to establish a serial path with the selected TDR register through the SIB cells.

[0086] Specifically, in conjunction with reference Figures 2-3 The initial state of multiple SIB units 131 in the SIB multilayer network 130 is closed. The SIB multilayer network 130 can establish a serial path between the TAP interface 120 and a selected TDR register 140 based on the opening of at least some of the SIB units 131. Depending on which SIB units 131 are opened each time, multiple SIB units 131 can establish a serial path between the TAP interface 120 and different TDR registers 140.

[0087] In the path construction transition, at least some SIBs are opened by the corresponding state transition of the FSM state machine to build a serial path connecting the TAP interface 120 to the selected TDR register 140.

[0088] For example, but not limited to, during a path construction jump, controller 110 connects the selected TDR register 140 to the serial path to be constructed as needed, thereby opening the corresponding SIB unit 131 and constructing the corresponding serial path.

[0089] Specifically, the Select interface of the control TAP interface 120 outputs an enable signal to the SIB unit 131 that constructs the serial path and is located in the first level. The SIB unit 131 that constructs the serial path and is located in a subsequent level can accept the enable signal output by the SIB unit that constructs the serial path and is located in the previous level through the ToSelect interface. In this way, the SIBs in the serial path to be constructed can be enabled, and the corresponding state transitions of the FSM state machine can be used to control the opening of the corresponding SIB units.

[0090] For details on the specific construction method of the serial path, please refer to the relevant descriptions in the existing technologies related to the IEEE 1687-2014 standard, which will not be repeated here.

[0091] Step S120: Enable the SIB unit and TDR register in the serial path to control the serial transmission of data in the serial path.

[0092] Specifically, in conjunction with reference Figures 2-3 The SIB unit 131 and TDR register 140 located in the serial path can serially transmit data located in the serial path by serial shifting.

[0093] Optionally, the data transmitted in the serial path includes, but is not limited to, configuration data or test stimuli transmitted by the TAP interface 120 to the TDR register 140 via the serial path. Optionally, the data transmitted in the transmission path includes, but is not limited to, data captured from the circuit under test 200 transmitted by the TDR register 140 to the TAP interface 120 via the serial path.

[0094] Step S130: Each SIB unit 131 in the serial path receives set data for turning off the SIB from outside the serial path, and controls itself to switch to the off state.

[0095] Specifically, each SIB unit 131 has a preset bit signal terminal b0 for connection to a preset bit signal source outside the serial path, so that each SIB unit 131 can bypass the serial path and receive set data for turning off the SIB unit 131 from outside the serial path.

[0096] In this way, even if some SIB units 131 or TDR registers 140 in the serial path fail, causing the faulty SIB unit 131 or TDR register 140 to be clamped to a first control value for opening the SIB unit 131, after the first control value is shifted through the serial path, all SIB units 131 in the serial path following the faulty SIB unit 131 or the faulty TDR register 140 are set to the first control value, thus being abnormally opened and unable to be closed normally. At this time, by using the SIB close jump control, each SIB unit 131 in the serial path receives the set data for closing the SIB from outside the serial path, thereby controlling each SIB unit 131 in the serial path to switch itself to the closed state (in short, making all SIB units 131 in the SIB multilayer network 130 return to the closed state). This allows the SIB unit 131 located after the faulty SIB unit 131 or the faulty TDR register 140 in the currently constructed serial path to be shut down. This enables the SIB unit 131 located after the faulty SIB unit 131 or the faulty TDR register 140 in the previously constructed serial path to participate normally in the construction of the serial path when accessing other TDR registers 140, thereby improving the robustness of the test network 100.

[0097] The control method of the IJTAG-based test network 100 in the second embodiment of this application is further defined based on the control method of the IJTAG-based test network 100 in the first embodiment, and the further definition is as follows.

[0098] The SIB shutdown transition includes loading the DR state and then sequentially transitioning from the loading DR state to the exit DR state and the update DR state, skipping the shift DR state. Step S130 includes steps S131 to S132.

[0099] Step S131: The SIB unit in the serial path responds to the control signal corresponding to the loaded DR state and captures the set data outside the serial path used to turn off the SIB.

[0100] Specifically, in conjunction with reference Figure 6 The first data selection circuit 132 responds to the control signal corresponding to the loaded DR state, and selects the preset bit signal terminal b0 and the first shift register unit 133, so that the first shift register unit 133 captures the set data for turning off the SIB unit 131 through the preset bit signal terminal b0.

[0101] Step S132: The SIB unit in the serial path responds to the control signal corresponding to the updated DR state and controls itself to shut down according to the set data.

[0102] Specifically, in conjunction with reference Figure 6 The first update register unit 134 is configured to latch the set data registered by the first shift register unit 133 in response to the control signal corresponding to the update DR state, so as to control the first data selection circuit 132 to set the connection state of the serial transmission terminal to switch the SIB to the off state through the set data.

[0103] The control method of the IJTAG-based test network 100 in the third embodiment of this application is further defined based on the control method of the IJTAG-based test network 100 in the second embodiment, and the further definition is as follows.

[0104] TDR access jump includes loading DR state and sequentially jumping from loading DR state to shift DR state and update DR state; step S120 includes steps S121 to S123.

[0105] Step S121: The TDR register in the serial path responds to the control signal corresponding to the loaded DR state and retrieves the circuit state or test result from the circuit under test.

[0106] For example, rather than limiting, in combination Figure 9 and Figure 11 See Figure 10 The third data selection circuit 142b responds to the control signal corresponding to the loaded DR state, selecting the FromDataOut terminal and the third shift register unit 143b, causing the third shift register unit 143b to capture the circuit state or test result output by the circuit under test 200, replacing the previously registered data. Thus, in step S121, the circuit state or test result can be registered in the third shift register unit 143b.

[0107] Step S122: The SIB unit and TDR register in the serial path respond to the control signal corresponding to the shift DR state, so that the data in the serial path is transmitted serially.

[0108] For example, rather than limiting, in combination Figure 3 See Figure 6 When data in the serial path is transmitted serially, the first data selection circuit 132 responds to the control signal corresponding to the shift DR state, selects the first serial transmission terminal and the first shift register unit 133, so that the first shift register unit 133 shifts data from the serial path to replace the original registered data.

[0109] Optionally, the data transmitted in the transmission path may be, for example, configuration data or test stimuli for the circuit under test 200. Optionally, the data transmitted in the serial path may be, for example, current state or detection results captured from the circuit under test 200.

[0110] Step S123: The TDR register in the serial path responds to the control signal corresponding to the update DR state and updates the configuration data or test stimulus to the circuit under test 200.

[0111] For example, rather than limiting, in combination Figure 7 and Figure 11 See Figure 8 In response to the control signal corresponding to the update DR state, the second update register unit 144a latches the data registered in the second shift register unit 143a and writes it to the ToDataIn terminal as configuration data or test stimulus to be updated to the circuit under test 200.

[0112] The control method of the IJTAG-based test network 100 in the fourth embodiment of this application is further defined based on the control method of the IJTAG-based test network 100 in the third embodiment, and the further definition is as follows.

[0113] See Figure 13 As shown, before the FSM state machine controlling the TAP interface 120 sequentially performs the path construction jump, TDR access jump, and SIB shutdown jump, step S100 is included. Step S110 includes step S110a, and step S140 is included after step S130.

[0114] Step S100: Group and sort multiple TDR registers according to predetermined rules based on predetermined relative access order and risk areas.

[0115] Specifically, in combination Figures 2-3 See Figure 7 , Figure 9 and Figure 11 Risk region 300 is a pre-selected region. For example, and not limited to, risk region 300 is determined by the probability of physical defects occurring; for example, risk region 300 is a region where the probability of physical defects occurring is greater than a predetermined threshold.

[0116] After grouping, there are m access groups, which are ordered as access group 1 to access group m. The predetermined relative access order is the relative access order of at least some of the TDR registers 140 preset for achieving the predetermined test purpose, and each risk area 300 includes at least one TDR register 140.

[0117] The predetermined rules include that the sorting order of the m access groups after grouping satisfies the predetermined relative access order, and that TDR registers 140 belonging to the same risk area 300 and not specified in the predetermined relative access order are assigned to the same access group, and that TDR registers 140 belonging to different risk areas 300 and not specified in the predetermined relative access order are assigned to different access groups.

[0118] Step S110a: Control the FSM state machine of the TAP interface to perform a path establishment jump, so that the TAP interface can build a serial path with the TDR register of the i-th access group through the corresponding SIB unit.

[0119] Step S120: Enable the SIB unit and TDR register in the serial path to control the serial transmission of data in the serial path.

[0120] In this fourth embodiment, step S120 is the same as step S120 in the first embodiment described above, and will not be repeated here.

[0121] See also Figure 3 Because the TDR register 140 of the i-th access group may probabilistically malfunction, it may be clamped to the first control value used to control the opening of the SIB unit 131. This means the location of the TDR register 140 in the i-th access group may become a clamping failure point. In step S120, the first control value of the TDR register 140 at this clamping failure point is transmitted via the serial path to the SIB unit 131 following the clamping failure point. This causes the data in the subsequent SIB unit 131 to be set to the first control value, preventing the abnormal opening of the subsequent SIB unit 131 from being closed by transmitting data via the serial path. In other words, the location of the subsequent SIB unit 131 may become an abnormally open point.

[0122] Step S130: Each SIB unit in the serial path receives set data for turning off the SIB from outside the serial path, and controls itself to switch to the off state.

[0123] In this fourth embodiment, step S130 is the same as step S130 in the first embodiment described above, and will not be repeated here.

[0124] See also Figure 3 In step S130, by having each SIB unit 131 in the serial path receive set data for disabling the SIB from outside the serial path, the original first control value of the abnormally open SIB unit 131 can be replaced with set data, thus controlling the abnormally open SIB unit 131 to switch to the closed state. In other words, the original abnormally open SIB unit 131 is corrected to the closed state. Therefore, when subsequently constructing the serial path between the TAP and the TDR register 140 of other access groups, if it is necessary to selectively use the SIB unit 131 corrected to the closed state, the corrected SIB unit 131 can still be selectively opened to avoid affecting the subsequent construction of the serial path between the TAP interface 120 and the other TDR register 140.

[0125] Step S140: increment i by 1 and repeat steps S110a to S140 to traverse the TDR registers of the 1st access group to the m-th access group.

[0126] In an example, step S140 specifically includes step S141 and step S142.

[0127] Step S141: set i = i + 1.

[0128] Step S142: determine whether i>m is true.

[0129] In step S142, if i>m is true, the process ends. If i<m in step S142, steps S110a to S140 are repeated. As a result, i gradually increases from 1 to m+1, so that after repeating steps S110a to S140, the TDR registers of the 1st access group to the m-th access group can be traversed.

[0130] In another example, step S140 may be implemented by first determining whether i=m is true; if i=m is true, the process ends; if i=m is not true, after setting i=i+1, steps S110a to S140 are repeated to realize traversal of the TDR registers of the 1st access group to the m-th access group.

[0131] The control method for the IJTAG-based test network 100 according to the fifth embodiment of the present application is further defined on the basis of the control method for the IJTAG-based test network 100 according to the fourth embodiment, and the further definitions are as follows.

[0132] With reference to Figure 3 , the number of TDR registers 140 in the test network 100 is 4, and the 4 TDR registers 140 are respectively a first TDR register 140a, a second TDR register 140b, a third TDR register 140c, and a fourth TDR register 140d. The predetermined relative access order is:

[0133] (1) The access order of the first TDR register 140a precedes the access order of the second TDR register 140b;

[0134] (2) The access order of the third TDR register 140c and the fourth TDR register 140d is later than the access order of the second TDR register 140b, and the third TDR register 140c and the fourth TDR register 140d need to be accessed in the same group.

[0135] The divided risk regions 300 have three, which are respectively:

[0136] (1) A first risk region 300a, including the first TDR register 140a;

[0137] (2) The second risk area 300b includes the second TDR register 140b;

[0138] (3) The third risk area 300c includes the third TDR register 140c and the fourth TDR register 140d.

[0139] Thus, in step S100, m equals 3, resulting in 3 access groups after grouping. These 3 access groups are ordered as Access Group 1 to Access Group 3, and the TDR register 140 included in each access group is as follows:

[0140] (1) The first access group includes the first TDR register 140a;

[0141] (2) The second access group includes the second TDR register 140b;

[0142] (3) The third access group includes the third TDR register 140c and the fourth TDR register 140d.

[0143] The control method of the IJTAG-based test network (not shown in the figure of the sixth embodiment) of this application is further limited based on the control method of the IJTAG-based test network 100 of the fourth embodiment, and the further limitations are as follows.

[0144] The test network has six TDR registers: the first TDR register, the second TDR register, the third TDR register, the fourth TDR register, the fifth TDR register, and the sixth TDR register. The predetermined relative access order is as follows:

[0145] (1) The access order of the first TDR register and the second TDR register is before the access order of the third TDR register and the fourth TDR register. There is no specific requirement for the access order between the first TDR register and the second TDR register. They can be accessed one after the other or in the same group.

[0146] (2) The third TDR register and the fourth TDR register need to be accessed in the same group.

[0147] (3) The access order of the fifth TDR register and the sixth TDR register is after the access order of the third TDR register and the fourth TDR register. There is no specific requirement for the access order between the fifth TDR register and the sixth TDR register. They can be accessed one after the other or in the same group.

[0148] The risk zone 300 is divided into four areas:

[0149] (1) The first risk area includes the first TDR register and the fifth TDR register;

[0150] (2) The second risk area includes the third TDR register and the fourth TDR register;

[0151] (3) The third risk area includes the second TDR register and the sixth TDR register.

[0152] Thus, in step S100, m equals 5, resulting in 5 access groups after grouping. These 5 access groups are ordered as Access Group 1 to Access Group 5, and the TDR registers included in each access group are as follows:

[0153] (1) The first access group, including the first TDR register;

[0154] (2) The second access group, including the second TDR register;

[0155] (3) The third access group includes the third TDR register and the fourth TDR register;

[0156] (4) The fourth access group includes the fifth TDR register;

[0157] (5) The fifth access group, including the sixth TDR register.

[0158] The control method of the IJTAG-based test network (not shown in the figure of the seventh embodiment) of this application is further limited based on the control method of the IJTAG-based test network 100 of the fourth embodiment, and the further limitations are as follows.

[0159] The test network has four TDR registers: the first TDR register, the second TDR register, the third TDR register, and the fourth TDR register. The predetermined relative access order is as follows:

[0160] (1) The access order of the first TDR register and the second TDR register is before the access order of the third TDR register and the fourth TDR register, and the first TDR register and the second TDR register must be accessed in the same group;

[0161] (2) There is no specific requirement for the access order between the third TDR register and the fourth TDR register. They can be accessed sequentially or in the same group.

[0162] The risk zones are divided into four categories:

[0163] (1) The first risk area includes the first TDR register;

[0164] (2) The second risk area includes the second TDR register;

[0165] (3) The third risk area, including the third TDR register;

[0166] (4) The fourth risk area includes the fourth TDR register.

[0167] Thus, two sorting schemes for the access groups can be selected. One specific sorting scheme is as follows: in step S100, m equals 3, resulting in 3 access groups after grouping. The 3 access groups are sorted in order from access group 1 to access group 3. The TDR registers included in each access group are as follows:

[0168] (1) The first access group includes the first TDR register and the second TDR register;

[0169] (2) Second access group, including the third TDR register;

[0170] (3) The third access group includes the fourth TDR register.

[0171] One of the other access group sorting arrangements is as follows: In step S100, m equals 3, resulting in 3 access groups after grouping. These 3 access groups are sorted in order from access group 1 to access group 3. The TDR registers included in each access group are as follows:

[0172] (1) The first access group includes the first TDR register and the second TDR register;

[0173] (2) The second access group includes the fourth TDR register;

[0174] (3) The third access group, including the third TDR register.

[0175] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A control method for a test network based on IJTAG, characterized in that, The control method includes: The FSM state machine controlling the TAP interface performs DR access transitions, which include sequential path construction transitions, TDR access transitions, and SIB shutdown transitions. The path construction jump control execution step S110: At least some of the SIB units in the SIB multilayer network are turned on, allowing the TAP interface to construct a serial path with the selected TDR register through the SIB units; The TDR access jump control execution step S120: causes the SIB unit and TDR register in the serial path to control the data in the serial path to be transmitted serially; The SIB shutdown jump control execution step S130: causes each SIB unit in the serial path to receive set data for shutting down the SIB unit from outside the serial path, and controls itself to switch to the shutdown state; The SIB shutdown transition includes sequentially transitioning from the loaded DR state, skipping the shifted DR state, to the exited DR state and the updated DR state; step S130 includes: Each SIB unit in the serial path responds to the control signal corresponding to the loaded DR state and captures the set data outside the serial path used to turn off the SIB unit; The SIB unit in the serial path responds to the control signal corresponding to the updated DR state and controls itself to shut down according to the set data; Before the FSM state machine controlling the TAP interface sequentially performs path construction jump, TDR access jump, and SIB shutdown jump, the following steps are included: The multiple TDR registers are grouped and sorted according to a predetermined relative access order and risk area according to a predetermined rule. The grouping includes m access groups, and the m access groups are ordered as access group 1 to access group m in order. The predetermined relative access order is the relative access order of at least some of the TDR registers preset for achieving the predetermined test purpose. Each risk area includes at least one TDR register. The predetermined rule includes that the sorting order of the m access groups after grouping satisfies the predetermined relative access order, and that TDR registers belonging to the same risk area are not specified in the predetermined relative access order and are assigned to the same access group, and that TDR registers belonging to different risk areas are not specified in the predetermined relative access order and are assigned to different access groups. Step S110 includes: controlling the FSM state machine of the TAP interface to perform a path establishment jump, so that the TAP interface can build a serial path with the TDR register of the i-th access group through the corresponding SIB unit; After step S130, step S140 is included: incrementing i by 1 and repeating steps S110 to S140 to traverse the TDR registers of the first access group to the m-th access group.

2. The control method according to claim 1, characterized in that, The TDR access jump includes loading DR state and sequentially jumping from loading DR state to shift DR state and update DR state; Step S120 includes: The TDR register in the serial path responds to the control signal corresponding to the loaded DR state to capture the circuit state or test result from the circuit under test; The SIB unit and the TDR register in the serial path respond to the control signal corresponding to the shift DR state, so that the data in the serial path is transmitted serially. The TDR register in the serial path updates configuration data or test stimuli to the circuit under test in response to the control signal corresponding to the updated DR state.

3. A storage medium, characterized in that, The storage medium stores a computer program that can be executed by a processor to implement the control method according to any one of claims 1-2.

4. A test network based on IJTAG, characterized in that, The test network includes a controller, a TAP interface, a SIB multilayer network, and multiple TDR registers. The controller is connected to the multiple TDR registers sequentially through the TAP interface and the SIB multilayer network. The controller is used to control the FSM state machine of the TAP interface to implement the control method according to any one of claims 1-2.

5. The test network according to claim 4, characterized in that, The SIB unit includes a first serial transmission terminal, a preset bit signal terminal, a first data selection circuit, a first shift register unit, a first update register unit, and a delay register unit; the preset bit signal terminal is used to receive a second signal from outside the serial path; the first serial transmission terminal is used to be connected in series in the serial path; The first data selection circuit is configured to respond to the control signal corresponding to the loaded DR state, select the preset bit signal terminal and the first shift register unit, so that the first shift register unit captures the second signal to replace the originally registered data; The first data selection circuit is also configured to select the first serial transmission terminal and the first shift register unit in response to the control signal corresponding to the shift DR state, so that the first shift register unit shifts data from the serial path to replace the originally registered data. The first update register unit is configured to latch the data registered in the first shift register unit in response to the control signal corresponding to the update DR state, so as to control the first data selection circuit to set the connection state of the serial transmission terminal to switch the SIB unit to the open state or the closed state. The delayed register unit is configured to latch the data latched by the first update register unit after a delay of one clock cycle in response to the control signal corresponding to the updated DR state, so as to enable the next level of the SIB unit.

6. The test network according to claim 5, characterized in that, The TDR register includes multiple register units that are connected in series and used to connect to the serial path. The register units are write-only register units or read-only register units. The write-only register unit is configured to capture the configuration data or test stimulus it has written in response to the control signal corresponding to the loaded DR state and replace the data originally registered. The write-only register is configured to shift in data through the serial path to replace the previously registered data in response to the control signal corresponding to the shift DR state. The write-only register unit is configured to write the data it stores to the circuit under test in response to the control signal corresponding to the update DR state, as updated configuration data or test stimulus. The read-only register unit is configured to retrieve the circuit state or test result from the circuit under test in response to the control signal corresponding to the loaded DR state.

7. The test network according to claim 6, characterized in that, The write-only register unit includes a second serial transmission terminal, a set data selection circuit, a second shift register unit, and a second update register unit. The TDR register with the write-only register unit is configured to write data to the circuit under test (DUT) via the ToDataIn terminal and read data from the DUT via the FromDataOut terminal. The output terminal of the second update register unit is connected to the ToDataIn terminal. The ToDataIn terminal is connected to the FromDataOut terminal. The second serial transmission terminal is used to be connected in series in the serial path. The set data selection circuit is configured to respond to the control signal corresponding to the loaded DR state, select the FromDataOut terminal and the second shift register unit, so that the second shift register unit captures the configuration data or test stimulus written to the ToDataIn terminal by the second update register unit to replace the original registered data; The set data selection circuit is also configured to respond to the control signal corresponding to the shift DR state, select the second serial transmission terminal and the second shift register unit, so that the second shift register unit shifts data into the serial path to replace the original registered data; The second update register is configured to latch the data registered in the second shift register and write it to the ToDataIn terminal in response to the control signal corresponding to the update DR state, as configuration data or test stimulus to be updated to the circuit under test.

8. The test network according to claim 6, characterized in that, The read-only register unit includes a third serial transmission terminal, a third data selection circuit, and a third shift register unit; the third serial transmission terminal is used to be connected in series in the serial path. The TDR register, which is equipped with a read-only register unit, is configured to read data from the circuit under test via the FromDataOut terminal; The third data selection circuit is configured to respond to the control signal corresponding to the loaded DR state, select the FromDataOut terminal and the third shift register unit, so that the third shift register unit captures the circuit state or test result output by the circuit under test to replace the originally registered data. The third data selection circuit is also configured to select the third serial transmission terminal and the third shift register unit in response to the control signal corresponding to the shift DR state, so that the third shift register unit shifts data into the serial path to replace the original registered data.

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